1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HP Quicksilver AGP GART routines 4 * 5 * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org> 6 * 7 * Based on drivers/char/agpgart/hp-agp.c which is 8 * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P. 9 * Bjorn Helgaas <bjorn.helgaas@hp.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/klist.h> 16 #include <linux/agp_backend.h> 17 #include <linux/log2.h> 18 #include <linux/slab.h> 19 20 #include <asm/parisc-device.h> 21 #include <asm/ropes.h> 22 23 #include "agp.h" 24 25 #define DRVNAME "quicksilver" 26 #define DRVPFX DRVNAME ": " 27 28 #define AGP8X_MODE_BIT 3 29 #define AGP8X_MODE (1 << AGP8X_MODE_BIT) 30 31 static unsigned long 32 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, 33 int type); 34 35 static struct _parisc_agp_info { 36 void __iomem *ioc_regs; 37 void __iomem *lba_regs; 38 39 int lba_cap_offset; 40 41 u64 *gatt; 42 u64 gatt_entries; 43 44 u64 gart_base; 45 u64 gart_size; 46 47 int io_page_size; 48 int io_pages_per_kpage; 49 } parisc_agp_info; 50 51 static struct gatt_mask parisc_agp_masks[] = 52 { 53 { 54 .mask = SBA_PDIR_VALID_BIT, 55 .type = 0 56 } 57 }; 58 59 static struct aper_size_info_fixed parisc_agp_sizes[] = 60 { 61 {0, 0, 0}, /* filled in by parisc_agp_fetch_size() */ 62 }; 63 64 static int 65 parisc_agp_fetch_size(void) 66 { 67 int size; 68 69 size = parisc_agp_info.gart_size / MB(1); 70 parisc_agp_sizes[0].size = size; 71 agp_bridge->current_size = (void *) &parisc_agp_sizes[0]; 72 73 return size; 74 } 75 76 static int 77 parisc_agp_configure(void) 78 { 79 struct _parisc_agp_info *info = &parisc_agp_info; 80 81 agp_bridge->gart_bus_addr = info->gart_base; 82 agp_bridge->capndx = info->lba_cap_offset; 83 agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS); 84 85 return 0; 86 } 87 88 static void 89 parisc_agp_tlbflush(struct agp_memory *mem) 90 { 91 struct _parisc_agp_info *info = &parisc_agp_info; 92 93 /* force fdc ops to be visible to IOMMU */ 94 asm_io_sync(); 95 96 writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM); 97 readq(info->ioc_regs+IOC_PCOM); /* flush */ 98 } 99 100 static int 101 parisc_agp_create_gatt_table(struct agp_bridge_data *bridge) 102 { 103 struct _parisc_agp_info *info = &parisc_agp_info; 104 int i; 105 106 for (i = 0; i < info->gatt_entries; i++) { 107 info->gatt[i] = (unsigned long)agp_bridge->scratch_page; 108 } 109 110 return 0; 111 } 112 113 static int 114 parisc_agp_free_gatt_table(struct agp_bridge_data *bridge) 115 { 116 struct _parisc_agp_info *info = &parisc_agp_info; 117 118 info->gatt[0] = SBA_AGPGART_COOKIE; 119 120 return 0; 121 } 122 123 static int 124 parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 125 { 126 struct _parisc_agp_info *info = &parisc_agp_info; 127 int i, k; 128 off_t j, io_pg_start; 129 int io_pg_count; 130 131 if (type != mem->type || 132 agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { 133 return -EINVAL; 134 } 135 136 io_pg_start = info->io_pages_per_kpage * pg_start; 137 io_pg_count = info->io_pages_per_kpage * mem->page_count; 138 if ((io_pg_start + io_pg_count) > info->gatt_entries) { 139 return -EINVAL; 140 } 141 142 j = io_pg_start; 143 while (j < (io_pg_start + io_pg_count)) { 144 if (info->gatt[j]) 145 return -EBUSY; 146 j++; 147 } 148 149 if (!mem->is_flushed) { 150 global_cache_flush(); 151 mem->is_flushed = true; 152 } 153 154 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 155 unsigned long paddr; 156 157 paddr = page_to_phys(mem->pages[i]); 158 for (k = 0; 159 k < info->io_pages_per_kpage; 160 k++, j++, paddr += info->io_page_size) { 161 info->gatt[j] = 162 parisc_agp_mask_memory(agp_bridge, 163 paddr, type); 164 asm_io_fdc(&info->gatt[j]); 165 } 166 } 167 168 agp_bridge->driver->tlb_flush(mem); 169 170 return 0; 171 } 172 173 static int 174 parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 175 { 176 struct _parisc_agp_info *info = &parisc_agp_info; 177 int i, io_pg_start, io_pg_count; 178 179 if (type != mem->type || 180 agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { 181 return -EINVAL; 182 } 183 184 io_pg_start = info->io_pages_per_kpage * pg_start; 185 io_pg_count = info->io_pages_per_kpage * mem->page_count; 186 for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { 187 info->gatt[i] = agp_bridge->scratch_page; 188 } 189 190 agp_bridge->driver->tlb_flush(mem); 191 return 0; 192 } 193 194 static unsigned long 195 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, 196 int type) 197 { 198 unsigned ci; /* coherent index */ 199 dma_addr_t pa; 200 201 pa = addr & IOVP_MASK; 202 asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(pa))); 203 204 pa |= (ci >> PAGE_SHIFT) & 0xff;/* move CI (8 bits) into lowest byte */ 205 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 206 207 return cpu_to_le64(pa); 208 } 209 210 static void 211 parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode) 212 { 213 struct _parisc_agp_info *info = &parisc_agp_info; 214 u32 command; 215 216 command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS); 217 218 command = agp_collect_device_status(bridge, mode, command); 219 command |= 0x00000100; 220 221 writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND); 222 223 agp_device_command(command, (mode & AGP8X_MODE) != 0); 224 } 225 226 static const struct agp_bridge_driver parisc_agp_driver = { 227 .owner = THIS_MODULE, 228 .size_type = FIXED_APER_SIZE, 229 .configure = parisc_agp_configure, 230 .fetch_size = parisc_agp_fetch_size, 231 .tlb_flush = parisc_agp_tlbflush, 232 .mask_memory = parisc_agp_mask_memory, 233 .masks = parisc_agp_masks, 234 .agp_enable = parisc_agp_enable, 235 .cache_flush = global_cache_flush, 236 .create_gatt_table = parisc_agp_create_gatt_table, 237 .free_gatt_table = parisc_agp_free_gatt_table, 238 .insert_memory = parisc_agp_insert_memory, 239 .remove_memory = parisc_agp_remove_memory, 240 .alloc_by_type = agp_generic_alloc_by_type, 241 .free_by_type = agp_generic_free_by_type, 242 .agp_alloc_page = agp_generic_alloc_page, 243 .agp_alloc_pages = agp_generic_alloc_pages, 244 .agp_destroy_page = agp_generic_destroy_page, 245 .agp_destroy_pages = agp_generic_destroy_pages, 246 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 247 .cant_use_aperture = true, 248 }; 249 250 static int __init 251 agp_ioc_init(void __iomem *ioc_regs) 252 { 253 struct _parisc_agp_info *info = &parisc_agp_info; 254 u64 iova_base, *io_pdir, io_tlb_ps; 255 int io_tlb_shift; 256 257 printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n"); 258 259 info->ioc_regs = ioc_regs; 260 261 io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG); 262 switch (io_tlb_ps) { 263 case 0: io_tlb_shift = 12; break; 264 case 1: io_tlb_shift = 13; break; 265 case 2: io_tlb_shift = 14; break; 266 case 3: io_tlb_shift = 16; break; 267 default: 268 printk(KERN_ERR DRVPFX "Invalid IOTLB page size " 269 "configuration 0x%llx\n", io_tlb_ps); 270 info->gatt = NULL; 271 info->gatt_entries = 0; 272 return -ENODEV; 273 } 274 info->io_page_size = 1 << io_tlb_shift; 275 info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size; 276 277 iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1; 278 info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE; 279 280 info->gart_size = PLUTO_GART_SIZE; 281 info->gatt_entries = info->gart_size / info->io_page_size; 282 283 io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE)); 284 info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT]; 285 286 if (info->gatt[0] != SBA_AGPGART_COOKIE) { 287 info->gatt = NULL; 288 info->gatt_entries = 0; 289 printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; " 290 "GART disabled\n"); 291 return -ENODEV; 292 } 293 294 return 0; 295 } 296 297 static int __init 298 lba_find_capability(int cap) 299 { 300 struct _parisc_agp_info *info = &parisc_agp_info; 301 u16 status; 302 u8 pos, id; 303 int ttl = 48; 304 305 status = readw(info->lba_regs + PCI_STATUS); 306 if (!(status & PCI_STATUS_CAP_LIST)) 307 return 0; 308 pos = readb(info->lba_regs + PCI_CAPABILITY_LIST); 309 while (ttl-- && pos >= 0x40) { 310 pos &= ~3; 311 id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID); 312 if (id == 0xff) 313 break; 314 if (id == cap) 315 return pos; 316 pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT); 317 } 318 return 0; 319 } 320 321 static int __init 322 agp_lba_init(void __iomem *lba_hpa) 323 { 324 struct _parisc_agp_info *info = &parisc_agp_info; 325 int cap; 326 327 info->lba_regs = lba_hpa; 328 info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP); 329 330 cap = readl(lba_hpa + info->lba_cap_offset) & 0xff; 331 if (cap != PCI_CAP_ID_AGP) { 332 printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n", 333 cap, info->lba_cap_offset); 334 return -ENODEV; 335 } 336 337 return 0; 338 } 339 340 static int __init 341 parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa) 342 { 343 struct pci_dev *fake_bridge_dev = NULL; 344 struct agp_bridge_data *bridge; 345 int error = 0; 346 347 fake_bridge_dev = pci_alloc_dev(NULL); 348 if (!fake_bridge_dev) { 349 error = -ENOMEM; 350 goto fail; 351 } 352 353 error = agp_ioc_init(ioc_hpa); 354 if (error) 355 goto fail; 356 357 error = agp_lba_init(lba_hpa); 358 if (error) 359 goto fail; 360 361 bridge = agp_alloc_bridge(); 362 if (!bridge) { 363 error = -ENOMEM; 364 goto fail; 365 } 366 bridge->driver = &parisc_agp_driver; 367 368 fake_bridge_dev->vendor = PCI_VENDOR_ID_HP; 369 fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA; 370 bridge->dev = fake_bridge_dev; 371 372 error = agp_add_bridge(bridge); 373 if (error) 374 goto fail; 375 return 0; 376 377 fail: 378 kfree(fake_bridge_dev); 379 return error; 380 } 381 382 static int __init 383 find_quicksilver(struct device *dev, void *data) 384 { 385 struct parisc_device **lba = data; 386 struct parisc_device *padev = to_parisc_device(dev); 387 388 if (IS_QUICKSILVER(padev)) 389 *lba = padev; 390 391 return 0; 392 } 393 394 static int __init 395 parisc_agp_init(void) 396 { 397 extern struct sba_device *sba_list; 398 399 int err = -1; 400 struct parisc_device *sba = NULL, *lba = NULL; 401 struct lba_device *lbadev = NULL; 402 403 if (!sba_list) 404 goto out; 405 406 /* Find our parent Pluto */ 407 sba = sba_list->dev; 408 if (!IS_PLUTO(sba)) { 409 printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n"); 410 goto out; 411 } 412 413 /* Now search our Pluto for our precious AGP device... */ 414 device_for_each_child(&sba->dev, &lba, find_quicksilver); 415 416 if (!lba) { 417 printk(KERN_INFO DRVPFX "No AGP devices found.\n"); 418 goto out; 419 } 420 421 lbadev = parisc_get_drvdata(lba); 422 423 /* w00t, let's go find our cookies... */ 424 parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr); 425 426 return 0; 427 428 out: 429 return err; 430 } 431 432 module_init(parisc_agp_init); 433 434 MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>"); 435 MODULE_LICENSE("GPL"); 436