1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Setup routines for AGP 3.5 compliant bridges. 4 */ 5 6 #include <linux/list.h> 7 #include <linux/pci.h> 8 #include <linux/agp_backend.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 12 #include "agp.h" 13 14 /* Generic AGP 3.5 enabling routines */ 15 16 struct agp_3_5_dev { 17 struct list_head list; 18 u8 capndx; 19 u32 maxbw; 20 struct pci_dev *dev; 21 }; 22 23 static void agp_3_5_dev_list_insert(struct list_head *head, struct list_head *new) 24 { 25 struct agp_3_5_dev *cur, *n = list_entry(new, struct agp_3_5_dev, list); 26 struct list_head *pos; 27 28 list_for_each(pos, head) { 29 cur = list_entry(pos, struct agp_3_5_dev, list); 30 if (cur->maxbw > n->maxbw) 31 break; 32 } 33 list_add_tail(new, pos); 34 } 35 36 static void agp_3_5_dev_list_sort(struct agp_3_5_dev *list, unsigned int ndevs) 37 { 38 struct agp_3_5_dev *cur; 39 struct pci_dev *dev; 40 struct list_head *pos, *tmp, *head = &list->list, *start = head->next; 41 u32 nistat; 42 43 INIT_LIST_HEAD(head); 44 45 for (pos=start; pos!=head; ) { 46 cur = list_entry(pos, struct agp_3_5_dev, list); 47 dev = cur->dev; 48 49 pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &nistat); 50 cur->maxbw = (nistat >> 16) & 0xff; 51 52 tmp = pos; 53 pos = pos->next; 54 agp_3_5_dev_list_insert(head, tmp); 55 } 56 } 57 58 /* 59 * Initialize all isochronous transfer parameters for an AGP 3.0 60 * node (i.e. a host bridge in combination with the adapters 61 * lying behind it...) 62 */ 63 64 static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, 65 struct agp_3_5_dev *dev_list, unsigned int ndevs) 66 { 67 /* 68 * Convenience structure to make the calculations clearer 69 * here. The field names come straight from the AGP 3.0 spec. 70 */ 71 struct isoch_data { 72 u32 maxbw; 73 u32 n; 74 u32 y; 75 u32 l; 76 u32 rq; 77 struct agp_3_5_dev *dev; 78 }; 79 80 struct pci_dev *td = bridge->dev, *dev; 81 struct list_head *head = &dev_list->list, *pos; 82 struct agp_3_5_dev *cur; 83 struct isoch_data *master, target; 84 unsigned int cdev = 0; 85 u32 mnistat, tnistat, tstatus, mcmd; 86 u16 tnicmd, mnicmd; 87 u8 mcapndx; 88 u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; 89 u32 step, rem, rem_isoch, rem_async; 90 int ret = 0; 91 92 /* 93 * We'll work with an array of isoch_data's (one for each 94 * device in dev_list) throughout this function. 95 */ 96 if ((master = kmalloc(ndevs * sizeof(*master), GFP_KERNEL)) == NULL) { 97 ret = -ENOMEM; 98 goto get_out; 99 } 100 101 /* 102 * Sort the device list by maxbw. We need to do this because the 103 * spec suggests that the devices with the smallest requirements 104 * have their resources allocated first, with all remaining resources 105 * falling to the device with the largest requirement. 106 * 107 * We don't exactly do this, we divide target resources by ndevs 108 * and split them amongst the AGP 3.0 devices. The remainder of such 109 * division operations are dropped on the last device, sort of like 110 * the spec mentions it should be done. 111 * 112 * We can't do this sort when we initially construct the dev_list 113 * because we don't know until this function whether isochronous 114 * transfers are enabled and consequently whether maxbw will mean 115 * anything. 116 */ 117 agp_3_5_dev_list_sort(dev_list, ndevs); 118 119 pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); 120 pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); 121 122 /* Extract power-on defaults from the target */ 123 target.maxbw = (tnistat >> 16) & 0xff; 124 target.n = (tnistat >> 8) & 0xff; 125 target.y = (tnistat >> 6) & 0x3; 126 target.l = (tnistat >> 3) & 0x7; 127 target.rq = (tstatus >> 24) & 0xff; 128 129 y_max = target.y; 130 131 /* 132 * Extract power-on defaults for each device in dev_list. Along 133 * the way, calculate the total isochronous bandwidth required 134 * by these devices and the largest requested payload size. 135 */ 136 list_for_each(pos, head) { 137 cur = list_entry(pos, struct agp_3_5_dev, list); 138 dev = cur->dev; 139 140 mcapndx = cur->capndx; 141 142 pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat); 143 144 master[cdev].maxbw = (mnistat >> 16) & 0xff; 145 master[cdev].n = (mnistat >> 8) & 0xff; 146 master[cdev].y = (mnistat >> 6) & 0x3; 147 master[cdev].dev = cur; 148 149 tot_bw += master[cdev].maxbw; 150 y_max = max(y_max, master[cdev].y); 151 152 cdev++; 153 } 154 155 /* Check if this configuration has any chance of working */ 156 if (tot_bw > target.maxbw) { 157 dev_err(&td->dev, "isochronous bandwidth required " 158 "by AGP 3.0 devices exceeds that which is supported by " 159 "the AGP 3.0 bridge!\n"); 160 ret = -ENODEV; 161 goto free_and_exit; 162 } 163 164 target.y = y_max; 165 166 /* 167 * Write the calculated payload size into the target's NICMD 168 * register. Doing this directly effects the ISOCH_N value 169 * in the target's NISTAT register, so we need to do this now 170 * to get an accurate value for ISOCH_N later. 171 */ 172 pci_read_config_word(td, bridge->capndx+AGPNICMD, &tnicmd); 173 tnicmd &= ~(0x3 << 6); 174 tnicmd |= target.y << 6; 175 pci_write_config_word(td, bridge->capndx+AGPNICMD, tnicmd); 176 177 /* Reread the target's ISOCH_N */ 178 pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); 179 target.n = (tnistat >> 8) & 0xff; 180 181 /* Calculate the minimum ISOCH_N needed by each master */ 182 for (cdev=0; cdev<ndevs; cdev++) { 183 master[cdev].y = target.y; 184 master[cdev].n = master[cdev].maxbw / (master[cdev].y + 1); 185 186 tot_n += master[cdev].n; 187 } 188 189 /* Exit if the minimal ISOCH_N allocation among the masters is more 190 * than the target can handle. */ 191 if (tot_n > target.n) { 192 dev_err(&td->dev, "number of isochronous " 193 "transactions per period required by AGP 3.0 devices " 194 "exceeds that which is supported by the AGP 3.0 " 195 "bridge!\n"); 196 ret = -ENODEV; 197 goto free_and_exit; 198 } 199 200 /* Calculate left over ISOCH_N capability in the target. We'll give 201 * this to the hungriest device (as per the spec) */ 202 rem = target.n - tot_n; 203 204 /* 205 * Calculate the minimum isochronous RQ depth needed by each master. 206 * Along the way, distribute the extra ISOCH_N capability calculated 207 * above. 208 */ 209 for (cdev=0; cdev<ndevs; cdev++) { 210 /* 211 * This is a little subtle. If ISOCH_Y > 64B, then ISOCH_Y 212 * byte isochronous writes will be broken into 64B pieces. 213 * This means we need to budget more RQ depth to account for 214 * these kind of writes (each isochronous write is actually 215 * many writes on the AGP bus). 216 */ 217 master[cdev].rq = master[cdev].n; 218 if (master[cdev].y > 0x1) 219 master[cdev].rq *= (1 << (master[cdev].y - 1)); 220 221 tot_rq += master[cdev].rq; 222 } 223 master[ndevs-1].n += rem; 224 225 /* Figure the number of isochronous and asynchronous RQ slots the 226 * target is providing. */ 227 rq_isoch = (target.y > 0x1) ? target.n * (1 << (target.y - 1)) : target.n; 228 rq_async = target.rq - rq_isoch; 229 230 /* Exit if the minimal RQ needs of the masters exceeds what the target 231 * can provide. */ 232 if (tot_rq > rq_isoch) { 233 dev_err(&td->dev, "number of request queue slots " 234 "required by the isochronous bandwidth requested by " 235 "AGP 3.0 devices exceeds the number provided by the " 236 "AGP 3.0 bridge!\n"); 237 ret = -ENODEV; 238 goto free_and_exit; 239 } 240 241 /* Calculate asynchronous RQ capability in the target (per master) as 242 * well as the total number of leftover isochronous RQ slots. */ 243 step = rq_async / ndevs; 244 rem_async = step + (rq_async % ndevs); 245 rem_isoch = rq_isoch - tot_rq; 246 247 /* Distribute the extra RQ slots calculated above and write our 248 * isochronous settings out to the actual devices. */ 249 for (cdev=0; cdev<ndevs; cdev++) { 250 cur = master[cdev].dev; 251 dev = cur->dev; 252 253 mcapndx = cur->capndx; 254 255 master[cdev].rq += (cdev == ndevs - 1) 256 ? (rem_async + rem_isoch) : step; 257 258 pci_read_config_word(dev, cur->capndx+AGPNICMD, &mnicmd); 259 pci_read_config_dword(dev, cur->capndx+AGPCMD, &mcmd); 260 261 mnicmd &= ~(0xff << 8); 262 mnicmd &= ~(0x3 << 6); 263 mcmd &= ~(0xff << 24); 264 265 mnicmd |= master[cdev].n << 8; 266 mnicmd |= master[cdev].y << 6; 267 mcmd |= master[cdev].rq << 24; 268 269 pci_write_config_dword(dev, cur->capndx+AGPCMD, mcmd); 270 pci_write_config_word(dev, cur->capndx+AGPNICMD, mnicmd); 271 } 272 273 free_and_exit: 274 kfree(master); 275 276 get_out: 277 return ret; 278 } 279 280 /* 281 * This function basically allocates request queue slots among the 282 * AGP 3.0 systems in nonisochronous nodes. The algorithm is 283 * pretty stupid, divide the total number of RQ slots provided by the 284 * target by ndevs. Distribute this many slots to each AGP 3.0 device, 285 * giving any left over slots to the last device in dev_list. 286 */ 287 static void agp_3_5_nonisochronous_node_enable(struct agp_bridge_data *bridge, 288 struct agp_3_5_dev *dev_list, unsigned int ndevs) 289 { 290 struct agp_3_5_dev *cur; 291 struct list_head *head = &dev_list->list, *pos; 292 u32 tstatus, mcmd; 293 u32 trq, mrq, rem; 294 unsigned int cdev = 0; 295 296 pci_read_config_dword(bridge->dev, bridge->capndx+AGPSTAT, &tstatus); 297 298 trq = (tstatus >> 24) & 0xff; 299 mrq = trq / ndevs; 300 301 rem = mrq + (trq % ndevs); 302 303 for (pos=head->next; cdev<ndevs; cdev++, pos=pos->next) { 304 cur = list_entry(pos, struct agp_3_5_dev, list); 305 306 pci_read_config_dword(cur->dev, cur->capndx+AGPCMD, &mcmd); 307 mcmd &= ~(0xff << 24); 308 mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24; 309 pci_write_config_dword(cur->dev, cur->capndx+AGPCMD, mcmd); 310 } 311 } 312 313 /* 314 * Fully configure and enable an AGP 3.0 host bridge and all the devices 315 * lying behind it. 316 */ 317 int agp_3_5_enable(struct agp_bridge_data *bridge) 318 { 319 struct pci_dev *td = bridge->dev, *dev = NULL; 320 u8 mcapndx; 321 u32 isoch, arqsz; 322 u32 tstatus, mstatus, ncapid; 323 u32 mmajor; 324 u16 mpstat; 325 struct agp_3_5_dev *dev_list, *cur; 326 struct list_head *head, *pos; 327 unsigned int ndevs = 0; 328 int ret = 0; 329 330 /* Extract some power-on defaults from the target */ 331 pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); 332 isoch = (tstatus >> 17) & 0x1; 333 if (isoch == 0) /* isoch xfers not available, bail out. */ 334 return -ENODEV; 335 336 arqsz = (tstatus >> 13) & 0x7; 337 338 /* 339 * Allocate a head for our AGP 3.5 device list 340 * (multiple AGP v3 devices are allowed behind a single bridge). 341 */ 342 if ((dev_list = kmalloc(sizeof(*dev_list), GFP_KERNEL)) == NULL) { 343 ret = -ENOMEM; 344 goto get_out; 345 } 346 head = &dev_list->list; 347 INIT_LIST_HEAD(head); 348 349 /* Find all AGP devices, and add them to dev_list. */ 350 for_each_pci_dev(dev) { 351 mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP); 352 if (mcapndx == 0) 353 continue; 354 355 switch ((dev->class >>8) & 0xff00) { 356 case 0x0600: /* Bridge */ 357 /* Skip bridges. We should call this function for each one. */ 358 continue; 359 360 case 0x0001: /* Unclassified device */ 361 /* Don't know what this is, but log it for investigation. */ 362 if (mcapndx != 0) { 363 dev_info(&td->dev, "wacky, found unclassified AGP device %s [%04x/%04x]\n", 364 pci_name(dev), 365 dev->vendor, dev->device); 366 } 367 continue; 368 369 case 0x0300: /* Display controller */ 370 case 0x0400: /* Multimedia controller */ 371 if ((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) { 372 ret = -ENOMEM; 373 goto free_and_exit; 374 } 375 cur->dev = dev; 376 377 pos = &cur->list; 378 list_add(pos, head); 379 ndevs++; 380 continue; 381 382 default: 383 continue; 384 } 385 } 386 387 /* 388 * Take an initial pass through the devices lying behind our host 389 * bridge. Make sure each one is actually an AGP 3.0 device, otherwise 390 * exit with an error message. Along the way store the AGP 3.0 391 * cap_ptr for each device 392 */ 393 list_for_each(pos, head) { 394 cur = list_entry(pos, struct agp_3_5_dev, list); 395 dev = cur->dev; 396 397 pci_read_config_word(dev, PCI_STATUS, &mpstat); 398 if ((mpstat & PCI_STATUS_CAP_LIST) == 0) 399 continue; 400 401 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &mcapndx); 402 if (mcapndx != 0) { 403 do { 404 pci_read_config_dword(dev, mcapndx, &ncapid); 405 if ((ncapid & 0xff) != 2) 406 mcapndx = (ncapid >> 8) & 0xff; 407 } 408 while (((ncapid & 0xff) != 2) && (mcapndx != 0)); 409 } 410 411 if (mcapndx == 0) { 412 dev_err(&td->dev, "woah! Non-AGP device %s on " 413 "secondary bus of AGP 3.5 bridge!\n", 414 pci_name(dev)); 415 ret = -ENODEV; 416 goto free_and_exit; 417 } 418 419 mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf; 420 if (mmajor < 3) { 421 dev_err(&td->dev, "woah! AGP 2.0 device %s on " 422 "secondary bus of AGP 3.5 bridge operating " 423 "with AGP 3.0 electricals!\n", pci_name(dev)); 424 ret = -ENODEV; 425 goto free_and_exit; 426 } 427 428 cur->capndx = mcapndx; 429 430 pci_read_config_dword(dev, cur->capndx+AGPSTAT, &mstatus); 431 432 if (((mstatus >> 3) & 0x1) == 0) { 433 dev_err(&td->dev, "woah! AGP 3.x device %s not " 434 "operating in AGP 3.x mode on secondary bus " 435 "of AGP 3.5 bridge operating with AGP 3.0 " 436 "electricals!\n", pci_name(dev)); 437 ret = -ENODEV; 438 goto free_and_exit; 439 } 440 } 441 442 /* 443 * Call functions to divide target resources amongst the AGP 3.0 444 * masters. This process is dramatically different depending on 445 * whether isochronous transfers are supported. 446 */ 447 if (isoch) { 448 ret = agp_3_5_isochronous_node_enable(bridge, dev_list, ndevs); 449 if (ret) { 450 dev_info(&td->dev, "something bad happened setting " 451 "up isochronous xfers; falling back to " 452 "non-isochronous xfer mode\n"); 453 } else { 454 goto free_and_exit; 455 } 456 } 457 agp_3_5_nonisochronous_node_enable(bridge, dev_list, ndevs); 458 459 free_and_exit: 460 /* Be sure to free the dev_list */ 461 for (pos=head->next; pos!=head; ) { 462 cur = list_entry(pos, struct agp_3_5_dev, list); 463 464 pos = pos->next; 465 kfree(cur); 466 } 467 kfree(dev_list); 468 469 get_out: 470 return ret; 471 } 472