1 /* 2 * Intel GTT (Graphics Translation Table) routines 3 * 4 * Caveat: This driver implements the linux agp interface, but this is far from 5 * a agp driver! GTT support ended up here for purely historical reasons: The 6 * old userspace intel graphics drivers needed an interface to map memory into 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 9 * avoid having to create a new api. 10 * 11 * With gem this does not make much sense anymore, just needlessly complicates 12 * the code. But as long as the old graphics stack is still support, it's stuck 13 * here. 14 * 15 * /fairy-tale-mode off 16 */ 17 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/kernel.h> 21 #include <linux/pagemap.h> 22 #include <linux/agp_backend.h> 23 #include <linux/delay.h> 24 #include <asm/smp.h> 25 #include "agp.h" 26 #include "intel-agp.h" 27 #include <drm/intel-gtt.h> 28 29 /* 30 * If we have Intel graphics, we're not going to have anything other than 31 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 32 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 33 * Only newer chipsets need to bother with this, of course. 34 */ 35 #ifdef CONFIG_INTEL_IOMMU 36 #define USE_PCI_DMA_API 1 37 #else 38 #define USE_PCI_DMA_API 0 39 #endif 40 41 struct intel_gtt_driver { 42 unsigned int gen : 8; 43 unsigned int is_g33 : 1; 44 unsigned int is_pineview : 1; 45 unsigned int is_ironlake : 1; 46 unsigned int has_pgtbl_enable : 1; 47 unsigned int dma_mask_size : 8; 48 /* Chipset specific GTT setup */ 49 int (*setup)(void); 50 /* This should undo anything done in ->setup() save the unmapping 51 * of the mmio register file, that's done in the generic code. */ 52 void (*cleanup)(void); 53 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 54 /* Flags is a more or less chipset specific opaque value. 55 * For chipsets that need to support old ums (non-gem) code, this 56 * needs to be identical to the various supported agp memory types! */ 57 bool (*check_flags)(unsigned int flags); 58 void (*chipset_flush)(void); 59 }; 60 61 static struct _intel_private { 62 const struct intel_gtt_driver *driver; 63 struct pci_dev *pcidev; /* device one */ 64 struct pci_dev *bridge_dev; 65 u8 __iomem *registers; 66 phys_addr_t gtt_phys_addr; 67 u32 PGETBL_save; 68 u32 __iomem *gtt; /* I915G */ 69 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 70 int num_dcache_entries; 71 void __iomem *i9xx_flush_page; 72 char *i81x_gtt_table; 73 struct resource ifp_resource; 74 int resource_valid; 75 struct page *scratch_page; 76 phys_addr_t scratch_page_dma; 77 int refcount; 78 /* Whether i915 needs to use the dmar apis or not. */ 79 unsigned int needs_dmar : 1; 80 phys_addr_t gma_bus_addr; 81 /* Size of memory reserved for graphics by the BIOS */ 82 unsigned int stolen_size; 83 /* Total number of gtt entries. */ 84 unsigned int gtt_total_entries; 85 /* Part of the gtt that is mappable by the cpu, for those chips where 86 * this is not the full gtt. */ 87 unsigned int gtt_mappable_entries; 88 } intel_private; 89 90 #define INTEL_GTT_GEN intel_private.driver->gen 91 #define IS_G33 intel_private.driver->is_g33 92 #define IS_PINEVIEW intel_private.driver->is_pineview 93 #define IS_IRONLAKE intel_private.driver->is_ironlake 94 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 95 96 #if IS_ENABLED(CONFIG_AGP_INTEL) 97 static int intel_gtt_map_memory(struct page **pages, 98 unsigned int num_entries, 99 struct sg_table *st) 100 { 101 struct scatterlist *sg; 102 int i; 103 104 DBG("try mapping %lu pages\n", (unsigned long)num_entries); 105 106 if (sg_alloc_table(st, num_entries, GFP_KERNEL)) 107 goto err; 108 109 for_each_sg(st->sgl, sg, num_entries, i) 110 sg_set_page(sg, pages[i], PAGE_SIZE, 0); 111 112 if (!pci_map_sg(intel_private.pcidev, 113 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) 114 goto err; 115 116 return 0; 117 118 err: 119 sg_free_table(st); 120 return -ENOMEM; 121 } 122 123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 124 { 125 struct sg_table st; 126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 127 128 pci_unmap_sg(intel_private.pcidev, sg_list, 129 num_sg, PCI_DMA_BIDIRECTIONAL); 130 131 st.sgl = sg_list; 132 st.orig_nents = st.nents = num_sg; 133 134 sg_free_table(&st); 135 } 136 137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 138 { 139 return; 140 } 141 142 /* Exists to support ARGB cursors */ 143 static struct page *i8xx_alloc_pages(void) 144 { 145 struct page *page; 146 147 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 148 if (page == NULL) 149 return NULL; 150 151 if (set_pages_uc(page, 4) < 0) { 152 set_pages_wb(page, 4); 153 __free_pages(page, 2); 154 return NULL; 155 } 156 atomic_inc(&agp_bridge->current_memory_agp); 157 return page; 158 } 159 160 static void i8xx_destroy_pages(struct page *page) 161 { 162 if (page == NULL) 163 return; 164 165 set_pages_wb(page, 4); 166 __free_pages(page, 2); 167 atomic_dec(&agp_bridge->current_memory_agp); 168 } 169 #endif 170 171 #define I810_GTT_ORDER 4 172 static int i810_setup(void) 173 { 174 phys_addr_t reg_addr; 175 char *gtt_table; 176 177 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 178 gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 179 if (gtt_table == NULL) 180 return -ENOMEM; 181 intel_private.i81x_gtt_table = gtt_table; 182 183 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 184 185 intel_private.registers = ioremap(reg_addr, KB(64)); 186 if (!intel_private.registers) 187 return -ENOMEM; 188 189 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 190 intel_private.registers+I810_PGETBL_CTL); 191 192 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 193 194 if ((readl(intel_private.registers+I810_DRAM_CTL) 195 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 196 dev_info(&intel_private.pcidev->dev, 197 "detected 4MB dedicated video ram\n"); 198 intel_private.num_dcache_entries = 1024; 199 } 200 201 return 0; 202 } 203 204 static void i810_cleanup(void) 205 { 206 writel(0, intel_private.registers+I810_PGETBL_CTL); 207 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 208 } 209 210 #if IS_ENABLED(CONFIG_AGP_INTEL) 211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 212 int type) 213 { 214 int i; 215 216 if ((pg_start + mem->page_count) 217 > intel_private.num_dcache_entries) 218 return -EINVAL; 219 220 if (!mem->is_flushed) 221 global_cache_flush(); 222 223 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 224 dma_addr_t addr = i << PAGE_SHIFT; 225 intel_private.driver->write_entry(addr, 226 i, type); 227 } 228 wmb(); 229 230 return 0; 231 } 232 233 /* 234 * The i810/i830 requires a physical address to program its mouse 235 * pointer into hardware. 236 * However the Xserver still writes to it through the agp aperture. 237 */ 238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 239 { 240 struct agp_memory *new; 241 struct page *page; 242 243 switch (pg_count) { 244 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 245 break; 246 case 4: 247 /* kludge to get 4 physical pages for ARGB cursor */ 248 page = i8xx_alloc_pages(); 249 break; 250 default: 251 return NULL; 252 } 253 254 if (page == NULL) 255 return NULL; 256 257 new = agp_create_memory(pg_count); 258 if (new == NULL) 259 return NULL; 260 261 new->pages[0] = page; 262 if (pg_count == 4) { 263 /* kludge to get 4 physical pages for ARGB cursor */ 264 new->pages[1] = new->pages[0] + 1; 265 new->pages[2] = new->pages[1] + 1; 266 new->pages[3] = new->pages[2] + 1; 267 } 268 new->page_count = pg_count; 269 new->num_scratch_pages = pg_count; 270 new->type = AGP_PHYS_MEMORY; 271 new->physical = page_to_phys(new->pages[0]); 272 return new; 273 } 274 275 static void intel_i810_free_by_type(struct agp_memory *curr) 276 { 277 agp_free_key(curr->key); 278 if (curr->type == AGP_PHYS_MEMORY) { 279 if (curr->page_count == 4) 280 i8xx_destroy_pages(curr->pages[0]); 281 else { 282 agp_bridge->driver->agp_destroy_page(curr->pages[0], 283 AGP_PAGE_DESTROY_UNMAP); 284 agp_bridge->driver->agp_destroy_page(curr->pages[0], 285 AGP_PAGE_DESTROY_FREE); 286 } 287 agp_free_page_array(curr); 288 } 289 kfree(curr); 290 } 291 #endif 292 293 static int intel_gtt_setup_scratch_page(void) 294 { 295 struct page *page; 296 dma_addr_t dma_addr; 297 298 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 299 if (page == NULL) 300 return -ENOMEM; 301 set_pages_uc(page, 1); 302 303 if (intel_private.needs_dmar) { 304 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 305 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 306 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 307 return -EINVAL; 308 309 intel_private.scratch_page_dma = dma_addr; 310 } else 311 intel_private.scratch_page_dma = page_to_phys(page); 312 313 intel_private.scratch_page = page; 314 315 return 0; 316 } 317 318 static void i810_write_entry(dma_addr_t addr, unsigned int entry, 319 unsigned int flags) 320 { 321 u32 pte_flags = I810_PTE_VALID; 322 323 switch (flags) { 324 case AGP_DCACHE_MEMORY: 325 pte_flags |= I810_PTE_LOCAL; 326 break; 327 case AGP_USER_CACHED_MEMORY: 328 pte_flags |= I830_PTE_SYSTEM_CACHED; 329 break; 330 } 331 332 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); 333 } 334 335 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 336 {32, 8192, 3}, 337 {64, 16384, 4}, 338 {128, 32768, 5}, 339 {256, 65536, 6}, 340 {512, 131072, 7}, 341 }; 342 343 static unsigned int intel_gtt_stolen_size(void) 344 { 345 u16 gmch_ctrl; 346 u8 rdct; 347 int local = 0; 348 static const int ddt[4] = { 0, 16, 32, 64 }; 349 unsigned int stolen_size = 0; 350 351 if (INTEL_GTT_GEN == 1) 352 return 0; /* no stolen mem on i81x */ 353 354 pci_read_config_word(intel_private.bridge_dev, 355 I830_GMCH_CTRL, &gmch_ctrl); 356 357 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 358 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 359 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 360 case I830_GMCH_GMS_STOLEN_512: 361 stolen_size = KB(512); 362 break; 363 case I830_GMCH_GMS_STOLEN_1024: 364 stolen_size = MB(1); 365 break; 366 case I830_GMCH_GMS_STOLEN_8192: 367 stolen_size = MB(8); 368 break; 369 case I830_GMCH_GMS_LOCAL: 370 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 371 stolen_size = (I830_RDRAM_ND(rdct) + 1) * 372 MB(ddt[I830_RDRAM_DDT(rdct)]); 373 local = 1; 374 break; 375 default: 376 stolen_size = 0; 377 break; 378 } 379 } else { 380 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 381 case I855_GMCH_GMS_STOLEN_1M: 382 stolen_size = MB(1); 383 break; 384 case I855_GMCH_GMS_STOLEN_4M: 385 stolen_size = MB(4); 386 break; 387 case I855_GMCH_GMS_STOLEN_8M: 388 stolen_size = MB(8); 389 break; 390 case I855_GMCH_GMS_STOLEN_16M: 391 stolen_size = MB(16); 392 break; 393 case I855_GMCH_GMS_STOLEN_32M: 394 stolen_size = MB(32); 395 break; 396 case I915_GMCH_GMS_STOLEN_48M: 397 stolen_size = MB(48); 398 break; 399 case I915_GMCH_GMS_STOLEN_64M: 400 stolen_size = MB(64); 401 break; 402 case G33_GMCH_GMS_STOLEN_128M: 403 stolen_size = MB(128); 404 break; 405 case G33_GMCH_GMS_STOLEN_256M: 406 stolen_size = MB(256); 407 break; 408 case INTEL_GMCH_GMS_STOLEN_96M: 409 stolen_size = MB(96); 410 break; 411 case INTEL_GMCH_GMS_STOLEN_160M: 412 stolen_size = MB(160); 413 break; 414 case INTEL_GMCH_GMS_STOLEN_224M: 415 stolen_size = MB(224); 416 break; 417 case INTEL_GMCH_GMS_STOLEN_352M: 418 stolen_size = MB(352); 419 break; 420 default: 421 stolen_size = 0; 422 break; 423 } 424 } 425 426 if (stolen_size > 0) { 427 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 428 stolen_size / KB(1), local ? "local" : "stolen"); 429 } else { 430 dev_info(&intel_private.bridge_dev->dev, 431 "no pre-allocated video memory detected\n"); 432 stolen_size = 0; 433 } 434 435 return stolen_size; 436 } 437 438 static void i965_adjust_pgetbl_size(unsigned int size_flag) 439 { 440 u32 pgetbl_ctl, pgetbl_ctl2; 441 442 /* ensure that ppgtt is disabled */ 443 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 444 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 445 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 446 447 /* write the new ggtt size */ 448 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 449 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 450 pgetbl_ctl |= size_flag; 451 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 452 } 453 454 static unsigned int i965_gtt_total_entries(void) 455 { 456 int size; 457 u32 pgetbl_ctl; 458 u16 gmch_ctl; 459 460 pci_read_config_word(intel_private.bridge_dev, 461 I830_GMCH_CTRL, &gmch_ctl); 462 463 if (INTEL_GTT_GEN == 5) { 464 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 465 case G4x_GMCH_SIZE_1M: 466 case G4x_GMCH_SIZE_VT_1M: 467 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 468 break; 469 case G4x_GMCH_SIZE_VT_1_5M: 470 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 471 break; 472 case G4x_GMCH_SIZE_2M: 473 case G4x_GMCH_SIZE_VT_2M: 474 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 475 break; 476 } 477 } 478 479 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 480 481 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 482 case I965_PGETBL_SIZE_128KB: 483 size = KB(128); 484 break; 485 case I965_PGETBL_SIZE_256KB: 486 size = KB(256); 487 break; 488 case I965_PGETBL_SIZE_512KB: 489 size = KB(512); 490 break; 491 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 492 case I965_PGETBL_SIZE_1MB: 493 size = KB(1024); 494 break; 495 case I965_PGETBL_SIZE_2MB: 496 size = KB(2048); 497 break; 498 case I965_PGETBL_SIZE_1_5MB: 499 size = KB(1024 + 512); 500 break; 501 default: 502 dev_info(&intel_private.pcidev->dev, 503 "unknown page table size, assuming 512KB\n"); 504 size = KB(512); 505 } 506 507 return size/4; 508 } 509 510 static unsigned int intel_gtt_total_entries(void) 511 { 512 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 513 return i965_gtt_total_entries(); 514 else { 515 /* On previous hardware, the GTT size was just what was 516 * required to map the aperture. 517 */ 518 return intel_private.gtt_mappable_entries; 519 } 520 } 521 522 static unsigned int intel_gtt_mappable_entries(void) 523 { 524 unsigned int aperture_size; 525 526 if (INTEL_GTT_GEN == 1) { 527 u32 smram_miscc; 528 529 pci_read_config_dword(intel_private.bridge_dev, 530 I810_SMRAM_MISCC, &smram_miscc); 531 532 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 533 == I810_GFX_MEM_WIN_32M) 534 aperture_size = MB(32); 535 else 536 aperture_size = MB(64); 537 } else if (INTEL_GTT_GEN == 2) { 538 u16 gmch_ctrl; 539 540 pci_read_config_word(intel_private.bridge_dev, 541 I830_GMCH_CTRL, &gmch_ctrl); 542 543 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 544 aperture_size = MB(64); 545 else 546 aperture_size = MB(128); 547 } else { 548 /* 9xx supports large sizes, just look at the length */ 549 aperture_size = pci_resource_len(intel_private.pcidev, 2); 550 } 551 552 return aperture_size >> PAGE_SHIFT; 553 } 554 555 static void intel_gtt_teardown_scratch_page(void) 556 { 557 set_pages_wb(intel_private.scratch_page, 1); 558 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 559 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 560 __free_page(intel_private.scratch_page); 561 } 562 563 static void intel_gtt_cleanup(void) 564 { 565 intel_private.driver->cleanup(); 566 567 iounmap(intel_private.gtt); 568 iounmap(intel_private.registers); 569 570 intel_gtt_teardown_scratch_page(); 571 } 572 573 /* Certain Gen5 chipsets require require idling the GPU before 574 * unmapping anything from the GTT when VT-d is enabled. 575 */ 576 static inline int needs_ilk_vtd_wa(void) 577 { 578 #ifdef CONFIG_INTEL_IOMMU 579 const unsigned short gpu_devid = intel_private.pcidev->device; 580 581 /* Query intel_iommu to see if we need the workaround. Presumably that 582 * was loaded first. 583 */ 584 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG || 585 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && 586 intel_iommu_gfx_mapped) 587 return 1; 588 #endif 589 return 0; 590 } 591 592 static bool intel_gtt_can_wc(void) 593 { 594 if (INTEL_GTT_GEN <= 2) 595 return false; 596 597 if (INTEL_GTT_GEN >= 6) 598 return false; 599 600 /* Reports of major corruption with ILK vt'd enabled */ 601 if (needs_ilk_vtd_wa()) 602 return false; 603 604 return true; 605 } 606 607 static int intel_gtt_init(void) 608 { 609 u32 gtt_map_size; 610 int ret, bar; 611 612 ret = intel_private.driver->setup(); 613 if (ret != 0) 614 return ret; 615 616 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); 617 intel_private.gtt_total_entries = intel_gtt_total_entries(); 618 619 /* save the PGETBL reg for resume */ 620 intel_private.PGETBL_save = 621 readl(intel_private.registers+I810_PGETBL_CTL) 622 & ~I810_PGETBL_ENABLED; 623 /* we only ever restore the register when enabling the PGTBL... */ 624 if (HAS_PGTBL_EN) 625 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 626 627 dev_info(&intel_private.bridge_dev->dev, 628 "detected gtt size: %dK total, %dK mappable\n", 629 intel_private.gtt_total_entries * 4, 630 intel_private.gtt_mappable_entries * 4); 631 632 gtt_map_size = intel_private.gtt_total_entries * 4; 633 634 intel_private.gtt = NULL; 635 if (intel_gtt_can_wc()) 636 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, 637 gtt_map_size); 638 if (intel_private.gtt == NULL) 639 intel_private.gtt = ioremap(intel_private.gtt_phys_addr, 640 gtt_map_size); 641 if (intel_private.gtt == NULL) { 642 intel_private.driver->cleanup(); 643 iounmap(intel_private.registers); 644 return -ENOMEM; 645 } 646 647 #if IS_ENABLED(CONFIG_AGP_INTEL) 648 global_cache_flush(); /* FIXME: ? */ 649 #endif 650 651 intel_private.stolen_size = intel_gtt_stolen_size(); 652 653 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 654 655 ret = intel_gtt_setup_scratch_page(); 656 if (ret != 0) { 657 intel_gtt_cleanup(); 658 return ret; 659 } 660 661 if (INTEL_GTT_GEN <= 2) 662 bar = I810_GMADR_BAR; 663 else 664 bar = I915_GMADR_BAR; 665 666 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); 667 return 0; 668 } 669 670 #if IS_ENABLED(CONFIG_AGP_INTEL) 671 static int intel_fake_agp_fetch_size(void) 672 { 673 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 674 unsigned int aper_size; 675 int i; 676 677 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); 678 679 for (i = 0; i < num_sizes; i++) { 680 if (aper_size == intel_fake_agp_sizes[i].size) { 681 agp_bridge->current_size = 682 (void *) (intel_fake_agp_sizes + i); 683 return aper_size; 684 } 685 } 686 687 return 0; 688 } 689 #endif 690 691 static void i830_cleanup(void) 692 { 693 } 694 695 /* The chipset_flush interface needs to get data that has already been 696 * flushed out of the CPU all the way out to main memory, because the GPU 697 * doesn't snoop those buffers. 698 * 699 * The 8xx series doesn't have the same lovely interface for flushing the 700 * chipset write buffers that the later chips do. According to the 865 701 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 702 * that buffer out, we just fill 1KB and clflush it out, on the assumption 703 * that it'll push whatever was in there out. It appears to work. 704 */ 705 static void i830_chipset_flush(void) 706 { 707 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 708 709 /* Forcibly evict everything from the CPU write buffers. 710 * clflush appears to be insufficient. 711 */ 712 wbinvd_on_all_cpus(); 713 714 /* Now we've only seen documents for this magic bit on 855GM, 715 * we hope it exists for the other gen2 chipsets... 716 * 717 * Also works as advertised on my 845G. 718 */ 719 writel(readl(intel_private.registers+I830_HIC) | (1<<31), 720 intel_private.registers+I830_HIC); 721 722 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 723 if (time_after(jiffies, timeout)) 724 break; 725 726 udelay(50); 727 } 728 } 729 730 static void i830_write_entry(dma_addr_t addr, unsigned int entry, 731 unsigned int flags) 732 { 733 u32 pte_flags = I810_PTE_VALID; 734 735 if (flags == AGP_USER_CACHED_MEMORY) 736 pte_flags |= I830_PTE_SYSTEM_CACHED; 737 738 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); 739 } 740 741 bool intel_enable_gtt(void) 742 { 743 u8 __iomem *reg; 744 745 if (INTEL_GTT_GEN == 2) { 746 u16 gmch_ctrl; 747 748 pci_read_config_word(intel_private.bridge_dev, 749 I830_GMCH_CTRL, &gmch_ctrl); 750 gmch_ctrl |= I830_GMCH_ENABLED; 751 pci_write_config_word(intel_private.bridge_dev, 752 I830_GMCH_CTRL, gmch_ctrl); 753 754 pci_read_config_word(intel_private.bridge_dev, 755 I830_GMCH_CTRL, &gmch_ctrl); 756 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 757 dev_err(&intel_private.pcidev->dev, 758 "failed to enable the GTT: GMCH_CTRL=%x\n", 759 gmch_ctrl); 760 return false; 761 } 762 } 763 764 /* On the resume path we may be adjusting the PGTBL value, so 765 * be paranoid and flush all chipset write buffers... 766 */ 767 if (INTEL_GTT_GEN >= 3) 768 writel(0, intel_private.registers+GFX_FLSH_CNTL); 769 770 reg = intel_private.registers+I810_PGETBL_CTL; 771 writel(intel_private.PGETBL_save, reg); 772 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 773 dev_err(&intel_private.pcidev->dev, 774 "failed to enable the GTT: PGETBL=%x [expected %x]\n", 775 readl(reg), intel_private.PGETBL_save); 776 return false; 777 } 778 779 if (INTEL_GTT_GEN >= 3) 780 writel(0, intel_private.registers+GFX_FLSH_CNTL); 781 782 return true; 783 } 784 EXPORT_SYMBOL(intel_enable_gtt); 785 786 static int i830_setup(void) 787 { 788 phys_addr_t reg_addr; 789 790 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 791 792 intel_private.registers = ioremap(reg_addr, KB(64)); 793 if (!intel_private.registers) 794 return -ENOMEM; 795 796 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 797 798 return 0; 799 } 800 801 #if IS_ENABLED(CONFIG_AGP_INTEL) 802 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 803 { 804 agp_bridge->gatt_table_real = NULL; 805 agp_bridge->gatt_table = NULL; 806 agp_bridge->gatt_bus_addr = 0; 807 808 return 0; 809 } 810 811 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 812 { 813 return 0; 814 } 815 816 static int intel_fake_agp_configure(void) 817 { 818 if (!intel_enable_gtt()) 819 return -EIO; 820 821 intel_private.clear_fake_agp = true; 822 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 823 824 return 0; 825 } 826 #endif 827 828 static bool i830_check_flags(unsigned int flags) 829 { 830 switch (flags) { 831 case 0: 832 case AGP_PHYS_MEMORY: 833 case AGP_USER_CACHED_MEMORY: 834 case AGP_USER_MEMORY: 835 return true; 836 } 837 838 return false; 839 } 840 841 void intel_gtt_insert_sg_entries(struct sg_table *st, 842 unsigned int pg_start, 843 unsigned int flags) 844 { 845 struct scatterlist *sg; 846 unsigned int len, m; 847 int i, j; 848 849 j = pg_start; 850 851 /* sg may merge pages, but we have to separate 852 * per-page addr for GTT */ 853 for_each_sg(st->sgl, sg, st->nents, i) { 854 len = sg_dma_len(sg) >> PAGE_SHIFT; 855 for (m = 0; m < len; m++) { 856 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 857 intel_private.driver->write_entry(addr, j, flags); 858 j++; 859 } 860 } 861 wmb(); 862 } 863 EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 864 865 #if IS_ENABLED(CONFIG_AGP_INTEL) 866 static void intel_gtt_insert_pages(unsigned int first_entry, 867 unsigned int num_entries, 868 struct page **pages, 869 unsigned int flags) 870 { 871 int i, j; 872 873 for (i = 0, j = first_entry; i < num_entries; i++, j++) { 874 dma_addr_t addr = page_to_phys(pages[i]); 875 intel_private.driver->write_entry(addr, 876 j, flags); 877 } 878 wmb(); 879 } 880 881 static int intel_fake_agp_insert_entries(struct agp_memory *mem, 882 off_t pg_start, int type) 883 { 884 int ret = -EINVAL; 885 886 if (intel_private.clear_fake_agp) { 887 int start = intel_private.stolen_size / PAGE_SIZE; 888 int end = intel_private.gtt_mappable_entries; 889 intel_gtt_clear_range(start, end - start); 890 intel_private.clear_fake_agp = false; 891 } 892 893 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 894 return i810_insert_dcache_entries(mem, pg_start, type); 895 896 if (mem->page_count == 0) 897 goto out; 898 899 if (pg_start + mem->page_count > intel_private.gtt_total_entries) 900 goto out_err; 901 902 if (type != mem->type) 903 goto out_err; 904 905 if (!intel_private.driver->check_flags(type)) 906 goto out_err; 907 908 if (!mem->is_flushed) 909 global_cache_flush(); 910 911 if (intel_private.needs_dmar) { 912 struct sg_table st; 913 914 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); 915 if (ret != 0) 916 return ret; 917 918 intel_gtt_insert_sg_entries(&st, pg_start, type); 919 mem->sg_list = st.sgl; 920 mem->num_sg = st.nents; 921 } else 922 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 923 type); 924 925 out: 926 ret = 0; 927 out_err: 928 mem->is_flushed = true; 929 return ret; 930 } 931 #endif 932 933 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 934 { 935 unsigned int i; 936 937 for (i = first_entry; i < (first_entry + num_entries); i++) { 938 intel_private.driver->write_entry(intel_private.scratch_page_dma, 939 i, 0); 940 } 941 wmb(); 942 } 943 EXPORT_SYMBOL(intel_gtt_clear_range); 944 945 #if IS_ENABLED(CONFIG_AGP_INTEL) 946 static int intel_fake_agp_remove_entries(struct agp_memory *mem, 947 off_t pg_start, int type) 948 { 949 if (mem->page_count == 0) 950 return 0; 951 952 intel_gtt_clear_range(pg_start, mem->page_count); 953 954 if (intel_private.needs_dmar) { 955 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 956 mem->sg_list = NULL; 957 mem->num_sg = 0; 958 } 959 960 return 0; 961 } 962 963 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 964 int type) 965 { 966 struct agp_memory *new; 967 968 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 969 if (pg_count != intel_private.num_dcache_entries) 970 return NULL; 971 972 new = agp_create_memory(1); 973 if (new == NULL) 974 return NULL; 975 976 new->type = AGP_DCACHE_MEMORY; 977 new->page_count = pg_count; 978 new->num_scratch_pages = 0; 979 agp_free_page_array(new); 980 return new; 981 } 982 if (type == AGP_PHYS_MEMORY) 983 return alloc_agpphysmem_i8xx(pg_count, type); 984 /* always return NULL for other allocation types for now */ 985 return NULL; 986 } 987 #endif 988 989 static int intel_alloc_chipset_flush_resource(void) 990 { 991 int ret; 992 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 993 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 994 pcibios_align_resource, intel_private.bridge_dev); 995 996 return ret; 997 } 998 999 static void intel_i915_setup_chipset_flush(void) 1000 { 1001 int ret; 1002 u32 temp; 1003 1004 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1005 if (!(temp & 0x1)) { 1006 intel_alloc_chipset_flush_resource(); 1007 intel_private.resource_valid = 1; 1008 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1009 } else { 1010 temp &= ~1; 1011 1012 intel_private.resource_valid = 1; 1013 intel_private.ifp_resource.start = temp; 1014 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1015 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1016 /* some BIOSes reserve this area in a pnp some don't */ 1017 if (ret) 1018 intel_private.resource_valid = 0; 1019 } 1020 } 1021 1022 static void intel_i965_g33_setup_chipset_flush(void) 1023 { 1024 u32 temp_hi, temp_lo; 1025 int ret; 1026 1027 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1028 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1029 1030 if (!(temp_lo & 0x1)) { 1031 1032 intel_alloc_chipset_flush_resource(); 1033 1034 intel_private.resource_valid = 1; 1035 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1036 upper_32_bits(intel_private.ifp_resource.start)); 1037 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1038 } else { 1039 u64 l64; 1040 1041 temp_lo &= ~0x1; 1042 l64 = ((u64)temp_hi << 32) | temp_lo; 1043 1044 intel_private.resource_valid = 1; 1045 intel_private.ifp_resource.start = l64; 1046 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1047 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1048 /* some BIOSes reserve this area in a pnp some don't */ 1049 if (ret) 1050 intel_private.resource_valid = 0; 1051 } 1052 } 1053 1054 static void intel_i9xx_setup_flush(void) 1055 { 1056 /* return if already configured */ 1057 if (intel_private.ifp_resource.start) 1058 return; 1059 1060 if (INTEL_GTT_GEN == 6) 1061 return; 1062 1063 /* setup a resource for this object */ 1064 intel_private.ifp_resource.name = "Intel Flush Page"; 1065 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1066 1067 /* Setup chipset flush for 915 */ 1068 if (IS_G33 || INTEL_GTT_GEN >= 4) { 1069 intel_i965_g33_setup_chipset_flush(); 1070 } else { 1071 intel_i915_setup_chipset_flush(); 1072 } 1073 1074 if (intel_private.ifp_resource.start) 1075 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1076 if (!intel_private.i9xx_flush_page) 1077 dev_err(&intel_private.pcidev->dev, 1078 "can't ioremap flush page - no chipset flushing\n"); 1079 } 1080 1081 static void i9xx_cleanup(void) 1082 { 1083 if (intel_private.i9xx_flush_page) 1084 iounmap(intel_private.i9xx_flush_page); 1085 if (intel_private.resource_valid) 1086 release_resource(&intel_private.ifp_resource); 1087 intel_private.ifp_resource.start = 0; 1088 intel_private.resource_valid = 0; 1089 } 1090 1091 static void i9xx_chipset_flush(void) 1092 { 1093 if (intel_private.i9xx_flush_page) 1094 writel(1, intel_private.i9xx_flush_page); 1095 } 1096 1097 static void i965_write_entry(dma_addr_t addr, 1098 unsigned int entry, 1099 unsigned int flags) 1100 { 1101 u32 pte_flags; 1102 1103 pte_flags = I810_PTE_VALID; 1104 if (flags == AGP_USER_CACHED_MEMORY) 1105 pte_flags |= I830_PTE_SYSTEM_CACHED; 1106 1107 /* Shift high bits down */ 1108 addr |= (addr >> 28) & 0xf0; 1109 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); 1110 } 1111 1112 static int i9xx_setup(void) 1113 { 1114 phys_addr_t reg_addr; 1115 int size = KB(512); 1116 1117 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); 1118 1119 intel_private.registers = ioremap(reg_addr, size); 1120 if (!intel_private.registers) 1121 return -ENOMEM; 1122 1123 switch (INTEL_GTT_GEN) { 1124 case 3: 1125 intel_private.gtt_phys_addr = 1126 pci_resource_start(intel_private.pcidev, I915_PTE_BAR); 1127 break; 1128 case 5: 1129 intel_private.gtt_phys_addr = reg_addr + MB(2); 1130 break; 1131 default: 1132 intel_private.gtt_phys_addr = reg_addr + KB(512); 1133 break; 1134 } 1135 1136 intel_i9xx_setup_flush(); 1137 1138 return 0; 1139 } 1140 1141 #if IS_ENABLED(CONFIG_AGP_INTEL) 1142 static const struct agp_bridge_driver intel_fake_agp_driver = { 1143 .owner = THIS_MODULE, 1144 .size_type = FIXED_APER_SIZE, 1145 .aperture_sizes = intel_fake_agp_sizes, 1146 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1147 .configure = intel_fake_agp_configure, 1148 .fetch_size = intel_fake_agp_fetch_size, 1149 .cleanup = intel_gtt_cleanup, 1150 .agp_enable = intel_fake_agp_enable, 1151 .cache_flush = global_cache_flush, 1152 .create_gatt_table = intel_fake_agp_create_gatt_table, 1153 .free_gatt_table = intel_fake_agp_free_gatt_table, 1154 .insert_memory = intel_fake_agp_insert_entries, 1155 .remove_memory = intel_fake_agp_remove_entries, 1156 .alloc_by_type = intel_fake_agp_alloc_by_type, 1157 .free_by_type = intel_i810_free_by_type, 1158 .agp_alloc_page = agp_generic_alloc_page, 1159 .agp_alloc_pages = agp_generic_alloc_pages, 1160 .agp_destroy_page = agp_generic_destroy_page, 1161 .agp_destroy_pages = agp_generic_destroy_pages, 1162 }; 1163 #endif 1164 1165 static const struct intel_gtt_driver i81x_gtt_driver = { 1166 .gen = 1, 1167 .has_pgtbl_enable = 1, 1168 .dma_mask_size = 32, 1169 .setup = i810_setup, 1170 .cleanup = i810_cleanup, 1171 .check_flags = i830_check_flags, 1172 .write_entry = i810_write_entry, 1173 }; 1174 static const struct intel_gtt_driver i8xx_gtt_driver = { 1175 .gen = 2, 1176 .has_pgtbl_enable = 1, 1177 .setup = i830_setup, 1178 .cleanup = i830_cleanup, 1179 .write_entry = i830_write_entry, 1180 .dma_mask_size = 32, 1181 .check_flags = i830_check_flags, 1182 .chipset_flush = i830_chipset_flush, 1183 }; 1184 static const struct intel_gtt_driver i915_gtt_driver = { 1185 .gen = 3, 1186 .has_pgtbl_enable = 1, 1187 .setup = i9xx_setup, 1188 .cleanup = i9xx_cleanup, 1189 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1190 .write_entry = i830_write_entry, 1191 .dma_mask_size = 32, 1192 .check_flags = i830_check_flags, 1193 .chipset_flush = i9xx_chipset_flush, 1194 }; 1195 static const struct intel_gtt_driver g33_gtt_driver = { 1196 .gen = 3, 1197 .is_g33 = 1, 1198 .setup = i9xx_setup, 1199 .cleanup = i9xx_cleanup, 1200 .write_entry = i965_write_entry, 1201 .dma_mask_size = 36, 1202 .check_flags = i830_check_flags, 1203 .chipset_flush = i9xx_chipset_flush, 1204 }; 1205 static const struct intel_gtt_driver pineview_gtt_driver = { 1206 .gen = 3, 1207 .is_pineview = 1, .is_g33 = 1, 1208 .setup = i9xx_setup, 1209 .cleanup = i9xx_cleanup, 1210 .write_entry = i965_write_entry, 1211 .dma_mask_size = 36, 1212 .check_flags = i830_check_flags, 1213 .chipset_flush = i9xx_chipset_flush, 1214 }; 1215 static const struct intel_gtt_driver i965_gtt_driver = { 1216 .gen = 4, 1217 .has_pgtbl_enable = 1, 1218 .setup = i9xx_setup, 1219 .cleanup = i9xx_cleanup, 1220 .write_entry = i965_write_entry, 1221 .dma_mask_size = 36, 1222 .check_flags = i830_check_flags, 1223 .chipset_flush = i9xx_chipset_flush, 1224 }; 1225 static const struct intel_gtt_driver g4x_gtt_driver = { 1226 .gen = 5, 1227 .setup = i9xx_setup, 1228 .cleanup = i9xx_cleanup, 1229 .write_entry = i965_write_entry, 1230 .dma_mask_size = 36, 1231 .check_flags = i830_check_flags, 1232 .chipset_flush = i9xx_chipset_flush, 1233 }; 1234 static const struct intel_gtt_driver ironlake_gtt_driver = { 1235 .gen = 5, 1236 .is_ironlake = 1, 1237 .setup = i9xx_setup, 1238 .cleanup = i9xx_cleanup, 1239 .write_entry = i965_write_entry, 1240 .dma_mask_size = 36, 1241 .check_flags = i830_check_flags, 1242 .chipset_flush = i9xx_chipset_flush, 1243 }; 1244 1245 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1246 * driver and gmch_driver must be non-null, and find_gmch will determine 1247 * which one should be used if a gmch_chip_id is present. 1248 */ 1249 static const struct intel_gtt_driver_description { 1250 unsigned int gmch_chip_id; 1251 char *name; 1252 const struct intel_gtt_driver *gtt_driver; 1253 } intel_gtt_chipsets[] = { 1254 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1255 &i81x_gtt_driver}, 1256 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1257 &i81x_gtt_driver}, 1258 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1259 &i81x_gtt_driver}, 1260 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1261 &i81x_gtt_driver}, 1262 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1263 &i8xx_gtt_driver}, 1264 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1265 &i8xx_gtt_driver}, 1266 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1267 &i8xx_gtt_driver}, 1268 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1269 &i8xx_gtt_driver}, 1270 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1271 &i8xx_gtt_driver}, 1272 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1273 &i915_gtt_driver }, 1274 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1275 &i915_gtt_driver }, 1276 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1277 &i915_gtt_driver }, 1278 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1279 &i915_gtt_driver }, 1280 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1281 &i915_gtt_driver }, 1282 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1283 &i915_gtt_driver }, 1284 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1285 &i965_gtt_driver }, 1286 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1287 &i965_gtt_driver }, 1288 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1289 &i965_gtt_driver }, 1290 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1291 &i965_gtt_driver }, 1292 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1293 &i965_gtt_driver }, 1294 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1295 &i965_gtt_driver }, 1296 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1297 &g33_gtt_driver }, 1298 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1299 &g33_gtt_driver }, 1300 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1301 &g33_gtt_driver }, 1302 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1303 &pineview_gtt_driver }, 1304 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1305 &pineview_gtt_driver }, 1306 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1307 &g4x_gtt_driver }, 1308 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1309 &g4x_gtt_driver }, 1310 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1311 &g4x_gtt_driver }, 1312 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1313 &g4x_gtt_driver }, 1314 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1315 &g4x_gtt_driver }, 1316 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1317 &g4x_gtt_driver }, 1318 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1319 &g4x_gtt_driver }, 1320 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1321 "HD Graphics", &ironlake_gtt_driver }, 1322 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1323 "HD Graphics", &ironlake_gtt_driver }, 1324 { 0, NULL, NULL } 1325 }; 1326 1327 static int find_gmch(u16 device) 1328 { 1329 struct pci_dev *gmch_device; 1330 1331 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1332 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1333 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1334 device, gmch_device); 1335 } 1336 1337 if (!gmch_device) 1338 return 0; 1339 1340 intel_private.pcidev = gmch_device; 1341 return 1; 1342 } 1343 1344 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 1345 struct agp_bridge_data *bridge) 1346 { 1347 int i, mask; 1348 1349 /* 1350 * Can be called from the fake agp driver but also directly from 1351 * drm/i915.ko. Hence we need to check whether everything is set up 1352 * already. 1353 */ 1354 if (intel_private.driver) { 1355 intel_private.refcount++; 1356 return 1; 1357 } 1358 1359 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1360 if (gpu_pdev) { 1361 if (gpu_pdev->device == 1362 intel_gtt_chipsets[i].gmch_chip_id) { 1363 intel_private.pcidev = pci_dev_get(gpu_pdev); 1364 intel_private.driver = 1365 intel_gtt_chipsets[i].gtt_driver; 1366 1367 break; 1368 } 1369 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1370 intel_private.driver = 1371 intel_gtt_chipsets[i].gtt_driver; 1372 break; 1373 } 1374 } 1375 1376 if (!intel_private.driver) 1377 return 0; 1378 1379 intel_private.refcount++; 1380 1381 #if IS_ENABLED(CONFIG_AGP_INTEL) 1382 if (bridge) { 1383 bridge->driver = &intel_fake_agp_driver; 1384 bridge->dev_private_data = &intel_private; 1385 bridge->dev = bridge_pdev; 1386 } 1387 #endif 1388 1389 intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1390 1391 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1392 1393 mask = intel_private.driver->dma_mask_size; 1394 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1395 dev_err(&intel_private.pcidev->dev, 1396 "set gfx device dma mask %d-bit failed!\n", mask); 1397 else 1398 pci_set_consistent_dma_mask(intel_private.pcidev, 1399 DMA_BIT_MASK(mask)); 1400 1401 if (intel_gtt_init() != 0) { 1402 intel_gmch_remove(); 1403 1404 return 0; 1405 } 1406 1407 return 1; 1408 } 1409 EXPORT_SYMBOL(intel_gmch_probe); 1410 1411 void intel_gtt_get(u64 *gtt_total, size_t *stolen_size, 1412 phys_addr_t *mappable_base, u64 *mappable_end) 1413 { 1414 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; 1415 *stolen_size = intel_private.stolen_size; 1416 *mappable_base = intel_private.gma_bus_addr; 1417 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; 1418 } 1419 EXPORT_SYMBOL(intel_gtt_get); 1420 1421 void intel_gtt_chipset_flush(void) 1422 { 1423 if (intel_private.driver->chipset_flush) 1424 intel_private.driver->chipset_flush(); 1425 } 1426 EXPORT_SYMBOL(intel_gtt_chipset_flush); 1427 1428 void intel_gmch_remove(void) 1429 { 1430 if (--intel_private.refcount) 1431 return; 1432 1433 if (intel_private.pcidev) 1434 pci_dev_put(intel_private.pcidev); 1435 if (intel_private.bridge_dev) 1436 pci_dev_put(intel_private.bridge_dev); 1437 intel_private.driver = NULL; 1438 } 1439 EXPORT_SYMBOL(intel_gmch_remove); 1440 1441 MODULE_AUTHOR("Dave Jones, Various @Intel"); 1442 MODULE_LICENSE("GPL and additional rights"); 1443