xref: /openbmc/linux/drivers/char/agp/intel-gtt.c (revision 82003e04)
1 /*
2  * Intel GTT (Graphics Translation Table) routines
3  *
4  * Caveat: This driver implements the linux agp interface, but this is far from
5  * a agp driver! GTT support ended up here for purely historical reasons: The
6  * old userspace intel graphics drivers needed an interface to map memory into
7  * the GTT. And the drm provides a default interface for graphic devices sitting
8  * on an agp port. So it made sense to fake the GTT support as an agp port to
9  * avoid having to create a new api.
10  *
11  * With gem this does not make much sense anymore, just needlessly complicates
12  * the code. But as long as the old graphics stack is still support, it's stuck
13  * here.
14  *
15  * /fairy-tale-mode off
16  */
17 
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/kernel.h>
21 #include <linux/pagemap.h>
22 #include <linux/agp_backend.h>
23 #include <linux/delay.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
28 
29 /*
30  * If we have Intel graphics, we're not going to have anything other than
31  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
32  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
33  * Only newer chipsets need to bother with this, of course.
34  */
35 #ifdef CONFIG_INTEL_IOMMU
36 #define USE_PCI_DMA_API 1
37 #else
38 #define USE_PCI_DMA_API 0
39 #endif
40 
41 struct intel_gtt_driver {
42 	unsigned int gen : 8;
43 	unsigned int is_g33 : 1;
44 	unsigned int is_pineview : 1;
45 	unsigned int is_ironlake : 1;
46 	unsigned int has_pgtbl_enable : 1;
47 	unsigned int dma_mask_size : 8;
48 	/* Chipset specific GTT setup */
49 	int (*setup)(void);
50 	/* This should undo anything done in ->setup() save the unmapping
51 	 * of the mmio register file, that's done in the generic code. */
52 	void (*cleanup)(void);
53 	void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
54 	/* Flags is a more or less chipset specific opaque value.
55 	 * For chipsets that need to support old ums (non-gem) code, this
56 	 * needs to be identical to the various supported agp memory types! */
57 	bool (*check_flags)(unsigned int flags);
58 	void (*chipset_flush)(void);
59 };
60 
61 static struct _intel_private {
62 	const struct intel_gtt_driver *driver;
63 	struct pci_dev *pcidev;	/* device one */
64 	struct pci_dev *bridge_dev;
65 	u8 __iomem *registers;
66 	phys_addr_t gtt_phys_addr;
67 	u32 PGETBL_save;
68 	u32 __iomem *gtt;		/* I915G */
69 	bool clear_fake_agp; /* on first access via agp, fill with scratch */
70 	int num_dcache_entries;
71 	void __iomem *i9xx_flush_page;
72 	char *i81x_gtt_table;
73 	struct resource ifp_resource;
74 	int resource_valid;
75 	struct page *scratch_page;
76 	phys_addr_t scratch_page_dma;
77 	int refcount;
78 	/* Whether i915 needs to use the dmar apis or not. */
79 	unsigned int needs_dmar : 1;
80 	phys_addr_t gma_bus_addr;
81 	/*  Size of memory reserved for graphics by the BIOS */
82 	unsigned int stolen_size;
83 	/* Total number of gtt entries. */
84 	unsigned int gtt_total_entries;
85 	/* Part of the gtt that is mappable by the cpu, for those chips where
86 	 * this is not the full gtt. */
87 	unsigned int gtt_mappable_entries;
88 } intel_private;
89 
90 #define INTEL_GTT_GEN	intel_private.driver->gen
91 #define IS_G33		intel_private.driver->is_g33
92 #define IS_PINEVIEW	intel_private.driver->is_pineview
93 #define IS_IRONLAKE	intel_private.driver->is_ironlake
94 #define HAS_PGTBL_EN	intel_private.driver->has_pgtbl_enable
95 
96 #if IS_ENABLED(CONFIG_AGP_INTEL)
97 static int intel_gtt_map_memory(struct page **pages,
98 				unsigned int num_entries,
99 				struct sg_table *st)
100 {
101 	struct scatterlist *sg;
102 	int i;
103 
104 	DBG("try mapping %lu pages\n", (unsigned long)num_entries);
105 
106 	if (sg_alloc_table(st, num_entries, GFP_KERNEL))
107 		goto err;
108 
109 	for_each_sg(st->sgl, sg, num_entries, i)
110 		sg_set_page(sg, pages[i], PAGE_SIZE, 0);
111 
112 	if (!pci_map_sg(intel_private.pcidev,
113 			st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
114 		goto err;
115 
116 	return 0;
117 
118 err:
119 	sg_free_table(st);
120 	return -ENOMEM;
121 }
122 
123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
124 {
125 	struct sg_table st;
126 	DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
127 
128 	pci_unmap_sg(intel_private.pcidev, sg_list,
129 		     num_sg, PCI_DMA_BIDIRECTIONAL);
130 
131 	st.sgl = sg_list;
132 	st.orig_nents = st.nents = num_sg;
133 
134 	sg_free_table(&st);
135 }
136 
137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
138 {
139 	return;
140 }
141 
142 /* Exists to support ARGB cursors */
143 static struct page *i8xx_alloc_pages(void)
144 {
145 	struct page *page;
146 
147 	page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
148 	if (page == NULL)
149 		return NULL;
150 
151 	if (set_pages_uc(page, 4) < 0) {
152 		set_pages_wb(page, 4);
153 		__free_pages(page, 2);
154 		return NULL;
155 	}
156 	atomic_inc(&agp_bridge->current_memory_agp);
157 	return page;
158 }
159 
160 static void i8xx_destroy_pages(struct page *page)
161 {
162 	if (page == NULL)
163 		return;
164 
165 	set_pages_wb(page, 4);
166 	__free_pages(page, 2);
167 	atomic_dec(&agp_bridge->current_memory_agp);
168 }
169 #endif
170 
171 #define I810_GTT_ORDER 4
172 static int i810_setup(void)
173 {
174 	phys_addr_t reg_addr;
175 	char *gtt_table;
176 
177 	/* i81x does not preallocate the gtt. It's always 64kb in size. */
178 	gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
179 	if (gtt_table == NULL)
180 		return -ENOMEM;
181 	intel_private.i81x_gtt_table = gtt_table;
182 
183 	reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
184 
185 	intel_private.registers = ioremap(reg_addr, KB(64));
186 	if (!intel_private.registers)
187 		return -ENOMEM;
188 
189 	writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
190 	       intel_private.registers+I810_PGETBL_CTL);
191 
192 	intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
193 
194 	if ((readl(intel_private.registers+I810_DRAM_CTL)
195 		& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
196 		dev_info(&intel_private.pcidev->dev,
197 			 "detected 4MB dedicated video ram\n");
198 		intel_private.num_dcache_entries = 1024;
199 	}
200 
201 	return 0;
202 }
203 
204 static void i810_cleanup(void)
205 {
206 	writel(0, intel_private.registers+I810_PGETBL_CTL);
207 	free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
208 }
209 
210 #if IS_ENABLED(CONFIG_AGP_INTEL)
211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
212 				      int type)
213 {
214 	int i;
215 
216 	if ((pg_start + mem->page_count)
217 			> intel_private.num_dcache_entries)
218 		return -EINVAL;
219 
220 	if (!mem->is_flushed)
221 		global_cache_flush();
222 
223 	for (i = pg_start; i < (pg_start + mem->page_count); i++) {
224 		dma_addr_t addr = i << PAGE_SHIFT;
225 		intel_private.driver->write_entry(addr,
226 						  i, type);
227 	}
228 	wmb();
229 
230 	return 0;
231 }
232 
233 /*
234  * The i810/i830 requires a physical address to program its mouse
235  * pointer into hardware.
236  * However the Xserver still writes to it through the agp aperture.
237  */
238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
239 {
240 	struct agp_memory *new;
241 	struct page *page;
242 
243 	switch (pg_count) {
244 	case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
245 		break;
246 	case 4:
247 		/* kludge to get 4 physical pages for ARGB cursor */
248 		page = i8xx_alloc_pages();
249 		break;
250 	default:
251 		return NULL;
252 	}
253 
254 	if (page == NULL)
255 		return NULL;
256 
257 	new = agp_create_memory(pg_count);
258 	if (new == NULL)
259 		return NULL;
260 
261 	new->pages[0] = page;
262 	if (pg_count == 4) {
263 		/* kludge to get 4 physical pages for ARGB cursor */
264 		new->pages[1] = new->pages[0] + 1;
265 		new->pages[2] = new->pages[1] + 1;
266 		new->pages[3] = new->pages[2] + 1;
267 	}
268 	new->page_count = pg_count;
269 	new->num_scratch_pages = pg_count;
270 	new->type = AGP_PHYS_MEMORY;
271 	new->physical = page_to_phys(new->pages[0]);
272 	return new;
273 }
274 
275 static void intel_i810_free_by_type(struct agp_memory *curr)
276 {
277 	agp_free_key(curr->key);
278 	if (curr->type == AGP_PHYS_MEMORY) {
279 		if (curr->page_count == 4)
280 			i8xx_destroy_pages(curr->pages[0]);
281 		else {
282 			agp_bridge->driver->agp_destroy_page(curr->pages[0],
283 							     AGP_PAGE_DESTROY_UNMAP);
284 			agp_bridge->driver->agp_destroy_page(curr->pages[0],
285 							     AGP_PAGE_DESTROY_FREE);
286 		}
287 		agp_free_page_array(curr);
288 	}
289 	kfree(curr);
290 }
291 #endif
292 
293 static int intel_gtt_setup_scratch_page(void)
294 {
295 	struct page *page;
296 	dma_addr_t dma_addr;
297 
298 	page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
299 	if (page == NULL)
300 		return -ENOMEM;
301 	set_pages_uc(page, 1);
302 
303 	if (intel_private.needs_dmar) {
304 		dma_addr = pci_map_page(intel_private.pcidev, page, 0,
305 				    PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
306 		if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
307 			return -EINVAL;
308 
309 		intel_private.scratch_page_dma = dma_addr;
310 	} else
311 		intel_private.scratch_page_dma = page_to_phys(page);
312 
313 	intel_private.scratch_page = page;
314 
315 	return 0;
316 }
317 
318 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
319 			     unsigned int flags)
320 {
321 	u32 pte_flags = I810_PTE_VALID;
322 
323 	switch (flags) {
324 	case AGP_DCACHE_MEMORY:
325 		pte_flags |= I810_PTE_LOCAL;
326 		break;
327 	case AGP_USER_CACHED_MEMORY:
328 		pte_flags |= I830_PTE_SYSTEM_CACHED;
329 		break;
330 	}
331 
332 	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
333 }
334 
335 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
336 	{32, 8192, 3},
337 	{64, 16384, 4},
338 	{128, 32768, 5},
339 	{256, 65536, 6},
340 	{512, 131072, 7},
341 };
342 
343 static unsigned int intel_gtt_stolen_size(void)
344 {
345 	u16 gmch_ctrl;
346 	u8 rdct;
347 	int local = 0;
348 	static const int ddt[4] = { 0, 16, 32, 64 };
349 	unsigned int stolen_size = 0;
350 
351 	if (INTEL_GTT_GEN == 1)
352 		return 0; /* no stolen mem on i81x */
353 
354 	pci_read_config_word(intel_private.bridge_dev,
355 			     I830_GMCH_CTRL, &gmch_ctrl);
356 
357 	if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
358 	    intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
359 		switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
360 		case I830_GMCH_GMS_STOLEN_512:
361 			stolen_size = KB(512);
362 			break;
363 		case I830_GMCH_GMS_STOLEN_1024:
364 			stolen_size = MB(1);
365 			break;
366 		case I830_GMCH_GMS_STOLEN_8192:
367 			stolen_size = MB(8);
368 			break;
369 		case I830_GMCH_GMS_LOCAL:
370 			rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
371 			stolen_size = (I830_RDRAM_ND(rdct) + 1) *
372 					MB(ddt[I830_RDRAM_DDT(rdct)]);
373 			local = 1;
374 			break;
375 		default:
376 			stolen_size = 0;
377 			break;
378 		}
379 	} else {
380 		switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
381 		case I855_GMCH_GMS_STOLEN_1M:
382 			stolen_size = MB(1);
383 			break;
384 		case I855_GMCH_GMS_STOLEN_4M:
385 			stolen_size = MB(4);
386 			break;
387 		case I855_GMCH_GMS_STOLEN_8M:
388 			stolen_size = MB(8);
389 			break;
390 		case I855_GMCH_GMS_STOLEN_16M:
391 			stolen_size = MB(16);
392 			break;
393 		case I855_GMCH_GMS_STOLEN_32M:
394 			stolen_size = MB(32);
395 			break;
396 		case I915_GMCH_GMS_STOLEN_48M:
397 			stolen_size = MB(48);
398 			break;
399 		case I915_GMCH_GMS_STOLEN_64M:
400 			stolen_size = MB(64);
401 			break;
402 		case G33_GMCH_GMS_STOLEN_128M:
403 			stolen_size = MB(128);
404 			break;
405 		case G33_GMCH_GMS_STOLEN_256M:
406 			stolen_size = MB(256);
407 			break;
408 		case INTEL_GMCH_GMS_STOLEN_96M:
409 			stolen_size = MB(96);
410 			break;
411 		case INTEL_GMCH_GMS_STOLEN_160M:
412 			stolen_size = MB(160);
413 			break;
414 		case INTEL_GMCH_GMS_STOLEN_224M:
415 			stolen_size = MB(224);
416 			break;
417 		case INTEL_GMCH_GMS_STOLEN_352M:
418 			stolen_size = MB(352);
419 			break;
420 		default:
421 			stolen_size = 0;
422 			break;
423 		}
424 	}
425 
426 	if (stolen_size > 0) {
427 		dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
428 		       stolen_size / KB(1), local ? "local" : "stolen");
429 	} else {
430 		dev_info(&intel_private.bridge_dev->dev,
431 		       "no pre-allocated video memory detected\n");
432 		stolen_size = 0;
433 	}
434 
435 	return stolen_size;
436 }
437 
438 static void i965_adjust_pgetbl_size(unsigned int size_flag)
439 {
440 	u32 pgetbl_ctl, pgetbl_ctl2;
441 
442 	/* ensure that ppgtt is disabled */
443 	pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
444 	pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
445 	writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
446 
447 	/* write the new ggtt size */
448 	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
449 	pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
450 	pgetbl_ctl |= size_flag;
451 	writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
452 }
453 
454 static unsigned int i965_gtt_total_entries(void)
455 {
456 	int size;
457 	u32 pgetbl_ctl;
458 	u16 gmch_ctl;
459 
460 	pci_read_config_word(intel_private.bridge_dev,
461 			     I830_GMCH_CTRL, &gmch_ctl);
462 
463 	if (INTEL_GTT_GEN == 5) {
464 		switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
465 		case G4x_GMCH_SIZE_1M:
466 		case G4x_GMCH_SIZE_VT_1M:
467 			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
468 			break;
469 		case G4x_GMCH_SIZE_VT_1_5M:
470 			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
471 			break;
472 		case G4x_GMCH_SIZE_2M:
473 		case G4x_GMCH_SIZE_VT_2M:
474 			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
475 			break;
476 		}
477 	}
478 
479 	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
480 
481 	switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
482 	case I965_PGETBL_SIZE_128KB:
483 		size = KB(128);
484 		break;
485 	case I965_PGETBL_SIZE_256KB:
486 		size = KB(256);
487 		break;
488 	case I965_PGETBL_SIZE_512KB:
489 		size = KB(512);
490 		break;
491 	/* GTT pagetable sizes bigger than 512KB are not possible on G33! */
492 	case I965_PGETBL_SIZE_1MB:
493 		size = KB(1024);
494 		break;
495 	case I965_PGETBL_SIZE_2MB:
496 		size = KB(2048);
497 		break;
498 	case I965_PGETBL_SIZE_1_5MB:
499 		size = KB(1024 + 512);
500 		break;
501 	default:
502 		dev_info(&intel_private.pcidev->dev,
503 			 "unknown page table size, assuming 512KB\n");
504 		size = KB(512);
505 	}
506 
507 	return size/4;
508 }
509 
510 static unsigned int intel_gtt_total_entries(void)
511 {
512 	if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
513 		return i965_gtt_total_entries();
514 	else {
515 		/* On previous hardware, the GTT size was just what was
516 		 * required to map the aperture.
517 		 */
518 		return intel_private.gtt_mappable_entries;
519 	}
520 }
521 
522 static unsigned int intel_gtt_mappable_entries(void)
523 {
524 	unsigned int aperture_size;
525 
526 	if (INTEL_GTT_GEN == 1) {
527 		u32 smram_miscc;
528 
529 		pci_read_config_dword(intel_private.bridge_dev,
530 				      I810_SMRAM_MISCC, &smram_miscc);
531 
532 		if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
533 				== I810_GFX_MEM_WIN_32M)
534 			aperture_size = MB(32);
535 		else
536 			aperture_size = MB(64);
537 	} else if (INTEL_GTT_GEN == 2) {
538 		u16 gmch_ctrl;
539 
540 		pci_read_config_word(intel_private.bridge_dev,
541 				     I830_GMCH_CTRL, &gmch_ctrl);
542 
543 		if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
544 			aperture_size = MB(64);
545 		else
546 			aperture_size = MB(128);
547 	} else {
548 		/* 9xx supports large sizes, just look at the length */
549 		aperture_size = pci_resource_len(intel_private.pcidev, 2);
550 	}
551 
552 	return aperture_size >> PAGE_SHIFT;
553 }
554 
555 static void intel_gtt_teardown_scratch_page(void)
556 {
557 	set_pages_wb(intel_private.scratch_page, 1);
558 	if (intel_private.needs_dmar)
559 		pci_unmap_page(intel_private.pcidev,
560 			       intel_private.scratch_page_dma,
561 			       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
562 	__free_page(intel_private.scratch_page);
563 }
564 
565 static void intel_gtt_cleanup(void)
566 {
567 	intel_private.driver->cleanup();
568 
569 	iounmap(intel_private.gtt);
570 	iounmap(intel_private.registers);
571 
572 	intel_gtt_teardown_scratch_page();
573 }
574 
575 /* Certain Gen5 chipsets require require idling the GPU before
576  * unmapping anything from the GTT when VT-d is enabled.
577  */
578 static inline int needs_ilk_vtd_wa(void)
579 {
580 #ifdef CONFIG_INTEL_IOMMU
581 	const unsigned short gpu_devid = intel_private.pcidev->device;
582 
583 	/* Query intel_iommu to see if we need the workaround. Presumably that
584 	 * was loaded first.
585 	 */
586 	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
587 	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
588 	     intel_iommu_gfx_mapped)
589 		return 1;
590 #endif
591 	return 0;
592 }
593 
594 static bool intel_gtt_can_wc(void)
595 {
596 	if (INTEL_GTT_GEN <= 2)
597 		return false;
598 
599 	if (INTEL_GTT_GEN >= 6)
600 		return false;
601 
602 	/* Reports of major corruption with ILK vt'd enabled */
603 	if (needs_ilk_vtd_wa())
604 		return false;
605 
606 	return true;
607 }
608 
609 static int intel_gtt_init(void)
610 {
611 	u32 gtt_map_size;
612 	int ret, bar;
613 
614 	ret = intel_private.driver->setup();
615 	if (ret != 0)
616 		return ret;
617 
618 	intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
619 	intel_private.gtt_total_entries = intel_gtt_total_entries();
620 
621 	/* save the PGETBL reg for resume */
622 	intel_private.PGETBL_save =
623 		readl(intel_private.registers+I810_PGETBL_CTL)
624 			& ~I810_PGETBL_ENABLED;
625 	/* we only ever restore the register when enabling the PGTBL... */
626 	if (HAS_PGTBL_EN)
627 		intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
628 
629 	dev_info(&intel_private.bridge_dev->dev,
630 			"detected gtt size: %dK total, %dK mappable\n",
631 			intel_private.gtt_total_entries * 4,
632 			intel_private.gtt_mappable_entries * 4);
633 
634 	gtt_map_size = intel_private.gtt_total_entries * 4;
635 
636 	intel_private.gtt = NULL;
637 	if (intel_gtt_can_wc())
638 		intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
639 					       gtt_map_size);
640 	if (intel_private.gtt == NULL)
641 		intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
642 					    gtt_map_size);
643 	if (intel_private.gtt == NULL) {
644 		intel_private.driver->cleanup();
645 		iounmap(intel_private.registers);
646 		return -ENOMEM;
647 	}
648 
649 #if IS_ENABLED(CONFIG_AGP_INTEL)
650 	global_cache_flush();   /* FIXME: ? */
651 #endif
652 
653 	intel_private.stolen_size = intel_gtt_stolen_size();
654 
655 	intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
656 
657 	ret = intel_gtt_setup_scratch_page();
658 	if (ret != 0) {
659 		intel_gtt_cleanup();
660 		return ret;
661 	}
662 
663 	if (INTEL_GTT_GEN <= 2)
664 		bar = I810_GMADR_BAR;
665 	else
666 		bar = I915_GMADR_BAR;
667 
668 	intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
669 	return 0;
670 }
671 
672 #if IS_ENABLED(CONFIG_AGP_INTEL)
673 static int intel_fake_agp_fetch_size(void)
674 {
675 	int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
676 	unsigned int aper_size;
677 	int i;
678 
679 	aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
680 
681 	for (i = 0; i < num_sizes; i++) {
682 		if (aper_size == intel_fake_agp_sizes[i].size) {
683 			agp_bridge->current_size =
684 				(void *) (intel_fake_agp_sizes + i);
685 			return aper_size;
686 		}
687 	}
688 
689 	return 0;
690 }
691 #endif
692 
693 static void i830_cleanup(void)
694 {
695 }
696 
697 /* The chipset_flush interface needs to get data that has already been
698  * flushed out of the CPU all the way out to main memory, because the GPU
699  * doesn't snoop those buffers.
700  *
701  * The 8xx series doesn't have the same lovely interface for flushing the
702  * chipset write buffers that the later chips do. According to the 865
703  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
704  * that buffer out, we just fill 1KB and clflush it out, on the assumption
705  * that it'll push whatever was in there out.  It appears to work.
706  */
707 static void i830_chipset_flush(void)
708 {
709 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
710 
711 	/* Forcibly evict everything from the CPU write buffers.
712 	 * clflush appears to be insufficient.
713 	 */
714 	wbinvd_on_all_cpus();
715 
716 	/* Now we've only seen documents for this magic bit on 855GM,
717 	 * we hope it exists for the other gen2 chipsets...
718 	 *
719 	 * Also works as advertised on my 845G.
720 	 */
721 	writel(readl(intel_private.registers+I830_HIC) | (1<<31),
722 	       intel_private.registers+I830_HIC);
723 
724 	while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
725 		if (time_after(jiffies, timeout))
726 			break;
727 
728 		udelay(50);
729 	}
730 }
731 
732 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
733 			     unsigned int flags)
734 {
735 	u32 pte_flags = I810_PTE_VALID;
736 
737 	if (flags ==  AGP_USER_CACHED_MEMORY)
738 		pte_flags |= I830_PTE_SYSTEM_CACHED;
739 
740 	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
741 }
742 
743 bool intel_enable_gtt(void)
744 {
745 	u8 __iomem *reg;
746 
747 	if (INTEL_GTT_GEN == 2) {
748 		u16 gmch_ctrl;
749 
750 		pci_read_config_word(intel_private.bridge_dev,
751 				     I830_GMCH_CTRL, &gmch_ctrl);
752 		gmch_ctrl |= I830_GMCH_ENABLED;
753 		pci_write_config_word(intel_private.bridge_dev,
754 				      I830_GMCH_CTRL, gmch_ctrl);
755 
756 		pci_read_config_word(intel_private.bridge_dev,
757 				     I830_GMCH_CTRL, &gmch_ctrl);
758 		if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
759 			dev_err(&intel_private.pcidev->dev,
760 				"failed to enable the GTT: GMCH_CTRL=%x\n",
761 				gmch_ctrl);
762 			return false;
763 		}
764 	}
765 
766 	/* On the resume path we may be adjusting the PGTBL value, so
767 	 * be paranoid and flush all chipset write buffers...
768 	 */
769 	if (INTEL_GTT_GEN >= 3)
770 		writel(0, intel_private.registers+GFX_FLSH_CNTL);
771 
772 	reg = intel_private.registers+I810_PGETBL_CTL;
773 	writel(intel_private.PGETBL_save, reg);
774 	if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
775 		dev_err(&intel_private.pcidev->dev,
776 			"failed to enable the GTT: PGETBL=%x [expected %x]\n",
777 			readl(reg), intel_private.PGETBL_save);
778 		return false;
779 	}
780 
781 	if (INTEL_GTT_GEN >= 3)
782 		writel(0, intel_private.registers+GFX_FLSH_CNTL);
783 
784 	return true;
785 }
786 EXPORT_SYMBOL(intel_enable_gtt);
787 
788 static int i830_setup(void)
789 {
790 	phys_addr_t reg_addr;
791 
792 	reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
793 
794 	intel_private.registers = ioremap(reg_addr, KB(64));
795 	if (!intel_private.registers)
796 		return -ENOMEM;
797 
798 	intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
799 
800 	return 0;
801 }
802 
803 #if IS_ENABLED(CONFIG_AGP_INTEL)
804 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
805 {
806 	agp_bridge->gatt_table_real = NULL;
807 	agp_bridge->gatt_table = NULL;
808 	agp_bridge->gatt_bus_addr = 0;
809 
810 	return 0;
811 }
812 
813 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
814 {
815 	return 0;
816 }
817 
818 static int intel_fake_agp_configure(void)
819 {
820 	if (!intel_enable_gtt())
821 	    return -EIO;
822 
823 	intel_private.clear_fake_agp = true;
824 	agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
825 
826 	return 0;
827 }
828 #endif
829 
830 static bool i830_check_flags(unsigned int flags)
831 {
832 	switch (flags) {
833 	case 0:
834 	case AGP_PHYS_MEMORY:
835 	case AGP_USER_CACHED_MEMORY:
836 	case AGP_USER_MEMORY:
837 		return true;
838 	}
839 
840 	return false;
841 }
842 
843 void intel_gtt_insert_page(dma_addr_t addr,
844 			   unsigned int pg,
845 			   unsigned int flags)
846 {
847 	intel_private.driver->write_entry(addr, pg, flags);
848 	if (intel_private.driver->chipset_flush)
849 		intel_private.driver->chipset_flush();
850 }
851 EXPORT_SYMBOL(intel_gtt_insert_page);
852 
853 void intel_gtt_insert_sg_entries(struct sg_table *st,
854 				 unsigned int pg_start,
855 				 unsigned int flags)
856 {
857 	struct scatterlist *sg;
858 	unsigned int len, m;
859 	int i, j;
860 
861 	j = pg_start;
862 
863 	/* sg may merge pages, but we have to separate
864 	 * per-page addr for GTT */
865 	for_each_sg(st->sgl, sg, st->nents, i) {
866 		len = sg_dma_len(sg) >> PAGE_SHIFT;
867 		for (m = 0; m < len; m++) {
868 			dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
869 			intel_private.driver->write_entry(addr, j, flags);
870 			j++;
871 		}
872 	}
873 	wmb();
874 }
875 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
876 
877 #if IS_ENABLED(CONFIG_AGP_INTEL)
878 static void intel_gtt_insert_pages(unsigned int first_entry,
879 				   unsigned int num_entries,
880 				   struct page **pages,
881 				   unsigned int flags)
882 {
883 	int i, j;
884 
885 	for (i = 0, j = first_entry; i < num_entries; i++, j++) {
886 		dma_addr_t addr = page_to_phys(pages[i]);
887 		intel_private.driver->write_entry(addr,
888 						  j, flags);
889 	}
890 	wmb();
891 }
892 
893 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
894 					 off_t pg_start, int type)
895 {
896 	int ret = -EINVAL;
897 
898 	if (intel_private.clear_fake_agp) {
899 		int start = intel_private.stolen_size / PAGE_SIZE;
900 		int end = intel_private.gtt_mappable_entries;
901 		intel_gtt_clear_range(start, end - start);
902 		intel_private.clear_fake_agp = false;
903 	}
904 
905 	if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
906 		return i810_insert_dcache_entries(mem, pg_start, type);
907 
908 	if (mem->page_count == 0)
909 		goto out;
910 
911 	if (pg_start + mem->page_count > intel_private.gtt_total_entries)
912 		goto out_err;
913 
914 	if (type != mem->type)
915 		goto out_err;
916 
917 	if (!intel_private.driver->check_flags(type))
918 		goto out_err;
919 
920 	if (!mem->is_flushed)
921 		global_cache_flush();
922 
923 	if (intel_private.needs_dmar) {
924 		struct sg_table st;
925 
926 		ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
927 		if (ret != 0)
928 			return ret;
929 
930 		intel_gtt_insert_sg_entries(&st, pg_start, type);
931 		mem->sg_list = st.sgl;
932 		mem->num_sg = st.nents;
933 	} else
934 		intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
935 				       type);
936 
937 out:
938 	ret = 0;
939 out_err:
940 	mem->is_flushed = true;
941 	return ret;
942 }
943 #endif
944 
945 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
946 {
947 	unsigned int i;
948 
949 	for (i = first_entry; i < (first_entry + num_entries); i++) {
950 		intel_private.driver->write_entry(intel_private.scratch_page_dma,
951 						  i, 0);
952 	}
953 	wmb();
954 }
955 EXPORT_SYMBOL(intel_gtt_clear_range);
956 
957 #if IS_ENABLED(CONFIG_AGP_INTEL)
958 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
959 					 off_t pg_start, int type)
960 {
961 	if (mem->page_count == 0)
962 		return 0;
963 
964 	intel_gtt_clear_range(pg_start, mem->page_count);
965 
966 	if (intel_private.needs_dmar) {
967 		intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
968 		mem->sg_list = NULL;
969 		mem->num_sg = 0;
970 	}
971 
972 	return 0;
973 }
974 
975 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
976 						       int type)
977 {
978 	struct agp_memory *new;
979 
980 	if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
981 		if (pg_count != intel_private.num_dcache_entries)
982 			return NULL;
983 
984 		new = agp_create_memory(1);
985 		if (new == NULL)
986 			return NULL;
987 
988 		new->type = AGP_DCACHE_MEMORY;
989 		new->page_count = pg_count;
990 		new->num_scratch_pages = 0;
991 		agp_free_page_array(new);
992 		return new;
993 	}
994 	if (type == AGP_PHYS_MEMORY)
995 		return alloc_agpphysmem_i8xx(pg_count, type);
996 	/* always return NULL for other allocation types for now */
997 	return NULL;
998 }
999 #endif
1000 
1001 static int intel_alloc_chipset_flush_resource(void)
1002 {
1003 	int ret;
1004 	ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1005 				     PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1006 				     pcibios_align_resource, intel_private.bridge_dev);
1007 
1008 	return ret;
1009 }
1010 
1011 static void intel_i915_setup_chipset_flush(void)
1012 {
1013 	int ret;
1014 	u32 temp;
1015 
1016 	pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1017 	if (!(temp & 0x1)) {
1018 		intel_alloc_chipset_flush_resource();
1019 		intel_private.resource_valid = 1;
1020 		pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1021 	} else {
1022 		temp &= ~1;
1023 
1024 		intel_private.resource_valid = 1;
1025 		intel_private.ifp_resource.start = temp;
1026 		intel_private.ifp_resource.end = temp + PAGE_SIZE;
1027 		ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1028 		/* some BIOSes reserve this area in a pnp some don't */
1029 		if (ret)
1030 			intel_private.resource_valid = 0;
1031 	}
1032 }
1033 
1034 static void intel_i965_g33_setup_chipset_flush(void)
1035 {
1036 	u32 temp_hi, temp_lo;
1037 	int ret;
1038 
1039 	pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1040 	pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1041 
1042 	if (!(temp_lo & 0x1)) {
1043 
1044 		intel_alloc_chipset_flush_resource();
1045 
1046 		intel_private.resource_valid = 1;
1047 		pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1048 			upper_32_bits(intel_private.ifp_resource.start));
1049 		pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1050 	} else {
1051 		u64 l64;
1052 
1053 		temp_lo &= ~0x1;
1054 		l64 = ((u64)temp_hi << 32) | temp_lo;
1055 
1056 		intel_private.resource_valid = 1;
1057 		intel_private.ifp_resource.start = l64;
1058 		intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1059 		ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1060 		/* some BIOSes reserve this area in a pnp some don't */
1061 		if (ret)
1062 			intel_private.resource_valid = 0;
1063 	}
1064 }
1065 
1066 static void intel_i9xx_setup_flush(void)
1067 {
1068 	/* return if already configured */
1069 	if (intel_private.ifp_resource.start)
1070 		return;
1071 
1072 	if (INTEL_GTT_GEN == 6)
1073 		return;
1074 
1075 	/* setup a resource for this object */
1076 	intel_private.ifp_resource.name = "Intel Flush Page";
1077 	intel_private.ifp_resource.flags = IORESOURCE_MEM;
1078 
1079 	/* Setup chipset flush for 915 */
1080 	if (IS_G33 || INTEL_GTT_GEN >= 4) {
1081 		intel_i965_g33_setup_chipset_flush();
1082 	} else {
1083 		intel_i915_setup_chipset_flush();
1084 	}
1085 
1086 	if (intel_private.ifp_resource.start)
1087 		intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1088 	if (!intel_private.i9xx_flush_page)
1089 		dev_err(&intel_private.pcidev->dev,
1090 			"can't ioremap flush page - no chipset flushing\n");
1091 }
1092 
1093 static void i9xx_cleanup(void)
1094 {
1095 	if (intel_private.i9xx_flush_page)
1096 		iounmap(intel_private.i9xx_flush_page);
1097 	if (intel_private.resource_valid)
1098 		release_resource(&intel_private.ifp_resource);
1099 	intel_private.ifp_resource.start = 0;
1100 	intel_private.resource_valid = 0;
1101 }
1102 
1103 static void i9xx_chipset_flush(void)
1104 {
1105 	if (intel_private.i9xx_flush_page)
1106 		writel(1, intel_private.i9xx_flush_page);
1107 }
1108 
1109 static void i965_write_entry(dma_addr_t addr,
1110 			     unsigned int entry,
1111 			     unsigned int flags)
1112 {
1113 	u32 pte_flags;
1114 
1115 	pte_flags = I810_PTE_VALID;
1116 	if (flags == AGP_USER_CACHED_MEMORY)
1117 		pte_flags |= I830_PTE_SYSTEM_CACHED;
1118 
1119 	/* Shift high bits down */
1120 	addr |= (addr >> 28) & 0xf0;
1121 	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1122 }
1123 
1124 static int i9xx_setup(void)
1125 {
1126 	phys_addr_t reg_addr;
1127 	int size = KB(512);
1128 
1129 	reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1130 
1131 	intel_private.registers = ioremap(reg_addr, size);
1132 	if (!intel_private.registers)
1133 		return -ENOMEM;
1134 
1135 	switch (INTEL_GTT_GEN) {
1136 	case 3:
1137 		intel_private.gtt_phys_addr =
1138 			pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1139 		break;
1140 	case 5:
1141 		intel_private.gtt_phys_addr = reg_addr + MB(2);
1142 		break;
1143 	default:
1144 		intel_private.gtt_phys_addr = reg_addr + KB(512);
1145 		break;
1146 	}
1147 
1148 	intel_i9xx_setup_flush();
1149 
1150 	return 0;
1151 }
1152 
1153 #if IS_ENABLED(CONFIG_AGP_INTEL)
1154 static const struct agp_bridge_driver intel_fake_agp_driver = {
1155 	.owner			= THIS_MODULE,
1156 	.size_type		= FIXED_APER_SIZE,
1157 	.aperture_sizes		= intel_fake_agp_sizes,
1158 	.num_aperture_sizes	= ARRAY_SIZE(intel_fake_agp_sizes),
1159 	.configure		= intel_fake_agp_configure,
1160 	.fetch_size		= intel_fake_agp_fetch_size,
1161 	.cleanup		= intel_gtt_cleanup,
1162 	.agp_enable		= intel_fake_agp_enable,
1163 	.cache_flush		= global_cache_flush,
1164 	.create_gatt_table	= intel_fake_agp_create_gatt_table,
1165 	.free_gatt_table	= intel_fake_agp_free_gatt_table,
1166 	.insert_memory		= intel_fake_agp_insert_entries,
1167 	.remove_memory		= intel_fake_agp_remove_entries,
1168 	.alloc_by_type		= intel_fake_agp_alloc_by_type,
1169 	.free_by_type		= intel_i810_free_by_type,
1170 	.agp_alloc_page		= agp_generic_alloc_page,
1171 	.agp_alloc_pages        = agp_generic_alloc_pages,
1172 	.agp_destroy_page	= agp_generic_destroy_page,
1173 	.agp_destroy_pages      = agp_generic_destroy_pages,
1174 };
1175 #endif
1176 
1177 static const struct intel_gtt_driver i81x_gtt_driver = {
1178 	.gen = 1,
1179 	.has_pgtbl_enable = 1,
1180 	.dma_mask_size = 32,
1181 	.setup = i810_setup,
1182 	.cleanup = i810_cleanup,
1183 	.check_flags = i830_check_flags,
1184 	.write_entry = i810_write_entry,
1185 };
1186 static const struct intel_gtt_driver i8xx_gtt_driver = {
1187 	.gen = 2,
1188 	.has_pgtbl_enable = 1,
1189 	.setup = i830_setup,
1190 	.cleanup = i830_cleanup,
1191 	.write_entry = i830_write_entry,
1192 	.dma_mask_size = 32,
1193 	.check_flags = i830_check_flags,
1194 	.chipset_flush = i830_chipset_flush,
1195 };
1196 static const struct intel_gtt_driver i915_gtt_driver = {
1197 	.gen = 3,
1198 	.has_pgtbl_enable = 1,
1199 	.setup = i9xx_setup,
1200 	.cleanup = i9xx_cleanup,
1201 	/* i945 is the last gpu to need phys mem (for overlay and cursors). */
1202 	.write_entry = i830_write_entry,
1203 	.dma_mask_size = 32,
1204 	.check_flags = i830_check_flags,
1205 	.chipset_flush = i9xx_chipset_flush,
1206 };
1207 static const struct intel_gtt_driver g33_gtt_driver = {
1208 	.gen = 3,
1209 	.is_g33 = 1,
1210 	.setup = i9xx_setup,
1211 	.cleanup = i9xx_cleanup,
1212 	.write_entry = i965_write_entry,
1213 	.dma_mask_size = 36,
1214 	.check_flags = i830_check_flags,
1215 	.chipset_flush = i9xx_chipset_flush,
1216 };
1217 static const struct intel_gtt_driver pineview_gtt_driver = {
1218 	.gen = 3,
1219 	.is_pineview = 1, .is_g33 = 1,
1220 	.setup = i9xx_setup,
1221 	.cleanup = i9xx_cleanup,
1222 	.write_entry = i965_write_entry,
1223 	.dma_mask_size = 36,
1224 	.check_flags = i830_check_flags,
1225 	.chipset_flush = i9xx_chipset_flush,
1226 };
1227 static const struct intel_gtt_driver i965_gtt_driver = {
1228 	.gen = 4,
1229 	.has_pgtbl_enable = 1,
1230 	.setup = i9xx_setup,
1231 	.cleanup = i9xx_cleanup,
1232 	.write_entry = i965_write_entry,
1233 	.dma_mask_size = 36,
1234 	.check_flags = i830_check_flags,
1235 	.chipset_flush = i9xx_chipset_flush,
1236 };
1237 static const struct intel_gtt_driver g4x_gtt_driver = {
1238 	.gen = 5,
1239 	.setup = i9xx_setup,
1240 	.cleanup = i9xx_cleanup,
1241 	.write_entry = i965_write_entry,
1242 	.dma_mask_size = 36,
1243 	.check_flags = i830_check_flags,
1244 	.chipset_flush = i9xx_chipset_flush,
1245 };
1246 static const struct intel_gtt_driver ironlake_gtt_driver = {
1247 	.gen = 5,
1248 	.is_ironlake = 1,
1249 	.setup = i9xx_setup,
1250 	.cleanup = i9xx_cleanup,
1251 	.write_entry = i965_write_entry,
1252 	.dma_mask_size = 36,
1253 	.check_flags = i830_check_flags,
1254 	.chipset_flush = i9xx_chipset_flush,
1255 };
1256 
1257 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1258  * driver and gmch_driver must be non-null, and find_gmch will determine
1259  * which one should be used if a gmch_chip_id is present.
1260  */
1261 static const struct intel_gtt_driver_description {
1262 	unsigned int gmch_chip_id;
1263 	char *name;
1264 	const struct intel_gtt_driver *gtt_driver;
1265 } intel_gtt_chipsets[] = {
1266 	{ PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1267 		&i81x_gtt_driver},
1268 	{ PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1269 		&i81x_gtt_driver},
1270 	{ PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1271 		&i81x_gtt_driver},
1272 	{ PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1273 		&i81x_gtt_driver},
1274 	{ PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1275 		&i8xx_gtt_driver},
1276 	{ PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1277 		&i8xx_gtt_driver},
1278 	{ PCI_DEVICE_ID_INTEL_82854_IG, "854",
1279 		&i8xx_gtt_driver},
1280 	{ PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1281 		&i8xx_gtt_driver},
1282 	{ PCI_DEVICE_ID_INTEL_82865_IG, "865",
1283 		&i8xx_gtt_driver},
1284 	{ PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1285 		&i915_gtt_driver },
1286 	{ PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1287 		&i915_gtt_driver },
1288 	{ PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1289 		&i915_gtt_driver },
1290 	{ PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1291 		&i915_gtt_driver },
1292 	{ PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1293 		&i915_gtt_driver },
1294 	{ PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1295 		&i915_gtt_driver },
1296 	{ PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1297 		&i965_gtt_driver },
1298 	{ PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1299 		&i965_gtt_driver },
1300 	{ PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1301 		&i965_gtt_driver },
1302 	{ PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1303 		&i965_gtt_driver },
1304 	{ PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1305 		&i965_gtt_driver },
1306 	{ PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1307 		&i965_gtt_driver },
1308 	{ PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1309 		&g33_gtt_driver },
1310 	{ PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1311 		&g33_gtt_driver },
1312 	{ PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1313 		&g33_gtt_driver },
1314 	{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1315 		&pineview_gtt_driver },
1316 	{ PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1317 		&pineview_gtt_driver },
1318 	{ PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1319 		&g4x_gtt_driver },
1320 	{ PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1321 		&g4x_gtt_driver },
1322 	{ PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1323 		&g4x_gtt_driver },
1324 	{ PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1325 		&g4x_gtt_driver },
1326 	{ PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1327 		&g4x_gtt_driver },
1328 	{ PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1329 		&g4x_gtt_driver },
1330 	{ PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1331 		&g4x_gtt_driver },
1332 	{ PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1333 	    "HD Graphics", &ironlake_gtt_driver },
1334 	{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1335 	    "HD Graphics", &ironlake_gtt_driver },
1336 	{ 0, NULL, NULL }
1337 };
1338 
1339 static int find_gmch(u16 device)
1340 {
1341 	struct pci_dev *gmch_device;
1342 
1343 	gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1344 	if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1345 		gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1346 					     device, gmch_device);
1347 	}
1348 
1349 	if (!gmch_device)
1350 		return 0;
1351 
1352 	intel_private.pcidev = gmch_device;
1353 	return 1;
1354 }
1355 
1356 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1357 		     struct agp_bridge_data *bridge)
1358 {
1359 	int i, mask;
1360 
1361 	for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1362 		if (gpu_pdev) {
1363 			if (gpu_pdev->device ==
1364 			    intel_gtt_chipsets[i].gmch_chip_id) {
1365 				intel_private.pcidev = pci_dev_get(gpu_pdev);
1366 				intel_private.driver =
1367 					intel_gtt_chipsets[i].gtt_driver;
1368 
1369 				break;
1370 			}
1371 		} else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1372 			intel_private.driver =
1373 				intel_gtt_chipsets[i].gtt_driver;
1374 			break;
1375 		}
1376 	}
1377 
1378 	if (!intel_private.driver)
1379 		return 0;
1380 
1381 #if IS_ENABLED(CONFIG_AGP_INTEL)
1382 	if (bridge) {
1383 		if (INTEL_GTT_GEN > 1)
1384 			return 0;
1385 
1386 		bridge->driver = &intel_fake_agp_driver;
1387 		bridge->dev_private_data = &intel_private;
1388 		bridge->dev = bridge_pdev;
1389 	}
1390 #endif
1391 
1392 
1393 	/*
1394 	 * Can be called from the fake agp driver but also directly from
1395 	 * drm/i915.ko. Hence we need to check whether everything is set up
1396 	 * already.
1397 	 */
1398 	if (intel_private.refcount++)
1399 		return 1;
1400 
1401 	intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1402 
1403 	dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1404 
1405 	mask = intel_private.driver->dma_mask_size;
1406 	if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1407 		dev_err(&intel_private.pcidev->dev,
1408 			"set gfx device dma mask %d-bit failed!\n", mask);
1409 	else
1410 		pci_set_consistent_dma_mask(intel_private.pcidev,
1411 					    DMA_BIT_MASK(mask));
1412 
1413 	if (intel_gtt_init() != 0) {
1414 		intel_gmch_remove();
1415 
1416 		return 0;
1417 	}
1418 
1419 	return 1;
1420 }
1421 EXPORT_SYMBOL(intel_gmch_probe);
1422 
1423 void intel_gtt_get(u64 *gtt_total, size_t *stolen_size,
1424 		   phys_addr_t *mappable_base, u64 *mappable_end)
1425 {
1426 	*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1427 	*stolen_size = intel_private.stolen_size;
1428 	*mappable_base = intel_private.gma_bus_addr;
1429 	*mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1430 }
1431 EXPORT_SYMBOL(intel_gtt_get);
1432 
1433 void intel_gtt_chipset_flush(void)
1434 {
1435 	if (intel_private.driver->chipset_flush)
1436 		intel_private.driver->chipset_flush();
1437 }
1438 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1439 
1440 void intel_gmch_remove(void)
1441 {
1442 	if (--intel_private.refcount)
1443 		return;
1444 
1445 	if (intel_private.scratch_page)
1446 		intel_gtt_teardown_scratch_page();
1447 	if (intel_private.pcidev)
1448 		pci_dev_put(intel_private.pcidev);
1449 	if (intel_private.bridge_dev)
1450 		pci_dev_put(intel_private.bridge_dev);
1451 	intel_private.driver = NULL;
1452 }
1453 EXPORT_SYMBOL(intel_gmch_remove);
1454 
1455 MODULE_AUTHOR("Dave Jones, Various @Intel");
1456 MODULE_LICENSE("GPL and additional rights");
1457