1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18f51b7662SDaniel Vetter /* 19f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 20f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 21f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 22f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 23f51b7662SDaniel Vetter */ 24f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 25f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 26f51b7662SDaniel Vetter #endif 27f51b7662SDaniel Vetter 28f51b7662SDaniel Vetter static const struct aper_size_info_fixed intel_i810_sizes[] = 29f51b7662SDaniel Vetter { 30f51b7662SDaniel Vetter {64, 16384, 4}, 31f51b7662SDaniel Vetter /* The 32M mode still requires a 64k gatt */ 32f51b7662SDaniel Vetter {32, 8192, 4} 33f51b7662SDaniel Vetter }; 34f51b7662SDaniel Vetter 35f51b7662SDaniel Vetter #define AGP_DCACHE_MEMORY 1 36f51b7662SDaniel Vetter #define AGP_PHYS_MEMORY 2 37f51b7662SDaniel Vetter #define INTEL_AGP_CACHED_MEMORY 3 38f51b7662SDaniel Vetter 39f51b7662SDaniel Vetter static struct gatt_mask intel_i810_masks[] = 40f51b7662SDaniel Vetter { 41f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 42f51b7662SDaniel Vetter {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 43f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 44f51b7662SDaniel Vetter {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 45f51b7662SDaniel Vetter .type = INTEL_AGP_CACHED_MEMORY} 46f51b7662SDaniel Vetter }; 47f51b7662SDaniel Vetter 48f51b7662SDaniel Vetter static struct _intel_private { 49f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 50f51b7662SDaniel Vetter u8 __iomem *registers; 51f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 52f51b7662SDaniel Vetter int num_dcache_entries; 53f51b7662SDaniel Vetter /* gtt_entries is the number of gtt entries that are already mapped 54f51b7662SDaniel Vetter * to stolen memory. Stolen memory is larger than the memory mapped 55f51b7662SDaniel Vetter * through gtt_entries, as it includes some reserved space for the BIOS 56f51b7662SDaniel Vetter * popup and for the GTT. 57f51b7662SDaniel Vetter */ 58f51b7662SDaniel Vetter int gtt_entries; /* i830+ */ 59f51b7662SDaniel Vetter int gtt_total_size; 60f51b7662SDaniel Vetter union { 61f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 62f51b7662SDaniel Vetter void *i8xx_flush_page; 63f51b7662SDaniel Vetter }; 64f51b7662SDaniel Vetter struct page *i8xx_page; 65f51b7662SDaniel Vetter struct resource ifp_resource; 66f51b7662SDaniel Vetter int resource_valid; 67f51b7662SDaniel Vetter } intel_private; 68f51b7662SDaniel Vetter 69f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 70f51b7662SDaniel Vetter static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 71f51b7662SDaniel Vetter { 72f51b7662SDaniel Vetter *ret = pci_map_page(intel_private.pcidev, page, 0, 73f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 74f51b7662SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 75f51b7662SDaniel Vetter return -EINVAL; 76f51b7662SDaniel Vetter return 0; 77f51b7662SDaniel Vetter } 78f51b7662SDaniel Vetter 79f51b7662SDaniel Vetter static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 80f51b7662SDaniel Vetter { 81f51b7662SDaniel Vetter pci_unmap_page(intel_private.pcidev, dma, 82f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 83f51b7662SDaniel Vetter } 84f51b7662SDaniel Vetter 85f51b7662SDaniel Vetter static void intel_agp_free_sglist(struct agp_memory *mem) 86f51b7662SDaniel Vetter { 87f51b7662SDaniel Vetter struct sg_table st; 88f51b7662SDaniel Vetter 89f51b7662SDaniel Vetter st.sgl = mem->sg_list; 90f51b7662SDaniel Vetter st.orig_nents = st.nents = mem->page_count; 91f51b7662SDaniel Vetter 92f51b7662SDaniel Vetter sg_free_table(&st); 93f51b7662SDaniel Vetter 94f51b7662SDaniel Vetter mem->sg_list = NULL; 95f51b7662SDaniel Vetter mem->num_sg = 0; 96f51b7662SDaniel Vetter } 97f51b7662SDaniel Vetter 98f51b7662SDaniel Vetter static int intel_agp_map_memory(struct agp_memory *mem) 99f51b7662SDaniel Vetter { 100f51b7662SDaniel Vetter struct sg_table st; 101f51b7662SDaniel Vetter struct scatterlist *sg; 102f51b7662SDaniel Vetter int i; 103f51b7662SDaniel Vetter 104f51b7662SDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 105f51b7662SDaniel Vetter 106f51b7662SDaniel Vetter if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 107f51b7662SDaniel Vetter return -ENOMEM; 108f51b7662SDaniel Vetter 109f51b7662SDaniel Vetter mem->sg_list = sg = st.sgl; 110f51b7662SDaniel Vetter 111f51b7662SDaniel Vetter for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 112f51b7662SDaniel Vetter sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 113f51b7662SDaniel Vetter 114f51b7662SDaniel Vetter mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 115f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 116f51b7662SDaniel Vetter if (unlikely(!mem->num_sg)) { 117f51b7662SDaniel Vetter intel_agp_free_sglist(mem); 118f51b7662SDaniel Vetter return -ENOMEM; 119f51b7662SDaniel Vetter } 120f51b7662SDaniel Vetter return 0; 121f51b7662SDaniel Vetter } 122f51b7662SDaniel Vetter 123f51b7662SDaniel Vetter static void intel_agp_unmap_memory(struct agp_memory *mem) 124f51b7662SDaniel Vetter { 125f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 126f51b7662SDaniel Vetter 127f51b7662SDaniel Vetter pci_unmap_sg(intel_private.pcidev, mem->sg_list, 128f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 129f51b7662SDaniel Vetter intel_agp_free_sglist(mem); 130f51b7662SDaniel Vetter } 131f51b7662SDaniel Vetter 132f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 133f51b7662SDaniel Vetter off_t pg_start, int mask_type) 134f51b7662SDaniel Vetter { 135f51b7662SDaniel Vetter struct scatterlist *sg; 136f51b7662SDaniel Vetter int i, j; 137f51b7662SDaniel Vetter 138f51b7662SDaniel Vetter j = pg_start; 139f51b7662SDaniel Vetter 140f51b7662SDaniel Vetter WARN_ON(!mem->num_sg); 141f51b7662SDaniel Vetter 142f51b7662SDaniel Vetter if (mem->num_sg == mem->page_count) { 143f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->page_count, i) { 144f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 145f51b7662SDaniel Vetter sg_dma_address(sg), mask_type), 146f51b7662SDaniel Vetter intel_private.gtt+j); 147f51b7662SDaniel Vetter j++; 148f51b7662SDaniel Vetter } 149f51b7662SDaniel Vetter } else { 150f51b7662SDaniel Vetter /* sg may merge pages, but we have to separate 151f51b7662SDaniel Vetter * per-page addr for GTT */ 152f51b7662SDaniel Vetter unsigned int len, m; 153f51b7662SDaniel Vetter 154f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 155f51b7662SDaniel Vetter len = sg_dma_len(sg) / PAGE_SIZE; 156f51b7662SDaniel Vetter for (m = 0; m < len; m++) { 157f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 158f51b7662SDaniel Vetter sg_dma_address(sg) + m * PAGE_SIZE, 159f51b7662SDaniel Vetter mask_type), 160f51b7662SDaniel Vetter intel_private.gtt+j); 161f51b7662SDaniel Vetter j++; 162f51b7662SDaniel Vetter } 163f51b7662SDaniel Vetter } 164f51b7662SDaniel Vetter } 165f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 166f51b7662SDaniel Vetter } 167f51b7662SDaniel Vetter 168f51b7662SDaniel Vetter #else 169f51b7662SDaniel Vetter 170f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 171f51b7662SDaniel Vetter off_t pg_start, int mask_type) 172f51b7662SDaniel Vetter { 173f51b7662SDaniel Vetter int i, j; 174f51b7662SDaniel Vetter u32 cache_bits = 0; 175f51b7662SDaniel Vetter 176f51b7662SDaniel Vetter if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || 177f51b7662SDaniel Vetter agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) 178f51b7662SDaniel Vetter { 179f51b7662SDaniel Vetter cache_bits = I830_PTE_SYSTEM_CACHED; 180f51b7662SDaniel Vetter } 181f51b7662SDaniel Vetter 182f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 183f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 184f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 185f51b7662SDaniel Vetter intel_private.gtt+j); 186f51b7662SDaniel Vetter } 187f51b7662SDaniel Vetter 188f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 189f51b7662SDaniel Vetter } 190f51b7662SDaniel Vetter 191f51b7662SDaniel Vetter #endif 192f51b7662SDaniel Vetter 193f51b7662SDaniel Vetter static int intel_i810_fetch_size(void) 194f51b7662SDaniel Vetter { 195f51b7662SDaniel Vetter u32 smram_miscc; 196f51b7662SDaniel Vetter struct aper_size_info_fixed *values; 197f51b7662SDaniel Vetter 198f51b7662SDaniel Vetter pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 199f51b7662SDaniel Vetter values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 200f51b7662SDaniel Vetter 201f51b7662SDaniel Vetter if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 202f51b7662SDaniel Vetter dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 203f51b7662SDaniel Vetter return 0; 204f51b7662SDaniel Vetter } 205f51b7662SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 206f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values + 1); 207f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 1; 208f51b7662SDaniel Vetter return values[1].size; 209f51b7662SDaniel Vetter } else { 210f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values); 211f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 212f51b7662SDaniel Vetter return values[0].size; 213f51b7662SDaniel Vetter } 214f51b7662SDaniel Vetter 215f51b7662SDaniel Vetter return 0; 216f51b7662SDaniel Vetter } 217f51b7662SDaniel Vetter 218f51b7662SDaniel Vetter static int intel_i810_configure(void) 219f51b7662SDaniel Vetter { 220f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 221f51b7662SDaniel Vetter u32 temp; 222f51b7662SDaniel Vetter int i; 223f51b7662SDaniel Vetter 224f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 225f51b7662SDaniel Vetter 226f51b7662SDaniel Vetter if (!intel_private.registers) { 227f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 228f51b7662SDaniel Vetter temp &= 0xfff80000; 229f51b7662SDaniel Vetter 230f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 231f51b7662SDaniel Vetter if (!intel_private.registers) { 232f51b7662SDaniel Vetter dev_err(&intel_private.pcidev->dev, 233f51b7662SDaniel Vetter "can't remap memory\n"); 234f51b7662SDaniel Vetter return -ENOMEM; 235f51b7662SDaniel Vetter } 236f51b7662SDaniel Vetter } 237f51b7662SDaniel Vetter 238f51b7662SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 239f51b7662SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 240f51b7662SDaniel Vetter /* This will need to be dynamically assigned */ 241f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 242f51b7662SDaniel Vetter "detected 4MB dedicated video ram\n"); 243f51b7662SDaniel Vetter intel_private.num_dcache_entries = 1024; 244f51b7662SDaniel Vetter } 245f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 246f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 247f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 248f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 249f51b7662SDaniel Vetter 250f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 251f51b7662SDaniel Vetter for (i = 0; i < current_size->num_entries; i++) { 252f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 253f51b7662SDaniel Vetter } 254f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 255f51b7662SDaniel Vetter } 256f51b7662SDaniel Vetter global_cache_flush(); 257f51b7662SDaniel Vetter return 0; 258f51b7662SDaniel Vetter } 259f51b7662SDaniel Vetter 260f51b7662SDaniel Vetter static void intel_i810_cleanup(void) 261f51b7662SDaniel Vetter { 262f51b7662SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 263f51b7662SDaniel Vetter readl(intel_private.registers); /* PCI Posting. */ 264f51b7662SDaniel Vetter iounmap(intel_private.registers); 265f51b7662SDaniel Vetter } 266f51b7662SDaniel Vetter 267f51b7662SDaniel Vetter static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 268f51b7662SDaniel Vetter { 269f51b7662SDaniel Vetter return; 270f51b7662SDaniel Vetter } 271f51b7662SDaniel Vetter 272f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 273f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 274f51b7662SDaniel Vetter { 275f51b7662SDaniel Vetter struct page *page; 276f51b7662SDaniel Vetter 277f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 278f51b7662SDaniel Vetter if (page == NULL) 279f51b7662SDaniel Vetter return NULL; 280f51b7662SDaniel Vetter 281f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 282f51b7662SDaniel Vetter set_pages_wb(page, 4); 283f51b7662SDaniel Vetter __free_pages(page, 2); 284f51b7662SDaniel Vetter return NULL; 285f51b7662SDaniel Vetter } 286f51b7662SDaniel Vetter get_page(page); 287f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 288f51b7662SDaniel Vetter return page; 289f51b7662SDaniel Vetter } 290f51b7662SDaniel Vetter 291f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 292f51b7662SDaniel Vetter { 293f51b7662SDaniel Vetter if (page == NULL) 294f51b7662SDaniel Vetter return; 295f51b7662SDaniel Vetter 296f51b7662SDaniel Vetter set_pages_wb(page, 4); 297f51b7662SDaniel Vetter put_page(page); 298f51b7662SDaniel Vetter __free_pages(page, 2); 299f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 300f51b7662SDaniel Vetter } 301f51b7662SDaniel Vetter 302f51b7662SDaniel Vetter static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 303f51b7662SDaniel Vetter int type) 304f51b7662SDaniel Vetter { 305f51b7662SDaniel Vetter if (type < AGP_USER_TYPES) 306f51b7662SDaniel Vetter return type; 307f51b7662SDaniel Vetter else if (type == AGP_USER_CACHED_MEMORY) 308f51b7662SDaniel Vetter return INTEL_AGP_CACHED_MEMORY; 309f51b7662SDaniel Vetter else 310f51b7662SDaniel Vetter return 0; 311f51b7662SDaniel Vetter } 312f51b7662SDaniel Vetter 313f51b7662SDaniel Vetter static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 314f51b7662SDaniel Vetter int type) 315f51b7662SDaniel Vetter { 316f51b7662SDaniel Vetter int i, j, num_entries; 317f51b7662SDaniel Vetter void *temp; 318f51b7662SDaniel Vetter int ret = -EINVAL; 319f51b7662SDaniel Vetter int mask_type; 320f51b7662SDaniel Vetter 321f51b7662SDaniel Vetter if (mem->page_count == 0) 322f51b7662SDaniel Vetter goto out; 323f51b7662SDaniel Vetter 324f51b7662SDaniel Vetter temp = agp_bridge->current_size; 325f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 326f51b7662SDaniel Vetter 327f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 328f51b7662SDaniel Vetter goto out_err; 329f51b7662SDaniel Vetter 330f51b7662SDaniel Vetter 331f51b7662SDaniel Vetter for (j = pg_start; j < (pg_start + mem->page_count); j++) { 332f51b7662SDaniel Vetter if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 333f51b7662SDaniel Vetter ret = -EBUSY; 334f51b7662SDaniel Vetter goto out_err; 335f51b7662SDaniel Vetter } 336f51b7662SDaniel Vetter } 337f51b7662SDaniel Vetter 338f51b7662SDaniel Vetter if (type != mem->type) 339f51b7662SDaniel Vetter goto out_err; 340f51b7662SDaniel Vetter 341f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 342f51b7662SDaniel Vetter 343f51b7662SDaniel Vetter switch (mask_type) { 344f51b7662SDaniel Vetter case AGP_DCACHE_MEMORY: 345f51b7662SDaniel Vetter if (!mem->is_flushed) 346f51b7662SDaniel Vetter global_cache_flush(); 347f51b7662SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 348f51b7662SDaniel Vetter writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 349f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(i*4)); 350f51b7662SDaniel Vetter } 351f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 352f51b7662SDaniel Vetter break; 353f51b7662SDaniel Vetter case AGP_PHYS_MEMORY: 354f51b7662SDaniel Vetter case AGP_NORMAL_MEMORY: 355f51b7662SDaniel Vetter if (!mem->is_flushed) 356f51b7662SDaniel Vetter global_cache_flush(); 357f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 358f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 359f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 360f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(j*4)); 361f51b7662SDaniel Vetter } 362f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 363f51b7662SDaniel Vetter break; 364f51b7662SDaniel Vetter default: 365f51b7662SDaniel Vetter goto out_err; 366f51b7662SDaniel Vetter } 367f51b7662SDaniel Vetter 368f51b7662SDaniel Vetter out: 369f51b7662SDaniel Vetter ret = 0; 370f51b7662SDaniel Vetter out_err: 371f51b7662SDaniel Vetter mem->is_flushed = true; 372f51b7662SDaniel Vetter return ret; 373f51b7662SDaniel Vetter } 374f51b7662SDaniel Vetter 375f51b7662SDaniel Vetter static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 376f51b7662SDaniel Vetter int type) 377f51b7662SDaniel Vetter { 378f51b7662SDaniel Vetter int i; 379f51b7662SDaniel Vetter 380f51b7662SDaniel Vetter if (mem->page_count == 0) 381f51b7662SDaniel Vetter return 0; 382f51b7662SDaniel Vetter 383f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 384f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 385f51b7662SDaniel Vetter } 386f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 387f51b7662SDaniel Vetter 388f51b7662SDaniel Vetter return 0; 389f51b7662SDaniel Vetter } 390f51b7662SDaniel Vetter 391f51b7662SDaniel Vetter /* 392f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 393f51b7662SDaniel Vetter * pointer into hardware. 394f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 395f51b7662SDaniel Vetter */ 396f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 397f51b7662SDaniel Vetter { 398f51b7662SDaniel Vetter struct agp_memory *new; 399f51b7662SDaniel Vetter struct page *page; 400f51b7662SDaniel Vetter 401f51b7662SDaniel Vetter switch (pg_count) { 402f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 403f51b7662SDaniel Vetter break; 404f51b7662SDaniel Vetter case 4: 405f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 406f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 407f51b7662SDaniel Vetter break; 408f51b7662SDaniel Vetter default: 409f51b7662SDaniel Vetter return NULL; 410f51b7662SDaniel Vetter } 411f51b7662SDaniel Vetter 412f51b7662SDaniel Vetter if (page == NULL) 413f51b7662SDaniel Vetter return NULL; 414f51b7662SDaniel Vetter 415f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 416f51b7662SDaniel Vetter if (new == NULL) 417f51b7662SDaniel Vetter return NULL; 418f51b7662SDaniel Vetter 419f51b7662SDaniel Vetter new->pages[0] = page; 420f51b7662SDaniel Vetter if (pg_count == 4) { 421f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 422f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 423f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 424f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 425f51b7662SDaniel Vetter } 426f51b7662SDaniel Vetter new->page_count = pg_count; 427f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 428f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 429f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 430f51b7662SDaniel Vetter return new; 431f51b7662SDaniel Vetter } 432f51b7662SDaniel Vetter 433f51b7662SDaniel Vetter static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 434f51b7662SDaniel Vetter { 435f51b7662SDaniel Vetter struct agp_memory *new; 436f51b7662SDaniel Vetter 437f51b7662SDaniel Vetter if (type == AGP_DCACHE_MEMORY) { 438f51b7662SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 439f51b7662SDaniel Vetter return NULL; 440f51b7662SDaniel Vetter 441f51b7662SDaniel Vetter new = agp_create_memory(1); 442f51b7662SDaniel Vetter if (new == NULL) 443f51b7662SDaniel Vetter return NULL; 444f51b7662SDaniel Vetter 445f51b7662SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 446f51b7662SDaniel Vetter new->page_count = pg_count; 447f51b7662SDaniel Vetter new->num_scratch_pages = 0; 448f51b7662SDaniel Vetter agp_free_page_array(new); 449f51b7662SDaniel Vetter return new; 450f51b7662SDaniel Vetter } 451f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 452f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 453f51b7662SDaniel Vetter return NULL; 454f51b7662SDaniel Vetter } 455f51b7662SDaniel Vetter 456f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 457f51b7662SDaniel Vetter { 458f51b7662SDaniel Vetter agp_free_key(curr->key); 459f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 460f51b7662SDaniel Vetter if (curr->page_count == 4) 461f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 462f51b7662SDaniel Vetter else { 463f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 464f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 465f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 466f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 467f51b7662SDaniel Vetter } 468f51b7662SDaniel Vetter agp_free_page_array(curr); 469f51b7662SDaniel Vetter } 470f51b7662SDaniel Vetter kfree(curr); 471f51b7662SDaniel Vetter } 472f51b7662SDaniel Vetter 473f51b7662SDaniel Vetter static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 474f51b7662SDaniel Vetter dma_addr_t addr, int type) 475f51b7662SDaniel Vetter { 476f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 477f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 478f51b7662SDaniel Vetter } 479f51b7662SDaniel Vetter 480f51b7662SDaniel Vetter static struct aper_size_info_fixed intel_i830_sizes[] = 481f51b7662SDaniel Vetter { 482f51b7662SDaniel Vetter {128, 32768, 5}, 483f51b7662SDaniel Vetter /* The 64M mode still requires a 128k gatt */ 484f51b7662SDaniel Vetter {64, 16384, 5}, 485f51b7662SDaniel Vetter {256, 65536, 6}, 486f51b7662SDaniel Vetter {512, 131072, 7}, 487f51b7662SDaniel Vetter }; 488f51b7662SDaniel Vetter 489f51b7662SDaniel Vetter static void intel_i830_init_gtt_entries(void) 490f51b7662SDaniel Vetter { 491f51b7662SDaniel Vetter u16 gmch_ctrl; 492f51b7662SDaniel Vetter int gtt_entries = 0; 493f51b7662SDaniel Vetter u8 rdct; 494f51b7662SDaniel Vetter int local = 0; 495f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 496f51b7662SDaniel Vetter int size; /* reserved space (in kb) at the top of stolen memory */ 497f51b7662SDaniel Vetter 498f51b7662SDaniel Vetter pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 499f51b7662SDaniel Vetter 500f51b7662SDaniel Vetter if (IS_I965) { 501f51b7662SDaniel Vetter u32 pgetbl_ctl; 502f51b7662SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 503f51b7662SDaniel Vetter 504f51b7662SDaniel Vetter /* The 965 has a field telling us the size of the GTT, 505f51b7662SDaniel Vetter * which may be larger than what is necessary to map the 506f51b7662SDaniel Vetter * aperture. 507f51b7662SDaniel Vetter */ 508f51b7662SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 509f51b7662SDaniel Vetter case I965_PGETBL_SIZE_128KB: 510f51b7662SDaniel Vetter size = 128; 511f51b7662SDaniel Vetter break; 512f51b7662SDaniel Vetter case I965_PGETBL_SIZE_256KB: 513f51b7662SDaniel Vetter size = 256; 514f51b7662SDaniel Vetter break; 515f51b7662SDaniel Vetter case I965_PGETBL_SIZE_512KB: 516f51b7662SDaniel Vetter size = 512; 517f51b7662SDaniel Vetter break; 518f51b7662SDaniel Vetter case I965_PGETBL_SIZE_1MB: 519f51b7662SDaniel Vetter size = 1024; 520f51b7662SDaniel Vetter break; 521f51b7662SDaniel Vetter case I965_PGETBL_SIZE_2MB: 522f51b7662SDaniel Vetter size = 2048; 523f51b7662SDaniel Vetter break; 524f51b7662SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 525f51b7662SDaniel Vetter size = 1024 + 512; 526f51b7662SDaniel Vetter break; 527f51b7662SDaniel Vetter default: 528f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 529f51b7662SDaniel Vetter "unknown page table size, assuming 512KB\n"); 530f51b7662SDaniel Vetter size = 512; 531f51b7662SDaniel Vetter } 532f51b7662SDaniel Vetter size += 4; /* add in BIOS popup space */ 533f51b7662SDaniel Vetter } else if (IS_G33 && !IS_PINEVIEW) { 534f51b7662SDaniel Vetter /* G33's GTT size defined in gmch_ctrl */ 535f51b7662SDaniel Vetter switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 536f51b7662SDaniel Vetter case G33_PGETBL_SIZE_1M: 537f51b7662SDaniel Vetter size = 1024; 538f51b7662SDaniel Vetter break; 539f51b7662SDaniel Vetter case G33_PGETBL_SIZE_2M: 540f51b7662SDaniel Vetter size = 2048; 541f51b7662SDaniel Vetter break; 542f51b7662SDaniel Vetter default: 543f51b7662SDaniel Vetter dev_info(&agp_bridge->dev->dev, 544f51b7662SDaniel Vetter "unknown page table size 0x%x, assuming 512KB\n", 545f51b7662SDaniel Vetter (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 546f51b7662SDaniel Vetter size = 512; 547f51b7662SDaniel Vetter } 548f51b7662SDaniel Vetter size += 4; 549f51b7662SDaniel Vetter } else if (IS_G4X || IS_PINEVIEW) { 550f51b7662SDaniel Vetter /* On 4 series hardware, GTT stolen is separate from graphics 551f51b7662SDaniel Vetter * stolen, ignore it in stolen gtt entries counting. However, 552f51b7662SDaniel Vetter * 4KB of the stolen memory doesn't get mapped to the GTT. 553f51b7662SDaniel Vetter */ 554f51b7662SDaniel Vetter size = 4; 555f51b7662SDaniel Vetter } else { 556f51b7662SDaniel Vetter /* On previous hardware, the GTT size was just what was 557f51b7662SDaniel Vetter * required to map the aperture. 558f51b7662SDaniel Vetter */ 559f51b7662SDaniel Vetter size = agp_bridge->driver->fetch_size() + 4; 560f51b7662SDaniel Vetter } 561f51b7662SDaniel Vetter 562f51b7662SDaniel Vetter if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 563f51b7662SDaniel Vetter agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 564f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 565f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 566f51b7662SDaniel Vetter gtt_entries = KB(512) - KB(size); 567f51b7662SDaniel Vetter break; 568f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 569f51b7662SDaniel Vetter gtt_entries = MB(1) - KB(size); 570f51b7662SDaniel Vetter break; 571f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 572f51b7662SDaniel Vetter gtt_entries = MB(8) - KB(size); 573f51b7662SDaniel Vetter break; 574f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 575f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 576f51b7662SDaniel Vetter gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 577f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 578f51b7662SDaniel Vetter local = 1; 579f51b7662SDaniel Vetter break; 580f51b7662SDaniel Vetter default: 581f51b7662SDaniel Vetter gtt_entries = 0; 582f51b7662SDaniel Vetter break; 583f51b7662SDaniel Vetter } 584f51b7662SDaniel Vetter } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || 585f51b7662SDaniel Vetter agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) { 586f51b7662SDaniel Vetter /* 587f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 588f51b7662SDaniel Vetter */ 589f51b7662SDaniel Vetter u16 snb_gmch_ctl; 590f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 591f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 592f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 593f51b7662SDaniel Vetter gtt_entries = MB(32) - KB(size); 594f51b7662SDaniel Vetter break; 595f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 596f51b7662SDaniel Vetter gtt_entries = MB(64) - KB(size); 597f51b7662SDaniel Vetter break; 598f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 599f51b7662SDaniel Vetter gtt_entries = MB(96) - KB(size); 600f51b7662SDaniel Vetter break; 601f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 602f51b7662SDaniel Vetter gtt_entries = MB(128) - KB(size); 603f51b7662SDaniel Vetter break; 604f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 605f51b7662SDaniel Vetter gtt_entries = MB(160) - KB(size); 606f51b7662SDaniel Vetter break; 607f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 608f51b7662SDaniel Vetter gtt_entries = MB(192) - KB(size); 609f51b7662SDaniel Vetter break; 610f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 611f51b7662SDaniel Vetter gtt_entries = MB(224) - KB(size); 612f51b7662SDaniel Vetter break; 613f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 614f51b7662SDaniel Vetter gtt_entries = MB(256) - KB(size); 615f51b7662SDaniel Vetter break; 616f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 617f51b7662SDaniel Vetter gtt_entries = MB(288) - KB(size); 618f51b7662SDaniel Vetter break; 619f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 620f51b7662SDaniel Vetter gtt_entries = MB(320) - KB(size); 621f51b7662SDaniel Vetter break; 622f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 623f51b7662SDaniel Vetter gtt_entries = MB(352) - KB(size); 624f51b7662SDaniel Vetter break; 625f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 626f51b7662SDaniel Vetter gtt_entries = MB(384) - KB(size); 627f51b7662SDaniel Vetter break; 628f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 629f51b7662SDaniel Vetter gtt_entries = MB(416) - KB(size); 630f51b7662SDaniel Vetter break; 631f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 632f51b7662SDaniel Vetter gtt_entries = MB(448) - KB(size); 633f51b7662SDaniel Vetter break; 634f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 635f51b7662SDaniel Vetter gtt_entries = MB(480) - KB(size); 636f51b7662SDaniel Vetter break; 637f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 638f51b7662SDaniel Vetter gtt_entries = MB(512) - KB(size); 639f51b7662SDaniel Vetter break; 640f51b7662SDaniel Vetter } 641f51b7662SDaniel Vetter } else { 642f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 643f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 644f51b7662SDaniel Vetter gtt_entries = MB(1) - KB(size); 645f51b7662SDaniel Vetter break; 646f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 647f51b7662SDaniel Vetter gtt_entries = MB(4) - KB(size); 648f51b7662SDaniel Vetter break; 649f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 650f51b7662SDaniel Vetter gtt_entries = MB(8) - KB(size); 651f51b7662SDaniel Vetter break; 652f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 653f51b7662SDaniel Vetter gtt_entries = MB(16) - KB(size); 654f51b7662SDaniel Vetter break; 655f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 656f51b7662SDaniel Vetter gtt_entries = MB(32) - KB(size); 657f51b7662SDaniel Vetter break; 658f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 659f51b7662SDaniel Vetter /* Check it's really I915G */ 660f51b7662SDaniel Vetter if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 661f51b7662SDaniel Vetter gtt_entries = MB(48) - KB(size); 662f51b7662SDaniel Vetter else 663f51b7662SDaniel Vetter gtt_entries = 0; 664f51b7662SDaniel Vetter break; 665f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 666f51b7662SDaniel Vetter /* Check it's really I915G */ 667f51b7662SDaniel Vetter if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 668f51b7662SDaniel Vetter gtt_entries = MB(64) - KB(size); 669f51b7662SDaniel Vetter else 670f51b7662SDaniel Vetter gtt_entries = 0; 671f51b7662SDaniel Vetter break; 672f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 673f51b7662SDaniel Vetter if (IS_G33 || IS_I965 || IS_G4X) 674f51b7662SDaniel Vetter gtt_entries = MB(128) - KB(size); 675f51b7662SDaniel Vetter else 676f51b7662SDaniel Vetter gtt_entries = 0; 677f51b7662SDaniel Vetter break; 678f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 679f51b7662SDaniel Vetter if (IS_G33 || IS_I965 || IS_G4X) 680f51b7662SDaniel Vetter gtt_entries = MB(256) - KB(size); 681f51b7662SDaniel Vetter else 682f51b7662SDaniel Vetter gtt_entries = 0; 683f51b7662SDaniel Vetter break; 684f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 685f51b7662SDaniel Vetter if (IS_I965 || IS_G4X) 686f51b7662SDaniel Vetter gtt_entries = MB(96) - KB(size); 687f51b7662SDaniel Vetter else 688f51b7662SDaniel Vetter gtt_entries = 0; 689f51b7662SDaniel Vetter break; 690f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 691f51b7662SDaniel Vetter if (IS_I965 || IS_G4X) 692f51b7662SDaniel Vetter gtt_entries = MB(160) - KB(size); 693f51b7662SDaniel Vetter else 694f51b7662SDaniel Vetter gtt_entries = 0; 695f51b7662SDaniel Vetter break; 696f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 697f51b7662SDaniel Vetter if (IS_I965 || IS_G4X) 698f51b7662SDaniel Vetter gtt_entries = MB(224) - KB(size); 699f51b7662SDaniel Vetter else 700f51b7662SDaniel Vetter gtt_entries = 0; 701f51b7662SDaniel Vetter break; 702f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 703f51b7662SDaniel Vetter if (IS_I965 || IS_G4X) 704f51b7662SDaniel Vetter gtt_entries = MB(352) - KB(size); 705f51b7662SDaniel Vetter else 706f51b7662SDaniel Vetter gtt_entries = 0; 707f51b7662SDaniel Vetter break; 708f51b7662SDaniel Vetter default: 709f51b7662SDaniel Vetter gtt_entries = 0; 710f51b7662SDaniel Vetter break; 711f51b7662SDaniel Vetter } 712f51b7662SDaniel Vetter } 713f51b7662SDaniel Vetter if (gtt_entries > 0) { 714f51b7662SDaniel Vetter dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 715f51b7662SDaniel Vetter gtt_entries / KB(1), local ? "local" : "stolen"); 716f51b7662SDaniel Vetter gtt_entries /= KB(4); 717f51b7662SDaniel Vetter } else { 718f51b7662SDaniel Vetter dev_info(&agp_bridge->dev->dev, 719f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 720f51b7662SDaniel Vetter gtt_entries = 0; 721f51b7662SDaniel Vetter } 722f51b7662SDaniel Vetter 723f51b7662SDaniel Vetter intel_private.gtt_entries = gtt_entries; 724f51b7662SDaniel Vetter } 725f51b7662SDaniel Vetter 726f51b7662SDaniel Vetter static void intel_i830_fini_flush(void) 727f51b7662SDaniel Vetter { 728f51b7662SDaniel Vetter kunmap(intel_private.i8xx_page); 729f51b7662SDaniel Vetter intel_private.i8xx_flush_page = NULL; 730f51b7662SDaniel Vetter unmap_page_from_agp(intel_private.i8xx_page); 731f51b7662SDaniel Vetter 732f51b7662SDaniel Vetter __free_page(intel_private.i8xx_page); 733f51b7662SDaniel Vetter intel_private.i8xx_page = NULL; 734f51b7662SDaniel Vetter } 735f51b7662SDaniel Vetter 736f51b7662SDaniel Vetter static void intel_i830_setup_flush(void) 737f51b7662SDaniel Vetter { 738f51b7662SDaniel Vetter /* return if we've already set the flush mechanism up */ 739f51b7662SDaniel Vetter if (intel_private.i8xx_page) 740f51b7662SDaniel Vetter return; 741f51b7662SDaniel Vetter 742f51b7662SDaniel Vetter intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 743f51b7662SDaniel Vetter if (!intel_private.i8xx_page) 744f51b7662SDaniel Vetter return; 745f51b7662SDaniel Vetter 746f51b7662SDaniel Vetter intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 747f51b7662SDaniel Vetter if (!intel_private.i8xx_flush_page) 748f51b7662SDaniel Vetter intel_i830_fini_flush(); 749f51b7662SDaniel Vetter } 750f51b7662SDaniel Vetter 751f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 752f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 753f51b7662SDaniel Vetter * doesn't snoop those buffers. 754f51b7662SDaniel Vetter * 755f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 756f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 757f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 758f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 759f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 760f51b7662SDaniel Vetter */ 761f51b7662SDaniel Vetter static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 762f51b7662SDaniel Vetter { 763f51b7662SDaniel Vetter unsigned int *pg = intel_private.i8xx_flush_page; 764f51b7662SDaniel Vetter 765f51b7662SDaniel Vetter memset(pg, 0, 1024); 766f51b7662SDaniel Vetter 767f51b7662SDaniel Vetter if (cpu_has_clflush) 768f51b7662SDaniel Vetter clflush_cache_range(pg, 1024); 769f51b7662SDaniel Vetter else if (wbinvd_on_all_cpus() != 0) 770f51b7662SDaniel Vetter printk(KERN_ERR "Timed out waiting for cache flush.\n"); 771f51b7662SDaniel Vetter } 772f51b7662SDaniel Vetter 773f51b7662SDaniel Vetter /* The intel i830 automatically initializes the agp aperture during POST. 774f51b7662SDaniel Vetter * Use the memory already set aside for in the GTT. 775f51b7662SDaniel Vetter */ 776f51b7662SDaniel Vetter static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 777f51b7662SDaniel Vetter { 778f51b7662SDaniel Vetter int page_order; 779f51b7662SDaniel Vetter struct aper_size_info_fixed *size; 780f51b7662SDaniel Vetter int num_entries; 781f51b7662SDaniel Vetter u32 temp; 782f51b7662SDaniel Vetter 783f51b7662SDaniel Vetter size = agp_bridge->current_size; 784f51b7662SDaniel Vetter page_order = size->page_order; 785f51b7662SDaniel Vetter num_entries = size->num_entries; 786f51b7662SDaniel Vetter agp_bridge->gatt_table_real = NULL; 787f51b7662SDaniel Vetter 788f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 789f51b7662SDaniel Vetter temp &= 0xfff80000; 790f51b7662SDaniel Vetter 791f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 792f51b7662SDaniel Vetter if (!intel_private.registers) 793f51b7662SDaniel Vetter return -ENOMEM; 794f51b7662SDaniel Vetter 795f51b7662SDaniel Vetter temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 796f51b7662SDaniel Vetter global_cache_flush(); /* FIXME: ?? */ 797f51b7662SDaniel Vetter 798f51b7662SDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 799f51b7662SDaniel Vetter intel_i830_init_gtt_entries(); 800f51b7662SDaniel Vetter 801f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 802f51b7662SDaniel Vetter 803f51b7662SDaniel Vetter agp_bridge->gatt_bus_addr = temp; 804f51b7662SDaniel Vetter 805f51b7662SDaniel Vetter return 0; 806f51b7662SDaniel Vetter } 807f51b7662SDaniel Vetter 808f51b7662SDaniel Vetter /* Return the gatt table to a sane state. Use the top of stolen 809f51b7662SDaniel Vetter * memory for the GTT. 810f51b7662SDaniel Vetter */ 811f51b7662SDaniel Vetter static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 812f51b7662SDaniel Vetter { 813f51b7662SDaniel Vetter return 0; 814f51b7662SDaniel Vetter } 815f51b7662SDaniel Vetter 816f51b7662SDaniel Vetter static int intel_i830_fetch_size(void) 817f51b7662SDaniel Vetter { 818f51b7662SDaniel Vetter u16 gmch_ctrl; 819f51b7662SDaniel Vetter struct aper_size_info_fixed *values; 820f51b7662SDaniel Vetter 821f51b7662SDaniel Vetter values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 822f51b7662SDaniel Vetter 823f51b7662SDaniel Vetter if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 824f51b7662SDaniel Vetter agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 825f51b7662SDaniel Vetter /* 855GM/852GM/865G has 128MB aperture size */ 826e1583165SDaniel Vetter agp_bridge->current_size = (void *) values; 827f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 828f51b7662SDaniel Vetter return values[0].size; 829f51b7662SDaniel Vetter } 830f51b7662SDaniel Vetter 831f51b7662SDaniel Vetter pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 832f51b7662SDaniel Vetter 833f51b7662SDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 834e1583165SDaniel Vetter agp_bridge->current_size = (void *) values; 835f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 836f51b7662SDaniel Vetter return values[0].size; 837f51b7662SDaniel Vetter } else { 838e1583165SDaniel Vetter agp_bridge->current_size = (void *) (values + 1); 839f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 1; 840f51b7662SDaniel Vetter return values[1].size; 841f51b7662SDaniel Vetter } 842f51b7662SDaniel Vetter 843f51b7662SDaniel Vetter return 0; 844f51b7662SDaniel Vetter } 845f51b7662SDaniel Vetter 846f51b7662SDaniel Vetter static int intel_i830_configure(void) 847f51b7662SDaniel Vetter { 848f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 849f51b7662SDaniel Vetter u32 temp; 850f51b7662SDaniel Vetter u16 gmch_ctrl; 851f51b7662SDaniel Vetter int i; 852f51b7662SDaniel Vetter 853f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 854f51b7662SDaniel Vetter 855f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 856f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 857f51b7662SDaniel Vetter 858f51b7662SDaniel Vetter pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 859f51b7662SDaniel Vetter gmch_ctrl |= I830_GMCH_ENABLED; 860f51b7662SDaniel Vetter pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 861f51b7662SDaniel Vetter 862f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 863f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 864f51b7662SDaniel Vetter 865f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 866f51b7662SDaniel Vetter for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 867f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 868f51b7662SDaniel Vetter } 869f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 870f51b7662SDaniel Vetter } 871f51b7662SDaniel Vetter 872f51b7662SDaniel Vetter global_cache_flush(); 873f51b7662SDaniel Vetter 874f51b7662SDaniel Vetter intel_i830_setup_flush(); 875f51b7662SDaniel Vetter return 0; 876f51b7662SDaniel Vetter } 877f51b7662SDaniel Vetter 878f51b7662SDaniel Vetter static void intel_i830_cleanup(void) 879f51b7662SDaniel Vetter { 880f51b7662SDaniel Vetter iounmap(intel_private.registers); 881f51b7662SDaniel Vetter } 882f51b7662SDaniel Vetter 883f51b7662SDaniel Vetter static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 884f51b7662SDaniel Vetter int type) 885f51b7662SDaniel Vetter { 886f51b7662SDaniel Vetter int i, j, num_entries; 887f51b7662SDaniel Vetter void *temp; 888f51b7662SDaniel Vetter int ret = -EINVAL; 889f51b7662SDaniel Vetter int mask_type; 890f51b7662SDaniel Vetter 891f51b7662SDaniel Vetter if (mem->page_count == 0) 892f51b7662SDaniel Vetter goto out; 893f51b7662SDaniel Vetter 894f51b7662SDaniel Vetter temp = agp_bridge->current_size; 895f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 896f51b7662SDaniel Vetter 897f51b7662SDaniel Vetter if (pg_start < intel_private.gtt_entries) { 898f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 899f51b7662SDaniel Vetter "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 900f51b7662SDaniel Vetter pg_start, intel_private.gtt_entries); 901f51b7662SDaniel Vetter 902f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 903f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 904f51b7662SDaniel Vetter goto out_err; 905f51b7662SDaniel Vetter } 906f51b7662SDaniel Vetter 907f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 908f51b7662SDaniel Vetter goto out_err; 909f51b7662SDaniel Vetter 910f51b7662SDaniel Vetter /* The i830 can't check the GTT for entries since its read only, 911f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 912f51b7662SDaniel Vetter */ 913f51b7662SDaniel Vetter 914f51b7662SDaniel Vetter if (type != mem->type) 915f51b7662SDaniel Vetter goto out_err; 916f51b7662SDaniel Vetter 917f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 918f51b7662SDaniel Vetter 919f51b7662SDaniel Vetter if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 920f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 921f51b7662SDaniel Vetter goto out_err; 922f51b7662SDaniel Vetter 923f51b7662SDaniel Vetter if (!mem->is_flushed) 924f51b7662SDaniel Vetter global_cache_flush(); 925f51b7662SDaniel Vetter 926f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 927f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 928f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 929f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(j*4)); 930f51b7662SDaniel Vetter } 931f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 932f51b7662SDaniel Vetter 933f51b7662SDaniel Vetter out: 934f51b7662SDaniel Vetter ret = 0; 935f51b7662SDaniel Vetter out_err: 936f51b7662SDaniel Vetter mem->is_flushed = true; 937f51b7662SDaniel Vetter return ret; 938f51b7662SDaniel Vetter } 939f51b7662SDaniel Vetter 940f51b7662SDaniel Vetter static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 941f51b7662SDaniel Vetter int type) 942f51b7662SDaniel Vetter { 943f51b7662SDaniel Vetter int i; 944f51b7662SDaniel Vetter 945f51b7662SDaniel Vetter if (mem->page_count == 0) 946f51b7662SDaniel Vetter return 0; 947f51b7662SDaniel Vetter 948f51b7662SDaniel Vetter if (pg_start < intel_private.gtt_entries) { 949f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 950f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 951f51b7662SDaniel Vetter return -EINVAL; 952f51b7662SDaniel Vetter } 953f51b7662SDaniel Vetter 954f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 955f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 956f51b7662SDaniel Vetter } 957f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 958f51b7662SDaniel Vetter 959f51b7662SDaniel Vetter return 0; 960f51b7662SDaniel Vetter } 961f51b7662SDaniel Vetter 962f51b7662SDaniel Vetter static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 963f51b7662SDaniel Vetter { 964f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 965f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 966f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 967f51b7662SDaniel Vetter return NULL; 968f51b7662SDaniel Vetter } 969f51b7662SDaniel Vetter 970f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 971f51b7662SDaniel Vetter { 972f51b7662SDaniel Vetter int ret; 973f51b7662SDaniel Vetter ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 974f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 975f51b7662SDaniel Vetter pcibios_align_resource, agp_bridge->dev); 976f51b7662SDaniel Vetter 977f51b7662SDaniel Vetter return ret; 978f51b7662SDaniel Vetter } 979f51b7662SDaniel Vetter 980f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 981f51b7662SDaniel Vetter { 982f51b7662SDaniel Vetter int ret; 983f51b7662SDaniel Vetter u32 temp; 984f51b7662SDaniel Vetter 985f51b7662SDaniel Vetter pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 986f51b7662SDaniel Vetter if (!(temp & 0x1)) { 987f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 988f51b7662SDaniel Vetter intel_private.resource_valid = 1; 989f51b7662SDaniel Vetter pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 990f51b7662SDaniel Vetter } else { 991f51b7662SDaniel Vetter temp &= ~1; 992f51b7662SDaniel Vetter 993f51b7662SDaniel Vetter intel_private.resource_valid = 1; 994f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 995f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 996f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 997f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 998f51b7662SDaniel Vetter if (ret) 999f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1000f51b7662SDaniel Vetter } 1001f51b7662SDaniel Vetter } 1002f51b7662SDaniel Vetter 1003f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1004f51b7662SDaniel Vetter { 1005f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1006f51b7662SDaniel Vetter int ret; 1007f51b7662SDaniel Vetter 1008f51b7662SDaniel Vetter pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1009f51b7662SDaniel Vetter pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1010f51b7662SDaniel Vetter 1011f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1012f51b7662SDaniel Vetter 1013f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1014f51b7662SDaniel Vetter 1015f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1016f51b7662SDaniel Vetter pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1017f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1018f51b7662SDaniel Vetter pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1019f51b7662SDaniel Vetter } else { 1020f51b7662SDaniel Vetter u64 l64; 1021f51b7662SDaniel Vetter 1022f51b7662SDaniel Vetter temp_lo &= ~0x1; 1023f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1024f51b7662SDaniel Vetter 1025f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1026f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1027f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1028f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1029f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1030f51b7662SDaniel Vetter if (ret) 1031f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1032f51b7662SDaniel Vetter } 1033f51b7662SDaniel Vetter } 1034f51b7662SDaniel Vetter 1035f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1036f51b7662SDaniel Vetter { 1037f51b7662SDaniel Vetter /* return if already configured */ 1038f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1039f51b7662SDaniel Vetter return; 1040f51b7662SDaniel Vetter 1041f51b7662SDaniel Vetter if (IS_SNB) 1042f51b7662SDaniel Vetter return; 1043f51b7662SDaniel Vetter 1044f51b7662SDaniel Vetter /* setup a resource for this object */ 1045f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1046f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1047f51b7662SDaniel Vetter 1048f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 1049f51b7662SDaniel Vetter if (IS_I965 || IS_G33 || IS_G4X) { 1050f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1051f51b7662SDaniel Vetter } else { 1052f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1053f51b7662SDaniel Vetter } 1054f51b7662SDaniel Vetter 1055f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) { 1056f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1057f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1058f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 1059f51b7662SDaniel Vetter } 1060f51b7662SDaniel Vetter } 1061f51b7662SDaniel Vetter 1062f1befe71SChris Wilson static int intel_i9xx_configure(void) 1063f51b7662SDaniel Vetter { 1064f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 1065f51b7662SDaniel Vetter u32 temp; 1066f51b7662SDaniel Vetter u16 gmch_ctrl; 1067f51b7662SDaniel Vetter int i; 1068f51b7662SDaniel Vetter 1069f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 1070f51b7662SDaniel Vetter 1071f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1072f51b7662SDaniel Vetter 1073f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1074f51b7662SDaniel Vetter 1075f51b7662SDaniel Vetter pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1076f51b7662SDaniel Vetter gmch_ctrl |= I830_GMCH_ENABLED; 1077f51b7662SDaniel Vetter pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1078f51b7662SDaniel Vetter 1079f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1080f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1081f51b7662SDaniel Vetter 1082f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 1083f51b7662SDaniel Vetter for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { 1084f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1085f51b7662SDaniel Vetter } 1086f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1087f51b7662SDaniel Vetter } 1088f51b7662SDaniel Vetter 1089f51b7662SDaniel Vetter global_cache_flush(); 1090f51b7662SDaniel Vetter 1091f51b7662SDaniel Vetter intel_i9xx_setup_flush(); 1092f51b7662SDaniel Vetter 1093f51b7662SDaniel Vetter return 0; 1094f51b7662SDaniel Vetter } 1095f51b7662SDaniel Vetter 1096f51b7662SDaniel Vetter static void intel_i915_cleanup(void) 1097f51b7662SDaniel Vetter { 1098f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1099f51b7662SDaniel Vetter iounmap(intel_private.i9xx_flush_page); 1100f51b7662SDaniel Vetter if (intel_private.resource_valid) 1101f51b7662SDaniel Vetter release_resource(&intel_private.ifp_resource); 1102f51b7662SDaniel Vetter intel_private.ifp_resource.start = 0; 1103f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1104f51b7662SDaniel Vetter iounmap(intel_private.gtt); 1105f51b7662SDaniel Vetter iounmap(intel_private.registers); 1106f51b7662SDaniel Vetter } 1107f51b7662SDaniel Vetter 1108f51b7662SDaniel Vetter static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1109f51b7662SDaniel Vetter { 1110f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1111f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1112f51b7662SDaniel Vetter } 1113f51b7662SDaniel Vetter 1114f51b7662SDaniel Vetter static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1115f51b7662SDaniel Vetter int type) 1116f51b7662SDaniel Vetter { 1117f51b7662SDaniel Vetter int num_entries; 1118f51b7662SDaniel Vetter void *temp; 1119f51b7662SDaniel Vetter int ret = -EINVAL; 1120f51b7662SDaniel Vetter int mask_type; 1121f51b7662SDaniel Vetter 1122f51b7662SDaniel Vetter if (mem->page_count == 0) 1123f51b7662SDaniel Vetter goto out; 1124f51b7662SDaniel Vetter 1125f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1126f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1127f51b7662SDaniel Vetter 1128f51b7662SDaniel Vetter if (pg_start < intel_private.gtt_entries) { 1129f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1130f51b7662SDaniel Vetter "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1131f51b7662SDaniel Vetter pg_start, intel_private.gtt_entries); 1132f51b7662SDaniel Vetter 1133f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1134f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1135f51b7662SDaniel Vetter goto out_err; 1136f51b7662SDaniel Vetter } 1137f51b7662SDaniel Vetter 1138f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1139f51b7662SDaniel Vetter goto out_err; 1140f51b7662SDaniel Vetter 1141f51b7662SDaniel Vetter /* The i915 can't check the GTT for entries since it's read only; 1142f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1143f51b7662SDaniel Vetter */ 1144f51b7662SDaniel Vetter 1145f51b7662SDaniel Vetter if (type != mem->type) 1146f51b7662SDaniel Vetter goto out_err; 1147f51b7662SDaniel Vetter 1148f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1149f51b7662SDaniel Vetter 1150f51b7662SDaniel Vetter if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1151f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1152f51b7662SDaniel Vetter goto out_err; 1153f51b7662SDaniel Vetter 1154f51b7662SDaniel Vetter if (!mem->is_flushed) 1155f51b7662SDaniel Vetter global_cache_flush(); 1156f51b7662SDaniel Vetter 1157f51b7662SDaniel Vetter intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1158f51b7662SDaniel Vetter 1159f51b7662SDaniel Vetter out: 1160f51b7662SDaniel Vetter ret = 0; 1161f51b7662SDaniel Vetter out_err: 1162f51b7662SDaniel Vetter mem->is_flushed = true; 1163f51b7662SDaniel Vetter return ret; 1164f51b7662SDaniel Vetter } 1165f51b7662SDaniel Vetter 1166f51b7662SDaniel Vetter static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1167f51b7662SDaniel Vetter int type) 1168f51b7662SDaniel Vetter { 1169f51b7662SDaniel Vetter int i; 1170f51b7662SDaniel Vetter 1171f51b7662SDaniel Vetter if (mem->page_count == 0) 1172f51b7662SDaniel Vetter return 0; 1173f51b7662SDaniel Vetter 1174f51b7662SDaniel Vetter if (pg_start < intel_private.gtt_entries) { 1175f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1176f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1177f51b7662SDaniel Vetter return -EINVAL; 1178f51b7662SDaniel Vetter } 1179f51b7662SDaniel Vetter 1180f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) 1181f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1182f51b7662SDaniel Vetter 1183f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); 1184f51b7662SDaniel Vetter 1185f51b7662SDaniel Vetter return 0; 1186f51b7662SDaniel Vetter } 1187f51b7662SDaniel Vetter 1188f51b7662SDaniel Vetter /* Return the aperture size by just checking the resource length. The effect 1189f51b7662SDaniel Vetter * described in the spec of the MSAC registers is just changing of the 1190f51b7662SDaniel Vetter * resource size. 1191f51b7662SDaniel Vetter */ 1192f51b7662SDaniel Vetter static int intel_i9xx_fetch_size(void) 1193f51b7662SDaniel Vetter { 1194f51b7662SDaniel Vetter int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1195f51b7662SDaniel Vetter int aper_size; /* size in megabytes */ 1196f51b7662SDaniel Vetter int i; 1197f51b7662SDaniel Vetter 1198f51b7662SDaniel Vetter aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1199f51b7662SDaniel Vetter 1200f51b7662SDaniel Vetter for (i = 0; i < num_sizes; i++) { 1201f51b7662SDaniel Vetter if (aper_size == intel_i830_sizes[i].size) { 1202f51b7662SDaniel Vetter agp_bridge->current_size = intel_i830_sizes + i; 1203f51b7662SDaniel Vetter return aper_size; 1204f51b7662SDaniel Vetter } 1205f51b7662SDaniel Vetter } 1206f51b7662SDaniel Vetter 1207f51b7662SDaniel Vetter return 0; 1208f51b7662SDaniel Vetter } 1209f51b7662SDaniel Vetter 1210f1befe71SChris Wilson static int intel_i915_get_gtt_size(void) 1211f1befe71SChris Wilson { 1212f1befe71SChris Wilson int size; 1213f1befe71SChris Wilson 1214f1befe71SChris Wilson if (IS_G33) { 1215f1befe71SChris Wilson u16 gmch_ctrl; 1216f1befe71SChris Wilson 1217f1befe71SChris Wilson /* G33's GTT size defined in gmch_ctrl */ 1218f1befe71SChris Wilson pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1219f1befe71SChris Wilson switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 1220f1befe71SChris Wilson case G33_PGETBL_SIZE_1M: 1221f1befe71SChris Wilson size = 1024; 1222f1befe71SChris Wilson break; 1223f1befe71SChris Wilson case G33_PGETBL_SIZE_2M: 1224f1befe71SChris Wilson size = 2048; 1225f1befe71SChris Wilson break; 1226f1befe71SChris Wilson default: 1227f1befe71SChris Wilson dev_info(&agp_bridge->dev->dev, 1228f1befe71SChris Wilson "unknown page table size 0x%x, assuming 512KB\n", 1229f1befe71SChris Wilson (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 1230f1befe71SChris Wilson size = 512; 1231f1befe71SChris Wilson } 1232f1befe71SChris Wilson } else { 1233f1befe71SChris Wilson /* On previous hardware, the GTT size was just what was 1234f1befe71SChris Wilson * required to map the aperture. 1235f1befe71SChris Wilson */ 1236f1befe71SChris Wilson size = agp_bridge->driver->fetch_size(); 1237f1befe71SChris Wilson } 1238f1befe71SChris Wilson 1239f1befe71SChris Wilson return KB(size); 1240f1befe71SChris Wilson } 1241f1befe71SChris Wilson 1242f51b7662SDaniel Vetter /* The intel i915 automatically initializes the agp aperture during POST. 1243f51b7662SDaniel Vetter * Use the memory already set aside for in the GTT. 1244f51b7662SDaniel Vetter */ 1245f51b7662SDaniel Vetter static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1246f51b7662SDaniel Vetter { 1247f51b7662SDaniel Vetter int page_order; 1248f51b7662SDaniel Vetter struct aper_size_info_fixed *size; 1249f51b7662SDaniel Vetter int num_entries; 1250f51b7662SDaniel Vetter u32 temp, temp2; 1251f1befe71SChris Wilson int gtt_map_size; 1252f51b7662SDaniel Vetter 1253f51b7662SDaniel Vetter size = agp_bridge->current_size; 1254f51b7662SDaniel Vetter page_order = size->page_order; 1255f51b7662SDaniel Vetter num_entries = size->num_entries; 1256f51b7662SDaniel Vetter agp_bridge->gatt_table_real = NULL; 1257f51b7662SDaniel Vetter 1258f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1259f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1260f51b7662SDaniel Vetter 1261f1befe71SChris Wilson gtt_map_size = intel_i915_get_gtt_size(); 1262f1befe71SChris Wilson 1263f51b7662SDaniel Vetter intel_private.gtt = ioremap(temp2, gtt_map_size); 1264f51b7662SDaniel Vetter if (!intel_private.gtt) 1265f51b7662SDaniel Vetter return -ENOMEM; 1266f51b7662SDaniel Vetter 1267f51b7662SDaniel Vetter intel_private.gtt_total_size = gtt_map_size / 4; 1268f51b7662SDaniel Vetter 1269f51b7662SDaniel Vetter temp &= 0xfff80000; 1270f51b7662SDaniel Vetter 1271f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 1272f51b7662SDaniel Vetter if (!intel_private.registers) { 1273f51b7662SDaniel Vetter iounmap(intel_private.gtt); 1274f51b7662SDaniel Vetter return -ENOMEM; 1275f51b7662SDaniel Vetter } 1276f51b7662SDaniel Vetter 1277f51b7662SDaniel Vetter temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1278f51b7662SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 1279f51b7662SDaniel Vetter 1280f51b7662SDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 1281f51b7662SDaniel Vetter intel_i830_init_gtt_entries(); 1282f51b7662SDaniel Vetter 1283f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 1284f51b7662SDaniel Vetter 1285f51b7662SDaniel Vetter agp_bridge->gatt_bus_addr = temp; 1286f51b7662SDaniel Vetter 1287f51b7662SDaniel Vetter return 0; 1288f51b7662SDaniel Vetter } 1289f51b7662SDaniel Vetter 1290f51b7662SDaniel Vetter /* 1291f51b7662SDaniel Vetter * The i965 supports 36-bit physical addresses, but to keep 1292f51b7662SDaniel Vetter * the format of the GTT the same, the bits that don't fit 1293f51b7662SDaniel Vetter * in a 32-bit word are shifted down to bits 4..7. 1294f51b7662SDaniel Vetter * 1295f51b7662SDaniel Vetter * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1296f51b7662SDaniel Vetter * is always zero on 32-bit architectures, so no need to make 1297f51b7662SDaniel Vetter * this conditional. 1298f51b7662SDaniel Vetter */ 1299f51b7662SDaniel Vetter static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1300f51b7662SDaniel Vetter dma_addr_t addr, int type) 1301f51b7662SDaniel Vetter { 1302f51b7662SDaniel Vetter /* Shift high bits down */ 1303f51b7662SDaniel Vetter addr |= (addr >> 28) & 0xf0; 1304f51b7662SDaniel Vetter 1305f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 1306f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 1307f51b7662SDaniel Vetter } 1308f51b7662SDaniel Vetter 1309f51b7662SDaniel Vetter static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1310f51b7662SDaniel Vetter { 1311f51b7662SDaniel Vetter u16 snb_gmch_ctl; 1312f51b7662SDaniel Vetter 1313f51b7662SDaniel Vetter switch (agp_bridge->dev->device) { 1314f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_GM45_HB: 1315f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: 1316f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_Q45_HB: 1317f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_G45_HB: 1318f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_G41_HB: 1319f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_B43_HB: 1320f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB: 1321f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: 1322f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: 1323f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: 1324f51b7662SDaniel Vetter *gtt_offset = *gtt_size = MB(2); 1325f51b7662SDaniel Vetter break; 1326f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: 1327f51b7662SDaniel Vetter case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: 1328f51b7662SDaniel Vetter *gtt_offset = MB(2); 1329f51b7662SDaniel Vetter 1330f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 1331f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 1332f51b7662SDaniel Vetter default: 1333f51b7662SDaniel Vetter case SNB_GTT_SIZE_0M: 1334f51b7662SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 1335f51b7662SDaniel Vetter *gtt_size = MB(0); 1336f51b7662SDaniel Vetter break; 1337f51b7662SDaniel Vetter case SNB_GTT_SIZE_1M: 1338f51b7662SDaniel Vetter *gtt_size = MB(1); 1339f51b7662SDaniel Vetter break; 1340f51b7662SDaniel Vetter case SNB_GTT_SIZE_2M: 1341f51b7662SDaniel Vetter *gtt_size = MB(2); 1342f51b7662SDaniel Vetter break; 1343f51b7662SDaniel Vetter } 1344f51b7662SDaniel Vetter break; 1345f51b7662SDaniel Vetter default: 1346f51b7662SDaniel Vetter *gtt_offset = *gtt_size = KB(512); 1347f51b7662SDaniel Vetter } 1348f51b7662SDaniel Vetter } 1349f51b7662SDaniel Vetter 1350f51b7662SDaniel Vetter /* The intel i965 automatically initializes the agp aperture during POST. 1351f51b7662SDaniel Vetter * Use the memory already set aside for in the GTT. 1352f51b7662SDaniel Vetter */ 1353f51b7662SDaniel Vetter static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1354f51b7662SDaniel Vetter { 1355f51b7662SDaniel Vetter int page_order; 1356f51b7662SDaniel Vetter struct aper_size_info_fixed *size; 1357f51b7662SDaniel Vetter int num_entries; 1358f51b7662SDaniel Vetter u32 temp; 1359f51b7662SDaniel Vetter int gtt_offset, gtt_size; 1360f51b7662SDaniel Vetter 1361f51b7662SDaniel Vetter size = agp_bridge->current_size; 1362f51b7662SDaniel Vetter page_order = size->page_order; 1363f51b7662SDaniel Vetter num_entries = size->num_entries; 1364f51b7662SDaniel Vetter agp_bridge->gatt_table_real = NULL; 1365f51b7662SDaniel Vetter 1366f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1367f51b7662SDaniel Vetter 1368f51b7662SDaniel Vetter temp &= 0xfff00000; 1369f51b7662SDaniel Vetter 1370f51b7662SDaniel Vetter intel_i965_get_gtt_range(>t_offset, >t_size); 1371f51b7662SDaniel Vetter 1372f51b7662SDaniel Vetter intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1373f51b7662SDaniel Vetter 1374f51b7662SDaniel Vetter if (!intel_private.gtt) 1375f51b7662SDaniel Vetter return -ENOMEM; 1376f51b7662SDaniel Vetter 1377f51b7662SDaniel Vetter intel_private.gtt_total_size = gtt_size / 4; 1378f51b7662SDaniel Vetter 1379f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 1380f51b7662SDaniel Vetter if (!intel_private.registers) { 1381f51b7662SDaniel Vetter iounmap(intel_private.gtt); 1382f51b7662SDaniel Vetter return -ENOMEM; 1383f51b7662SDaniel Vetter } 1384f51b7662SDaniel Vetter 1385f51b7662SDaniel Vetter temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1386f51b7662SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 1387f51b7662SDaniel Vetter 1388f51b7662SDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 1389f51b7662SDaniel Vetter intel_i830_init_gtt_entries(); 1390f51b7662SDaniel Vetter 1391f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 1392f51b7662SDaniel Vetter 1393f51b7662SDaniel Vetter agp_bridge->gatt_bus_addr = temp; 1394f51b7662SDaniel Vetter 1395f51b7662SDaniel Vetter return 0; 1396f51b7662SDaniel Vetter } 1397f51b7662SDaniel Vetter 1398f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_810_driver = { 1399f51b7662SDaniel Vetter .owner = THIS_MODULE, 1400f51b7662SDaniel Vetter .aperture_sizes = intel_i810_sizes, 1401f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1402f51b7662SDaniel Vetter .num_aperture_sizes = 2, 1403f51b7662SDaniel Vetter .needs_scratch_page = true, 1404f51b7662SDaniel Vetter .configure = intel_i810_configure, 1405f51b7662SDaniel Vetter .fetch_size = intel_i810_fetch_size, 1406f51b7662SDaniel Vetter .cleanup = intel_i810_cleanup, 1407f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1408f51b7662SDaniel Vetter .masks = intel_i810_masks, 1409f51b7662SDaniel Vetter .agp_enable = intel_i810_agp_enable, 1410f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1411f51b7662SDaniel Vetter .create_gatt_table = agp_generic_create_gatt_table, 1412f51b7662SDaniel Vetter .free_gatt_table = agp_generic_free_gatt_table, 1413f51b7662SDaniel Vetter .insert_memory = intel_i810_insert_entries, 1414f51b7662SDaniel Vetter .remove_memory = intel_i810_remove_entries, 1415f51b7662SDaniel Vetter .alloc_by_type = intel_i810_alloc_by_type, 1416f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1417f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1418f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1419f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1420f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1421f51b7662SDaniel Vetter .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1422f51b7662SDaniel Vetter }; 1423f51b7662SDaniel Vetter 1424f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_830_driver = { 1425f51b7662SDaniel Vetter .owner = THIS_MODULE, 1426f51b7662SDaniel Vetter .aperture_sizes = intel_i830_sizes, 1427f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1428f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1429f51b7662SDaniel Vetter .needs_scratch_page = true, 1430f51b7662SDaniel Vetter .configure = intel_i830_configure, 1431f51b7662SDaniel Vetter .fetch_size = intel_i830_fetch_size, 1432f51b7662SDaniel Vetter .cleanup = intel_i830_cleanup, 1433f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1434f51b7662SDaniel Vetter .masks = intel_i810_masks, 1435f51b7662SDaniel Vetter .agp_enable = intel_i810_agp_enable, 1436f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1437f51b7662SDaniel Vetter .create_gatt_table = intel_i830_create_gatt_table, 1438f51b7662SDaniel Vetter .free_gatt_table = intel_i830_free_gatt_table, 1439f51b7662SDaniel Vetter .insert_memory = intel_i830_insert_entries, 1440f51b7662SDaniel Vetter .remove_memory = intel_i830_remove_entries, 1441f51b7662SDaniel Vetter .alloc_by_type = intel_i830_alloc_by_type, 1442f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1443f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1444f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1445f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1446f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1447f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1448f51b7662SDaniel Vetter .chipset_flush = intel_i830_chipset_flush, 1449f51b7662SDaniel Vetter }; 1450f51b7662SDaniel Vetter 1451f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_915_driver = { 1452f51b7662SDaniel Vetter .owner = THIS_MODULE, 1453f51b7662SDaniel Vetter .aperture_sizes = intel_i830_sizes, 1454f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1455f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1456f51b7662SDaniel Vetter .needs_scratch_page = true, 1457f1befe71SChris Wilson .configure = intel_i9xx_configure, 1458f51b7662SDaniel Vetter .fetch_size = intel_i9xx_fetch_size, 1459f51b7662SDaniel Vetter .cleanup = intel_i915_cleanup, 1460f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1461f51b7662SDaniel Vetter .masks = intel_i810_masks, 1462f51b7662SDaniel Vetter .agp_enable = intel_i810_agp_enable, 1463f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1464f51b7662SDaniel Vetter .create_gatt_table = intel_i915_create_gatt_table, 1465f51b7662SDaniel Vetter .free_gatt_table = intel_i830_free_gatt_table, 1466f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1467f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1468f51b7662SDaniel Vetter .alloc_by_type = intel_i830_alloc_by_type, 1469f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1470f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1471f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1472f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1473f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1474f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1475f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1476f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1477f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1478f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1479f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1480f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1481f51b7662SDaniel Vetter #endif 1482f51b7662SDaniel Vetter }; 1483f51b7662SDaniel Vetter 1484f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_i965_driver = { 1485f51b7662SDaniel Vetter .owner = THIS_MODULE, 1486f51b7662SDaniel Vetter .aperture_sizes = intel_i830_sizes, 1487f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1488f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1489f51b7662SDaniel Vetter .needs_scratch_page = true, 1490f1befe71SChris Wilson .configure = intel_i9xx_configure, 1491f51b7662SDaniel Vetter .fetch_size = intel_i9xx_fetch_size, 1492f51b7662SDaniel Vetter .cleanup = intel_i915_cleanup, 1493f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1494f51b7662SDaniel Vetter .masks = intel_i810_masks, 1495f51b7662SDaniel Vetter .agp_enable = intel_i810_agp_enable, 1496f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1497f51b7662SDaniel Vetter .create_gatt_table = intel_i965_create_gatt_table, 1498f51b7662SDaniel Vetter .free_gatt_table = intel_i830_free_gatt_table, 1499f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1500f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1501f51b7662SDaniel Vetter .alloc_by_type = intel_i830_alloc_by_type, 1502f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1503f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1504f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1505f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1506f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1507f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1508f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1509f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1510f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1511f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1512f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1513f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1514f51b7662SDaniel Vetter #endif 1515f51b7662SDaniel Vetter }; 1516f51b7662SDaniel Vetter 1517f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_g33_driver = { 1518f51b7662SDaniel Vetter .owner = THIS_MODULE, 1519f51b7662SDaniel Vetter .aperture_sizes = intel_i830_sizes, 1520f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1521f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1522f51b7662SDaniel Vetter .needs_scratch_page = true, 1523f1befe71SChris Wilson .configure = intel_i9xx_configure, 1524f51b7662SDaniel Vetter .fetch_size = intel_i9xx_fetch_size, 1525f51b7662SDaniel Vetter .cleanup = intel_i915_cleanup, 1526f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1527f51b7662SDaniel Vetter .masks = intel_i810_masks, 1528f51b7662SDaniel Vetter .agp_enable = intel_i810_agp_enable, 1529f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1530f51b7662SDaniel Vetter .create_gatt_table = intel_i915_create_gatt_table, 1531f51b7662SDaniel Vetter .free_gatt_table = intel_i830_free_gatt_table, 1532f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1533f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1534f51b7662SDaniel Vetter .alloc_by_type = intel_i830_alloc_by_type, 1535f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1536f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1537f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1538f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1539f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1540f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1541f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1542f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1543f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1544f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1545f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1546f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1547f51b7662SDaniel Vetter #endif 1548f51b7662SDaniel Vetter }; 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