1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24e2404e7cSDaniel Vetter #include <asm/smp.h> 25e2404e7cSDaniel Vetter #include "agp.h" 26e2404e7cSDaniel Vetter #include "intel-agp.h" 270ade6386SDaniel Vetter #include <drm/intel-gtt.h> 28e2404e7cSDaniel Vetter 29f51b7662SDaniel Vetter /* 30f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 31f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 32f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 33f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 34f51b7662SDaniel Vetter */ 35f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 36f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 370e87d2b0SDaniel Vetter #else 380e87d2b0SDaniel Vetter #define USE_PCI_DMA_API 0 39f51b7662SDaniel Vetter #endif 40f51b7662SDaniel Vetter 411a997ff2SDaniel Vetter struct intel_gtt_driver { 421a997ff2SDaniel Vetter unsigned int gen : 8; 431a997ff2SDaniel Vetter unsigned int is_g33 : 1; 441a997ff2SDaniel Vetter unsigned int is_pineview : 1; 451a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 46100519e2SChris Wilson unsigned int has_pgtbl_enable : 1; 4722533b49SDaniel Vetter unsigned int dma_mask_size : 8; 4873800422SDaniel Vetter /* Chipset specific GTT setup */ 4973800422SDaniel Vetter int (*setup)(void); 50ae83dd5cSDaniel Vetter /* This should undo anything done in ->setup() save the unmapping 51ae83dd5cSDaniel Vetter * of the mmio register file, that's done in the generic code. */ 52ae83dd5cSDaniel Vetter void (*cleanup)(void); 53351bb278SDaniel Vetter void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 54351bb278SDaniel Vetter /* Flags is a more or less chipset specific opaque value. 55351bb278SDaniel Vetter * For chipsets that need to support old ums (non-gem) code, this 56351bb278SDaniel Vetter * needs to be identical to the various supported agp memory types! */ 575cbecafcSDaniel Vetter bool (*check_flags)(unsigned int flags); 581b263f24SDaniel Vetter void (*chipset_flush)(void); 591a997ff2SDaniel Vetter }; 601a997ff2SDaniel Vetter 61f51b7662SDaniel Vetter static struct _intel_private { 620ade6386SDaniel Vetter struct intel_gtt base; 631a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 64f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 65d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 66f51b7662SDaniel Vetter u8 __iomem *registers; 67f67eab66SDaniel Vetter phys_addr_t gtt_bus_addr; 6873800422SDaniel Vetter phys_addr_t gma_bus_addr; 69b3eafc5aSDaniel Vetter u32 PGETBL_save; 70f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 71f51b7662SDaniel Vetter int num_dcache_entries; 72f51b7662SDaniel Vetter union { 73f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 74f51b7662SDaniel Vetter void *i8xx_flush_page; 75f51b7662SDaniel Vetter }; 76820647b9SDaniel Vetter char *i81x_gtt_table; 77f51b7662SDaniel Vetter struct page *i8xx_page; 78f51b7662SDaniel Vetter struct resource ifp_resource; 79f51b7662SDaniel Vetter int resource_valid; 800e87d2b0SDaniel Vetter struct page *scratch_page; 810e87d2b0SDaniel Vetter dma_addr_t scratch_page_dma; 82f51b7662SDaniel Vetter } intel_private; 83f51b7662SDaniel Vetter 841a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 851a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 861a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 871a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 88100519e2SChris Wilson #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 891a997ff2SDaniel Vetter 904080775bSDaniel Vetter int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, 914080775bSDaniel Vetter struct scatterlist **sg_list, int *num_sg) 92f51b7662SDaniel Vetter { 93f51b7662SDaniel Vetter struct sg_table st; 94f51b7662SDaniel Vetter struct scatterlist *sg; 95f51b7662SDaniel Vetter int i; 96f51b7662SDaniel Vetter 974080775bSDaniel Vetter if (*sg_list) 98fefaa70fSDaniel Vetter return 0; /* already mapped (for e.g. resume */ 99fefaa70fSDaniel Vetter 1004080775bSDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)num_entries); 101f51b7662SDaniel Vetter 1024080775bSDaniel Vetter if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) 103831cd445SChris Wilson goto err; 104f51b7662SDaniel Vetter 1054080775bSDaniel Vetter *sg_list = sg = st.sgl; 106f51b7662SDaniel Vetter 1074080775bSDaniel Vetter for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) 1084080775bSDaniel Vetter sg_set_page(sg, pages[i], PAGE_SIZE, 0); 109f51b7662SDaniel Vetter 1104080775bSDaniel Vetter *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, 1114080775bSDaniel Vetter num_entries, PCI_DMA_BIDIRECTIONAL); 1124080775bSDaniel Vetter if (unlikely(!*num_sg)) 113831cd445SChris Wilson goto err; 114831cd445SChris Wilson 115f51b7662SDaniel Vetter return 0; 116831cd445SChris Wilson 117831cd445SChris Wilson err: 118831cd445SChris Wilson sg_free_table(&st); 119831cd445SChris Wilson return -ENOMEM; 120f51b7662SDaniel Vetter } 1214080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_map_memory); 122f51b7662SDaniel Vetter 1234080775bSDaniel Vetter void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 124f51b7662SDaniel Vetter { 1254080775bSDaniel Vetter struct sg_table st; 126f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 127f51b7662SDaniel Vetter 1284080775bSDaniel Vetter pci_unmap_sg(intel_private.pcidev, sg_list, 1294080775bSDaniel Vetter num_sg, PCI_DMA_BIDIRECTIONAL); 1304080775bSDaniel Vetter 1314080775bSDaniel Vetter st.sgl = sg_list; 1324080775bSDaniel Vetter st.orig_nents = st.nents = num_sg; 1334080775bSDaniel Vetter 1344080775bSDaniel Vetter sg_free_table(&st); 135f51b7662SDaniel Vetter } 1364080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_unmap_memory); 137f51b7662SDaniel Vetter 138ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 139f51b7662SDaniel Vetter { 140f51b7662SDaniel Vetter return; 141f51b7662SDaniel Vetter } 142f51b7662SDaniel Vetter 143f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 144f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 145f51b7662SDaniel Vetter { 146f51b7662SDaniel Vetter struct page *page; 147f51b7662SDaniel Vetter 148f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 149f51b7662SDaniel Vetter if (page == NULL) 150f51b7662SDaniel Vetter return NULL; 151f51b7662SDaniel Vetter 152f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 153f51b7662SDaniel Vetter set_pages_wb(page, 4); 154f51b7662SDaniel Vetter __free_pages(page, 2); 155f51b7662SDaniel Vetter return NULL; 156f51b7662SDaniel Vetter } 157f51b7662SDaniel Vetter get_page(page); 158f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 159f51b7662SDaniel Vetter return page; 160f51b7662SDaniel Vetter } 161f51b7662SDaniel Vetter 162f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 163f51b7662SDaniel Vetter { 164f51b7662SDaniel Vetter if (page == NULL) 165f51b7662SDaniel Vetter return; 166f51b7662SDaniel Vetter 167f51b7662SDaniel Vetter set_pages_wb(page, 4); 168f51b7662SDaniel Vetter put_page(page); 169f51b7662SDaniel Vetter __free_pages(page, 2); 170f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 171f51b7662SDaniel Vetter } 172f51b7662SDaniel Vetter 173820647b9SDaniel Vetter #define I810_GTT_ORDER 4 174820647b9SDaniel Vetter static int i810_setup(void) 175820647b9SDaniel Vetter { 176820647b9SDaniel Vetter u32 reg_addr; 177820647b9SDaniel Vetter char *gtt_table; 178820647b9SDaniel Vetter 179820647b9SDaniel Vetter /* i81x does not preallocate the gtt. It's always 64kb in size. */ 180820647b9SDaniel Vetter gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 181820647b9SDaniel Vetter if (gtt_table == NULL) 182820647b9SDaniel Vetter return -ENOMEM; 183820647b9SDaniel Vetter intel_private.i81x_gtt_table = gtt_table; 184820647b9SDaniel Vetter 185820647b9SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 186820647b9SDaniel Vetter reg_addr &= 0xfff80000; 187820647b9SDaniel Vetter 188820647b9SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 189820647b9SDaniel Vetter if (!intel_private.registers) 190820647b9SDaniel Vetter return -ENOMEM; 191820647b9SDaniel Vetter 192820647b9SDaniel Vetter writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 193820647b9SDaniel Vetter intel_private.registers+I810_PGETBL_CTL); 194820647b9SDaniel Vetter 195820647b9SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 196820647b9SDaniel Vetter 197820647b9SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 198820647b9SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 199820647b9SDaniel Vetter dev_info(&intel_private.pcidev->dev, 200820647b9SDaniel Vetter "detected 4MB dedicated video ram\n"); 201820647b9SDaniel Vetter intel_private.num_dcache_entries = 1024; 202820647b9SDaniel Vetter } 203820647b9SDaniel Vetter 204820647b9SDaniel Vetter return 0; 205820647b9SDaniel Vetter } 206820647b9SDaniel Vetter 207820647b9SDaniel Vetter static void i810_cleanup(void) 208820647b9SDaniel Vetter { 209820647b9SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 210820647b9SDaniel Vetter free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 211820647b9SDaniel Vetter } 212820647b9SDaniel Vetter 213ff26860fSDaniel Vetter static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 214f51b7662SDaniel Vetter int type) 215f51b7662SDaniel Vetter { 216f51b7662SDaniel Vetter int i; 217f51b7662SDaniel Vetter 218625dd9d3SDaniel Vetter if ((pg_start + mem->page_count) 219625dd9d3SDaniel Vetter > intel_private.num_dcache_entries) 220625dd9d3SDaniel Vetter return -EINVAL; 221f51b7662SDaniel Vetter 222625dd9d3SDaniel Vetter if (!mem->is_flushed) 223625dd9d3SDaniel Vetter global_cache_flush(); 224625dd9d3SDaniel Vetter 225625dd9d3SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 226625dd9d3SDaniel Vetter dma_addr_t addr = i << PAGE_SHIFT; 227625dd9d3SDaniel Vetter intel_private.driver->write_entry(addr, 228625dd9d3SDaniel Vetter i, type); 229f51b7662SDaniel Vetter } 230625dd9d3SDaniel Vetter readl(intel_private.gtt+i-1); 231f51b7662SDaniel Vetter 232f51b7662SDaniel Vetter return 0; 233f51b7662SDaniel Vetter } 234f51b7662SDaniel Vetter 235f51b7662SDaniel Vetter /* 236f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 237f51b7662SDaniel Vetter * pointer into hardware. 238f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 239f51b7662SDaniel Vetter */ 240f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 241f51b7662SDaniel Vetter { 242f51b7662SDaniel Vetter struct agp_memory *new; 243f51b7662SDaniel Vetter struct page *page; 244f51b7662SDaniel Vetter 245f51b7662SDaniel Vetter switch (pg_count) { 246f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 247f51b7662SDaniel Vetter break; 248f51b7662SDaniel Vetter case 4: 249f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 250f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 251f51b7662SDaniel Vetter break; 252f51b7662SDaniel Vetter default: 253f51b7662SDaniel Vetter return NULL; 254f51b7662SDaniel Vetter } 255f51b7662SDaniel Vetter 256f51b7662SDaniel Vetter if (page == NULL) 257f51b7662SDaniel Vetter return NULL; 258f51b7662SDaniel Vetter 259f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 260f51b7662SDaniel Vetter if (new == NULL) 261f51b7662SDaniel Vetter return NULL; 262f51b7662SDaniel Vetter 263f51b7662SDaniel Vetter new->pages[0] = page; 264f51b7662SDaniel Vetter if (pg_count == 4) { 265f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 266f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 267f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 268f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 269f51b7662SDaniel Vetter } 270f51b7662SDaniel Vetter new->page_count = pg_count; 271f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 272f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 273f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 274f51b7662SDaniel Vetter return new; 275f51b7662SDaniel Vetter } 276f51b7662SDaniel Vetter 277f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 278f51b7662SDaniel Vetter { 279f51b7662SDaniel Vetter agp_free_key(curr->key); 280f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 281f51b7662SDaniel Vetter if (curr->page_count == 4) 282f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 283f51b7662SDaniel Vetter else { 284f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 285f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 286f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 287f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 288f51b7662SDaniel Vetter } 289f51b7662SDaniel Vetter agp_free_page_array(curr); 290f51b7662SDaniel Vetter } 291f51b7662SDaniel Vetter kfree(curr); 292f51b7662SDaniel Vetter } 293f51b7662SDaniel Vetter 2940e87d2b0SDaniel Vetter static int intel_gtt_setup_scratch_page(void) 2950e87d2b0SDaniel Vetter { 2960e87d2b0SDaniel Vetter struct page *page; 2970e87d2b0SDaniel Vetter dma_addr_t dma_addr; 2980e87d2b0SDaniel Vetter 2990e87d2b0SDaniel Vetter page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 3000e87d2b0SDaniel Vetter if (page == NULL) 3010e87d2b0SDaniel Vetter return -ENOMEM; 3020e87d2b0SDaniel Vetter get_page(page); 3030e87d2b0SDaniel Vetter set_pages_uc(page, 1); 3040e87d2b0SDaniel Vetter 3054080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 3060e87d2b0SDaniel Vetter dma_addr = pci_map_page(intel_private.pcidev, page, 0, 3070e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 3080e87d2b0SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 3090e87d2b0SDaniel Vetter return -EINVAL; 3100e87d2b0SDaniel Vetter 3110e87d2b0SDaniel Vetter intel_private.scratch_page_dma = dma_addr; 3120e87d2b0SDaniel Vetter } else 3130e87d2b0SDaniel Vetter intel_private.scratch_page_dma = page_to_phys(page); 3140e87d2b0SDaniel Vetter 3150e87d2b0SDaniel Vetter intel_private.scratch_page = page; 3160e87d2b0SDaniel Vetter 3170e87d2b0SDaniel Vetter return 0; 3180e87d2b0SDaniel Vetter } 3190e87d2b0SDaniel Vetter 320625dd9d3SDaniel Vetter static void i810_write_entry(dma_addr_t addr, unsigned int entry, 321625dd9d3SDaniel Vetter unsigned int flags) 322625dd9d3SDaniel Vetter { 323625dd9d3SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 324625dd9d3SDaniel Vetter 325625dd9d3SDaniel Vetter switch (flags) { 326625dd9d3SDaniel Vetter case AGP_DCACHE_MEMORY: 327625dd9d3SDaniel Vetter pte_flags |= I810_PTE_LOCAL; 328625dd9d3SDaniel Vetter break; 329625dd9d3SDaniel Vetter case AGP_USER_CACHED_MEMORY: 330625dd9d3SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 331625dd9d3SDaniel Vetter break; 332625dd9d3SDaniel Vetter } 333625dd9d3SDaniel Vetter 334625dd9d3SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 335625dd9d3SDaniel Vetter } 336625dd9d3SDaniel Vetter 3377bdc9ab0SChris Wilson static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 338820647b9SDaniel Vetter {32, 8192, 3}, 339820647b9SDaniel Vetter {64, 16384, 4}, 340f51b7662SDaniel Vetter {128, 32768, 5}, 341f51b7662SDaniel Vetter {256, 65536, 6}, 342f51b7662SDaniel Vetter {512, 131072, 7}, 343f51b7662SDaniel Vetter }; 344f51b7662SDaniel Vetter 345c64f7ba5SChris Wilson static unsigned int intel_gtt_stolen_size(void) 346f51b7662SDaniel Vetter { 347f51b7662SDaniel Vetter u16 gmch_ctrl; 348f51b7662SDaniel Vetter u8 rdct; 349f51b7662SDaniel Vetter int local = 0; 350f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 351d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 352f51b7662SDaniel Vetter 353820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) 354820647b9SDaniel Vetter return 0; /* no stolen mem on i81x */ 355820647b9SDaniel Vetter 356d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 357d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 358f51b7662SDaniel Vetter 359d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 360d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 361f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 362f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 363d8d9abcdSDaniel Vetter stolen_size = KB(512); 364f51b7662SDaniel Vetter break; 365f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 366d8d9abcdSDaniel Vetter stolen_size = MB(1); 367f51b7662SDaniel Vetter break; 368f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 369d8d9abcdSDaniel Vetter stolen_size = MB(8); 370f51b7662SDaniel Vetter break; 371f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 372f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 373d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 374f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 375f51b7662SDaniel Vetter local = 1; 376f51b7662SDaniel Vetter break; 377f51b7662SDaniel Vetter default: 378d8d9abcdSDaniel Vetter stolen_size = 0; 379f51b7662SDaniel Vetter break; 380f51b7662SDaniel Vetter } 3811a997ff2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 382f51b7662SDaniel Vetter /* 383f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 384f51b7662SDaniel Vetter */ 385f51b7662SDaniel Vetter u16 snb_gmch_ctl; 386f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 387f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 388f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 389d8d9abcdSDaniel Vetter stolen_size = MB(32); 390f51b7662SDaniel Vetter break; 391f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 392d8d9abcdSDaniel Vetter stolen_size = MB(64); 393f51b7662SDaniel Vetter break; 394f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 395d8d9abcdSDaniel Vetter stolen_size = MB(96); 396f51b7662SDaniel Vetter break; 397f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 398d8d9abcdSDaniel Vetter stolen_size = MB(128); 399f51b7662SDaniel Vetter break; 400f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 401d8d9abcdSDaniel Vetter stolen_size = MB(160); 402f51b7662SDaniel Vetter break; 403f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 404d8d9abcdSDaniel Vetter stolen_size = MB(192); 405f51b7662SDaniel Vetter break; 406f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 407d8d9abcdSDaniel Vetter stolen_size = MB(224); 408f51b7662SDaniel Vetter break; 409f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 410d8d9abcdSDaniel Vetter stolen_size = MB(256); 411f51b7662SDaniel Vetter break; 412f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 413d8d9abcdSDaniel Vetter stolen_size = MB(288); 414f51b7662SDaniel Vetter break; 415f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 416d8d9abcdSDaniel Vetter stolen_size = MB(320); 417f51b7662SDaniel Vetter break; 418f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 419d8d9abcdSDaniel Vetter stolen_size = MB(352); 420f51b7662SDaniel Vetter break; 421f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 422d8d9abcdSDaniel Vetter stolen_size = MB(384); 423f51b7662SDaniel Vetter break; 424f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 425d8d9abcdSDaniel Vetter stolen_size = MB(416); 426f51b7662SDaniel Vetter break; 427f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 428d8d9abcdSDaniel Vetter stolen_size = MB(448); 429f51b7662SDaniel Vetter break; 430f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 431d8d9abcdSDaniel Vetter stolen_size = MB(480); 432f51b7662SDaniel Vetter break; 433f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 434d8d9abcdSDaniel Vetter stolen_size = MB(512); 435f51b7662SDaniel Vetter break; 436f51b7662SDaniel Vetter } 437f51b7662SDaniel Vetter } else { 438f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 439f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 440d8d9abcdSDaniel Vetter stolen_size = MB(1); 441f51b7662SDaniel Vetter break; 442f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 443d8d9abcdSDaniel Vetter stolen_size = MB(4); 444f51b7662SDaniel Vetter break; 445f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 446d8d9abcdSDaniel Vetter stolen_size = MB(8); 447f51b7662SDaniel Vetter break; 448f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 449d8d9abcdSDaniel Vetter stolen_size = MB(16); 450f51b7662SDaniel Vetter break; 451f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 452d8d9abcdSDaniel Vetter stolen_size = MB(32); 453f51b7662SDaniel Vetter break; 454f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 455d8d9abcdSDaniel Vetter stolen_size = MB(48); 456f51b7662SDaniel Vetter break; 457f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 458d8d9abcdSDaniel Vetter stolen_size = MB(64); 459f51b7662SDaniel Vetter break; 460f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 461d8d9abcdSDaniel Vetter stolen_size = MB(128); 462f51b7662SDaniel Vetter break; 463f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 464d8d9abcdSDaniel Vetter stolen_size = MB(256); 465f51b7662SDaniel Vetter break; 466f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 467d8d9abcdSDaniel Vetter stolen_size = MB(96); 468f51b7662SDaniel Vetter break; 469f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 470d8d9abcdSDaniel Vetter stolen_size = MB(160); 471f51b7662SDaniel Vetter break; 472f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 473d8d9abcdSDaniel Vetter stolen_size = MB(224); 474f51b7662SDaniel Vetter break; 475f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 476d8d9abcdSDaniel Vetter stolen_size = MB(352); 477f51b7662SDaniel Vetter break; 478f51b7662SDaniel Vetter default: 479d8d9abcdSDaniel Vetter stolen_size = 0; 480f51b7662SDaniel Vetter break; 481f51b7662SDaniel Vetter } 482f51b7662SDaniel Vetter } 4831784a5fbSDaniel Vetter 4841b6064d7SChris Wilson if (stolen_size > 0) { 485d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 486d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 487f51b7662SDaniel Vetter } else { 488d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 489f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 490d8d9abcdSDaniel Vetter stolen_size = 0; 491f51b7662SDaniel Vetter } 492f51b7662SDaniel Vetter 493c64f7ba5SChris Wilson return stolen_size; 494f51b7662SDaniel Vetter } 495f51b7662SDaniel Vetter 49620172842SDaniel Vetter static void i965_adjust_pgetbl_size(unsigned int size_flag) 49720172842SDaniel Vetter { 49820172842SDaniel Vetter u32 pgetbl_ctl, pgetbl_ctl2; 49920172842SDaniel Vetter 50020172842SDaniel Vetter /* ensure that ppgtt is disabled */ 50120172842SDaniel Vetter pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 50220172842SDaniel Vetter pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 50320172842SDaniel Vetter writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 50420172842SDaniel Vetter 50520172842SDaniel Vetter /* write the new ggtt size */ 50620172842SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 50720172842SDaniel Vetter pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 50820172842SDaniel Vetter pgetbl_ctl |= size_flag; 50920172842SDaniel Vetter writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 51020172842SDaniel Vetter } 51120172842SDaniel Vetter 51220172842SDaniel Vetter static unsigned int i965_gtt_total_entries(void) 513fbe40783SDaniel Vetter { 514fbe40783SDaniel Vetter int size; 515fbe40783SDaniel Vetter u32 pgetbl_ctl; 51620172842SDaniel Vetter u16 gmch_ctl; 51720172842SDaniel Vetter 51820172842SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 51920172842SDaniel Vetter I830_GMCH_CTRL, &gmch_ctl); 52020172842SDaniel Vetter 52120172842SDaniel Vetter if (INTEL_GTT_GEN == 5) { 52220172842SDaniel Vetter switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 52320172842SDaniel Vetter case G4x_GMCH_SIZE_1M: 52420172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1M: 52520172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 52620172842SDaniel Vetter break; 52720172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1_5M: 52820172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 52920172842SDaniel Vetter break; 53020172842SDaniel Vetter case G4x_GMCH_SIZE_2M: 53120172842SDaniel Vetter case G4x_GMCH_SIZE_VT_2M: 53220172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 53320172842SDaniel Vetter break; 53420172842SDaniel Vetter } 53520172842SDaniel Vetter } 53620172842SDaniel Vetter 537fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 538fbe40783SDaniel Vetter 539fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 540fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 541e5e408fcSDaniel Vetter size = KB(128); 542fbe40783SDaniel Vetter break; 543fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 544e5e408fcSDaniel Vetter size = KB(256); 545fbe40783SDaniel Vetter break; 546fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 547e5e408fcSDaniel Vetter size = KB(512); 548fbe40783SDaniel Vetter break; 54920172842SDaniel Vetter /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 550fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 551e5e408fcSDaniel Vetter size = KB(1024); 552fbe40783SDaniel Vetter break; 553fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 554e5e408fcSDaniel Vetter size = KB(2048); 555fbe40783SDaniel Vetter break; 556fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 557e5e408fcSDaniel Vetter size = KB(1024 + 512); 558fbe40783SDaniel Vetter break; 559fbe40783SDaniel Vetter default: 560fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 561fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 562e5e408fcSDaniel Vetter size = KB(512); 563fbe40783SDaniel Vetter } 564e5e408fcSDaniel Vetter 565e5e408fcSDaniel Vetter return size/4; 56620172842SDaniel Vetter } 56720172842SDaniel Vetter 56820172842SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 56920172842SDaniel Vetter { 57020172842SDaniel Vetter int size; 57120172842SDaniel Vetter 57220172842SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 57320172842SDaniel Vetter return i965_gtt_total_entries(); 57420172842SDaniel Vetter else if (INTEL_GTT_GEN == 6) { 575210b23c2SDaniel Vetter u16 snb_gmch_ctl; 576210b23c2SDaniel Vetter 577210b23c2SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 578210b23c2SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 579210b23c2SDaniel Vetter default: 580210b23c2SDaniel Vetter case SNB_GTT_SIZE_0M: 581210b23c2SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 582210b23c2SDaniel Vetter size = MB(0); 583210b23c2SDaniel Vetter break; 584210b23c2SDaniel Vetter case SNB_GTT_SIZE_1M: 585210b23c2SDaniel Vetter size = MB(1); 586210b23c2SDaniel Vetter break; 587210b23c2SDaniel Vetter case SNB_GTT_SIZE_2M: 588210b23c2SDaniel Vetter size = MB(2); 589210b23c2SDaniel Vetter break; 590210b23c2SDaniel Vetter } 591210b23c2SDaniel Vetter return size/4; 592fbe40783SDaniel Vetter } else { 593fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 594fbe40783SDaniel Vetter * required to map the aperture. 595fbe40783SDaniel Vetter */ 596e5e408fcSDaniel Vetter return intel_private.base.gtt_mappable_entries; 597fbe40783SDaniel Vetter } 598fbe40783SDaniel Vetter } 599fbe40783SDaniel Vetter 6001784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 6011784a5fbSDaniel Vetter { 6021784a5fbSDaniel Vetter unsigned int aperture_size; 6031784a5fbSDaniel Vetter 604820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) { 605820647b9SDaniel Vetter u32 smram_miscc; 606820647b9SDaniel Vetter 607820647b9SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 608820647b9SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 609820647b9SDaniel Vetter 610820647b9SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 611820647b9SDaniel Vetter == I810_GFX_MEM_WIN_32M) 612820647b9SDaniel Vetter aperture_size = MB(32); 613820647b9SDaniel Vetter else 614820647b9SDaniel Vetter aperture_size = MB(64); 615820647b9SDaniel Vetter } else if (INTEL_GTT_GEN == 2) { 616b1c5b0f8SChris Wilson u16 gmch_ctrl; 6171784a5fbSDaniel Vetter 6181784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 6191784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 6201784a5fbSDaniel Vetter 6211784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 622b1c5b0f8SChris Wilson aperture_size = MB(64); 6231784a5fbSDaniel Vetter else 624b1c5b0f8SChris Wilson aperture_size = MB(128); 625239918f7SDaniel Vetter } else { 6261784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 6271784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 6281784a5fbSDaniel Vetter } 6291784a5fbSDaniel Vetter 6301784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 6311784a5fbSDaniel Vetter } 6321784a5fbSDaniel Vetter 6330e87d2b0SDaniel Vetter static void intel_gtt_teardown_scratch_page(void) 6340e87d2b0SDaniel Vetter { 6350e87d2b0SDaniel Vetter set_pages_wb(intel_private.scratch_page, 1); 6360e87d2b0SDaniel Vetter pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 6370e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 6380e87d2b0SDaniel Vetter put_page(intel_private.scratch_page); 6390e87d2b0SDaniel Vetter __free_page(intel_private.scratch_page); 6400e87d2b0SDaniel Vetter } 6410e87d2b0SDaniel Vetter 6420e87d2b0SDaniel Vetter static void intel_gtt_cleanup(void) 6430e87d2b0SDaniel Vetter { 644ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 645ae83dd5cSDaniel Vetter 6460e87d2b0SDaniel Vetter iounmap(intel_private.gtt); 6470e87d2b0SDaniel Vetter iounmap(intel_private.registers); 6480e87d2b0SDaniel Vetter 6490e87d2b0SDaniel Vetter intel_gtt_teardown_scratch_page(); 6500e87d2b0SDaniel Vetter } 6510e87d2b0SDaniel Vetter 6521784a5fbSDaniel Vetter static int intel_gtt_init(void) 6531784a5fbSDaniel Vetter { 654f67eab66SDaniel Vetter u32 gtt_map_size; 6553b15a9d7SDaniel Vetter int ret; 6563b15a9d7SDaniel Vetter 6573b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 6583b15a9d7SDaniel Vetter if (ret != 0) 6593b15a9d7SDaniel Vetter return ret; 660f67eab66SDaniel Vetter 661f67eab66SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 662f67eab66SDaniel Vetter intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 663f67eab66SDaniel Vetter 664b3eafc5aSDaniel Vetter /* save the PGETBL reg for resume */ 665b3eafc5aSDaniel Vetter intel_private.PGETBL_save = 666b3eafc5aSDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL) 667b3eafc5aSDaniel Vetter & ~I810_PGETBL_ENABLED; 668100519e2SChris Wilson /* we only ever restore the register when enabling the PGTBL... */ 669100519e2SChris Wilson if (HAS_PGTBL_EN) 670100519e2SChris Wilson intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 671b3eafc5aSDaniel Vetter 6720af9e92eSDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 6730af9e92eSDaniel Vetter "detected gtt size: %dK total, %dK mappable\n", 6740af9e92eSDaniel Vetter intel_private.base.gtt_total_entries * 4, 6750af9e92eSDaniel Vetter intel_private.base.gtt_mappable_entries * 4); 6760af9e92eSDaniel Vetter 677f67eab66SDaniel Vetter gtt_map_size = intel_private.base.gtt_total_entries * 4; 678f67eab66SDaniel Vetter 679f67eab66SDaniel Vetter intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 680f67eab66SDaniel Vetter gtt_map_size); 681f67eab66SDaniel Vetter if (!intel_private.gtt) { 682ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 683f67eab66SDaniel Vetter iounmap(intel_private.registers); 684f67eab66SDaniel Vetter return -ENOMEM; 685f67eab66SDaniel Vetter } 686f67eab66SDaniel Vetter 687f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 688f67eab66SDaniel Vetter 689c64f7ba5SChris Wilson intel_private.base.stolen_size = intel_gtt_stolen_size(); 6901784a5fbSDaniel Vetter 691a46f3108SDave Airlie intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 692a46f3108SDave Airlie 6930e87d2b0SDaniel Vetter ret = intel_gtt_setup_scratch_page(); 6940e87d2b0SDaniel Vetter if (ret != 0) { 6950e87d2b0SDaniel Vetter intel_gtt_cleanup(); 6960e87d2b0SDaniel Vetter return ret; 6970e87d2b0SDaniel Vetter } 6980e87d2b0SDaniel Vetter 6991784a5fbSDaniel Vetter return 0; 7001784a5fbSDaniel Vetter } 7011784a5fbSDaniel Vetter 7023e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 7033e921f98SDaniel Vetter { 7049e76e7b8SChris Wilson int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 7053e921f98SDaniel Vetter unsigned int aper_size; 7063e921f98SDaniel Vetter int i; 7073e921f98SDaniel Vetter 7083e921f98SDaniel Vetter aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 7093e921f98SDaniel Vetter / MB(1); 7103e921f98SDaniel Vetter 7113e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 712ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 7139e76e7b8SChris Wilson agp_bridge->current_size = 7149e76e7b8SChris Wilson (void *) (intel_fake_agp_sizes + i); 7153e921f98SDaniel Vetter return aper_size; 7163e921f98SDaniel Vetter } 7173e921f98SDaniel Vetter } 7183e921f98SDaniel Vetter 7193e921f98SDaniel Vetter return 0; 7203e921f98SDaniel Vetter } 7213e921f98SDaniel Vetter 722ae83dd5cSDaniel Vetter static void i830_cleanup(void) 723f51b7662SDaniel Vetter { 724136711beSTakashi Iwai if (intel_private.i8xx_flush_page) { 725136711beSTakashi Iwai kunmap(intel_private.i8xx_flush_page); 726f51b7662SDaniel Vetter intel_private.i8xx_flush_page = NULL; 727136711beSTakashi Iwai } 728f51b7662SDaniel Vetter 729f51b7662SDaniel Vetter __free_page(intel_private.i8xx_page); 730f51b7662SDaniel Vetter intel_private.i8xx_page = NULL; 731f51b7662SDaniel Vetter } 732f51b7662SDaniel Vetter 733f51b7662SDaniel Vetter static void intel_i830_setup_flush(void) 734f51b7662SDaniel Vetter { 735f51b7662SDaniel Vetter /* return if we've already set the flush mechanism up */ 736f51b7662SDaniel Vetter if (intel_private.i8xx_page) 737f51b7662SDaniel Vetter return; 738f51b7662SDaniel Vetter 739e61cb0d5SJan Beulich intel_private.i8xx_page = alloc_page(GFP_KERNEL); 740f51b7662SDaniel Vetter if (!intel_private.i8xx_page) 741f51b7662SDaniel Vetter return; 742f51b7662SDaniel Vetter 743f51b7662SDaniel Vetter intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 744f51b7662SDaniel Vetter if (!intel_private.i8xx_flush_page) 745ae83dd5cSDaniel Vetter i830_cleanup(); 746f51b7662SDaniel Vetter } 747f51b7662SDaniel Vetter 748f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 749f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 750f51b7662SDaniel Vetter * doesn't snoop those buffers. 751f51b7662SDaniel Vetter * 752f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 753f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 754f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 755f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 756f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 757f51b7662SDaniel Vetter */ 7581b263f24SDaniel Vetter static void i830_chipset_flush(void) 759f51b7662SDaniel Vetter { 760f51b7662SDaniel Vetter unsigned int *pg = intel_private.i8xx_flush_page; 761f51b7662SDaniel Vetter 762f51b7662SDaniel Vetter memset(pg, 0, 1024); 763f51b7662SDaniel Vetter 764f51b7662SDaniel Vetter if (cpu_has_clflush) 765f51b7662SDaniel Vetter clflush_cache_range(pg, 1024); 766f51b7662SDaniel Vetter else if (wbinvd_on_all_cpus() != 0) 767f51b7662SDaniel Vetter printk(KERN_ERR "Timed out waiting for cache flush.\n"); 768f51b7662SDaniel Vetter } 769f51b7662SDaniel Vetter 770351bb278SDaniel Vetter static void i830_write_entry(dma_addr_t addr, unsigned int entry, 771351bb278SDaniel Vetter unsigned int flags) 772351bb278SDaniel Vetter { 773351bb278SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 774351bb278SDaniel Vetter 775b47cf66fSDaniel Vetter if (flags == AGP_USER_CACHED_MEMORY) 776351bb278SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 777351bb278SDaniel Vetter 778351bb278SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 779351bb278SDaniel Vetter } 780351bb278SDaniel Vetter 781e380f60bSChris Wilson static bool intel_enable_gtt(void) 78273800422SDaniel Vetter { 7833f08e4efSChris Wilson u32 gma_addr; 784e380f60bSChris Wilson u8 __iomem *reg; 78573800422SDaniel Vetter 786820647b9SDaniel Vetter if (INTEL_GTT_GEN <= 2) 7872d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 7882d2430cfSDaniel Vetter &gma_addr); 7892d2430cfSDaniel Vetter else 7902d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 7912d2430cfSDaniel Vetter &gma_addr); 7922d2430cfSDaniel Vetter 79373800422SDaniel Vetter intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 79473800422SDaniel Vetter 795e380f60bSChris Wilson if (INTEL_GTT_GEN >= 6) 796e380f60bSChris Wilson return true; 79773800422SDaniel Vetter 798100519e2SChris Wilson if (INTEL_GTT_GEN == 2) { 799100519e2SChris Wilson u16 gmch_ctrl; 800100519e2SChris Wilson 801e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 802e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 803e380f60bSChris Wilson gmch_ctrl |= I830_GMCH_ENABLED; 804e380f60bSChris Wilson pci_write_config_word(intel_private.bridge_dev, 805e380f60bSChris Wilson I830_GMCH_CTRL, gmch_ctrl); 806e380f60bSChris Wilson 807e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 808e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 809e380f60bSChris Wilson if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 810e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 811e380f60bSChris Wilson "failed to enable the GTT: GMCH_CTRL=%x\n", 812e380f60bSChris Wilson gmch_ctrl); 813e380f60bSChris Wilson return false; 814e380f60bSChris Wilson } 815100519e2SChris Wilson } 816e380f60bSChris Wilson 817c97689d8SChris Wilson /* On the resume path we may be adjusting the PGTBL value, so 818c97689d8SChris Wilson * be paranoid and flush all chipset write buffers... 819c97689d8SChris Wilson */ 820c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 821c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 822c97689d8SChris Wilson 823e380f60bSChris Wilson reg = intel_private.registers+I810_PGETBL_CTL; 824100519e2SChris Wilson writel(intel_private.PGETBL_save, reg); 825100519e2SChris Wilson if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 826e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 827100519e2SChris Wilson "failed to enable the GTT: PGETBL=%x [expected %x]\n", 828e380f60bSChris Wilson readl(reg), intel_private.PGETBL_save); 829e380f60bSChris Wilson return false; 830e380f60bSChris Wilson } 831e380f60bSChris Wilson 832c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 833c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 834c97689d8SChris Wilson 835e380f60bSChris Wilson return true; 83673800422SDaniel Vetter } 83773800422SDaniel Vetter 83873800422SDaniel Vetter static int i830_setup(void) 83973800422SDaniel Vetter { 84073800422SDaniel Vetter u32 reg_addr; 84173800422SDaniel Vetter 84273800422SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 84373800422SDaniel Vetter reg_addr &= 0xfff80000; 84473800422SDaniel Vetter 84573800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 84673800422SDaniel Vetter if (!intel_private.registers) 84773800422SDaniel Vetter return -ENOMEM; 84873800422SDaniel Vetter 84973800422SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 85073800422SDaniel Vetter 85173800422SDaniel Vetter intel_i830_setup_flush(); 85273800422SDaniel Vetter 85373800422SDaniel Vetter return 0; 85473800422SDaniel Vetter } 85573800422SDaniel Vetter 8563b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 857f51b7662SDaniel Vetter { 85873800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 859f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 86073800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 861f51b7662SDaniel Vetter 862f51b7662SDaniel Vetter return 0; 863f51b7662SDaniel Vetter } 864f51b7662SDaniel Vetter 865ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 866f51b7662SDaniel Vetter { 867f51b7662SDaniel Vetter return 0; 868f51b7662SDaniel Vetter } 869f51b7662SDaniel Vetter 870351bb278SDaniel Vetter static int intel_fake_agp_configure(void) 871f51b7662SDaniel Vetter { 872f51b7662SDaniel Vetter int i; 873f51b7662SDaniel Vetter 874e380f60bSChris Wilson if (!intel_enable_gtt()) 875e380f60bSChris Wilson return -EIO; 876f51b7662SDaniel Vetter 87773800422SDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 878f51b7662SDaniel Vetter 879c64f7ba5SChris Wilson for (i = 0; i < intel_private.base.gtt_total_entries; i++) { 880351bb278SDaniel Vetter intel_private.driver->write_entry(intel_private.scratch_page_dma, 881351bb278SDaniel Vetter i, 0); 882f51b7662SDaniel Vetter } 883fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 884f51b7662SDaniel Vetter 885f51b7662SDaniel Vetter global_cache_flush(); 886f51b7662SDaniel Vetter 887f51b7662SDaniel Vetter return 0; 888f51b7662SDaniel Vetter } 889f51b7662SDaniel Vetter 8905cbecafcSDaniel Vetter static bool i830_check_flags(unsigned int flags) 891f51b7662SDaniel Vetter { 8925cbecafcSDaniel Vetter switch (flags) { 8935cbecafcSDaniel Vetter case 0: 8945cbecafcSDaniel Vetter case AGP_PHYS_MEMORY: 8955cbecafcSDaniel Vetter case AGP_USER_CACHED_MEMORY: 8965cbecafcSDaniel Vetter case AGP_USER_MEMORY: 8975cbecafcSDaniel Vetter return true; 8985cbecafcSDaniel Vetter } 8995cbecafcSDaniel Vetter 9005cbecafcSDaniel Vetter return false; 9015cbecafcSDaniel Vetter } 9025cbecafcSDaniel Vetter 9034080775bSDaniel Vetter void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 904fefaa70fSDaniel Vetter unsigned int sg_len, 905fefaa70fSDaniel Vetter unsigned int pg_start, 906fefaa70fSDaniel Vetter unsigned int flags) 907fefaa70fSDaniel Vetter { 908fefaa70fSDaniel Vetter struct scatterlist *sg; 909fefaa70fSDaniel Vetter unsigned int len, m; 910fefaa70fSDaniel Vetter int i, j; 911fefaa70fSDaniel Vetter 912fefaa70fSDaniel Vetter j = pg_start; 913fefaa70fSDaniel Vetter 914fefaa70fSDaniel Vetter /* sg may merge pages, but we have to separate 915fefaa70fSDaniel Vetter * per-page addr for GTT */ 916fefaa70fSDaniel Vetter for_each_sg(sg_list, sg, sg_len, i) { 917fefaa70fSDaniel Vetter len = sg_dma_len(sg) >> PAGE_SHIFT; 918fefaa70fSDaniel Vetter for (m = 0; m < len; m++) { 919fefaa70fSDaniel Vetter dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 920fefaa70fSDaniel Vetter intel_private.driver->write_entry(addr, 921fefaa70fSDaniel Vetter j, flags); 922fefaa70fSDaniel Vetter j++; 923fefaa70fSDaniel Vetter } 924fefaa70fSDaniel Vetter } 925fefaa70fSDaniel Vetter readl(intel_private.gtt+j-1); 926fefaa70fSDaniel Vetter } 9274080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 9284080775bSDaniel Vetter 9294080775bSDaniel Vetter void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 9304080775bSDaniel Vetter struct page **pages, unsigned int flags) 9314080775bSDaniel Vetter { 9324080775bSDaniel Vetter int i, j; 9334080775bSDaniel Vetter 9344080775bSDaniel Vetter for (i = 0, j = first_entry; i < num_entries; i++, j++) { 9354080775bSDaniel Vetter dma_addr_t addr = page_to_phys(pages[i]); 9364080775bSDaniel Vetter intel_private.driver->write_entry(addr, 9374080775bSDaniel Vetter j, flags); 9384080775bSDaniel Vetter } 9394080775bSDaniel Vetter readl(intel_private.gtt+j-1); 9404080775bSDaniel Vetter } 9414080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_insert_pages); 942fefaa70fSDaniel Vetter 9435cbecafcSDaniel Vetter static int intel_fake_agp_insert_entries(struct agp_memory *mem, 9445cbecafcSDaniel Vetter off_t pg_start, int type) 9455cbecafcSDaniel Vetter { 946f51b7662SDaniel Vetter int ret = -EINVAL; 947f51b7662SDaniel Vetter 948ff26860fSDaniel Vetter if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 949ff26860fSDaniel Vetter return i810_insert_dcache_entries(mem, pg_start, type); 950ff26860fSDaniel Vetter 951f51b7662SDaniel Vetter if (mem->page_count == 0) 952f51b7662SDaniel Vetter goto out; 953f51b7662SDaniel Vetter 954c64f7ba5SChris Wilson if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) 955f51b7662SDaniel Vetter goto out_err; 956f51b7662SDaniel Vetter 957f51b7662SDaniel Vetter if (type != mem->type) 958f51b7662SDaniel Vetter goto out_err; 959f51b7662SDaniel Vetter 9605cbecafcSDaniel Vetter if (!intel_private.driver->check_flags(type)) 961f51b7662SDaniel Vetter goto out_err; 962f51b7662SDaniel Vetter 963f51b7662SDaniel Vetter if (!mem->is_flushed) 964f51b7662SDaniel Vetter global_cache_flush(); 965f51b7662SDaniel Vetter 9664080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 9674080775bSDaniel Vetter ret = intel_gtt_map_memory(mem->pages, mem->page_count, 9684080775bSDaniel Vetter &mem->sg_list, &mem->num_sg); 969fefaa70fSDaniel Vetter if (ret != 0) 970fefaa70fSDaniel Vetter return ret; 971fefaa70fSDaniel Vetter 972fefaa70fSDaniel Vetter intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, 973fefaa70fSDaniel Vetter pg_start, type); 9744080775bSDaniel Vetter } else 9754080775bSDaniel Vetter intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 9764080775bSDaniel Vetter type); 977f51b7662SDaniel Vetter 978f51b7662SDaniel Vetter out: 979f51b7662SDaniel Vetter ret = 0; 980f51b7662SDaniel Vetter out_err: 981f51b7662SDaniel Vetter mem->is_flushed = true; 982f51b7662SDaniel Vetter return ret; 983f51b7662SDaniel Vetter } 984f51b7662SDaniel Vetter 9854080775bSDaniel Vetter void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 986f51b7662SDaniel Vetter { 9874080775bSDaniel Vetter unsigned int i; 988f51b7662SDaniel Vetter 9894080775bSDaniel Vetter for (i = first_entry; i < (first_entry + num_entries); i++) { 9905cbecafcSDaniel Vetter intel_private.driver->write_entry(intel_private.scratch_page_dma, 9915cbecafcSDaniel Vetter i, 0); 992f51b7662SDaniel Vetter } 993fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 9944080775bSDaniel Vetter } 9954080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_clear_range); 9964080775bSDaniel Vetter 9974080775bSDaniel Vetter static int intel_fake_agp_remove_entries(struct agp_memory *mem, 9984080775bSDaniel Vetter off_t pg_start, int type) 9994080775bSDaniel Vetter { 10004080775bSDaniel Vetter if (mem->page_count == 0) 10014080775bSDaniel Vetter return 0; 10024080775bSDaniel Vetter 1003d15eda5cSDave Airlie intel_gtt_clear_range(pg_start, mem->page_count); 1004d15eda5cSDave Airlie 10054080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 10064080775bSDaniel Vetter intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 10074080775bSDaniel Vetter mem->sg_list = NULL; 10084080775bSDaniel Vetter mem->num_sg = 0; 10094080775bSDaniel Vetter } 10104080775bSDaniel Vetter 1011f51b7662SDaniel Vetter return 0; 1012f51b7662SDaniel Vetter } 1013f51b7662SDaniel Vetter 1014ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1015ffdd7510SDaniel Vetter int type) 1016f51b7662SDaniel Vetter { 1017625dd9d3SDaniel Vetter struct agp_memory *new; 1018625dd9d3SDaniel Vetter 1019625dd9d3SDaniel Vetter if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 1020625dd9d3SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 1021625dd9d3SDaniel Vetter return NULL; 1022625dd9d3SDaniel Vetter 1023625dd9d3SDaniel Vetter new = agp_create_memory(1); 1024625dd9d3SDaniel Vetter if (new == NULL) 1025625dd9d3SDaniel Vetter return NULL; 1026625dd9d3SDaniel Vetter 1027625dd9d3SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 1028625dd9d3SDaniel Vetter new->page_count = pg_count; 1029625dd9d3SDaniel Vetter new->num_scratch_pages = 0; 1030625dd9d3SDaniel Vetter agp_free_page_array(new); 1031625dd9d3SDaniel Vetter return new; 1032625dd9d3SDaniel Vetter } 1033f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 1034f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 1035f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 1036f51b7662SDaniel Vetter return NULL; 1037f51b7662SDaniel Vetter } 1038f51b7662SDaniel Vetter 1039f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 1040f51b7662SDaniel Vetter { 1041f51b7662SDaniel Vetter int ret; 1042d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1043f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1044d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 1045f51b7662SDaniel Vetter 1046f51b7662SDaniel Vetter return ret; 1047f51b7662SDaniel Vetter } 1048f51b7662SDaniel Vetter 1049f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 1050f51b7662SDaniel Vetter { 1051f51b7662SDaniel Vetter int ret; 1052f51b7662SDaniel Vetter u32 temp; 1053f51b7662SDaniel Vetter 1054d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1055f51b7662SDaniel Vetter if (!(temp & 0x1)) { 1056f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1057f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1058d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1059f51b7662SDaniel Vetter } else { 1060f51b7662SDaniel Vetter temp &= ~1; 1061f51b7662SDaniel Vetter 1062f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1063f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1064f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1065f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1066f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1067f51b7662SDaniel Vetter if (ret) 1068f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1069f51b7662SDaniel Vetter } 1070f51b7662SDaniel Vetter } 1071f51b7662SDaniel Vetter 1072f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1073f51b7662SDaniel Vetter { 1074f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1075f51b7662SDaniel Vetter int ret; 1076f51b7662SDaniel Vetter 1077d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1078d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1079f51b7662SDaniel Vetter 1080f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1081f51b7662SDaniel Vetter 1082f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1083f51b7662SDaniel Vetter 1084f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1085d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1086f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1087d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1088f51b7662SDaniel Vetter } else { 1089f51b7662SDaniel Vetter u64 l64; 1090f51b7662SDaniel Vetter 1091f51b7662SDaniel Vetter temp_lo &= ~0x1; 1092f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1093f51b7662SDaniel Vetter 1094f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1095f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1096f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1097f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1098f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1099f51b7662SDaniel Vetter if (ret) 1100f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1101f51b7662SDaniel Vetter } 1102f51b7662SDaniel Vetter } 1103f51b7662SDaniel Vetter 1104f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1105f51b7662SDaniel Vetter { 1106f51b7662SDaniel Vetter /* return if already configured */ 1107f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1108f51b7662SDaniel Vetter return; 1109f51b7662SDaniel Vetter 11101a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1111f51b7662SDaniel Vetter return; 1112f51b7662SDaniel Vetter 1113f51b7662SDaniel Vetter /* setup a resource for this object */ 1114f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1115f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1116f51b7662SDaniel Vetter 1117f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 11181a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1119f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1120f51b7662SDaniel Vetter } else { 1121f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1122f51b7662SDaniel Vetter } 1123f51b7662SDaniel Vetter 1124df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1125f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1126f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1127df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1128df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1129f51b7662SDaniel Vetter } 1130f51b7662SDaniel Vetter 1131ae83dd5cSDaniel Vetter static void i9xx_cleanup(void) 1132ae83dd5cSDaniel Vetter { 1133ae83dd5cSDaniel Vetter if (intel_private.i9xx_flush_page) 1134ae83dd5cSDaniel Vetter iounmap(intel_private.i9xx_flush_page); 1135ae83dd5cSDaniel Vetter if (intel_private.resource_valid) 1136ae83dd5cSDaniel Vetter release_resource(&intel_private.ifp_resource); 1137ae83dd5cSDaniel Vetter intel_private.ifp_resource.start = 0; 1138ae83dd5cSDaniel Vetter intel_private.resource_valid = 0; 1139ae83dd5cSDaniel Vetter } 1140ae83dd5cSDaniel Vetter 11411b263f24SDaniel Vetter static void i9xx_chipset_flush(void) 1142f51b7662SDaniel Vetter { 1143f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1144f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1145f51b7662SDaniel Vetter } 1146f51b7662SDaniel Vetter 114771f45660SChris Wilson static void i965_write_entry(dma_addr_t addr, 114871f45660SChris Wilson unsigned int entry, 1149a6963596SDaniel Vetter unsigned int flags) 1150a6963596SDaniel Vetter { 115171f45660SChris Wilson u32 pte_flags; 115271f45660SChris Wilson 115371f45660SChris Wilson pte_flags = I810_PTE_VALID; 115471f45660SChris Wilson if (flags == AGP_USER_CACHED_MEMORY) 115571f45660SChris Wilson pte_flags |= I830_PTE_SYSTEM_CACHED; 115671f45660SChris Wilson 1157a6963596SDaniel Vetter /* Shift high bits down */ 1158a6963596SDaniel Vetter addr |= (addr >> 28) & 0xf0; 115971f45660SChris Wilson writel(addr | pte_flags, intel_private.gtt + entry); 1160a6963596SDaniel Vetter } 1161a6963596SDaniel Vetter 116290cb149eSDaniel Vetter static bool gen6_check_flags(unsigned int flags) 116390cb149eSDaniel Vetter { 116490cb149eSDaniel Vetter return true; 116590cb149eSDaniel Vetter } 116690cb149eSDaniel Vetter 116797ef1bddSDaniel Vetter static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 116897ef1bddSDaniel Vetter unsigned int flags) 116997ef1bddSDaniel Vetter { 117097ef1bddSDaniel Vetter unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 117197ef1bddSDaniel Vetter unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 117297ef1bddSDaniel Vetter u32 pte_flags; 117397ef1bddSDaniel Vetter 1174897ef192SZhenyu Wang if (type_mask == AGP_USER_MEMORY) 117585ccc35bSChris Wilson pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; 117697ef1bddSDaniel Vetter else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1177d1108525SZhenyu Wang pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; 117897ef1bddSDaniel Vetter if (gfdt) 117997ef1bddSDaniel Vetter pte_flags |= GEN6_PTE_GFDT; 118097ef1bddSDaniel Vetter } else { /* set 'normal'/'cached' to LLC by default */ 1181d1108525SZhenyu Wang pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 118297ef1bddSDaniel Vetter if (gfdt) 118397ef1bddSDaniel Vetter pte_flags |= GEN6_PTE_GFDT; 118497ef1bddSDaniel Vetter } 118597ef1bddSDaniel Vetter 118697ef1bddSDaniel Vetter /* gen6 has bit11-4 for physical addr bit39-32 */ 118797ef1bddSDaniel Vetter addr |= (addr >> 28) & 0xff0; 118897ef1bddSDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 118997ef1bddSDaniel Vetter } 119097ef1bddSDaniel Vetter 1191ae83dd5cSDaniel Vetter static void gen6_cleanup(void) 1192ae83dd5cSDaniel Vetter { 1193ae83dd5cSDaniel Vetter } 1194ae83dd5cSDaniel Vetter 11952d2430cfSDaniel Vetter static int i9xx_setup(void) 11962d2430cfSDaniel Vetter { 11972d2430cfSDaniel Vetter u32 reg_addr; 11982d2430cfSDaniel Vetter 11992d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 12002d2430cfSDaniel Vetter 12012d2430cfSDaniel Vetter reg_addr &= 0xfff80000; 12022d2430cfSDaniel Vetter 12032d2430cfSDaniel Vetter intel_private.registers = ioremap(reg_addr, 128 * 4096); 12042d2430cfSDaniel Vetter if (!intel_private.registers) 12052d2430cfSDaniel Vetter return -ENOMEM; 12062d2430cfSDaniel Vetter 12072d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 3) { 12082d2430cfSDaniel Vetter u32 gtt_addr; 12093f08e4efSChris Wilson 12102d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, 12112d2430cfSDaniel Vetter I915_PTEADDR, >t_addr); 12122d2430cfSDaniel Vetter intel_private.gtt_bus_addr = gtt_addr; 12132d2430cfSDaniel Vetter } else { 12142d2430cfSDaniel Vetter u32 gtt_offset; 12152d2430cfSDaniel Vetter 12162d2430cfSDaniel Vetter switch (INTEL_GTT_GEN) { 12172d2430cfSDaniel Vetter case 5: 12182d2430cfSDaniel Vetter case 6: 12192d2430cfSDaniel Vetter gtt_offset = MB(2); 12202d2430cfSDaniel Vetter break; 12212d2430cfSDaniel Vetter case 4: 12222d2430cfSDaniel Vetter default: 12232d2430cfSDaniel Vetter gtt_offset = KB(512); 12242d2430cfSDaniel Vetter break; 12252d2430cfSDaniel Vetter } 12262d2430cfSDaniel Vetter intel_private.gtt_bus_addr = reg_addr + gtt_offset; 12272d2430cfSDaniel Vetter } 12282d2430cfSDaniel Vetter 12292d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 12302d2430cfSDaniel Vetter 12312d2430cfSDaniel Vetter return 0; 12322d2430cfSDaniel Vetter } 12332d2430cfSDaniel Vetter 1234e9b1cc81SDaniel Vetter static const struct agp_bridge_driver intel_fake_agp_driver = { 1235f51b7662SDaniel Vetter .owner = THIS_MODULE, 1236f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 12379e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 12389e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1239a6963596SDaniel Vetter .configure = intel_fake_agp_configure, 12403e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1241fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1242ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1243f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 12443b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1245ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1246450f2b3dSDaniel Vetter .insert_memory = intel_fake_agp_insert_entries, 1247450f2b3dSDaniel Vetter .remove_memory = intel_fake_agp_remove_entries, 1248ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1249f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1250f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1251f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1252f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1253f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1254f51b7662SDaniel Vetter }; 125502c026ceSDaniel Vetter 1256bdd30729SDaniel Vetter static const struct intel_gtt_driver i81x_gtt_driver = { 1257bdd30729SDaniel Vetter .gen = 1, 1258820647b9SDaniel Vetter .has_pgtbl_enable = 1, 125922533b49SDaniel Vetter .dma_mask_size = 32, 1260820647b9SDaniel Vetter .setup = i810_setup, 1261820647b9SDaniel Vetter .cleanup = i810_cleanup, 1262625dd9d3SDaniel Vetter .check_flags = i830_check_flags, 1263625dd9d3SDaniel Vetter .write_entry = i810_write_entry, 1264bdd30729SDaniel Vetter }; 12651a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 12661a997ff2SDaniel Vetter .gen = 2, 1267100519e2SChris Wilson .has_pgtbl_enable = 1, 126873800422SDaniel Vetter .setup = i830_setup, 1269ae83dd5cSDaniel Vetter .cleanup = i830_cleanup, 1270351bb278SDaniel Vetter .write_entry = i830_write_entry, 127122533b49SDaniel Vetter .dma_mask_size = 32, 12725cbecafcSDaniel Vetter .check_flags = i830_check_flags, 12731b263f24SDaniel Vetter .chipset_flush = i830_chipset_flush, 12741a997ff2SDaniel Vetter }; 12751a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 12761a997ff2SDaniel Vetter .gen = 3, 1277100519e2SChris Wilson .has_pgtbl_enable = 1, 12782d2430cfSDaniel Vetter .setup = i9xx_setup, 1279ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1280351bb278SDaniel Vetter /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1281351bb278SDaniel Vetter .write_entry = i830_write_entry, 128222533b49SDaniel Vetter .dma_mask_size = 32, 1283fefaa70fSDaniel Vetter .check_flags = i830_check_flags, 12841b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12851a997ff2SDaniel Vetter }; 12861a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 12871a997ff2SDaniel Vetter .gen = 3, 12881a997ff2SDaniel Vetter .is_g33 = 1, 12892d2430cfSDaniel Vetter .setup = i9xx_setup, 1290ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1291a6963596SDaniel Vetter .write_entry = i965_write_entry, 129222533b49SDaniel Vetter .dma_mask_size = 36, 1293450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12941b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12951a997ff2SDaniel Vetter }; 12961a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 12971a997ff2SDaniel Vetter .gen = 3, 12981a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 12992d2430cfSDaniel Vetter .setup = i9xx_setup, 1300ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1301a6963596SDaniel Vetter .write_entry = i965_write_entry, 130222533b49SDaniel Vetter .dma_mask_size = 36, 1303450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13041b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13051a997ff2SDaniel Vetter }; 13061a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 13071a997ff2SDaniel Vetter .gen = 4, 1308100519e2SChris Wilson .has_pgtbl_enable = 1, 13092d2430cfSDaniel Vetter .setup = i9xx_setup, 1310ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1311a6963596SDaniel Vetter .write_entry = i965_write_entry, 131222533b49SDaniel Vetter .dma_mask_size = 36, 1313450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13141b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13151a997ff2SDaniel Vetter }; 13161a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 13171a997ff2SDaniel Vetter .gen = 5, 13182d2430cfSDaniel Vetter .setup = i9xx_setup, 1319ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1320a6963596SDaniel Vetter .write_entry = i965_write_entry, 132122533b49SDaniel Vetter .dma_mask_size = 36, 1322450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13231b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13241a997ff2SDaniel Vetter }; 13251a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 13261a997ff2SDaniel Vetter .gen = 5, 13271a997ff2SDaniel Vetter .is_ironlake = 1, 13282d2430cfSDaniel Vetter .setup = i9xx_setup, 1329ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1330a6963596SDaniel Vetter .write_entry = i965_write_entry, 133122533b49SDaniel Vetter .dma_mask_size = 36, 1332450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13331b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13341a997ff2SDaniel Vetter }; 13351a997ff2SDaniel Vetter static const struct intel_gtt_driver sandybridge_gtt_driver = { 13361a997ff2SDaniel Vetter .gen = 6, 13372d2430cfSDaniel Vetter .setup = i9xx_setup, 1338ae83dd5cSDaniel Vetter .cleanup = gen6_cleanup, 133997ef1bddSDaniel Vetter .write_entry = gen6_write_entry, 134022533b49SDaniel Vetter .dma_mask_size = 40, 134190cb149eSDaniel Vetter .check_flags = gen6_check_flags, 13421b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13431a997ff2SDaniel Vetter }; 13441a997ff2SDaniel Vetter 134502c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 134602c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 134702c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 134802c026ceSDaniel Vetter */ 134902c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 135002c026ceSDaniel Vetter unsigned int gmch_chip_id; 135102c026ceSDaniel Vetter char *name; 13521a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 135302c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 1354ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1355bdd30729SDaniel Vetter &i81x_gtt_driver}, 1356ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1357bdd30729SDaniel Vetter &i81x_gtt_driver}, 1358ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1359bdd30729SDaniel Vetter &i81x_gtt_driver}, 1360ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1361bdd30729SDaniel Vetter &i81x_gtt_driver}, 13621a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1363ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13641a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 1365ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13661a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1367ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13681a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1369ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13701a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1371ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13721a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1373ff26860fSDaniel Vetter &i915_gtt_driver }, 13741a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1375ff26860fSDaniel Vetter &i915_gtt_driver }, 13761a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1377ff26860fSDaniel Vetter &i915_gtt_driver }, 13781a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1379ff26860fSDaniel Vetter &i915_gtt_driver }, 13801a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1381ff26860fSDaniel Vetter &i915_gtt_driver }, 13821a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1383ff26860fSDaniel Vetter &i915_gtt_driver }, 13841a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1385ff26860fSDaniel Vetter &i965_gtt_driver }, 13861a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1387ff26860fSDaniel Vetter &i965_gtt_driver }, 13881a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1389ff26860fSDaniel Vetter &i965_gtt_driver }, 13901a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1391ff26860fSDaniel Vetter &i965_gtt_driver }, 13921a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1393ff26860fSDaniel Vetter &i965_gtt_driver }, 13941a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1395ff26860fSDaniel Vetter &i965_gtt_driver }, 13961a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1397ff26860fSDaniel Vetter &g33_gtt_driver }, 13981a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1399ff26860fSDaniel Vetter &g33_gtt_driver }, 14001a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1401ff26860fSDaniel Vetter &g33_gtt_driver }, 14021a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1403ff26860fSDaniel Vetter &pineview_gtt_driver }, 14041a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1405ff26860fSDaniel Vetter &pineview_gtt_driver }, 14061a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1407ff26860fSDaniel Vetter &g4x_gtt_driver }, 14081a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1409ff26860fSDaniel Vetter &g4x_gtt_driver }, 14101a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1411ff26860fSDaniel Vetter &g4x_gtt_driver }, 14121a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1413ff26860fSDaniel Vetter &g4x_gtt_driver }, 14141a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1415ff26860fSDaniel Vetter &g4x_gtt_driver }, 1416e9e5f8e8SChris Wilson { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1417ff26860fSDaniel Vetter &g4x_gtt_driver }, 14181a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1419ff26860fSDaniel Vetter &g4x_gtt_driver }, 142002c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1421ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 142202c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1423ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 142402c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 1425ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 142602c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 1427ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 142802c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 1429ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 143002c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 1431ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 143202c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 1433ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 143402c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 1435ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 143602c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 1437ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 143802c026ceSDaniel Vetter { 0, NULL, NULL } 143902c026ceSDaniel Vetter }; 144002c026ceSDaniel Vetter 144102c026ceSDaniel Vetter static int find_gmch(u16 device) 144202c026ceSDaniel Vetter { 144302c026ceSDaniel Vetter struct pci_dev *gmch_device; 144402c026ceSDaniel Vetter 144502c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 144602c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 144702c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 144802c026ceSDaniel Vetter device, gmch_device); 144902c026ceSDaniel Vetter } 145002c026ceSDaniel Vetter 145102c026ceSDaniel Vetter if (!gmch_device) 145202c026ceSDaniel Vetter return 0; 145302c026ceSDaniel Vetter 145402c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 145502c026ceSDaniel Vetter return 1; 145602c026ceSDaniel Vetter } 145702c026ceSDaniel Vetter 1458e2404e7cSDaniel Vetter int intel_gmch_probe(struct pci_dev *pdev, 145902c026ceSDaniel Vetter struct agp_bridge_data *bridge) 146002c026ceSDaniel Vetter { 146102c026ceSDaniel Vetter int i, mask; 1462ff26860fSDaniel Vetter intel_private.driver = NULL; 146302c026ceSDaniel Vetter 146402c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 146502c026ceSDaniel Vetter if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 14661a997ff2SDaniel Vetter intel_private.driver = 14671a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 146802c026ceSDaniel Vetter break; 146902c026ceSDaniel Vetter } 147002c026ceSDaniel Vetter } 147102c026ceSDaniel Vetter 1472ff26860fSDaniel Vetter if (!intel_private.driver) 147302c026ceSDaniel Vetter return 0; 147402c026ceSDaniel Vetter 1475ff26860fSDaniel Vetter bridge->driver = &intel_fake_agp_driver; 147602c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 147702c026ceSDaniel Vetter bridge->dev = pdev; 147802c026ceSDaniel Vetter 1479d7cca2f7SDaniel Vetter intel_private.bridge_dev = pci_dev_get(pdev); 1480d7cca2f7SDaniel Vetter 148102c026ceSDaniel Vetter dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 148202c026ceSDaniel Vetter 148322533b49SDaniel Vetter mask = intel_private.driver->dma_mask_size; 148402c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 148502c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 148602c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 148702c026ceSDaniel Vetter else 148802c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 148902c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 149002c026ceSDaniel Vetter 1491820647b9SDaniel Vetter /*if (bridge->driver == &intel_810_driver) 1492820647b9SDaniel Vetter return 1;*/ 14931784a5fbSDaniel Vetter 14943b15a9d7SDaniel Vetter if (intel_gtt_init() != 0) 14953b15a9d7SDaniel Vetter return 0; 14961784a5fbSDaniel Vetter 149702c026ceSDaniel Vetter return 1; 149802c026ceSDaniel Vetter } 1499e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 150002c026ceSDaniel Vetter 1501c64f7ba5SChris Wilson const struct intel_gtt *intel_gtt_get(void) 150219966754SDaniel Vetter { 150319966754SDaniel Vetter return &intel_private.base; 150419966754SDaniel Vetter } 150519966754SDaniel Vetter EXPORT_SYMBOL(intel_gtt_get); 150619966754SDaniel Vetter 150740ce6575SDaniel Vetter void intel_gtt_chipset_flush(void) 150840ce6575SDaniel Vetter { 150940ce6575SDaniel Vetter if (intel_private.driver->chipset_flush) 151040ce6575SDaniel Vetter intel_private.driver->chipset_flush(); 151140ce6575SDaniel Vetter } 151240ce6575SDaniel Vetter EXPORT_SYMBOL(intel_gtt_chipset_flush); 151340ce6575SDaniel Vetter 1514e2404e7cSDaniel Vetter void intel_gmch_remove(struct pci_dev *pdev) 151502c026ceSDaniel Vetter { 151602c026ceSDaniel Vetter if (intel_private.pcidev) 151702c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1518d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1519d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 152002c026ceSDaniel Vetter } 1521e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1522e2404e7cSDaniel Vetter 1523e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1524e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1525