1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24e2404e7cSDaniel Vetter #include <asm/smp.h> 25e2404e7cSDaniel Vetter #include "agp.h" 26e2404e7cSDaniel Vetter #include "intel-agp.h" 27e2404e7cSDaniel Vetter #include <linux/intel-gtt.h> 280ade6386SDaniel Vetter #include <drm/intel-gtt.h> 29e2404e7cSDaniel Vetter 30f51b7662SDaniel Vetter /* 31f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 32f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 34f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 35f51b7662SDaniel Vetter */ 36f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 37f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 38f51b7662SDaniel Vetter #endif 39f51b7662SDaniel Vetter 40d1d6ca73SJesse Barnes /* Max amount of stolen space, anything above will be returned to Linux */ 41d1d6ca73SJesse Barnes int intel_max_stolen = 32 * 1024 * 1024; 42d1d6ca73SJesse Barnes EXPORT_SYMBOL(intel_max_stolen); 43d1d6ca73SJesse Barnes 44f51b7662SDaniel Vetter static const struct aper_size_info_fixed intel_i810_sizes[] = 45f51b7662SDaniel Vetter { 46f51b7662SDaniel Vetter {64, 16384, 4}, 47f51b7662SDaniel Vetter /* The 32M mode still requires a 64k gatt */ 48f51b7662SDaniel Vetter {32, 8192, 4} 49f51b7662SDaniel Vetter }; 50f51b7662SDaniel Vetter 51f51b7662SDaniel Vetter #define AGP_DCACHE_MEMORY 1 52f51b7662SDaniel Vetter #define AGP_PHYS_MEMORY 2 53f51b7662SDaniel Vetter #define INTEL_AGP_CACHED_MEMORY 3 54f51b7662SDaniel Vetter 55f51b7662SDaniel Vetter static struct gatt_mask intel_i810_masks[] = 56f51b7662SDaniel Vetter { 57f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 58f51b7662SDaniel Vetter {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 59f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 60f51b7662SDaniel Vetter {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 61f51b7662SDaniel Vetter .type = INTEL_AGP_CACHED_MEMORY} 62f51b7662SDaniel Vetter }; 63f51b7662SDaniel Vetter 64f8f235e5SZhenyu Wang #define INTEL_AGP_UNCACHED_MEMORY 0 65f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC 1 66f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 67f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 68f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 69f8f235e5SZhenyu Wang 70f8f235e5SZhenyu Wang static struct gatt_mask intel_gen6_masks[] = 71f8f235e5SZhenyu Wang { 72f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED, 73f8f235e5SZhenyu Wang .type = INTEL_AGP_UNCACHED_MEMORY }, 74f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC, 75f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC }, 76f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT, 77f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT }, 78f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC, 79f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC }, 80f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT, 81f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, 82f8f235e5SZhenyu Wang }; 83f8f235e5SZhenyu Wang 841a997ff2SDaniel Vetter struct intel_gtt_driver { 851a997ff2SDaniel Vetter unsigned int gen : 8; 861a997ff2SDaniel Vetter unsigned int is_g33 : 1; 871a997ff2SDaniel Vetter unsigned int is_pineview : 1; 881a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 8973800422SDaniel Vetter /* Chipset specific GTT setup */ 9073800422SDaniel Vetter int (*setup)(void); 911a997ff2SDaniel Vetter }; 921a997ff2SDaniel Vetter 93f51b7662SDaniel Vetter static struct _intel_private { 940ade6386SDaniel Vetter struct intel_gtt base; 951a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 96f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 97d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 98f51b7662SDaniel Vetter u8 __iomem *registers; 99f67eab66SDaniel Vetter phys_addr_t gtt_bus_addr; 10073800422SDaniel Vetter phys_addr_t gma_bus_addr; 101f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 102f51b7662SDaniel Vetter int num_dcache_entries; 103f51b7662SDaniel Vetter union { 104f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 105f51b7662SDaniel Vetter void *i8xx_flush_page; 106f51b7662SDaniel Vetter }; 107f51b7662SDaniel Vetter struct page *i8xx_page; 108f51b7662SDaniel Vetter struct resource ifp_resource; 109f51b7662SDaniel Vetter int resource_valid; 110f51b7662SDaniel Vetter } intel_private; 111f51b7662SDaniel Vetter 1121a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 1131a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 1141a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 1151a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 1161a997ff2SDaniel Vetter 117f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 118f51b7662SDaniel Vetter static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 119f51b7662SDaniel Vetter { 120f51b7662SDaniel Vetter *ret = pci_map_page(intel_private.pcidev, page, 0, 121f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 122f51b7662SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 123f51b7662SDaniel Vetter return -EINVAL; 124f51b7662SDaniel Vetter return 0; 125f51b7662SDaniel Vetter } 126f51b7662SDaniel Vetter 127f51b7662SDaniel Vetter static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 128f51b7662SDaniel Vetter { 129f51b7662SDaniel Vetter pci_unmap_page(intel_private.pcidev, dma, 130f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 131f51b7662SDaniel Vetter } 132f51b7662SDaniel Vetter 133f51b7662SDaniel Vetter static void intel_agp_free_sglist(struct agp_memory *mem) 134f51b7662SDaniel Vetter { 135f51b7662SDaniel Vetter struct sg_table st; 136f51b7662SDaniel Vetter 137f51b7662SDaniel Vetter st.sgl = mem->sg_list; 138f51b7662SDaniel Vetter st.orig_nents = st.nents = mem->page_count; 139f51b7662SDaniel Vetter 140f51b7662SDaniel Vetter sg_free_table(&st); 141f51b7662SDaniel Vetter 142f51b7662SDaniel Vetter mem->sg_list = NULL; 143f51b7662SDaniel Vetter mem->num_sg = 0; 144f51b7662SDaniel Vetter } 145f51b7662SDaniel Vetter 146f51b7662SDaniel Vetter static int intel_agp_map_memory(struct agp_memory *mem) 147f51b7662SDaniel Vetter { 148f51b7662SDaniel Vetter struct sg_table st; 149f51b7662SDaniel Vetter struct scatterlist *sg; 150f51b7662SDaniel Vetter int i; 151f51b7662SDaniel Vetter 152f51b7662SDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 153f51b7662SDaniel Vetter 154f51b7662SDaniel Vetter if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 155831cd445SChris Wilson goto err; 156f51b7662SDaniel Vetter 157f51b7662SDaniel Vetter mem->sg_list = sg = st.sgl; 158f51b7662SDaniel Vetter 159f51b7662SDaniel Vetter for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 160f51b7662SDaniel Vetter sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 161f51b7662SDaniel Vetter 162f51b7662SDaniel Vetter mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 163f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 164831cd445SChris Wilson if (unlikely(!mem->num_sg)) 165831cd445SChris Wilson goto err; 166831cd445SChris Wilson 167f51b7662SDaniel Vetter return 0; 168831cd445SChris Wilson 169831cd445SChris Wilson err: 170831cd445SChris Wilson sg_free_table(&st); 171831cd445SChris Wilson return -ENOMEM; 172f51b7662SDaniel Vetter } 173f51b7662SDaniel Vetter 174f51b7662SDaniel Vetter static void intel_agp_unmap_memory(struct agp_memory *mem) 175f51b7662SDaniel Vetter { 176f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 177f51b7662SDaniel Vetter 178f51b7662SDaniel Vetter pci_unmap_sg(intel_private.pcidev, mem->sg_list, 179f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 180f51b7662SDaniel Vetter intel_agp_free_sglist(mem); 181f51b7662SDaniel Vetter } 182f51b7662SDaniel Vetter 183f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 184f51b7662SDaniel Vetter off_t pg_start, int mask_type) 185f51b7662SDaniel Vetter { 186f51b7662SDaniel Vetter struct scatterlist *sg; 187f51b7662SDaniel Vetter int i, j; 188f51b7662SDaniel Vetter 189f51b7662SDaniel Vetter j = pg_start; 190f51b7662SDaniel Vetter 191f51b7662SDaniel Vetter WARN_ON(!mem->num_sg); 192f51b7662SDaniel Vetter 193f51b7662SDaniel Vetter if (mem->num_sg == mem->page_count) { 194f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->page_count, i) { 195f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 196f51b7662SDaniel Vetter sg_dma_address(sg), mask_type), 197f51b7662SDaniel Vetter intel_private.gtt+j); 198f51b7662SDaniel Vetter j++; 199f51b7662SDaniel Vetter } 200f51b7662SDaniel Vetter } else { 201f51b7662SDaniel Vetter /* sg may merge pages, but we have to separate 202f51b7662SDaniel Vetter * per-page addr for GTT */ 203f51b7662SDaniel Vetter unsigned int len, m; 204f51b7662SDaniel Vetter 205f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 206f51b7662SDaniel Vetter len = sg_dma_len(sg) / PAGE_SIZE; 207f51b7662SDaniel Vetter for (m = 0; m < len; m++) { 208f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 209f51b7662SDaniel Vetter sg_dma_address(sg) + m * PAGE_SIZE, 210f51b7662SDaniel Vetter mask_type), 211f51b7662SDaniel Vetter intel_private.gtt+j); 212f51b7662SDaniel Vetter j++; 213f51b7662SDaniel Vetter } 214f51b7662SDaniel Vetter } 215f51b7662SDaniel Vetter } 216f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 217f51b7662SDaniel Vetter } 218f51b7662SDaniel Vetter 219f51b7662SDaniel Vetter #else 220f51b7662SDaniel Vetter 221f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 222f51b7662SDaniel Vetter off_t pg_start, int mask_type) 223f51b7662SDaniel Vetter { 224f51b7662SDaniel Vetter int i, j; 225f51b7662SDaniel Vetter 226f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 227f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 228f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 229f51b7662SDaniel Vetter intel_private.gtt+j); 230f51b7662SDaniel Vetter } 231f51b7662SDaniel Vetter 232f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 233f51b7662SDaniel Vetter } 234f51b7662SDaniel Vetter 235f51b7662SDaniel Vetter #endif 236f51b7662SDaniel Vetter 237f51b7662SDaniel Vetter static int intel_i810_fetch_size(void) 238f51b7662SDaniel Vetter { 239f51b7662SDaniel Vetter u32 smram_miscc; 240f51b7662SDaniel Vetter struct aper_size_info_fixed *values; 241f51b7662SDaniel Vetter 242d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 243d7cca2f7SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 244f51b7662SDaniel Vetter values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 245f51b7662SDaniel Vetter 246f51b7662SDaniel Vetter if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 247d7cca2f7SDaniel Vetter dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); 248f51b7662SDaniel Vetter return 0; 249f51b7662SDaniel Vetter } 250f51b7662SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 251f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values + 1); 252f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 1; 253f51b7662SDaniel Vetter return values[1].size; 254f51b7662SDaniel Vetter } else { 255f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values); 256f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 257f51b7662SDaniel Vetter return values[0].size; 258f51b7662SDaniel Vetter } 259f51b7662SDaniel Vetter 260f51b7662SDaniel Vetter return 0; 261f51b7662SDaniel Vetter } 262f51b7662SDaniel Vetter 263f51b7662SDaniel Vetter static int intel_i810_configure(void) 264f51b7662SDaniel Vetter { 265f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 266f51b7662SDaniel Vetter u32 temp; 267f51b7662SDaniel Vetter int i; 268f51b7662SDaniel Vetter 269f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 270f51b7662SDaniel Vetter 271f51b7662SDaniel Vetter if (!intel_private.registers) { 272f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 273f51b7662SDaniel Vetter temp &= 0xfff80000; 274f51b7662SDaniel Vetter 275f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 276f51b7662SDaniel Vetter if (!intel_private.registers) { 277f51b7662SDaniel Vetter dev_err(&intel_private.pcidev->dev, 278f51b7662SDaniel Vetter "can't remap memory\n"); 279f51b7662SDaniel Vetter return -ENOMEM; 280f51b7662SDaniel Vetter } 281f51b7662SDaniel Vetter } 282f51b7662SDaniel Vetter 283f51b7662SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 284f51b7662SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 285f51b7662SDaniel Vetter /* This will need to be dynamically assigned */ 286f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 287f51b7662SDaniel Vetter "detected 4MB dedicated video ram\n"); 288f51b7662SDaniel Vetter intel_private.num_dcache_entries = 1024; 289f51b7662SDaniel Vetter } 290f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 291f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 292f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 293f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 294f51b7662SDaniel Vetter 295f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 296f51b7662SDaniel Vetter for (i = 0; i < current_size->num_entries; i++) { 297f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 298f51b7662SDaniel Vetter } 299f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 300f51b7662SDaniel Vetter } 301f51b7662SDaniel Vetter global_cache_flush(); 302f51b7662SDaniel Vetter return 0; 303f51b7662SDaniel Vetter } 304f51b7662SDaniel Vetter 305f51b7662SDaniel Vetter static void intel_i810_cleanup(void) 306f51b7662SDaniel Vetter { 307f51b7662SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 308f51b7662SDaniel Vetter readl(intel_private.registers); /* PCI Posting. */ 309f51b7662SDaniel Vetter iounmap(intel_private.registers); 310f51b7662SDaniel Vetter } 311f51b7662SDaniel Vetter 312ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 313f51b7662SDaniel Vetter { 314f51b7662SDaniel Vetter return; 315f51b7662SDaniel Vetter } 316f51b7662SDaniel Vetter 317f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 318f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 319f51b7662SDaniel Vetter { 320f51b7662SDaniel Vetter struct page *page; 321f51b7662SDaniel Vetter 322f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 323f51b7662SDaniel Vetter if (page == NULL) 324f51b7662SDaniel Vetter return NULL; 325f51b7662SDaniel Vetter 326f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 327f51b7662SDaniel Vetter set_pages_wb(page, 4); 328f51b7662SDaniel Vetter __free_pages(page, 2); 329f51b7662SDaniel Vetter return NULL; 330f51b7662SDaniel Vetter } 331f51b7662SDaniel Vetter get_page(page); 332f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 333f51b7662SDaniel Vetter return page; 334f51b7662SDaniel Vetter } 335f51b7662SDaniel Vetter 336f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 337f51b7662SDaniel Vetter { 338f51b7662SDaniel Vetter if (page == NULL) 339f51b7662SDaniel Vetter return; 340f51b7662SDaniel Vetter 341f51b7662SDaniel Vetter set_pages_wb(page, 4); 342f51b7662SDaniel Vetter put_page(page); 343f51b7662SDaniel Vetter __free_pages(page, 2); 344f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 345f51b7662SDaniel Vetter } 346f51b7662SDaniel Vetter 347f51b7662SDaniel Vetter static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 348f51b7662SDaniel Vetter int type) 349f51b7662SDaniel Vetter { 350f51b7662SDaniel Vetter if (type < AGP_USER_TYPES) 351f51b7662SDaniel Vetter return type; 352f51b7662SDaniel Vetter else if (type == AGP_USER_CACHED_MEMORY) 353f51b7662SDaniel Vetter return INTEL_AGP_CACHED_MEMORY; 354f51b7662SDaniel Vetter else 355f51b7662SDaniel Vetter return 0; 356f51b7662SDaniel Vetter } 357f51b7662SDaniel Vetter 358f8f235e5SZhenyu Wang static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge, 359f8f235e5SZhenyu Wang int type) 360f8f235e5SZhenyu Wang { 361f8f235e5SZhenyu Wang unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; 362f8f235e5SZhenyu Wang unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; 363f8f235e5SZhenyu Wang 364f8f235e5SZhenyu Wang if (type_mask == AGP_USER_UNCACHED_MEMORY) 365f8f235e5SZhenyu Wang return INTEL_AGP_UNCACHED_MEMORY; 366f8f235e5SZhenyu Wang else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) 367f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT : 368f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC_MLC; 369f8f235e5SZhenyu Wang else /* set 'normal'/'cached' to LLC by default */ 370f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT : 371f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC; 372f8f235e5SZhenyu Wang } 373f8f235e5SZhenyu Wang 374f8f235e5SZhenyu Wang 375f51b7662SDaniel Vetter static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 376f51b7662SDaniel Vetter int type) 377f51b7662SDaniel Vetter { 378f51b7662SDaniel Vetter int i, j, num_entries; 379f51b7662SDaniel Vetter void *temp; 380f51b7662SDaniel Vetter int ret = -EINVAL; 381f51b7662SDaniel Vetter int mask_type; 382f51b7662SDaniel Vetter 383f51b7662SDaniel Vetter if (mem->page_count == 0) 384f51b7662SDaniel Vetter goto out; 385f51b7662SDaniel Vetter 386f51b7662SDaniel Vetter temp = agp_bridge->current_size; 387f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 388f51b7662SDaniel Vetter 389f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 390f51b7662SDaniel Vetter goto out_err; 391f51b7662SDaniel Vetter 392f51b7662SDaniel Vetter 393f51b7662SDaniel Vetter for (j = pg_start; j < (pg_start + mem->page_count); j++) { 394f51b7662SDaniel Vetter if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 395f51b7662SDaniel Vetter ret = -EBUSY; 396f51b7662SDaniel Vetter goto out_err; 397f51b7662SDaniel Vetter } 398f51b7662SDaniel Vetter } 399f51b7662SDaniel Vetter 400f51b7662SDaniel Vetter if (type != mem->type) 401f51b7662SDaniel Vetter goto out_err; 402f51b7662SDaniel Vetter 403f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 404f51b7662SDaniel Vetter 405f51b7662SDaniel Vetter switch (mask_type) { 406f51b7662SDaniel Vetter case AGP_DCACHE_MEMORY: 407f51b7662SDaniel Vetter if (!mem->is_flushed) 408f51b7662SDaniel Vetter global_cache_flush(); 409f51b7662SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 410f51b7662SDaniel Vetter writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 411f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(i*4)); 412f51b7662SDaniel Vetter } 413f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 414f51b7662SDaniel Vetter break; 415f51b7662SDaniel Vetter case AGP_PHYS_MEMORY: 416f51b7662SDaniel Vetter case AGP_NORMAL_MEMORY: 417f51b7662SDaniel Vetter if (!mem->is_flushed) 418f51b7662SDaniel Vetter global_cache_flush(); 419f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 420f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 421f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 422f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(j*4)); 423f51b7662SDaniel Vetter } 424f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 425f51b7662SDaniel Vetter break; 426f51b7662SDaniel Vetter default: 427f51b7662SDaniel Vetter goto out_err; 428f51b7662SDaniel Vetter } 429f51b7662SDaniel Vetter 430f51b7662SDaniel Vetter out: 431f51b7662SDaniel Vetter ret = 0; 432f51b7662SDaniel Vetter out_err: 433f51b7662SDaniel Vetter mem->is_flushed = true; 434f51b7662SDaniel Vetter return ret; 435f51b7662SDaniel Vetter } 436f51b7662SDaniel Vetter 437f51b7662SDaniel Vetter static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 438f51b7662SDaniel Vetter int type) 439f51b7662SDaniel Vetter { 440f51b7662SDaniel Vetter int i; 441f51b7662SDaniel Vetter 442f51b7662SDaniel Vetter if (mem->page_count == 0) 443f51b7662SDaniel Vetter return 0; 444f51b7662SDaniel Vetter 445f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 446f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 447f51b7662SDaniel Vetter } 448f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 449f51b7662SDaniel Vetter 450f51b7662SDaniel Vetter return 0; 451f51b7662SDaniel Vetter } 452f51b7662SDaniel Vetter 453f51b7662SDaniel Vetter /* 454f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 455f51b7662SDaniel Vetter * pointer into hardware. 456f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 457f51b7662SDaniel Vetter */ 458f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 459f51b7662SDaniel Vetter { 460f51b7662SDaniel Vetter struct agp_memory *new; 461f51b7662SDaniel Vetter struct page *page; 462f51b7662SDaniel Vetter 463f51b7662SDaniel Vetter switch (pg_count) { 464f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 465f51b7662SDaniel Vetter break; 466f51b7662SDaniel Vetter case 4: 467f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 468f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 469f51b7662SDaniel Vetter break; 470f51b7662SDaniel Vetter default: 471f51b7662SDaniel Vetter return NULL; 472f51b7662SDaniel Vetter } 473f51b7662SDaniel Vetter 474f51b7662SDaniel Vetter if (page == NULL) 475f51b7662SDaniel Vetter return NULL; 476f51b7662SDaniel Vetter 477f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 478f51b7662SDaniel Vetter if (new == NULL) 479f51b7662SDaniel Vetter return NULL; 480f51b7662SDaniel Vetter 481f51b7662SDaniel Vetter new->pages[0] = page; 482f51b7662SDaniel Vetter if (pg_count == 4) { 483f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 484f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 485f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 486f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 487f51b7662SDaniel Vetter } 488f51b7662SDaniel Vetter new->page_count = pg_count; 489f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 490f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 491f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 492f51b7662SDaniel Vetter return new; 493f51b7662SDaniel Vetter } 494f51b7662SDaniel Vetter 495f51b7662SDaniel Vetter static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 496f51b7662SDaniel Vetter { 497f51b7662SDaniel Vetter struct agp_memory *new; 498f51b7662SDaniel Vetter 499f51b7662SDaniel Vetter if (type == AGP_DCACHE_MEMORY) { 500f51b7662SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 501f51b7662SDaniel Vetter return NULL; 502f51b7662SDaniel Vetter 503f51b7662SDaniel Vetter new = agp_create_memory(1); 504f51b7662SDaniel Vetter if (new == NULL) 505f51b7662SDaniel Vetter return NULL; 506f51b7662SDaniel Vetter 507f51b7662SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 508f51b7662SDaniel Vetter new->page_count = pg_count; 509f51b7662SDaniel Vetter new->num_scratch_pages = 0; 510f51b7662SDaniel Vetter agp_free_page_array(new); 511f51b7662SDaniel Vetter return new; 512f51b7662SDaniel Vetter } 513f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 514f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 515f51b7662SDaniel Vetter return NULL; 516f51b7662SDaniel Vetter } 517f51b7662SDaniel Vetter 518f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 519f51b7662SDaniel Vetter { 520f51b7662SDaniel Vetter agp_free_key(curr->key); 521f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 522f51b7662SDaniel Vetter if (curr->page_count == 4) 523f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 524f51b7662SDaniel Vetter else { 525f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 526f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 527f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 528f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 529f51b7662SDaniel Vetter } 530f51b7662SDaniel Vetter agp_free_page_array(curr); 531f51b7662SDaniel Vetter } 532f51b7662SDaniel Vetter kfree(curr); 533f51b7662SDaniel Vetter } 534f51b7662SDaniel Vetter 535f51b7662SDaniel Vetter static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 536f51b7662SDaniel Vetter dma_addr_t addr, int type) 537f51b7662SDaniel Vetter { 538f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 539f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 540f51b7662SDaniel Vetter } 541f51b7662SDaniel Vetter 542ffdd7510SDaniel Vetter static struct aper_size_info_fixed intel_fake_agp_sizes[] = 543f51b7662SDaniel Vetter { 544f51b7662SDaniel Vetter {128, 32768, 5}, 545f51b7662SDaniel Vetter /* The 64M mode still requires a 128k gatt */ 546f51b7662SDaniel Vetter {64, 16384, 5}, 547f51b7662SDaniel Vetter {256, 65536, 6}, 548f51b7662SDaniel Vetter {512, 131072, 7}, 549f51b7662SDaniel Vetter }; 550f51b7662SDaniel Vetter 551bfde067bSDaniel Vetter static unsigned int intel_gtt_stolen_entries(void) 552f51b7662SDaniel Vetter { 553f51b7662SDaniel Vetter u16 gmch_ctrl; 554f51b7662SDaniel Vetter u8 rdct; 555f51b7662SDaniel Vetter int local = 0; 556f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 557d8d9abcdSDaniel Vetter unsigned int overhead_entries, stolen_entries; 558d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 559f51b7662SDaniel Vetter 560d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 561d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 562f51b7662SDaniel Vetter 5631a997ff2SDaniel Vetter if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) 564fbe40783SDaniel Vetter overhead_entries = 0; 565fbe40783SDaniel Vetter else 566fbe40783SDaniel Vetter overhead_entries = intel_private.base.gtt_mappable_entries 567fbe40783SDaniel Vetter / 1024; 568f51b7662SDaniel Vetter 569fbe40783SDaniel Vetter overhead_entries += 1; /* BIOS popup */ 570d8d9abcdSDaniel Vetter 571d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 572d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 573f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 574f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 575d8d9abcdSDaniel Vetter stolen_size = KB(512); 576f51b7662SDaniel Vetter break; 577f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 578d8d9abcdSDaniel Vetter stolen_size = MB(1); 579f51b7662SDaniel Vetter break; 580f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 581d8d9abcdSDaniel Vetter stolen_size = MB(8); 582f51b7662SDaniel Vetter break; 583f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 584f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 585d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 586f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 587f51b7662SDaniel Vetter local = 1; 588f51b7662SDaniel Vetter break; 589f51b7662SDaniel Vetter default: 590d8d9abcdSDaniel Vetter stolen_size = 0; 591f51b7662SDaniel Vetter break; 592f51b7662SDaniel Vetter } 5931a997ff2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 594f51b7662SDaniel Vetter /* 595f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 596f51b7662SDaniel Vetter */ 597f51b7662SDaniel Vetter u16 snb_gmch_ctl; 598f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 599f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 600f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 601d8d9abcdSDaniel Vetter stolen_size = MB(32); 602f51b7662SDaniel Vetter break; 603f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 604d8d9abcdSDaniel Vetter stolen_size = MB(64); 605f51b7662SDaniel Vetter break; 606f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 607d8d9abcdSDaniel Vetter stolen_size = MB(96); 608f51b7662SDaniel Vetter break; 609f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 610d8d9abcdSDaniel Vetter stolen_size = MB(128); 611f51b7662SDaniel Vetter break; 612f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 613d8d9abcdSDaniel Vetter stolen_size = MB(160); 614f51b7662SDaniel Vetter break; 615f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 616d8d9abcdSDaniel Vetter stolen_size = MB(192); 617f51b7662SDaniel Vetter break; 618f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 619d8d9abcdSDaniel Vetter stolen_size = MB(224); 620f51b7662SDaniel Vetter break; 621f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 622d8d9abcdSDaniel Vetter stolen_size = MB(256); 623f51b7662SDaniel Vetter break; 624f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 625d8d9abcdSDaniel Vetter stolen_size = MB(288); 626f51b7662SDaniel Vetter break; 627f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 628d8d9abcdSDaniel Vetter stolen_size = MB(320); 629f51b7662SDaniel Vetter break; 630f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 631d8d9abcdSDaniel Vetter stolen_size = MB(352); 632f51b7662SDaniel Vetter break; 633f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 634d8d9abcdSDaniel Vetter stolen_size = MB(384); 635f51b7662SDaniel Vetter break; 636f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 637d8d9abcdSDaniel Vetter stolen_size = MB(416); 638f51b7662SDaniel Vetter break; 639f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 640d8d9abcdSDaniel Vetter stolen_size = MB(448); 641f51b7662SDaniel Vetter break; 642f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 643d8d9abcdSDaniel Vetter stolen_size = MB(480); 644f51b7662SDaniel Vetter break; 645f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 646d8d9abcdSDaniel Vetter stolen_size = MB(512); 647f51b7662SDaniel Vetter break; 648f51b7662SDaniel Vetter } 649f51b7662SDaniel Vetter } else { 650f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 651f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 652d8d9abcdSDaniel Vetter stolen_size = MB(1); 653f51b7662SDaniel Vetter break; 654f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 655d8d9abcdSDaniel Vetter stolen_size = MB(4); 656f51b7662SDaniel Vetter break; 657f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 658d8d9abcdSDaniel Vetter stolen_size = MB(8); 659f51b7662SDaniel Vetter break; 660f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 661d8d9abcdSDaniel Vetter stolen_size = MB(16); 662f51b7662SDaniel Vetter break; 663f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 664d8d9abcdSDaniel Vetter stolen_size = MB(32); 665f51b7662SDaniel Vetter break; 666f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 667d8d9abcdSDaniel Vetter stolen_size = MB(48); 668f51b7662SDaniel Vetter break; 669f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 670d8d9abcdSDaniel Vetter stolen_size = MB(64); 671f51b7662SDaniel Vetter break; 672f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 673d8d9abcdSDaniel Vetter stolen_size = MB(128); 674f51b7662SDaniel Vetter break; 675f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 676d8d9abcdSDaniel Vetter stolen_size = MB(256); 677f51b7662SDaniel Vetter break; 678f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 679d8d9abcdSDaniel Vetter stolen_size = MB(96); 680f51b7662SDaniel Vetter break; 681f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 682d8d9abcdSDaniel Vetter stolen_size = MB(160); 683f51b7662SDaniel Vetter break; 684f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 685d8d9abcdSDaniel Vetter stolen_size = MB(224); 686f51b7662SDaniel Vetter break; 687f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 688d8d9abcdSDaniel Vetter stolen_size = MB(352); 689f51b7662SDaniel Vetter break; 690f51b7662SDaniel Vetter default: 691d8d9abcdSDaniel Vetter stolen_size = 0; 692f51b7662SDaniel Vetter break; 693f51b7662SDaniel Vetter } 694f51b7662SDaniel Vetter } 6951784a5fbSDaniel Vetter 696d8d9abcdSDaniel Vetter if (!local && stolen_size > intel_max_stolen) { 697d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 698d1d6ca73SJesse Barnes "detected %dK stolen memory, trimming to %dK\n", 699d8d9abcdSDaniel Vetter stolen_size / KB(1), intel_max_stolen / KB(1)); 700d8d9abcdSDaniel Vetter stolen_size = intel_max_stolen; 701d8d9abcdSDaniel Vetter } else if (stolen_size > 0) { 702d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 703d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 704f51b7662SDaniel Vetter } else { 705d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 706f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 707d8d9abcdSDaniel Vetter stolen_size = 0; 708f51b7662SDaniel Vetter } 709f51b7662SDaniel Vetter 710d8d9abcdSDaniel Vetter stolen_entries = stolen_size/KB(4) - overhead_entries; 711d8d9abcdSDaniel Vetter 712d8d9abcdSDaniel Vetter return stolen_entries; 713f51b7662SDaniel Vetter } 714f51b7662SDaniel Vetter 715fbe40783SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 716fbe40783SDaniel Vetter { 717fbe40783SDaniel Vetter int size; 718fbe40783SDaniel Vetter 719210b23c2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { 720fbe40783SDaniel Vetter u32 pgetbl_ctl; 721fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 722fbe40783SDaniel Vetter 723fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 724fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 725e5e408fcSDaniel Vetter size = KB(128); 726fbe40783SDaniel Vetter break; 727fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 728e5e408fcSDaniel Vetter size = KB(256); 729fbe40783SDaniel Vetter break; 730fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 731e5e408fcSDaniel Vetter size = KB(512); 732fbe40783SDaniel Vetter break; 733fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 734e5e408fcSDaniel Vetter size = KB(1024); 735fbe40783SDaniel Vetter break; 736fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 737e5e408fcSDaniel Vetter size = KB(2048); 738fbe40783SDaniel Vetter break; 739fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 740e5e408fcSDaniel Vetter size = KB(1024 + 512); 741fbe40783SDaniel Vetter break; 742fbe40783SDaniel Vetter default: 743fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 744fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 745e5e408fcSDaniel Vetter size = KB(512); 746fbe40783SDaniel Vetter } 747e5e408fcSDaniel Vetter 748e5e408fcSDaniel Vetter return size/4; 749210b23c2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 750210b23c2SDaniel Vetter u16 snb_gmch_ctl; 751210b23c2SDaniel Vetter 752210b23c2SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 753210b23c2SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 754210b23c2SDaniel Vetter default: 755210b23c2SDaniel Vetter case SNB_GTT_SIZE_0M: 756210b23c2SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 757210b23c2SDaniel Vetter size = MB(0); 758210b23c2SDaniel Vetter break; 759210b23c2SDaniel Vetter case SNB_GTT_SIZE_1M: 760210b23c2SDaniel Vetter size = MB(1); 761210b23c2SDaniel Vetter break; 762210b23c2SDaniel Vetter case SNB_GTT_SIZE_2M: 763210b23c2SDaniel Vetter size = MB(2); 764210b23c2SDaniel Vetter break; 765210b23c2SDaniel Vetter } 766210b23c2SDaniel Vetter return size/4; 767fbe40783SDaniel Vetter } else { 768fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 769fbe40783SDaniel Vetter * required to map the aperture. 770fbe40783SDaniel Vetter */ 771e5e408fcSDaniel Vetter return intel_private.base.gtt_mappable_entries; 772fbe40783SDaniel Vetter } 773fbe40783SDaniel Vetter } 774fbe40783SDaniel Vetter 7751784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 7761784a5fbSDaniel Vetter { 7771784a5fbSDaniel Vetter unsigned int aperture_size; 7781784a5fbSDaniel Vetter u16 gmch_ctrl; 7791784a5fbSDaniel Vetter 7801784a5fbSDaniel Vetter aperture_size = 1024 * 1024; 7811784a5fbSDaniel Vetter 7821784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 7831784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 7841784a5fbSDaniel Vetter 7851784a5fbSDaniel Vetter switch (intel_private.pcidev->device) { 7861784a5fbSDaniel Vetter case PCI_DEVICE_ID_INTEL_82830_CGC: 7871784a5fbSDaniel Vetter case PCI_DEVICE_ID_INTEL_82845G_IG: 7881784a5fbSDaniel Vetter case PCI_DEVICE_ID_INTEL_82855GM_IG: 7891784a5fbSDaniel Vetter case PCI_DEVICE_ID_INTEL_82865_IG: 7901784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 7911784a5fbSDaniel Vetter aperture_size *= 64; 7921784a5fbSDaniel Vetter else 7931784a5fbSDaniel Vetter aperture_size *= 128; 7941784a5fbSDaniel Vetter break; 7951784a5fbSDaniel Vetter default: 7961784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 7971784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 7981784a5fbSDaniel Vetter break; 7991784a5fbSDaniel Vetter } 8001784a5fbSDaniel Vetter 8011784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 8021784a5fbSDaniel Vetter } 8031784a5fbSDaniel Vetter 8041784a5fbSDaniel Vetter static int intel_gtt_init(void) 8051784a5fbSDaniel Vetter { 806f67eab66SDaniel Vetter u32 gtt_map_size; 8073b15a9d7SDaniel Vetter int ret; 8083b15a9d7SDaniel Vetter 8093b15a9d7SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 8103b15a9d7SDaniel Vetter 8113b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 8123b15a9d7SDaniel Vetter if (ret != 0) 8133b15a9d7SDaniel Vetter return ret; 814f67eab66SDaniel Vetter 815f67eab66SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 816f67eab66SDaniel Vetter intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 817f67eab66SDaniel Vetter 818f67eab66SDaniel Vetter gtt_map_size = intel_private.base.gtt_total_entries * 4; 819f67eab66SDaniel Vetter 820f67eab66SDaniel Vetter intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 821f67eab66SDaniel Vetter gtt_map_size); 822f67eab66SDaniel Vetter if (!intel_private.gtt) { 823f67eab66SDaniel Vetter iounmap(intel_private.registers); 824f67eab66SDaniel Vetter return -ENOMEM; 825f67eab66SDaniel Vetter } 826f67eab66SDaniel Vetter 827f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 828f67eab66SDaniel Vetter 8291784a5fbSDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 8301784a5fbSDaniel Vetter intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); 8311784a5fbSDaniel Vetter if (intel_private.base.gtt_stolen_entries == 0) { 8321784a5fbSDaniel Vetter iounmap(intel_private.registers); 833f67eab66SDaniel Vetter iounmap(intel_private.gtt); 8341784a5fbSDaniel Vetter return -ENOMEM; 8351784a5fbSDaniel Vetter } 8361784a5fbSDaniel Vetter 8371784a5fbSDaniel Vetter return 0; 8381784a5fbSDaniel Vetter } 8391784a5fbSDaniel Vetter 8403e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 8413e921f98SDaniel Vetter { 8423e921f98SDaniel Vetter unsigned int aper_size; 8433e921f98SDaniel Vetter int i; 844ffdd7510SDaniel Vetter int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 8453e921f98SDaniel Vetter 8463e921f98SDaniel Vetter aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 8473e921f98SDaniel Vetter / MB(1); 8483e921f98SDaniel Vetter 8493e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 850ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 851ffdd7510SDaniel Vetter agp_bridge->current_size = intel_fake_agp_sizes + i; 8523e921f98SDaniel Vetter return aper_size; 8533e921f98SDaniel Vetter } 8543e921f98SDaniel Vetter } 8553e921f98SDaniel Vetter 8563e921f98SDaniel Vetter return 0; 8573e921f98SDaniel Vetter } 8583e921f98SDaniel Vetter 859f51b7662SDaniel Vetter static void intel_i830_fini_flush(void) 860f51b7662SDaniel Vetter { 861f51b7662SDaniel Vetter kunmap(intel_private.i8xx_page); 862f51b7662SDaniel Vetter intel_private.i8xx_flush_page = NULL; 863f51b7662SDaniel Vetter unmap_page_from_agp(intel_private.i8xx_page); 864f51b7662SDaniel Vetter 865f51b7662SDaniel Vetter __free_page(intel_private.i8xx_page); 866f51b7662SDaniel Vetter intel_private.i8xx_page = NULL; 867f51b7662SDaniel Vetter } 868f51b7662SDaniel Vetter 869f51b7662SDaniel Vetter static void intel_i830_setup_flush(void) 870f51b7662SDaniel Vetter { 871f51b7662SDaniel Vetter /* return if we've already set the flush mechanism up */ 872f51b7662SDaniel Vetter if (intel_private.i8xx_page) 873f51b7662SDaniel Vetter return; 874f51b7662SDaniel Vetter 875f51b7662SDaniel Vetter intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 876f51b7662SDaniel Vetter if (!intel_private.i8xx_page) 877f51b7662SDaniel Vetter return; 878f51b7662SDaniel Vetter 879f51b7662SDaniel Vetter intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 880f51b7662SDaniel Vetter if (!intel_private.i8xx_flush_page) 881f51b7662SDaniel Vetter intel_i830_fini_flush(); 882f51b7662SDaniel Vetter } 883f51b7662SDaniel Vetter 884f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 885f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 886f51b7662SDaniel Vetter * doesn't snoop those buffers. 887f51b7662SDaniel Vetter * 888f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 889f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 890f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 891f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 892f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 893f51b7662SDaniel Vetter */ 894f51b7662SDaniel Vetter static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 895f51b7662SDaniel Vetter { 896f51b7662SDaniel Vetter unsigned int *pg = intel_private.i8xx_flush_page; 897f51b7662SDaniel Vetter 898f51b7662SDaniel Vetter memset(pg, 0, 1024); 899f51b7662SDaniel Vetter 900f51b7662SDaniel Vetter if (cpu_has_clflush) 901f51b7662SDaniel Vetter clflush_cache_range(pg, 1024); 902f51b7662SDaniel Vetter else if (wbinvd_on_all_cpus() != 0) 903f51b7662SDaniel Vetter printk(KERN_ERR "Timed out waiting for cache flush.\n"); 904f51b7662SDaniel Vetter } 905f51b7662SDaniel Vetter 90673800422SDaniel Vetter static void intel_enable_gtt(void) 90773800422SDaniel Vetter { 90873800422SDaniel Vetter u32 ptetbl_addr, gma_addr; 90973800422SDaniel Vetter u16 gmch_ctrl; 91073800422SDaniel Vetter 91173800422SDaniel Vetter ptetbl_addr = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 91273800422SDaniel Vetter 9132d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 2) 9142d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 9152d2430cfSDaniel Vetter &gma_addr); 9162d2430cfSDaniel Vetter else 9172d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 9182d2430cfSDaniel Vetter &gma_addr); 9192d2430cfSDaniel Vetter 92073800422SDaniel Vetter intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 92173800422SDaniel Vetter 92273800422SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); 92373800422SDaniel Vetter gmch_ctrl |= I830_GMCH_ENABLED; 92473800422SDaniel Vetter pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); 92573800422SDaniel Vetter 92673800422SDaniel Vetter writel(ptetbl_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 92773800422SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 92873800422SDaniel Vetter } 92973800422SDaniel Vetter 93073800422SDaniel Vetter static int i830_setup(void) 93173800422SDaniel Vetter { 93273800422SDaniel Vetter u32 reg_addr; 93373800422SDaniel Vetter 93473800422SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 93573800422SDaniel Vetter reg_addr &= 0xfff80000; 93673800422SDaniel Vetter 93773800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 93873800422SDaniel Vetter if (!intel_private.registers) 93973800422SDaniel Vetter return -ENOMEM; 94073800422SDaniel Vetter 94173800422SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 94273800422SDaniel Vetter 94373800422SDaniel Vetter intel_i830_setup_flush(); 94473800422SDaniel Vetter 94573800422SDaniel Vetter return 0; 94673800422SDaniel Vetter } 94773800422SDaniel Vetter 9483b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 949f51b7662SDaniel Vetter { 95073800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 951f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 95273800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 953f51b7662SDaniel Vetter 954f51b7662SDaniel Vetter return 0; 955f51b7662SDaniel Vetter } 956f51b7662SDaniel Vetter 957ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 958f51b7662SDaniel Vetter { 959f51b7662SDaniel Vetter return 0; 960f51b7662SDaniel Vetter } 961f51b7662SDaniel Vetter 962f51b7662SDaniel Vetter static int intel_i830_configure(void) 963f51b7662SDaniel Vetter { 964f51b7662SDaniel Vetter int i; 965f51b7662SDaniel Vetter 96673800422SDaniel Vetter intel_enable_gtt(); 967f51b7662SDaniel Vetter 96873800422SDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 969f51b7662SDaniel Vetter 970f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 97173800422SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; 97273800422SDaniel Vetter i < intel_private.base.gtt_total_entries; i++) { 973fdfb58a9SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 974f51b7662SDaniel Vetter } 975fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 976f51b7662SDaniel Vetter } 977f51b7662SDaniel Vetter 978f51b7662SDaniel Vetter global_cache_flush(); 979f51b7662SDaniel Vetter 980f51b7662SDaniel Vetter return 0; 981f51b7662SDaniel Vetter } 982f51b7662SDaniel Vetter 983f51b7662SDaniel Vetter static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 984f51b7662SDaniel Vetter int type) 985f51b7662SDaniel Vetter { 986f51b7662SDaniel Vetter int i, j, num_entries; 987f51b7662SDaniel Vetter void *temp; 988f51b7662SDaniel Vetter int ret = -EINVAL; 989f51b7662SDaniel Vetter int mask_type; 990f51b7662SDaniel Vetter 991f51b7662SDaniel Vetter if (mem->page_count == 0) 992f51b7662SDaniel Vetter goto out; 993f51b7662SDaniel Vetter 994f51b7662SDaniel Vetter temp = agp_bridge->current_size; 995f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 996f51b7662SDaniel Vetter 9970ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 998f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 9990ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 10000ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1001f51b7662SDaniel Vetter 1002f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1003f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1004f51b7662SDaniel Vetter goto out_err; 1005f51b7662SDaniel Vetter } 1006f51b7662SDaniel Vetter 1007f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1008f51b7662SDaniel Vetter goto out_err; 1009f51b7662SDaniel Vetter 1010f51b7662SDaniel Vetter /* The i830 can't check the GTT for entries since its read only, 1011f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1012f51b7662SDaniel Vetter */ 1013f51b7662SDaniel Vetter 1014f51b7662SDaniel Vetter if (type != mem->type) 1015f51b7662SDaniel Vetter goto out_err; 1016f51b7662SDaniel Vetter 1017f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1018f51b7662SDaniel Vetter 1019f51b7662SDaniel Vetter if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1020f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1021f51b7662SDaniel Vetter goto out_err; 1022f51b7662SDaniel Vetter 1023f51b7662SDaniel Vetter if (!mem->is_flushed) 1024f51b7662SDaniel Vetter global_cache_flush(); 1025f51b7662SDaniel Vetter 1026f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1027f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 1028f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 1029fdfb58a9SDaniel Vetter intel_private.gtt+j); 1030f51b7662SDaniel Vetter } 1031fdfb58a9SDaniel Vetter readl(intel_private.gtt+j-1); 1032f51b7662SDaniel Vetter 1033f51b7662SDaniel Vetter out: 1034f51b7662SDaniel Vetter ret = 0; 1035f51b7662SDaniel Vetter out_err: 1036f51b7662SDaniel Vetter mem->is_flushed = true; 1037f51b7662SDaniel Vetter return ret; 1038f51b7662SDaniel Vetter } 1039f51b7662SDaniel Vetter 1040f51b7662SDaniel Vetter static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1041f51b7662SDaniel Vetter int type) 1042f51b7662SDaniel Vetter { 1043f51b7662SDaniel Vetter int i; 1044f51b7662SDaniel Vetter 1045f51b7662SDaniel Vetter if (mem->page_count == 0) 1046f51b7662SDaniel Vetter return 0; 1047f51b7662SDaniel Vetter 10480ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1049f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1050f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1051f51b7662SDaniel Vetter return -EINVAL; 1052f51b7662SDaniel Vetter } 1053f51b7662SDaniel Vetter 1054f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1055fdfb58a9SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1056f51b7662SDaniel Vetter } 1057fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 1058f51b7662SDaniel Vetter 1059f51b7662SDaniel Vetter return 0; 1060f51b7662SDaniel Vetter } 1061f51b7662SDaniel Vetter 1062ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1063ffdd7510SDaniel Vetter int type) 1064f51b7662SDaniel Vetter { 1065f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 1066f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 1067f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 1068f51b7662SDaniel Vetter return NULL; 1069f51b7662SDaniel Vetter } 1070f51b7662SDaniel Vetter 1071f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 1072f51b7662SDaniel Vetter { 1073f51b7662SDaniel Vetter int ret; 1074d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1075f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1076d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 1077f51b7662SDaniel Vetter 1078f51b7662SDaniel Vetter return ret; 1079f51b7662SDaniel Vetter } 1080f51b7662SDaniel Vetter 1081f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 1082f51b7662SDaniel Vetter { 1083f51b7662SDaniel Vetter int ret; 1084f51b7662SDaniel Vetter u32 temp; 1085f51b7662SDaniel Vetter 1086d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1087f51b7662SDaniel Vetter if (!(temp & 0x1)) { 1088f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1089f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1090d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1091f51b7662SDaniel Vetter } else { 1092f51b7662SDaniel Vetter temp &= ~1; 1093f51b7662SDaniel Vetter 1094f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1095f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1096f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1097f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1098f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1099f51b7662SDaniel Vetter if (ret) 1100f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1101f51b7662SDaniel Vetter } 1102f51b7662SDaniel Vetter } 1103f51b7662SDaniel Vetter 1104f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1105f51b7662SDaniel Vetter { 1106f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1107f51b7662SDaniel Vetter int ret; 1108f51b7662SDaniel Vetter 1109d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1110d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1111f51b7662SDaniel Vetter 1112f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1113f51b7662SDaniel Vetter 1114f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1115f51b7662SDaniel Vetter 1116f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1117d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1118f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1119d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1120f51b7662SDaniel Vetter } else { 1121f51b7662SDaniel Vetter u64 l64; 1122f51b7662SDaniel Vetter 1123f51b7662SDaniel Vetter temp_lo &= ~0x1; 1124f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1125f51b7662SDaniel Vetter 1126f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1127f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1128f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1129f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1130f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1131f51b7662SDaniel Vetter if (ret) 1132f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1133f51b7662SDaniel Vetter } 1134f51b7662SDaniel Vetter } 1135f51b7662SDaniel Vetter 1136f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1137f51b7662SDaniel Vetter { 1138f51b7662SDaniel Vetter /* return if already configured */ 1139f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1140f51b7662SDaniel Vetter return; 1141f51b7662SDaniel Vetter 11421a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1143f51b7662SDaniel Vetter return; 1144f51b7662SDaniel Vetter 1145f51b7662SDaniel Vetter /* setup a resource for this object */ 1146f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1147f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1148f51b7662SDaniel Vetter 1149f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 11501a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1151f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1152f51b7662SDaniel Vetter } else { 1153f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1154f51b7662SDaniel Vetter } 1155f51b7662SDaniel Vetter 1156df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1157f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1158f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1159df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1160df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1161f51b7662SDaniel Vetter } 1162f51b7662SDaniel Vetter 1163f1befe71SChris Wilson static int intel_i9xx_configure(void) 1164f51b7662SDaniel Vetter { 1165f51b7662SDaniel Vetter int i; 1166f51b7662SDaniel Vetter 11672d2430cfSDaniel Vetter intel_enable_gtt(); 1168f51b7662SDaniel Vetter 11692d2430cfSDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1170f51b7662SDaniel Vetter 1171f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 11720ade6386SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; i < 11730ade6386SDaniel Vetter intel_private.base.gtt_total_entries; i++) { 1174f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1175f51b7662SDaniel Vetter } 1176f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1177f51b7662SDaniel Vetter } 1178f51b7662SDaniel Vetter 1179f51b7662SDaniel Vetter global_cache_flush(); 1180f51b7662SDaniel Vetter 1181f51b7662SDaniel Vetter return 0; 1182f51b7662SDaniel Vetter } 1183f51b7662SDaniel Vetter 1184fdfb58a9SDaniel Vetter static void intel_gtt_cleanup(void) 1185f51b7662SDaniel Vetter { 1186f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1187f51b7662SDaniel Vetter iounmap(intel_private.i9xx_flush_page); 1188f51b7662SDaniel Vetter if (intel_private.resource_valid) 1189f51b7662SDaniel Vetter release_resource(&intel_private.ifp_resource); 1190f51b7662SDaniel Vetter intel_private.ifp_resource.start = 0; 1191f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1192f51b7662SDaniel Vetter iounmap(intel_private.gtt); 1193f51b7662SDaniel Vetter iounmap(intel_private.registers); 1194f51b7662SDaniel Vetter } 1195f51b7662SDaniel Vetter 1196f51b7662SDaniel Vetter static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1197f51b7662SDaniel Vetter { 1198f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1199f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1200f51b7662SDaniel Vetter } 1201f51b7662SDaniel Vetter 1202f51b7662SDaniel Vetter static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1203f51b7662SDaniel Vetter int type) 1204f51b7662SDaniel Vetter { 1205f51b7662SDaniel Vetter int num_entries; 1206f51b7662SDaniel Vetter void *temp; 1207f51b7662SDaniel Vetter int ret = -EINVAL; 1208f51b7662SDaniel Vetter int mask_type; 1209f51b7662SDaniel Vetter 1210f51b7662SDaniel Vetter if (mem->page_count == 0) 1211f51b7662SDaniel Vetter goto out; 1212f51b7662SDaniel Vetter 1213f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1214f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1215f51b7662SDaniel Vetter 12160ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1217f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 12180ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 12190ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1220f51b7662SDaniel Vetter 1221f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1222f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1223f51b7662SDaniel Vetter goto out_err; 1224f51b7662SDaniel Vetter } 1225f51b7662SDaniel Vetter 1226f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1227f51b7662SDaniel Vetter goto out_err; 1228f51b7662SDaniel Vetter 1229f51b7662SDaniel Vetter /* The i915 can't check the GTT for entries since it's read only; 1230f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1231f51b7662SDaniel Vetter */ 1232f51b7662SDaniel Vetter 1233f51b7662SDaniel Vetter if (type != mem->type) 1234f51b7662SDaniel Vetter goto out_err; 1235f51b7662SDaniel Vetter 1236f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1237f51b7662SDaniel Vetter 12381a997ff2SDaniel Vetter if (INTEL_GTT_GEN != 6 && mask_type != 0 && 12391a997ff2SDaniel Vetter mask_type != AGP_PHYS_MEMORY && 1240f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1241f51b7662SDaniel Vetter goto out_err; 1242f51b7662SDaniel Vetter 1243f51b7662SDaniel Vetter if (!mem->is_flushed) 1244f51b7662SDaniel Vetter global_cache_flush(); 1245f51b7662SDaniel Vetter 1246f51b7662SDaniel Vetter intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1247f51b7662SDaniel Vetter 1248f51b7662SDaniel Vetter out: 1249f51b7662SDaniel Vetter ret = 0; 1250f51b7662SDaniel Vetter out_err: 1251f51b7662SDaniel Vetter mem->is_flushed = true; 1252f51b7662SDaniel Vetter return ret; 1253f51b7662SDaniel Vetter } 1254f51b7662SDaniel Vetter 1255f51b7662SDaniel Vetter static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1256f51b7662SDaniel Vetter int type) 1257f51b7662SDaniel Vetter { 1258f51b7662SDaniel Vetter int i; 1259f51b7662SDaniel Vetter 1260f51b7662SDaniel Vetter if (mem->page_count == 0) 1261f51b7662SDaniel Vetter return 0; 1262f51b7662SDaniel Vetter 12630ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1264f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1265f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1266f51b7662SDaniel Vetter return -EINVAL; 1267f51b7662SDaniel Vetter } 1268f51b7662SDaniel Vetter 1269f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) 1270f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1271f51b7662SDaniel Vetter 1272f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); 1273f51b7662SDaniel Vetter 1274f51b7662SDaniel Vetter return 0; 1275f51b7662SDaniel Vetter } 1276f51b7662SDaniel Vetter 12772d2430cfSDaniel Vetter static int i9xx_setup(void) 12782d2430cfSDaniel Vetter { 12792d2430cfSDaniel Vetter u32 reg_addr; 12802d2430cfSDaniel Vetter 12812d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 12822d2430cfSDaniel Vetter 12832d2430cfSDaniel Vetter reg_addr &= 0xfff80000; 12842d2430cfSDaniel Vetter 12852d2430cfSDaniel Vetter intel_private.registers = ioremap(reg_addr, 128 * 4096); 12862d2430cfSDaniel Vetter if (!intel_private.registers) 12872d2430cfSDaniel Vetter return -ENOMEM; 12882d2430cfSDaniel Vetter 12892d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 3) { 12902d2430cfSDaniel Vetter u32 gtt_addr; 12912d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, 12922d2430cfSDaniel Vetter I915_PTEADDR, >t_addr); 12932d2430cfSDaniel Vetter intel_private.gtt_bus_addr = gtt_addr; 12942d2430cfSDaniel Vetter } else { 12952d2430cfSDaniel Vetter u32 gtt_offset; 12962d2430cfSDaniel Vetter 12972d2430cfSDaniel Vetter switch (INTEL_GTT_GEN) { 12982d2430cfSDaniel Vetter case 5: 12992d2430cfSDaniel Vetter case 6: 13002d2430cfSDaniel Vetter gtt_offset = MB(2); 13012d2430cfSDaniel Vetter break; 13022d2430cfSDaniel Vetter case 4: 13032d2430cfSDaniel Vetter default: 13042d2430cfSDaniel Vetter gtt_offset = KB(512); 13052d2430cfSDaniel Vetter break; 13062d2430cfSDaniel Vetter } 13072d2430cfSDaniel Vetter intel_private.gtt_bus_addr = reg_addr + gtt_offset; 13082d2430cfSDaniel Vetter } 13092d2430cfSDaniel Vetter 13102d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 13112d2430cfSDaniel Vetter 13122d2430cfSDaniel Vetter return 0; 13132d2430cfSDaniel Vetter } 13142d2430cfSDaniel Vetter 1315f51b7662SDaniel Vetter /* 1316f51b7662SDaniel Vetter * The i965 supports 36-bit physical addresses, but to keep 1317f51b7662SDaniel Vetter * the format of the GTT the same, the bits that don't fit 1318f51b7662SDaniel Vetter * in a 32-bit word are shifted down to bits 4..7. 1319f51b7662SDaniel Vetter * 1320f51b7662SDaniel Vetter * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1321f51b7662SDaniel Vetter * is always zero on 32-bit architectures, so no need to make 1322f51b7662SDaniel Vetter * this conditional. 1323f51b7662SDaniel Vetter */ 1324f51b7662SDaniel Vetter static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1325f51b7662SDaniel Vetter dma_addr_t addr, int type) 1326f51b7662SDaniel Vetter { 1327f51b7662SDaniel Vetter /* Shift high bits down */ 1328f51b7662SDaniel Vetter addr |= (addr >> 28) & 0xf0; 1329f51b7662SDaniel Vetter 1330f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 1331f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 1332f51b7662SDaniel Vetter } 1333f51b7662SDaniel Vetter 13343869d4a8SZhenyu Wang static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, 13353869d4a8SZhenyu Wang dma_addr_t addr, int type) 13363869d4a8SZhenyu Wang { 13378dfc2b14SZhenyu Wang /* gen6 has bit11-4 for physical addr bit39-32 */ 13388dfc2b14SZhenyu Wang addr |= (addr >> 28) & 0xff0; 13393869d4a8SZhenyu Wang 13403869d4a8SZhenyu Wang /* Type checking must be done elsewhere */ 13413869d4a8SZhenyu Wang return addr | bridge->driver->masks[type].mask; 13423869d4a8SZhenyu Wang } 13433869d4a8SZhenyu Wang 1344f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_810_driver = { 1345f51b7662SDaniel Vetter .owner = THIS_MODULE, 1346f51b7662SDaniel Vetter .aperture_sizes = intel_i810_sizes, 1347f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1348f51b7662SDaniel Vetter .num_aperture_sizes = 2, 1349f51b7662SDaniel Vetter .needs_scratch_page = true, 1350f51b7662SDaniel Vetter .configure = intel_i810_configure, 1351f51b7662SDaniel Vetter .fetch_size = intel_i810_fetch_size, 1352f51b7662SDaniel Vetter .cleanup = intel_i810_cleanup, 1353f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1354f51b7662SDaniel Vetter .masks = intel_i810_masks, 1355ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1356f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1357f51b7662SDaniel Vetter .create_gatt_table = agp_generic_create_gatt_table, 1358f51b7662SDaniel Vetter .free_gatt_table = agp_generic_free_gatt_table, 1359f51b7662SDaniel Vetter .insert_memory = intel_i810_insert_entries, 1360f51b7662SDaniel Vetter .remove_memory = intel_i810_remove_entries, 1361f51b7662SDaniel Vetter .alloc_by_type = intel_i810_alloc_by_type, 1362f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1363f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1364f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1365f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1366f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1367f51b7662SDaniel Vetter .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1368f51b7662SDaniel Vetter }; 1369f51b7662SDaniel Vetter 1370f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_830_driver = { 1371f51b7662SDaniel Vetter .owner = THIS_MODULE, 1372ffdd7510SDaniel Vetter .aperture_sizes = intel_fake_agp_sizes, 1373f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1374f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1375f51b7662SDaniel Vetter .needs_scratch_page = true, 1376f51b7662SDaniel Vetter .configure = intel_i830_configure, 13773e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1378fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1379f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1380f51b7662SDaniel Vetter .masks = intel_i810_masks, 1381ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1382f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 13833b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1384ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1385f51b7662SDaniel Vetter .insert_memory = intel_i830_insert_entries, 1386f51b7662SDaniel Vetter .remove_memory = intel_i830_remove_entries, 1387ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1388f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1389f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1390f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1391f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1392f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1393f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1394f51b7662SDaniel Vetter .chipset_flush = intel_i830_chipset_flush, 1395f51b7662SDaniel Vetter }; 1396f51b7662SDaniel Vetter 1397f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_915_driver = { 1398f51b7662SDaniel Vetter .owner = THIS_MODULE, 1399ffdd7510SDaniel Vetter .aperture_sizes = intel_fake_agp_sizes, 1400f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1401f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1402f51b7662SDaniel Vetter .needs_scratch_page = true, 1403f1befe71SChris Wilson .configure = intel_i9xx_configure, 14043e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1405fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1406f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1407f51b7662SDaniel Vetter .masks = intel_i810_masks, 1408ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1409f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14103b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1411ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1412f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1413f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1414ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1415f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1416f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1417f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1418f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1419f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1420f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1421f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1422f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1423f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1424f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1425f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1426f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1427f51b7662SDaniel Vetter #endif 1428f51b7662SDaniel Vetter }; 1429f51b7662SDaniel Vetter 1430f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_i965_driver = { 1431f51b7662SDaniel Vetter .owner = THIS_MODULE, 1432ffdd7510SDaniel Vetter .aperture_sizes = intel_fake_agp_sizes, 1433f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1434f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1435f51b7662SDaniel Vetter .needs_scratch_page = true, 1436f1befe71SChris Wilson .configure = intel_i9xx_configure, 14373e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1438fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1439f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1440f51b7662SDaniel Vetter .masks = intel_i810_masks, 1441ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1442f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14433b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1444ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1445f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1446f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1447ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1448f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1449f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1450f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1451f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1452f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1453f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1454f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1455f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1456f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1457f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1458f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1459f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1460f51b7662SDaniel Vetter #endif 1461f51b7662SDaniel Vetter }; 1462f51b7662SDaniel Vetter 14633869d4a8SZhenyu Wang static const struct agp_bridge_driver intel_gen6_driver = { 14643869d4a8SZhenyu Wang .owner = THIS_MODULE, 1465ffdd7510SDaniel Vetter .aperture_sizes = intel_fake_agp_sizes, 14663869d4a8SZhenyu Wang .size_type = FIXED_APER_SIZE, 14673869d4a8SZhenyu Wang .num_aperture_sizes = 4, 14683869d4a8SZhenyu Wang .needs_scratch_page = true, 14693869d4a8SZhenyu Wang .configure = intel_i9xx_configure, 14703e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1471fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 14723869d4a8SZhenyu Wang .mask_memory = intel_gen6_mask_memory, 1473f8f235e5SZhenyu Wang .masks = intel_gen6_masks, 1474ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 14753869d4a8SZhenyu Wang .cache_flush = global_cache_flush, 14763b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1477ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 14783869d4a8SZhenyu Wang .insert_memory = intel_i915_insert_entries, 14793869d4a8SZhenyu Wang .remove_memory = intel_i915_remove_entries, 1480ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 14813869d4a8SZhenyu Wang .free_by_type = intel_i810_free_by_type, 14823869d4a8SZhenyu Wang .agp_alloc_page = agp_generic_alloc_page, 14833869d4a8SZhenyu Wang .agp_alloc_pages = agp_generic_alloc_pages, 14843869d4a8SZhenyu Wang .agp_destroy_page = agp_generic_destroy_page, 14853869d4a8SZhenyu Wang .agp_destroy_pages = agp_generic_destroy_pages, 1486f8f235e5SZhenyu Wang .agp_type_to_mask_type = intel_gen6_type_to_mask_type, 14873869d4a8SZhenyu Wang .chipset_flush = intel_i915_chipset_flush, 14883869d4a8SZhenyu Wang #ifdef USE_PCI_DMA_API 14893869d4a8SZhenyu Wang .agp_map_page = intel_agp_map_page, 14903869d4a8SZhenyu Wang .agp_unmap_page = intel_agp_unmap_page, 14913869d4a8SZhenyu Wang .agp_map_memory = intel_agp_map_memory, 14923869d4a8SZhenyu Wang .agp_unmap_memory = intel_agp_unmap_memory, 14933869d4a8SZhenyu Wang #endif 14943869d4a8SZhenyu Wang }; 14953869d4a8SZhenyu Wang 1496f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_g33_driver = { 1497f51b7662SDaniel Vetter .owner = THIS_MODULE, 1498ffdd7510SDaniel Vetter .aperture_sizes = intel_fake_agp_sizes, 1499f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1500f51b7662SDaniel Vetter .num_aperture_sizes = 4, 1501f51b7662SDaniel Vetter .needs_scratch_page = true, 1502f1befe71SChris Wilson .configure = intel_i9xx_configure, 15033e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1504fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1505f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1506f51b7662SDaniel Vetter .masks = intel_i810_masks, 1507ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1508f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 15093b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1510ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1511f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1512f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1513ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1514f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1515f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1516f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1517f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1518f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1519f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1520f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 1521f51b7662SDaniel Vetter #ifdef USE_PCI_DMA_API 1522f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1523f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1524f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1525f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1526f51b7662SDaniel Vetter #endif 1527f51b7662SDaniel Vetter }; 152802c026ceSDaniel Vetter 15291a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 15301a997ff2SDaniel Vetter .gen = 2, 153173800422SDaniel Vetter .setup = i830_setup, 15321a997ff2SDaniel Vetter }; 15331a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 15341a997ff2SDaniel Vetter .gen = 3, 15352d2430cfSDaniel Vetter .setup = i9xx_setup, 15361a997ff2SDaniel Vetter }; 15371a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 15381a997ff2SDaniel Vetter .gen = 3, 15391a997ff2SDaniel Vetter .is_g33 = 1, 15402d2430cfSDaniel Vetter .setup = i9xx_setup, 15411a997ff2SDaniel Vetter }; 15421a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 15431a997ff2SDaniel Vetter .gen = 3, 15441a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 15452d2430cfSDaniel Vetter .setup = i9xx_setup, 15461a997ff2SDaniel Vetter }; 15471a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 15481a997ff2SDaniel Vetter .gen = 4, 15492d2430cfSDaniel Vetter .setup = i9xx_setup, 15501a997ff2SDaniel Vetter }; 15511a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 15521a997ff2SDaniel Vetter .gen = 5, 15532d2430cfSDaniel Vetter .setup = i9xx_setup, 15541a997ff2SDaniel Vetter }; 15551a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 15561a997ff2SDaniel Vetter .gen = 5, 15571a997ff2SDaniel Vetter .is_ironlake = 1, 15582d2430cfSDaniel Vetter .setup = i9xx_setup, 15591a997ff2SDaniel Vetter }; 15601a997ff2SDaniel Vetter static const struct intel_gtt_driver sandybridge_gtt_driver = { 15611a997ff2SDaniel Vetter .gen = 6, 15622d2430cfSDaniel Vetter .setup = i9xx_setup, 15631a997ff2SDaniel Vetter }; 15641a997ff2SDaniel Vetter 156502c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 156602c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 156702c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 156802c026ceSDaniel Vetter */ 156902c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 157002c026ceSDaniel Vetter unsigned int gmch_chip_id; 157102c026ceSDaniel Vetter char *name; 157202c026ceSDaniel Vetter const struct agp_bridge_driver *gmch_driver; 15731a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 157402c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 15751a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL}, 15761a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL}, 15771a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL}, 15781a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL}, 15791a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 15801a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 15811a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 15821a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 15831a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 15841a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 15851a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 15861a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 15871a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 15881a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 15891a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 15901a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 15911a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 15921a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 15931a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 15941a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 15951a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 15961a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 15971a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 15981a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 15991a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 16001a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16011a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 16021a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16031a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 16041a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16051a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 16061a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16071a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 16081a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16091a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 16101a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16111a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 16121a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16131a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 16141a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16151a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 16161a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16171a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 16181a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16191a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 16201a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16211a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 16221a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16231a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 16241a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16251a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 16261a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16271a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 16281a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16291a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 16301a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16311a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 16321a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16331a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 16341a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 163502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 16361a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 163702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 16381a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 163902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 16401a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 164102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 16421a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 164302c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 16441a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 164502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 16461a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 164702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 16481a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 164902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 16501a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 165102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 16521a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 165302c026ceSDaniel Vetter { 0, NULL, NULL } 165402c026ceSDaniel Vetter }; 165502c026ceSDaniel Vetter 165602c026ceSDaniel Vetter static int find_gmch(u16 device) 165702c026ceSDaniel Vetter { 165802c026ceSDaniel Vetter struct pci_dev *gmch_device; 165902c026ceSDaniel Vetter 166002c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 166102c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 166202c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 166302c026ceSDaniel Vetter device, gmch_device); 166402c026ceSDaniel Vetter } 166502c026ceSDaniel Vetter 166602c026ceSDaniel Vetter if (!gmch_device) 166702c026ceSDaniel Vetter return 0; 166802c026ceSDaniel Vetter 166902c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 167002c026ceSDaniel Vetter return 1; 167102c026ceSDaniel Vetter } 167202c026ceSDaniel Vetter 1673e2404e7cSDaniel Vetter int intel_gmch_probe(struct pci_dev *pdev, 167402c026ceSDaniel Vetter struct agp_bridge_data *bridge) 167502c026ceSDaniel Vetter { 167602c026ceSDaniel Vetter int i, mask; 167702c026ceSDaniel Vetter bridge->driver = NULL; 167802c026ceSDaniel Vetter 167902c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 168002c026ceSDaniel Vetter if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 168102c026ceSDaniel Vetter bridge->driver = 168202c026ceSDaniel Vetter intel_gtt_chipsets[i].gmch_driver; 16831a997ff2SDaniel Vetter intel_private.driver = 16841a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 168502c026ceSDaniel Vetter break; 168602c026ceSDaniel Vetter } 168702c026ceSDaniel Vetter } 168802c026ceSDaniel Vetter 168902c026ceSDaniel Vetter if (!bridge->driver) 169002c026ceSDaniel Vetter return 0; 169102c026ceSDaniel Vetter 169202c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 169302c026ceSDaniel Vetter bridge->dev = pdev; 169402c026ceSDaniel Vetter 1695d7cca2f7SDaniel Vetter intel_private.bridge_dev = pci_dev_get(pdev); 1696d7cca2f7SDaniel Vetter 169702c026ceSDaniel Vetter dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 169802c026ceSDaniel Vetter 169902c026ceSDaniel Vetter if (bridge->driver->mask_memory == intel_gen6_mask_memory) 170002c026ceSDaniel Vetter mask = 40; 170102c026ceSDaniel Vetter else if (bridge->driver->mask_memory == intel_i965_mask_memory) 170202c026ceSDaniel Vetter mask = 36; 170302c026ceSDaniel Vetter else 170402c026ceSDaniel Vetter mask = 32; 170502c026ceSDaniel Vetter 170602c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 170702c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 170802c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 170902c026ceSDaniel Vetter else 171002c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 171102c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 171202c026ceSDaniel Vetter 17131784a5fbSDaniel Vetter if (bridge->driver == &intel_810_driver) 17141784a5fbSDaniel Vetter return 1; 17151784a5fbSDaniel Vetter 17163b15a9d7SDaniel Vetter if (intel_gtt_init() != 0) 17173b15a9d7SDaniel Vetter return 0; 17181784a5fbSDaniel Vetter 171902c026ceSDaniel Vetter return 1; 172002c026ceSDaniel Vetter } 1721e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 172202c026ceSDaniel Vetter 1723e2404e7cSDaniel Vetter void intel_gmch_remove(struct pci_dev *pdev) 172402c026ceSDaniel Vetter { 172502c026ceSDaniel Vetter if (intel_private.pcidev) 172602c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1727d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1728d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 172902c026ceSDaniel Vetter } 1730e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1731e2404e7cSDaniel Vetter 1732e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1733e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1734