1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24bdb8b975SChris Wilson #include <linux/delay.h> 25e2404e7cSDaniel Vetter #include <asm/smp.h> 26e2404e7cSDaniel Vetter #include "agp.h" 27e2404e7cSDaniel Vetter #include "intel-agp.h" 280ade6386SDaniel Vetter #include <drm/intel-gtt.h> 29e2404e7cSDaniel Vetter 30f51b7662SDaniel Vetter /* 31f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 32f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 34f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 35f51b7662SDaniel Vetter */ 36f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 37f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 380e87d2b0SDaniel Vetter #else 390e87d2b0SDaniel Vetter #define USE_PCI_DMA_API 0 40f51b7662SDaniel Vetter #endif 41f51b7662SDaniel Vetter 421a997ff2SDaniel Vetter struct intel_gtt_driver { 431a997ff2SDaniel Vetter unsigned int gen : 8; 441a997ff2SDaniel Vetter unsigned int is_g33 : 1; 451a997ff2SDaniel Vetter unsigned int is_pineview : 1; 461a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 47100519e2SChris Wilson unsigned int has_pgtbl_enable : 1; 4822533b49SDaniel Vetter unsigned int dma_mask_size : 8; 4973800422SDaniel Vetter /* Chipset specific GTT setup */ 5073800422SDaniel Vetter int (*setup)(void); 51ae83dd5cSDaniel Vetter /* This should undo anything done in ->setup() save the unmapping 52ae83dd5cSDaniel Vetter * of the mmio register file, that's done in the generic code. */ 53ae83dd5cSDaniel Vetter void (*cleanup)(void); 54351bb278SDaniel Vetter void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55351bb278SDaniel Vetter /* Flags is a more or less chipset specific opaque value. 56351bb278SDaniel Vetter * For chipsets that need to support old ums (non-gem) code, this 57351bb278SDaniel Vetter * needs to be identical to the various supported agp memory types! */ 585cbecafcSDaniel Vetter bool (*check_flags)(unsigned int flags); 591b263f24SDaniel Vetter void (*chipset_flush)(void); 601a997ff2SDaniel Vetter }; 611a997ff2SDaniel Vetter 62f51b7662SDaniel Vetter static struct _intel_private { 630ade6386SDaniel Vetter struct intel_gtt base; 641a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 65f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 66d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 67f51b7662SDaniel Vetter u8 __iomem *registers; 68f67eab66SDaniel Vetter phys_addr_t gtt_bus_addr; 6973800422SDaniel Vetter phys_addr_t gma_bus_addr; 70b3eafc5aSDaniel Vetter u32 PGETBL_save; 71f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 72bee4a186SChris Wilson bool clear_fake_agp; /* on first access via agp, fill with scratch */ 73f51b7662SDaniel Vetter int num_dcache_entries; 74f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 75820647b9SDaniel Vetter char *i81x_gtt_table; 76f51b7662SDaniel Vetter struct resource ifp_resource; 77f51b7662SDaniel Vetter int resource_valid; 780e87d2b0SDaniel Vetter struct page *scratch_page; 790e87d2b0SDaniel Vetter dma_addr_t scratch_page_dma; 80f51b7662SDaniel Vetter } intel_private; 81f51b7662SDaniel Vetter 821a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 831a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 841a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 851a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 86100519e2SChris Wilson #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 871a997ff2SDaniel Vetter 884080775bSDaniel Vetter int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, 894080775bSDaniel Vetter struct scatterlist **sg_list, int *num_sg) 90f51b7662SDaniel Vetter { 91f51b7662SDaniel Vetter struct sg_table st; 92f51b7662SDaniel Vetter struct scatterlist *sg; 93f51b7662SDaniel Vetter int i; 94f51b7662SDaniel Vetter 954080775bSDaniel Vetter if (*sg_list) 96fefaa70fSDaniel Vetter return 0; /* already mapped (for e.g. resume */ 97fefaa70fSDaniel Vetter 984080775bSDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)num_entries); 99f51b7662SDaniel Vetter 1004080775bSDaniel Vetter if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) 101831cd445SChris Wilson goto err; 102f51b7662SDaniel Vetter 1034080775bSDaniel Vetter *sg_list = sg = st.sgl; 104f51b7662SDaniel Vetter 1054080775bSDaniel Vetter for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) 1064080775bSDaniel Vetter sg_set_page(sg, pages[i], PAGE_SIZE, 0); 107f51b7662SDaniel Vetter 1084080775bSDaniel Vetter *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, 1094080775bSDaniel Vetter num_entries, PCI_DMA_BIDIRECTIONAL); 1104080775bSDaniel Vetter if (unlikely(!*num_sg)) 111831cd445SChris Wilson goto err; 112831cd445SChris Wilson 113f51b7662SDaniel Vetter return 0; 114831cd445SChris Wilson 115831cd445SChris Wilson err: 116831cd445SChris Wilson sg_free_table(&st); 117831cd445SChris Wilson return -ENOMEM; 118f51b7662SDaniel Vetter } 1194080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_map_memory); 120f51b7662SDaniel Vetter 1214080775bSDaniel Vetter void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 122f51b7662SDaniel Vetter { 1234080775bSDaniel Vetter struct sg_table st; 124f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 125f51b7662SDaniel Vetter 1264080775bSDaniel Vetter pci_unmap_sg(intel_private.pcidev, sg_list, 1274080775bSDaniel Vetter num_sg, PCI_DMA_BIDIRECTIONAL); 1284080775bSDaniel Vetter 1294080775bSDaniel Vetter st.sgl = sg_list; 1304080775bSDaniel Vetter st.orig_nents = st.nents = num_sg; 1314080775bSDaniel Vetter 1324080775bSDaniel Vetter sg_free_table(&st); 133f51b7662SDaniel Vetter } 1344080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_unmap_memory); 135f51b7662SDaniel Vetter 136ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 137f51b7662SDaniel Vetter { 138f51b7662SDaniel Vetter return; 139f51b7662SDaniel Vetter } 140f51b7662SDaniel Vetter 141f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 142f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 143f51b7662SDaniel Vetter { 144f51b7662SDaniel Vetter struct page *page; 145f51b7662SDaniel Vetter 146f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 147f51b7662SDaniel Vetter if (page == NULL) 148f51b7662SDaniel Vetter return NULL; 149f51b7662SDaniel Vetter 150f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 151f51b7662SDaniel Vetter set_pages_wb(page, 4); 152f51b7662SDaniel Vetter __free_pages(page, 2); 153f51b7662SDaniel Vetter return NULL; 154f51b7662SDaniel Vetter } 155f51b7662SDaniel Vetter get_page(page); 156f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 157f51b7662SDaniel Vetter return page; 158f51b7662SDaniel Vetter } 159f51b7662SDaniel Vetter 160f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 161f51b7662SDaniel Vetter { 162f51b7662SDaniel Vetter if (page == NULL) 163f51b7662SDaniel Vetter return; 164f51b7662SDaniel Vetter 165f51b7662SDaniel Vetter set_pages_wb(page, 4); 166f51b7662SDaniel Vetter put_page(page); 167f51b7662SDaniel Vetter __free_pages(page, 2); 168f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 169f51b7662SDaniel Vetter } 170f51b7662SDaniel Vetter 171820647b9SDaniel Vetter #define I810_GTT_ORDER 4 172820647b9SDaniel Vetter static int i810_setup(void) 173820647b9SDaniel Vetter { 174820647b9SDaniel Vetter u32 reg_addr; 175820647b9SDaniel Vetter char *gtt_table; 176820647b9SDaniel Vetter 177820647b9SDaniel Vetter /* i81x does not preallocate the gtt. It's always 64kb in size. */ 178820647b9SDaniel Vetter gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 179820647b9SDaniel Vetter if (gtt_table == NULL) 180820647b9SDaniel Vetter return -ENOMEM; 181820647b9SDaniel Vetter intel_private.i81x_gtt_table = gtt_table; 182820647b9SDaniel Vetter 183820647b9SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 184820647b9SDaniel Vetter reg_addr &= 0xfff80000; 185820647b9SDaniel Vetter 186820647b9SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 187820647b9SDaniel Vetter if (!intel_private.registers) 188820647b9SDaniel Vetter return -ENOMEM; 189820647b9SDaniel Vetter 190820647b9SDaniel Vetter writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 191820647b9SDaniel Vetter intel_private.registers+I810_PGETBL_CTL); 192820647b9SDaniel Vetter 193820647b9SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 194820647b9SDaniel Vetter 195820647b9SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 196820647b9SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 197820647b9SDaniel Vetter dev_info(&intel_private.pcidev->dev, 198820647b9SDaniel Vetter "detected 4MB dedicated video ram\n"); 199820647b9SDaniel Vetter intel_private.num_dcache_entries = 1024; 200820647b9SDaniel Vetter } 201820647b9SDaniel Vetter 202820647b9SDaniel Vetter return 0; 203820647b9SDaniel Vetter } 204820647b9SDaniel Vetter 205820647b9SDaniel Vetter static void i810_cleanup(void) 206820647b9SDaniel Vetter { 207820647b9SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 208820647b9SDaniel Vetter free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 209820647b9SDaniel Vetter } 210820647b9SDaniel Vetter 211ff26860fSDaniel Vetter static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 212f51b7662SDaniel Vetter int type) 213f51b7662SDaniel Vetter { 214f51b7662SDaniel Vetter int i; 215f51b7662SDaniel Vetter 216625dd9d3SDaniel Vetter if ((pg_start + mem->page_count) 217625dd9d3SDaniel Vetter > intel_private.num_dcache_entries) 218625dd9d3SDaniel Vetter return -EINVAL; 219f51b7662SDaniel Vetter 220625dd9d3SDaniel Vetter if (!mem->is_flushed) 221625dd9d3SDaniel Vetter global_cache_flush(); 222625dd9d3SDaniel Vetter 223625dd9d3SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 224625dd9d3SDaniel Vetter dma_addr_t addr = i << PAGE_SHIFT; 225625dd9d3SDaniel Vetter intel_private.driver->write_entry(addr, 226625dd9d3SDaniel Vetter i, type); 227f51b7662SDaniel Vetter } 228625dd9d3SDaniel Vetter readl(intel_private.gtt+i-1); 229f51b7662SDaniel Vetter 230f51b7662SDaniel Vetter return 0; 231f51b7662SDaniel Vetter } 232f51b7662SDaniel Vetter 233f51b7662SDaniel Vetter /* 234f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 235f51b7662SDaniel Vetter * pointer into hardware. 236f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 237f51b7662SDaniel Vetter */ 238f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 239f51b7662SDaniel Vetter { 240f51b7662SDaniel Vetter struct agp_memory *new; 241f51b7662SDaniel Vetter struct page *page; 242f51b7662SDaniel Vetter 243f51b7662SDaniel Vetter switch (pg_count) { 244f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 245f51b7662SDaniel Vetter break; 246f51b7662SDaniel Vetter case 4: 247f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 248f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 249f51b7662SDaniel Vetter break; 250f51b7662SDaniel Vetter default: 251f51b7662SDaniel Vetter return NULL; 252f51b7662SDaniel Vetter } 253f51b7662SDaniel Vetter 254f51b7662SDaniel Vetter if (page == NULL) 255f51b7662SDaniel Vetter return NULL; 256f51b7662SDaniel Vetter 257f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 258f51b7662SDaniel Vetter if (new == NULL) 259f51b7662SDaniel Vetter return NULL; 260f51b7662SDaniel Vetter 261f51b7662SDaniel Vetter new->pages[0] = page; 262f51b7662SDaniel Vetter if (pg_count == 4) { 263f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 264f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 265f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 266f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 267f51b7662SDaniel Vetter } 268f51b7662SDaniel Vetter new->page_count = pg_count; 269f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 270f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 271f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 272f51b7662SDaniel Vetter return new; 273f51b7662SDaniel Vetter } 274f51b7662SDaniel Vetter 275f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 276f51b7662SDaniel Vetter { 277f51b7662SDaniel Vetter agp_free_key(curr->key); 278f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 279f51b7662SDaniel Vetter if (curr->page_count == 4) 280f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 281f51b7662SDaniel Vetter else { 282f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 283f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 284f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 285f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 286f51b7662SDaniel Vetter } 287f51b7662SDaniel Vetter agp_free_page_array(curr); 288f51b7662SDaniel Vetter } 289f51b7662SDaniel Vetter kfree(curr); 290f51b7662SDaniel Vetter } 291f51b7662SDaniel Vetter 2920e87d2b0SDaniel Vetter static int intel_gtt_setup_scratch_page(void) 2930e87d2b0SDaniel Vetter { 2940e87d2b0SDaniel Vetter struct page *page; 2950e87d2b0SDaniel Vetter dma_addr_t dma_addr; 2960e87d2b0SDaniel Vetter 2970e87d2b0SDaniel Vetter page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 2980e87d2b0SDaniel Vetter if (page == NULL) 2990e87d2b0SDaniel Vetter return -ENOMEM; 3000e87d2b0SDaniel Vetter get_page(page); 3010e87d2b0SDaniel Vetter set_pages_uc(page, 1); 3020e87d2b0SDaniel Vetter 3034080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 3040e87d2b0SDaniel Vetter dma_addr = pci_map_page(intel_private.pcidev, page, 0, 3050e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 3060e87d2b0SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 3070e87d2b0SDaniel Vetter return -EINVAL; 3080e87d2b0SDaniel Vetter 3090e87d2b0SDaniel Vetter intel_private.scratch_page_dma = dma_addr; 3100e87d2b0SDaniel Vetter } else 3110e87d2b0SDaniel Vetter intel_private.scratch_page_dma = page_to_phys(page); 3120e87d2b0SDaniel Vetter 3130e87d2b0SDaniel Vetter intel_private.scratch_page = page; 3140e87d2b0SDaniel Vetter 3150e87d2b0SDaniel Vetter return 0; 3160e87d2b0SDaniel Vetter } 3170e87d2b0SDaniel Vetter 318625dd9d3SDaniel Vetter static void i810_write_entry(dma_addr_t addr, unsigned int entry, 319625dd9d3SDaniel Vetter unsigned int flags) 320625dd9d3SDaniel Vetter { 321625dd9d3SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 322625dd9d3SDaniel Vetter 323625dd9d3SDaniel Vetter switch (flags) { 324625dd9d3SDaniel Vetter case AGP_DCACHE_MEMORY: 325625dd9d3SDaniel Vetter pte_flags |= I810_PTE_LOCAL; 326625dd9d3SDaniel Vetter break; 327625dd9d3SDaniel Vetter case AGP_USER_CACHED_MEMORY: 328625dd9d3SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 329625dd9d3SDaniel Vetter break; 330625dd9d3SDaniel Vetter } 331625dd9d3SDaniel Vetter 332625dd9d3SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 333625dd9d3SDaniel Vetter } 334625dd9d3SDaniel Vetter 3357bdc9ab0SChris Wilson static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 336820647b9SDaniel Vetter {32, 8192, 3}, 337820647b9SDaniel Vetter {64, 16384, 4}, 338f51b7662SDaniel Vetter {128, 32768, 5}, 339f51b7662SDaniel Vetter {256, 65536, 6}, 340f51b7662SDaniel Vetter {512, 131072, 7}, 341f51b7662SDaniel Vetter }; 342f51b7662SDaniel Vetter 343c64f7ba5SChris Wilson static unsigned int intel_gtt_stolen_size(void) 344f51b7662SDaniel Vetter { 345f51b7662SDaniel Vetter u16 gmch_ctrl; 346f51b7662SDaniel Vetter u8 rdct; 347f51b7662SDaniel Vetter int local = 0; 348f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 349d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 350f51b7662SDaniel Vetter 351820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) 352820647b9SDaniel Vetter return 0; /* no stolen mem on i81x */ 353820647b9SDaniel Vetter 354d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 355d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 356f51b7662SDaniel Vetter 357d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 358d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 359f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 360f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 361d8d9abcdSDaniel Vetter stolen_size = KB(512); 362f51b7662SDaniel Vetter break; 363f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 364d8d9abcdSDaniel Vetter stolen_size = MB(1); 365f51b7662SDaniel Vetter break; 366f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 367d8d9abcdSDaniel Vetter stolen_size = MB(8); 368f51b7662SDaniel Vetter break; 369f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 370f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 371d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 372f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 373f51b7662SDaniel Vetter local = 1; 374f51b7662SDaniel Vetter break; 375f51b7662SDaniel Vetter default: 376d8d9abcdSDaniel Vetter stolen_size = 0; 377f51b7662SDaniel Vetter break; 378f51b7662SDaniel Vetter } 3791a997ff2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 380f51b7662SDaniel Vetter /* 381f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 382f51b7662SDaniel Vetter */ 383f51b7662SDaniel Vetter u16 snb_gmch_ctl; 384f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 385f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 386f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 387d8d9abcdSDaniel Vetter stolen_size = MB(32); 388f51b7662SDaniel Vetter break; 389f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 390d8d9abcdSDaniel Vetter stolen_size = MB(64); 391f51b7662SDaniel Vetter break; 392f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 393d8d9abcdSDaniel Vetter stolen_size = MB(96); 394f51b7662SDaniel Vetter break; 395f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 396d8d9abcdSDaniel Vetter stolen_size = MB(128); 397f51b7662SDaniel Vetter break; 398f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 399d8d9abcdSDaniel Vetter stolen_size = MB(160); 400f51b7662SDaniel Vetter break; 401f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 402d8d9abcdSDaniel Vetter stolen_size = MB(192); 403f51b7662SDaniel Vetter break; 404f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 405d8d9abcdSDaniel Vetter stolen_size = MB(224); 406f51b7662SDaniel Vetter break; 407f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 408d8d9abcdSDaniel Vetter stolen_size = MB(256); 409f51b7662SDaniel Vetter break; 410f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 411d8d9abcdSDaniel Vetter stolen_size = MB(288); 412f51b7662SDaniel Vetter break; 413f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 414d8d9abcdSDaniel Vetter stolen_size = MB(320); 415f51b7662SDaniel Vetter break; 416f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 417d8d9abcdSDaniel Vetter stolen_size = MB(352); 418f51b7662SDaniel Vetter break; 419f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 420d8d9abcdSDaniel Vetter stolen_size = MB(384); 421f51b7662SDaniel Vetter break; 422f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 423d8d9abcdSDaniel Vetter stolen_size = MB(416); 424f51b7662SDaniel Vetter break; 425f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 426d8d9abcdSDaniel Vetter stolen_size = MB(448); 427f51b7662SDaniel Vetter break; 428f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 429d8d9abcdSDaniel Vetter stolen_size = MB(480); 430f51b7662SDaniel Vetter break; 431f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 432d8d9abcdSDaniel Vetter stolen_size = MB(512); 433f51b7662SDaniel Vetter break; 434f51b7662SDaniel Vetter } 435f51b7662SDaniel Vetter } else { 436f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 437f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 438d8d9abcdSDaniel Vetter stolen_size = MB(1); 439f51b7662SDaniel Vetter break; 440f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 441d8d9abcdSDaniel Vetter stolen_size = MB(4); 442f51b7662SDaniel Vetter break; 443f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 444d8d9abcdSDaniel Vetter stolen_size = MB(8); 445f51b7662SDaniel Vetter break; 446f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 447d8d9abcdSDaniel Vetter stolen_size = MB(16); 448f51b7662SDaniel Vetter break; 449f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 450d8d9abcdSDaniel Vetter stolen_size = MB(32); 451f51b7662SDaniel Vetter break; 452f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 453d8d9abcdSDaniel Vetter stolen_size = MB(48); 454f51b7662SDaniel Vetter break; 455f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 456d8d9abcdSDaniel Vetter stolen_size = MB(64); 457f51b7662SDaniel Vetter break; 458f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 459d8d9abcdSDaniel Vetter stolen_size = MB(128); 460f51b7662SDaniel Vetter break; 461f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 462d8d9abcdSDaniel Vetter stolen_size = MB(256); 463f51b7662SDaniel Vetter break; 464f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 465d8d9abcdSDaniel Vetter stolen_size = MB(96); 466f51b7662SDaniel Vetter break; 467f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 468d8d9abcdSDaniel Vetter stolen_size = MB(160); 469f51b7662SDaniel Vetter break; 470f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 471d8d9abcdSDaniel Vetter stolen_size = MB(224); 472f51b7662SDaniel Vetter break; 473f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 474d8d9abcdSDaniel Vetter stolen_size = MB(352); 475f51b7662SDaniel Vetter break; 476f51b7662SDaniel Vetter default: 477d8d9abcdSDaniel Vetter stolen_size = 0; 478f51b7662SDaniel Vetter break; 479f51b7662SDaniel Vetter } 480f51b7662SDaniel Vetter } 4811784a5fbSDaniel Vetter 4821b6064d7SChris Wilson if (stolen_size > 0) { 483d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 484d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 485f51b7662SDaniel Vetter } else { 486d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 487f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 488d8d9abcdSDaniel Vetter stolen_size = 0; 489f51b7662SDaniel Vetter } 490f51b7662SDaniel Vetter 491c64f7ba5SChris Wilson return stolen_size; 492f51b7662SDaniel Vetter } 493f51b7662SDaniel Vetter 49420172842SDaniel Vetter static void i965_adjust_pgetbl_size(unsigned int size_flag) 49520172842SDaniel Vetter { 49620172842SDaniel Vetter u32 pgetbl_ctl, pgetbl_ctl2; 49720172842SDaniel Vetter 49820172842SDaniel Vetter /* ensure that ppgtt is disabled */ 49920172842SDaniel Vetter pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 50020172842SDaniel Vetter pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 50120172842SDaniel Vetter writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 50220172842SDaniel Vetter 50320172842SDaniel Vetter /* write the new ggtt size */ 50420172842SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 50520172842SDaniel Vetter pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 50620172842SDaniel Vetter pgetbl_ctl |= size_flag; 50720172842SDaniel Vetter writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 50820172842SDaniel Vetter } 50920172842SDaniel Vetter 51020172842SDaniel Vetter static unsigned int i965_gtt_total_entries(void) 511fbe40783SDaniel Vetter { 512fbe40783SDaniel Vetter int size; 513fbe40783SDaniel Vetter u32 pgetbl_ctl; 51420172842SDaniel Vetter u16 gmch_ctl; 51520172842SDaniel Vetter 51620172842SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 51720172842SDaniel Vetter I830_GMCH_CTRL, &gmch_ctl); 51820172842SDaniel Vetter 51920172842SDaniel Vetter if (INTEL_GTT_GEN == 5) { 52020172842SDaniel Vetter switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 52120172842SDaniel Vetter case G4x_GMCH_SIZE_1M: 52220172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1M: 52320172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 52420172842SDaniel Vetter break; 52520172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1_5M: 52620172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 52720172842SDaniel Vetter break; 52820172842SDaniel Vetter case G4x_GMCH_SIZE_2M: 52920172842SDaniel Vetter case G4x_GMCH_SIZE_VT_2M: 53020172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 53120172842SDaniel Vetter break; 53220172842SDaniel Vetter } 53320172842SDaniel Vetter } 53420172842SDaniel Vetter 535fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 536fbe40783SDaniel Vetter 537fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 538fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 539e5e408fcSDaniel Vetter size = KB(128); 540fbe40783SDaniel Vetter break; 541fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 542e5e408fcSDaniel Vetter size = KB(256); 543fbe40783SDaniel Vetter break; 544fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 545e5e408fcSDaniel Vetter size = KB(512); 546fbe40783SDaniel Vetter break; 54720172842SDaniel Vetter /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 548fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 549e5e408fcSDaniel Vetter size = KB(1024); 550fbe40783SDaniel Vetter break; 551fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 552e5e408fcSDaniel Vetter size = KB(2048); 553fbe40783SDaniel Vetter break; 554fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 555e5e408fcSDaniel Vetter size = KB(1024 + 512); 556fbe40783SDaniel Vetter break; 557fbe40783SDaniel Vetter default: 558fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 559fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 560e5e408fcSDaniel Vetter size = KB(512); 561fbe40783SDaniel Vetter } 562e5e408fcSDaniel Vetter 563e5e408fcSDaniel Vetter return size/4; 56420172842SDaniel Vetter } 56520172842SDaniel Vetter 56620172842SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 56720172842SDaniel Vetter { 56820172842SDaniel Vetter int size; 56920172842SDaniel Vetter 57020172842SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 57120172842SDaniel Vetter return i965_gtt_total_entries(); 57220172842SDaniel Vetter else if (INTEL_GTT_GEN == 6) { 573210b23c2SDaniel Vetter u16 snb_gmch_ctl; 574210b23c2SDaniel Vetter 575210b23c2SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 576210b23c2SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 577210b23c2SDaniel Vetter default: 578210b23c2SDaniel Vetter case SNB_GTT_SIZE_0M: 579210b23c2SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 580210b23c2SDaniel Vetter size = MB(0); 581210b23c2SDaniel Vetter break; 582210b23c2SDaniel Vetter case SNB_GTT_SIZE_1M: 583210b23c2SDaniel Vetter size = MB(1); 584210b23c2SDaniel Vetter break; 585210b23c2SDaniel Vetter case SNB_GTT_SIZE_2M: 586210b23c2SDaniel Vetter size = MB(2); 587210b23c2SDaniel Vetter break; 588210b23c2SDaniel Vetter } 589210b23c2SDaniel Vetter return size/4; 590fbe40783SDaniel Vetter } else { 591fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 592fbe40783SDaniel Vetter * required to map the aperture. 593fbe40783SDaniel Vetter */ 594e5e408fcSDaniel Vetter return intel_private.base.gtt_mappable_entries; 595fbe40783SDaniel Vetter } 596fbe40783SDaniel Vetter } 597fbe40783SDaniel Vetter 5981784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 5991784a5fbSDaniel Vetter { 6001784a5fbSDaniel Vetter unsigned int aperture_size; 6011784a5fbSDaniel Vetter 602820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) { 603820647b9SDaniel Vetter u32 smram_miscc; 604820647b9SDaniel Vetter 605820647b9SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 606820647b9SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 607820647b9SDaniel Vetter 608820647b9SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 609820647b9SDaniel Vetter == I810_GFX_MEM_WIN_32M) 610820647b9SDaniel Vetter aperture_size = MB(32); 611820647b9SDaniel Vetter else 612820647b9SDaniel Vetter aperture_size = MB(64); 613820647b9SDaniel Vetter } else if (INTEL_GTT_GEN == 2) { 614b1c5b0f8SChris Wilson u16 gmch_ctrl; 6151784a5fbSDaniel Vetter 6161784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 6171784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 6181784a5fbSDaniel Vetter 6191784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 620b1c5b0f8SChris Wilson aperture_size = MB(64); 6211784a5fbSDaniel Vetter else 622b1c5b0f8SChris Wilson aperture_size = MB(128); 623239918f7SDaniel Vetter } else { 6241784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 6251784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 6261784a5fbSDaniel Vetter } 6271784a5fbSDaniel Vetter 6281784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 6291784a5fbSDaniel Vetter } 6301784a5fbSDaniel Vetter 6310e87d2b0SDaniel Vetter static void intel_gtt_teardown_scratch_page(void) 6320e87d2b0SDaniel Vetter { 6330e87d2b0SDaniel Vetter set_pages_wb(intel_private.scratch_page, 1); 6340e87d2b0SDaniel Vetter pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 6350e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 6360e87d2b0SDaniel Vetter put_page(intel_private.scratch_page); 6370e87d2b0SDaniel Vetter __free_page(intel_private.scratch_page); 6380e87d2b0SDaniel Vetter } 6390e87d2b0SDaniel Vetter 6400e87d2b0SDaniel Vetter static void intel_gtt_cleanup(void) 6410e87d2b0SDaniel Vetter { 642ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 643ae83dd5cSDaniel Vetter 6440e87d2b0SDaniel Vetter iounmap(intel_private.gtt); 6450e87d2b0SDaniel Vetter iounmap(intel_private.registers); 6460e87d2b0SDaniel Vetter 6470e87d2b0SDaniel Vetter intel_gtt_teardown_scratch_page(); 6480e87d2b0SDaniel Vetter } 6490e87d2b0SDaniel Vetter 6501784a5fbSDaniel Vetter static int intel_gtt_init(void) 6511784a5fbSDaniel Vetter { 652f67eab66SDaniel Vetter u32 gtt_map_size; 6533b15a9d7SDaniel Vetter int ret; 6543b15a9d7SDaniel Vetter 6553b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 6563b15a9d7SDaniel Vetter if (ret != 0) 6573b15a9d7SDaniel Vetter return ret; 658f67eab66SDaniel Vetter 659f67eab66SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 660f67eab66SDaniel Vetter intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 661f67eab66SDaniel Vetter 662b3eafc5aSDaniel Vetter /* save the PGETBL reg for resume */ 663b3eafc5aSDaniel Vetter intel_private.PGETBL_save = 664b3eafc5aSDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL) 665b3eafc5aSDaniel Vetter & ~I810_PGETBL_ENABLED; 666100519e2SChris Wilson /* we only ever restore the register when enabling the PGTBL... */ 667100519e2SChris Wilson if (HAS_PGTBL_EN) 668100519e2SChris Wilson intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 669b3eafc5aSDaniel Vetter 6700af9e92eSDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 6710af9e92eSDaniel Vetter "detected gtt size: %dK total, %dK mappable\n", 6720af9e92eSDaniel Vetter intel_private.base.gtt_total_entries * 4, 6730af9e92eSDaniel Vetter intel_private.base.gtt_mappable_entries * 4); 6740af9e92eSDaniel Vetter 675f67eab66SDaniel Vetter gtt_map_size = intel_private.base.gtt_total_entries * 4; 676f67eab66SDaniel Vetter 677f67eab66SDaniel Vetter intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 678f67eab66SDaniel Vetter gtt_map_size); 679f67eab66SDaniel Vetter if (!intel_private.gtt) { 680ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 681f67eab66SDaniel Vetter iounmap(intel_private.registers); 682f67eab66SDaniel Vetter return -ENOMEM; 683f67eab66SDaniel Vetter } 684f67eab66SDaniel Vetter 685f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 686f67eab66SDaniel Vetter 687c64f7ba5SChris Wilson intel_private.base.stolen_size = intel_gtt_stolen_size(); 6881784a5fbSDaniel Vetter 689a46f3108SDave Airlie intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 690a46f3108SDave Airlie 6910e87d2b0SDaniel Vetter ret = intel_gtt_setup_scratch_page(); 6920e87d2b0SDaniel Vetter if (ret != 0) { 6930e87d2b0SDaniel Vetter intel_gtt_cleanup(); 6940e87d2b0SDaniel Vetter return ret; 6950e87d2b0SDaniel Vetter } 6960e87d2b0SDaniel Vetter 6971784a5fbSDaniel Vetter return 0; 6981784a5fbSDaniel Vetter } 6991784a5fbSDaniel Vetter 7003e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 7013e921f98SDaniel Vetter { 7029e76e7b8SChris Wilson int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 7033e921f98SDaniel Vetter unsigned int aper_size; 7043e921f98SDaniel Vetter int i; 7053e921f98SDaniel Vetter 7063e921f98SDaniel Vetter aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 7073e921f98SDaniel Vetter / MB(1); 7083e921f98SDaniel Vetter 7093e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 710ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 7119e76e7b8SChris Wilson agp_bridge->current_size = 7129e76e7b8SChris Wilson (void *) (intel_fake_agp_sizes + i); 7133e921f98SDaniel Vetter return aper_size; 7143e921f98SDaniel Vetter } 7153e921f98SDaniel Vetter } 7163e921f98SDaniel Vetter 7173e921f98SDaniel Vetter return 0; 7183e921f98SDaniel Vetter } 7193e921f98SDaniel Vetter 720ae83dd5cSDaniel Vetter static void i830_cleanup(void) 721f51b7662SDaniel Vetter { 722f51b7662SDaniel Vetter } 723f51b7662SDaniel Vetter 724f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 725f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 726f51b7662SDaniel Vetter * doesn't snoop those buffers. 727f51b7662SDaniel Vetter * 728f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 729f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 730f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 731f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 732f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 733f51b7662SDaniel Vetter */ 7341b263f24SDaniel Vetter static void i830_chipset_flush(void) 735f51b7662SDaniel Vetter { 736bdb8b975SChris Wilson unsigned long timeout = jiffies + msecs_to_jiffies(1000); 737f51b7662SDaniel Vetter 738bdb8b975SChris Wilson /* Forcibly evict everything from the CPU write buffers. 739bdb8b975SChris Wilson * clflush appears to be insufficient. 740bdb8b975SChris Wilson */ 741bdb8b975SChris Wilson wbinvd_on_all_cpus(); 742f51b7662SDaniel Vetter 743bdb8b975SChris Wilson /* Now we've only seen documents for this magic bit on 855GM, 744bdb8b975SChris Wilson * we hope it exists for the other gen2 chipsets... 745bdb8b975SChris Wilson * 746bdb8b975SChris Wilson * Also works as advertised on my 845G. 747bdb8b975SChris Wilson */ 748bdb8b975SChris Wilson writel(readl(intel_private.registers+I830_HIC) | (1<<31), 749bdb8b975SChris Wilson intel_private.registers+I830_HIC); 750bdb8b975SChris Wilson 751bdb8b975SChris Wilson while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 752bdb8b975SChris Wilson if (time_after(jiffies, timeout)) 753bdb8b975SChris Wilson break; 754bdb8b975SChris Wilson 755bdb8b975SChris Wilson udelay(50); 756bdb8b975SChris Wilson } 757f51b7662SDaniel Vetter } 758f51b7662SDaniel Vetter 759351bb278SDaniel Vetter static void i830_write_entry(dma_addr_t addr, unsigned int entry, 760351bb278SDaniel Vetter unsigned int flags) 761351bb278SDaniel Vetter { 762351bb278SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 763351bb278SDaniel Vetter 764b47cf66fSDaniel Vetter if (flags == AGP_USER_CACHED_MEMORY) 765351bb278SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 766351bb278SDaniel Vetter 767351bb278SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 768351bb278SDaniel Vetter } 769351bb278SDaniel Vetter 770e380f60bSChris Wilson static bool intel_enable_gtt(void) 77173800422SDaniel Vetter { 7723f08e4efSChris Wilson u32 gma_addr; 773e380f60bSChris Wilson u8 __iomem *reg; 77473800422SDaniel Vetter 775820647b9SDaniel Vetter if (INTEL_GTT_GEN <= 2) 7762d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 7772d2430cfSDaniel Vetter &gma_addr); 7782d2430cfSDaniel Vetter else 7792d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 7802d2430cfSDaniel Vetter &gma_addr); 7812d2430cfSDaniel Vetter 78273800422SDaniel Vetter intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 78373800422SDaniel Vetter 784e380f60bSChris Wilson if (INTEL_GTT_GEN >= 6) 785e380f60bSChris Wilson return true; 78673800422SDaniel Vetter 787100519e2SChris Wilson if (INTEL_GTT_GEN == 2) { 788100519e2SChris Wilson u16 gmch_ctrl; 789100519e2SChris Wilson 790e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 791e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 792e380f60bSChris Wilson gmch_ctrl |= I830_GMCH_ENABLED; 793e380f60bSChris Wilson pci_write_config_word(intel_private.bridge_dev, 794e380f60bSChris Wilson I830_GMCH_CTRL, gmch_ctrl); 795e380f60bSChris Wilson 796e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 797e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 798e380f60bSChris Wilson if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 799e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 800e380f60bSChris Wilson "failed to enable the GTT: GMCH_CTRL=%x\n", 801e380f60bSChris Wilson gmch_ctrl); 802e380f60bSChris Wilson return false; 803e380f60bSChris Wilson } 804100519e2SChris Wilson } 805e380f60bSChris Wilson 806c97689d8SChris Wilson /* On the resume path we may be adjusting the PGTBL value, so 807c97689d8SChris Wilson * be paranoid and flush all chipset write buffers... 808c97689d8SChris Wilson */ 809c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 810c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 811c97689d8SChris Wilson 812e380f60bSChris Wilson reg = intel_private.registers+I810_PGETBL_CTL; 813100519e2SChris Wilson writel(intel_private.PGETBL_save, reg); 814100519e2SChris Wilson if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 815e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 816100519e2SChris Wilson "failed to enable the GTT: PGETBL=%x [expected %x]\n", 817e380f60bSChris Wilson readl(reg), intel_private.PGETBL_save); 818e380f60bSChris Wilson return false; 819e380f60bSChris Wilson } 820e380f60bSChris Wilson 821c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 822c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 823c97689d8SChris Wilson 824e380f60bSChris Wilson return true; 82573800422SDaniel Vetter } 82673800422SDaniel Vetter 82773800422SDaniel Vetter static int i830_setup(void) 82873800422SDaniel Vetter { 82973800422SDaniel Vetter u32 reg_addr; 83073800422SDaniel Vetter 83173800422SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 83273800422SDaniel Vetter reg_addr &= 0xfff80000; 83373800422SDaniel Vetter 83473800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 83573800422SDaniel Vetter if (!intel_private.registers) 83673800422SDaniel Vetter return -ENOMEM; 83773800422SDaniel Vetter 83873800422SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 83973800422SDaniel Vetter 84073800422SDaniel Vetter return 0; 84173800422SDaniel Vetter } 84273800422SDaniel Vetter 8433b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 844f51b7662SDaniel Vetter { 84573800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 846f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 84773800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 848f51b7662SDaniel Vetter 849f51b7662SDaniel Vetter return 0; 850f51b7662SDaniel Vetter } 851f51b7662SDaniel Vetter 852ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 853f51b7662SDaniel Vetter { 854f51b7662SDaniel Vetter return 0; 855f51b7662SDaniel Vetter } 856f51b7662SDaniel Vetter 857351bb278SDaniel Vetter static int intel_fake_agp_configure(void) 858f51b7662SDaniel Vetter { 859e380f60bSChris Wilson if (!intel_enable_gtt()) 860e380f60bSChris Wilson return -EIO; 861f51b7662SDaniel Vetter 862bee4a186SChris Wilson intel_private.clear_fake_agp = true; 86373800422SDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 864f51b7662SDaniel Vetter 865f51b7662SDaniel Vetter return 0; 866f51b7662SDaniel Vetter } 867f51b7662SDaniel Vetter 8685cbecafcSDaniel Vetter static bool i830_check_flags(unsigned int flags) 869f51b7662SDaniel Vetter { 8705cbecafcSDaniel Vetter switch (flags) { 8715cbecafcSDaniel Vetter case 0: 8725cbecafcSDaniel Vetter case AGP_PHYS_MEMORY: 8735cbecafcSDaniel Vetter case AGP_USER_CACHED_MEMORY: 8745cbecafcSDaniel Vetter case AGP_USER_MEMORY: 8755cbecafcSDaniel Vetter return true; 8765cbecafcSDaniel Vetter } 8775cbecafcSDaniel Vetter 8785cbecafcSDaniel Vetter return false; 8795cbecafcSDaniel Vetter } 8805cbecafcSDaniel Vetter 8814080775bSDaniel Vetter void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 882fefaa70fSDaniel Vetter unsigned int sg_len, 883fefaa70fSDaniel Vetter unsigned int pg_start, 884fefaa70fSDaniel Vetter unsigned int flags) 885fefaa70fSDaniel Vetter { 886fefaa70fSDaniel Vetter struct scatterlist *sg; 887fefaa70fSDaniel Vetter unsigned int len, m; 888fefaa70fSDaniel Vetter int i, j; 889fefaa70fSDaniel Vetter 890fefaa70fSDaniel Vetter j = pg_start; 891fefaa70fSDaniel Vetter 892fefaa70fSDaniel Vetter /* sg may merge pages, but we have to separate 893fefaa70fSDaniel Vetter * per-page addr for GTT */ 894fefaa70fSDaniel Vetter for_each_sg(sg_list, sg, sg_len, i) { 895fefaa70fSDaniel Vetter len = sg_dma_len(sg) >> PAGE_SHIFT; 896fefaa70fSDaniel Vetter for (m = 0; m < len; m++) { 897fefaa70fSDaniel Vetter dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 898fefaa70fSDaniel Vetter intel_private.driver->write_entry(addr, 899fefaa70fSDaniel Vetter j, flags); 900fefaa70fSDaniel Vetter j++; 901fefaa70fSDaniel Vetter } 902fefaa70fSDaniel Vetter } 903fefaa70fSDaniel Vetter readl(intel_private.gtt+j-1); 904fefaa70fSDaniel Vetter } 9054080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 9064080775bSDaniel Vetter 9074080775bSDaniel Vetter void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 9084080775bSDaniel Vetter struct page **pages, unsigned int flags) 9094080775bSDaniel Vetter { 9104080775bSDaniel Vetter int i, j; 9114080775bSDaniel Vetter 9124080775bSDaniel Vetter for (i = 0, j = first_entry; i < num_entries; i++, j++) { 9134080775bSDaniel Vetter dma_addr_t addr = page_to_phys(pages[i]); 9144080775bSDaniel Vetter intel_private.driver->write_entry(addr, 9154080775bSDaniel Vetter j, flags); 9164080775bSDaniel Vetter } 9174080775bSDaniel Vetter readl(intel_private.gtt+j-1); 9184080775bSDaniel Vetter } 9194080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_insert_pages); 920fefaa70fSDaniel Vetter 9215cbecafcSDaniel Vetter static int intel_fake_agp_insert_entries(struct agp_memory *mem, 9225cbecafcSDaniel Vetter off_t pg_start, int type) 9235cbecafcSDaniel Vetter { 924f51b7662SDaniel Vetter int ret = -EINVAL; 925f51b7662SDaniel Vetter 926bee4a186SChris Wilson if (intel_private.clear_fake_agp) { 927bee4a186SChris Wilson int start = intel_private.base.stolen_size / PAGE_SIZE; 928bee4a186SChris Wilson int end = intel_private.base.gtt_mappable_entries; 929bee4a186SChris Wilson intel_gtt_clear_range(start, end - start); 930bee4a186SChris Wilson intel_private.clear_fake_agp = false; 931bee4a186SChris Wilson } 932bee4a186SChris Wilson 933ff26860fSDaniel Vetter if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 934ff26860fSDaniel Vetter return i810_insert_dcache_entries(mem, pg_start, type); 935ff26860fSDaniel Vetter 936f51b7662SDaniel Vetter if (mem->page_count == 0) 937f51b7662SDaniel Vetter goto out; 938f51b7662SDaniel Vetter 939c64f7ba5SChris Wilson if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) 940f51b7662SDaniel Vetter goto out_err; 941f51b7662SDaniel Vetter 942f51b7662SDaniel Vetter if (type != mem->type) 943f51b7662SDaniel Vetter goto out_err; 944f51b7662SDaniel Vetter 9455cbecafcSDaniel Vetter if (!intel_private.driver->check_flags(type)) 946f51b7662SDaniel Vetter goto out_err; 947f51b7662SDaniel Vetter 948f51b7662SDaniel Vetter if (!mem->is_flushed) 949f51b7662SDaniel Vetter global_cache_flush(); 950f51b7662SDaniel Vetter 9514080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 9524080775bSDaniel Vetter ret = intel_gtt_map_memory(mem->pages, mem->page_count, 9534080775bSDaniel Vetter &mem->sg_list, &mem->num_sg); 954fefaa70fSDaniel Vetter if (ret != 0) 955fefaa70fSDaniel Vetter return ret; 956fefaa70fSDaniel Vetter 957fefaa70fSDaniel Vetter intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, 958fefaa70fSDaniel Vetter pg_start, type); 9594080775bSDaniel Vetter } else 9604080775bSDaniel Vetter intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 9614080775bSDaniel Vetter type); 962f51b7662SDaniel Vetter 963f51b7662SDaniel Vetter out: 964f51b7662SDaniel Vetter ret = 0; 965f51b7662SDaniel Vetter out_err: 966f51b7662SDaniel Vetter mem->is_flushed = true; 967f51b7662SDaniel Vetter return ret; 968f51b7662SDaniel Vetter } 969f51b7662SDaniel Vetter 9704080775bSDaniel Vetter void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 971f51b7662SDaniel Vetter { 9724080775bSDaniel Vetter unsigned int i; 973f51b7662SDaniel Vetter 9744080775bSDaniel Vetter for (i = first_entry; i < (first_entry + num_entries); i++) { 9755cbecafcSDaniel Vetter intel_private.driver->write_entry(intel_private.scratch_page_dma, 9765cbecafcSDaniel Vetter i, 0); 977f51b7662SDaniel Vetter } 978fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 9794080775bSDaniel Vetter } 9804080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_clear_range); 9814080775bSDaniel Vetter 9824080775bSDaniel Vetter static int intel_fake_agp_remove_entries(struct agp_memory *mem, 9834080775bSDaniel Vetter off_t pg_start, int type) 9844080775bSDaniel Vetter { 9854080775bSDaniel Vetter if (mem->page_count == 0) 9864080775bSDaniel Vetter return 0; 9874080775bSDaniel Vetter 988d15eda5cSDave Airlie intel_gtt_clear_range(pg_start, mem->page_count); 989d15eda5cSDave Airlie 9904080775bSDaniel Vetter if (intel_private.base.needs_dmar) { 9914080775bSDaniel Vetter intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 9924080775bSDaniel Vetter mem->sg_list = NULL; 9934080775bSDaniel Vetter mem->num_sg = 0; 9944080775bSDaniel Vetter } 9954080775bSDaniel Vetter 996f51b7662SDaniel Vetter return 0; 997f51b7662SDaniel Vetter } 998f51b7662SDaniel Vetter 999ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1000ffdd7510SDaniel Vetter int type) 1001f51b7662SDaniel Vetter { 1002625dd9d3SDaniel Vetter struct agp_memory *new; 1003625dd9d3SDaniel Vetter 1004625dd9d3SDaniel Vetter if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 1005625dd9d3SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 1006625dd9d3SDaniel Vetter return NULL; 1007625dd9d3SDaniel Vetter 1008625dd9d3SDaniel Vetter new = agp_create_memory(1); 1009625dd9d3SDaniel Vetter if (new == NULL) 1010625dd9d3SDaniel Vetter return NULL; 1011625dd9d3SDaniel Vetter 1012625dd9d3SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 1013625dd9d3SDaniel Vetter new->page_count = pg_count; 1014625dd9d3SDaniel Vetter new->num_scratch_pages = 0; 1015625dd9d3SDaniel Vetter agp_free_page_array(new); 1016625dd9d3SDaniel Vetter return new; 1017625dd9d3SDaniel Vetter } 1018f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 1019f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 1020f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 1021f51b7662SDaniel Vetter return NULL; 1022f51b7662SDaniel Vetter } 1023f51b7662SDaniel Vetter 1024f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 1025f51b7662SDaniel Vetter { 1026f51b7662SDaniel Vetter int ret; 1027d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1028f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1029d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 1030f51b7662SDaniel Vetter 1031f51b7662SDaniel Vetter return ret; 1032f51b7662SDaniel Vetter } 1033f51b7662SDaniel Vetter 1034f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 1035f51b7662SDaniel Vetter { 1036f51b7662SDaniel Vetter int ret; 1037f51b7662SDaniel Vetter u32 temp; 1038f51b7662SDaniel Vetter 1039d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1040f51b7662SDaniel Vetter if (!(temp & 0x1)) { 1041f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1042f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1043d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1044f51b7662SDaniel Vetter } else { 1045f51b7662SDaniel Vetter temp &= ~1; 1046f51b7662SDaniel Vetter 1047f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1048f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1049f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1050f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1051f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1052f51b7662SDaniel Vetter if (ret) 1053f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1054f51b7662SDaniel Vetter } 1055f51b7662SDaniel Vetter } 1056f51b7662SDaniel Vetter 1057f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1058f51b7662SDaniel Vetter { 1059f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1060f51b7662SDaniel Vetter int ret; 1061f51b7662SDaniel Vetter 1062d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1063d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1064f51b7662SDaniel Vetter 1065f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1066f51b7662SDaniel Vetter 1067f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1068f51b7662SDaniel Vetter 1069f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1070d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1071f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1072d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1073f51b7662SDaniel Vetter } else { 1074f51b7662SDaniel Vetter u64 l64; 1075f51b7662SDaniel Vetter 1076f51b7662SDaniel Vetter temp_lo &= ~0x1; 1077f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1078f51b7662SDaniel Vetter 1079f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1080f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1081f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1082f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1083f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1084f51b7662SDaniel Vetter if (ret) 1085f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1086f51b7662SDaniel Vetter } 1087f51b7662SDaniel Vetter } 1088f51b7662SDaniel Vetter 1089f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1090f51b7662SDaniel Vetter { 1091f51b7662SDaniel Vetter /* return if already configured */ 1092f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1093f51b7662SDaniel Vetter return; 1094f51b7662SDaniel Vetter 10951a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1096f51b7662SDaniel Vetter return; 1097f51b7662SDaniel Vetter 1098f51b7662SDaniel Vetter /* setup a resource for this object */ 1099f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1100f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1101f51b7662SDaniel Vetter 1102f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 11031a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1104f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1105f51b7662SDaniel Vetter } else { 1106f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1107f51b7662SDaniel Vetter } 1108f51b7662SDaniel Vetter 1109df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1110f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1111f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1112df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1113df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1114f51b7662SDaniel Vetter } 1115f51b7662SDaniel Vetter 1116ae83dd5cSDaniel Vetter static void i9xx_cleanup(void) 1117ae83dd5cSDaniel Vetter { 1118ae83dd5cSDaniel Vetter if (intel_private.i9xx_flush_page) 1119ae83dd5cSDaniel Vetter iounmap(intel_private.i9xx_flush_page); 1120ae83dd5cSDaniel Vetter if (intel_private.resource_valid) 1121ae83dd5cSDaniel Vetter release_resource(&intel_private.ifp_resource); 1122ae83dd5cSDaniel Vetter intel_private.ifp_resource.start = 0; 1123ae83dd5cSDaniel Vetter intel_private.resource_valid = 0; 1124ae83dd5cSDaniel Vetter } 1125ae83dd5cSDaniel Vetter 11261b263f24SDaniel Vetter static void i9xx_chipset_flush(void) 1127f51b7662SDaniel Vetter { 1128f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1129f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1130f51b7662SDaniel Vetter } 1131f51b7662SDaniel Vetter 113271f45660SChris Wilson static void i965_write_entry(dma_addr_t addr, 113371f45660SChris Wilson unsigned int entry, 1134a6963596SDaniel Vetter unsigned int flags) 1135a6963596SDaniel Vetter { 113671f45660SChris Wilson u32 pte_flags; 113771f45660SChris Wilson 113871f45660SChris Wilson pte_flags = I810_PTE_VALID; 113971f45660SChris Wilson if (flags == AGP_USER_CACHED_MEMORY) 114071f45660SChris Wilson pte_flags |= I830_PTE_SYSTEM_CACHED; 114171f45660SChris Wilson 1142a6963596SDaniel Vetter /* Shift high bits down */ 1143a6963596SDaniel Vetter addr |= (addr >> 28) & 0xf0; 114471f45660SChris Wilson writel(addr | pte_flags, intel_private.gtt + entry); 1145a6963596SDaniel Vetter } 1146a6963596SDaniel Vetter 114790cb149eSDaniel Vetter static bool gen6_check_flags(unsigned int flags) 114890cb149eSDaniel Vetter { 114990cb149eSDaniel Vetter return true; 115090cb149eSDaniel Vetter } 115190cb149eSDaniel Vetter 115297ef1bddSDaniel Vetter static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 115397ef1bddSDaniel Vetter unsigned int flags) 115497ef1bddSDaniel Vetter { 115597ef1bddSDaniel Vetter unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 115697ef1bddSDaniel Vetter unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 115797ef1bddSDaniel Vetter u32 pte_flags; 115897ef1bddSDaniel Vetter 1159897ef192SZhenyu Wang if (type_mask == AGP_USER_MEMORY) 116085ccc35bSChris Wilson pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; 116197ef1bddSDaniel Vetter else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1162d1108525SZhenyu Wang pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; 116397ef1bddSDaniel Vetter if (gfdt) 116497ef1bddSDaniel Vetter pte_flags |= GEN6_PTE_GFDT; 116597ef1bddSDaniel Vetter } else { /* set 'normal'/'cached' to LLC by default */ 1166d1108525SZhenyu Wang pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 116797ef1bddSDaniel Vetter if (gfdt) 116897ef1bddSDaniel Vetter pte_flags |= GEN6_PTE_GFDT; 116997ef1bddSDaniel Vetter } 117097ef1bddSDaniel Vetter 117197ef1bddSDaniel Vetter /* gen6 has bit11-4 for physical addr bit39-32 */ 117297ef1bddSDaniel Vetter addr |= (addr >> 28) & 0xff0; 117397ef1bddSDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 117497ef1bddSDaniel Vetter } 117597ef1bddSDaniel Vetter 1176ae83dd5cSDaniel Vetter static void gen6_cleanup(void) 1177ae83dd5cSDaniel Vetter { 1178ae83dd5cSDaniel Vetter } 1179ae83dd5cSDaniel Vetter 11802d2430cfSDaniel Vetter static int i9xx_setup(void) 11812d2430cfSDaniel Vetter { 11822d2430cfSDaniel Vetter u32 reg_addr; 11832d2430cfSDaniel Vetter 11842d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 11852d2430cfSDaniel Vetter 11862d2430cfSDaniel Vetter reg_addr &= 0xfff80000; 11872d2430cfSDaniel Vetter 11882d2430cfSDaniel Vetter intel_private.registers = ioremap(reg_addr, 128 * 4096); 11892d2430cfSDaniel Vetter if (!intel_private.registers) 11902d2430cfSDaniel Vetter return -ENOMEM; 11912d2430cfSDaniel Vetter 11922d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 3) { 11932d2430cfSDaniel Vetter u32 gtt_addr; 11943f08e4efSChris Wilson 11952d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, 11962d2430cfSDaniel Vetter I915_PTEADDR, >t_addr); 11972d2430cfSDaniel Vetter intel_private.gtt_bus_addr = gtt_addr; 11982d2430cfSDaniel Vetter } else { 11992d2430cfSDaniel Vetter u32 gtt_offset; 12002d2430cfSDaniel Vetter 12012d2430cfSDaniel Vetter switch (INTEL_GTT_GEN) { 12022d2430cfSDaniel Vetter case 5: 12032d2430cfSDaniel Vetter case 6: 12042d2430cfSDaniel Vetter gtt_offset = MB(2); 12052d2430cfSDaniel Vetter break; 12062d2430cfSDaniel Vetter case 4: 12072d2430cfSDaniel Vetter default: 12082d2430cfSDaniel Vetter gtt_offset = KB(512); 12092d2430cfSDaniel Vetter break; 12102d2430cfSDaniel Vetter } 12112d2430cfSDaniel Vetter intel_private.gtt_bus_addr = reg_addr + gtt_offset; 12122d2430cfSDaniel Vetter } 12132d2430cfSDaniel Vetter 12142d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 12152d2430cfSDaniel Vetter 12162d2430cfSDaniel Vetter return 0; 12172d2430cfSDaniel Vetter } 12182d2430cfSDaniel Vetter 1219e9b1cc81SDaniel Vetter static const struct agp_bridge_driver intel_fake_agp_driver = { 1220f51b7662SDaniel Vetter .owner = THIS_MODULE, 1221f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 12229e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 12239e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1224a6963596SDaniel Vetter .configure = intel_fake_agp_configure, 12253e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1226fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1227ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1228f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 12293b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1230ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1231450f2b3dSDaniel Vetter .insert_memory = intel_fake_agp_insert_entries, 1232450f2b3dSDaniel Vetter .remove_memory = intel_fake_agp_remove_entries, 1233ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1234f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1235f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1236f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1237f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1238f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1239f51b7662SDaniel Vetter }; 124002c026ceSDaniel Vetter 1241bdd30729SDaniel Vetter static const struct intel_gtt_driver i81x_gtt_driver = { 1242bdd30729SDaniel Vetter .gen = 1, 1243820647b9SDaniel Vetter .has_pgtbl_enable = 1, 124422533b49SDaniel Vetter .dma_mask_size = 32, 1245820647b9SDaniel Vetter .setup = i810_setup, 1246820647b9SDaniel Vetter .cleanup = i810_cleanup, 1247625dd9d3SDaniel Vetter .check_flags = i830_check_flags, 1248625dd9d3SDaniel Vetter .write_entry = i810_write_entry, 1249bdd30729SDaniel Vetter }; 12501a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 12511a997ff2SDaniel Vetter .gen = 2, 1252100519e2SChris Wilson .has_pgtbl_enable = 1, 125373800422SDaniel Vetter .setup = i830_setup, 1254ae83dd5cSDaniel Vetter .cleanup = i830_cleanup, 1255351bb278SDaniel Vetter .write_entry = i830_write_entry, 125622533b49SDaniel Vetter .dma_mask_size = 32, 12575cbecafcSDaniel Vetter .check_flags = i830_check_flags, 12581b263f24SDaniel Vetter .chipset_flush = i830_chipset_flush, 12591a997ff2SDaniel Vetter }; 12601a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 12611a997ff2SDaniel Vetter .gen = 3, 1262100519e2SChris Wilson .has_pgtbl_enable = 1, 12632d2430cfSDaniel Vetter .setup = i9xx_setup, 1264ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1265351bb278SDaniel Vetter /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1266351bb278SDaniel Vetter .write_entry = i830_write_entry, 126722533b49SDaniel Vetter .dma_mask_size = 32, 1268fefaa70fSDaniel Vetter .check_flags = i830_check_flags, 12691b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12701a997ff2SDaniel Vetter }; 12711a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 12721a997ff2SDaniel Vetter .gen = 3, 12731a997ff2SDaniel Vetter .is_g33 = 1, 12742d2430cfSDaniel Vetter .setup = i9xx_setup, 1275ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1276a6963596SDaniel Vetter .write_entry = i965_write_entry, 127722533b49SDaniel Vetter .dma_mask_size = 36, 1278450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12791b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12801a997ff2SDaniel Vetter }; 12811a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 12821a997ff2SDaniel Vetter .gen = 3, 12831a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 12842d2430cfSDaniel Vetter .setup = i9xx_setup, 1285ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1286a6963596SDaniel Vetter .write_entry = i965_write_entry, 128722533b49SDaniel Vetter .dma_mask_size = 36, 1288450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12891b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12901a997ff2SDaniel Vetter }; 12911a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 12921a997ff2SDaniel Vetter .gen = 4, 1293100519e2SChris Wilson .has_pgtbl_enable = 1, 12942d2430cfSDaniel Vetter .setup = i9xx_setup, 1295ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1296a6963596SDaniel Vetter .write_entry = i965_write_entry, 129722533b49SDaniel Vetter .dma_mask_size = 36, 1298450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12991b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13001a997ff2SDaniel Vetter }; 13011a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 13021a997ff2SDaniel Vetter .gen = 5, 13032d2430cfSDaniel Vetter .setup = i9xx_setup, 1304ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1305a6963596SDaniel Vetter .write_entry = i965_write_entry, 130622533b49SDaniel Vetter .dma_mask_size = 36, 1307450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13081b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13091a997ff2SDaniel Vetter }; 13101a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 13111a997ff2SDaniel Vetter .gen = 5, 13121a997ff2SDaniel Vetter .is_ironlake = 1, 13132d2430cfSDaniel Vetter .setup = i9xx_setup, 1314ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1315a6963596SDaniel Vetter .write_entry = i965_write_entry, 131622533b49SDaniel Vetter .dma_mask_size = 36, 1317450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 13181b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13191a997ff2SDaniel Vetter }; 13201a997ff2SDaniel Vetter static const struct intel_gtt_driver sandybridge_gtt_driver = { 13211a997ff2SDaniel Vetter .gen = 6, 13222d2430cfSDaniel Vetter .setup = i9xx_setup, 1323ae83dd5cSDaniel Vetter .cleanup = gen6_cleanup, 132497ef1bddSDaniel Vetter .write_entry = gen6_write_entry, 132522533b49SDaniel Vetter .dma_mask_size = 40, 132690cb149eSDaniel Vetter .check_flags = gen6_check_flags, 13271b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 13281a997ff2SDaniel Vetter }; 13291a997ff2SDaniel Vetter 133002c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 133102c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 133202c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 133302c026ceSDaniel Vetter */ 133402c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 133502c026ceSDaniel Vetter unsigned int gmch_chip_id; 133602c026ceSDaniel Vetter char *name; 13371a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 133802c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 1339ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1340bdd30729SDaniel Vetter &i81x_gtt_driver}, 1341ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1342bdd30729SDaniel Vetter &i81x_gtt_driver}, 1343ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1344bdd30729SDaniel Vetter &i81x_gtt_driver}, 1345ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1346bdd30729SDaniel Vetter &i81x_gtt_driver}, 13471a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1348ff26860fSDaniel Vetter &i8xx_gtt_driver}, 134953371edaSOswald Buddenhagen { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1350ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13511a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1352ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13531a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1354ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13551a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1356ff26860fSDaniel Vetter &i8xx_gtt_driver}, 13571a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1358ff26860fSDaniel Vetter &i915_gtt_driver }, 13591a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1360ff26860fSDaniel Vetter &i915_gtt_driver }, 13611a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1362ff26860fSDaniel Vetter &i915_gtt_driver }, 13631a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1364ff26860fSDaniel Vetter &i915_gtt_driver }, 13651a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1366ff26860fSDaniel Vetter &i915_gtt_driver }, 13671a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1368ff26860fSDaniel Vetter &i915_gtt_driver }, 13691a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1370ff26860fSDaniel Vetter &i965_gtt_driver }, 13711a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1372ff26860fSDaniel Vetter &i965_gtt_driver }, 13731a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1374ff26860fSDaniel Vetter &i965_gtt_driver }, 13751a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1376ff26860fSDaniel Vetter &i965_gtt_driver }, 13771a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1378ff26860fSDaniel Vetter &i965_gtt_driver }, 13791a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1380ff26860fSDaniel Vetter &i965_gtt_driver }, 13811a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1382ff26860fSDaniel Vetter &g33_gtt_driver }, 13831a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1384ff26860fSDaniel Vetter &g33_gtt_driver }, 13851a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1386ff26860fSDaniel Vetter &g33_gtt_driver }, 13871a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1388ff26860fSDaniel Vetter &pineview_gtt_driver }, 13891a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1390ff26860fSDaniel Vetter &pineview_gtt_driver }, 13911a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1392ff26860fSDaniel Vetter &g4x_gtt_driver }, 13931a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1394ff26860fSDaniel Vetter &g4x_gtt_driver }, 13951a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1396ff26860fSDaniel Vetter &g4x_gtt_driver }, 13971a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1398ff26860fSDaniel Vetter &g4x_gtt_driver }, 13991a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1400ff26860fSDaniel Vetter &g4x_gtt_driver }, 1401e9e5f8e8SChris Wilson { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1402ff26860fSDaniel Vetter &g4x_gtt_driver }, 14031a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1404ff26860fSDaniel Vetter &g4x_gtt_driver }, 140502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1406ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 140702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1408ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 140902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 1410ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 141102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 1412ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 141302c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 1414ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 141502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 1416ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 141702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 1418ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 141902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 1420ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 142102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 1422ff26860fSDaniel Vetter "Sandybridge", &sandybridge_gtt_driver }, 1423246d08b8SJesse Barnes { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, 1424246d08b8SJesse Barnes "Ivybridge", &sandybridge_gtt_driver }, 1425246d08b8SJesse Barnes { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, 1426246d08b8SJesse Barnes "Ivybridge", &sandybridge_gtt_driver }, 1427246d08b8SJesse Barnes { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, 1428246d08b8SJesse Barnes "Ivybridge", &sandybridge_gtt_driver }, 1429246d08b8SJesse Barnes { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, 1430246d08b8SJesse Barnes "Ivybridge", &sandybridge_gtt_driver }, 1431246d08b8SJesse Barnes { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, 1432246d08b8SJesse Barnes "Ivybridge", &sandybridge_gtt_driver }, 143302c026ceSDaniel Vetter { 0, NULL, NULL } 143402c026ceSDaniel Vetter }; 143502c026ceSDaniel Vetter 143602c026ceSDaniel Vetter static int find_gmch(u16 device) 143702c026ceSDaniel Vetter { 143802c026ceSDaniel Vetter struct pci_dev *gmch_device; 143902c026ceSDaniel Vetter 144002c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 144102c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 144202c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 144302c026ceSDaniel Vetter device, gmch_device); 144402c026ceSDaniel Vetter } 144502c026ceSDaniel Vetter 144602c026ceSDaniel Vetter if (!gmch_device) 144702c026ceSDaniel Vetter return 0; 144802c026ceSDaniel Vetter 144902c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 145002c026ceSDaniel Vetter return 1; 145102c026ceSDaniel Vetter } 145202c026ceSDaniel Vetter 1453e2404e7cSDaniel Vetter int intel_gmch_probe(struct pci_dev *pdev, 145402c026ceSDaniel Vetter struct agp_bridge_data *bridge) 145502c026ceSDaniel Vetter { 145602c026ceSDaniel Vetter int i, mask; 1457ff26860fSDaniel Vetter intel_private.driver = NULL; 145802c026ceSDaniel Vetter 145902c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 146002c026ceSDaniel Vetter if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 14611a997ff2SDaniel Vetter intel_private.driver = 14621a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 146302c026ceSDaniel Vetter break; 146402c026ceSDaniel Vetter } 146502c026ceSDaniel Vetter } 146602c026ceSDaniel Vetter 1467ff26860fSDaniel Vetter if (!intel_private.driver) 146802c026ceSDaniel Vetter return 0; 146902c026ceSDaniel Vetter 1470ff26860fSDaniel Vetter bridge->driver = &intel_fake_agp_driver; 147102c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 147202c026ceSDaniel Vetter bridge->dev = pdev; 147302c026ceSDaniel Vetter 1474d7cca2f7SDaniel Vetter intel_private.bridge_dev = pci_dev_get(pdev); 1475d7cca2f7SDaniel Vetter 147602c026ceSDaniel Vetter dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 147702c026ceSDaniel Vetter 147822533b49SDaniel Vetter mask = intel_private.driver->dma_mask_size; 147902c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 148002c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 148102c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 148202c026ceSDaniel Vetter else 148302c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 148402c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 148502c026ceSDaniel Vetter 1486820647b9SDaniel Vetter /*if (bridge->driver == &intel_810_driver) 1487820647b9SDaniel Vetter return 1;*/ 14881784a5fbSDaniel Vetter 14893b15a9d7SDaniel Vetter if (intel_gtt_init() != 0) 14903b15a9d7SDaniel Vetter return 0; 14911784a5fbSDaniel Vetter 149202c026ceSDaniel Vetter return 1; 149302c026ceSDaniel Vetter } 1494e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 149502c026ceSDaniel Vetter 1496c64f7ba5SChris Wilson const struct intel_gtt *intel_gtt_get(void) 149719966754SDaniel Vetter { 149819966754SDaniel Vetter return &intel_private.base; 149919966754SDaniel Vetter } 150019966754SDaniel Vetter EXPORT_SYMBOL(intel_gtt_get); 150119966754SDaniel Vetter 150240ce6575SDaniel Vetter void intel_gtt_chipset_flush(void) 150340ce6575SDaniel Vetter { 150440ce6575SDaniel Vetter if (intel_private.driver->chipset_flush) 150540ce6575SDaniel Vetter intel_private.driver->chipset_flush(); 150640ce6575SDaniel Vetter } 150740ce6575SDaniel Vetter EXPORT_SYMBOL(intel_gtt_chipset_flush); 150840ce6575SDaniel Vetter 1509e2404e7cSDaniel Vetter void intel_gmch_remove(struct pci_dev *pdev) 151002c026ceSDaniel Vetter { 151102c026ceSDaniel Vetter if (intel_private.pcidev) 151202c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1513d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1514d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 151502c026ceSDaniel Vetter } 1516e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1517e2404e7cSDaniel Vetter 1518e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1519e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1520