1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24e2404e7cSDaniel Vetter #include <asm/smp.h> 25e2404e7cSDaniel Vetter #include "agp.h" 26e2404e7cSDaniel Vetter #include "intel-agp.h" 27e2404e7cSDaniel Vetter #include <linux/intel-gtt.h> 280ade6386SDaniel Vetter #include <drm/intel-gtt.h> 29e2404e7cSDaniel Vetter 30f51b7662SDaniel Vetter /* 31f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 32f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 34f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 35f51b7662SDaniel Vetter */ 36f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 37f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 380e87d2b0SDaniel Vetter #else 390e87d2b0SDaniel Vetter #define USE_PCI_DMA_API 0 40f51b7662SDaniel Vetter #endif 41f51b7662SDaniel Vetter 42d1d6ca73SJesse Barnes /* Max amount of stolen space, anything above will be returned to Linux */ 43d1d6ca73SJesse Barnes int intel_max_stolen = 32 * 1024 * 1024; 44d1d6ca73SJesse Barnes EXPORT_SYMBOL(intel_max_stolen); 45d1d6ca73SJesse Barnes 46f51b7662SDaniel Vetter static const struct aper_size_info_fixed intel_i810_sizes[] = 47f51b7662SDaniel Vetter { 48f51b7662SDaniel Vetter {64, 16384, 4}, 49f51b7662SDaniel Vetter /* The 32M mode still requires a 64k gatt */ 50f51b7662SDaniel Vetter {32, 8192, 4} 51f51b7662SDaniel Vetter }; 52f51b7662SDaniel Vetter 53f51b7662SDaniel Vetter #define AGP_DCACHE_MEMORY 1 54f51b7662SDaniel Vetter #define AGP_PHYS_MEMORY 2 55f51b7662SDaniel Vetter #define INTEL_AGP_CACHED_MEMORY 3 56f51b7662SDaniel Vetter 57f51b7662SDaniel Vetter static struct gatt_mask intel_i810_masks[] = 58f51b7662SDaniel Vetter { 59f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 60f51b7662SDaniel Vetter {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 61f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 62f51b7662SDaniel Vetter {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 63f51b7662SDaniel Vetter .type = INTEL_AGP_CACHED_MEMORY} 64f51b7662SDaniel Vetter }; 65f51b7662SDaniel Vetter 66f8f235e5SZhenyu Wang #define INTEL_AGP_UNCACHED_MEMORY 0 67f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC 1 68f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 69f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 70f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 71f8f235e5SZhenyu Wang 72f8f235e5SZhenyu Wang static struct gatt_mask intel_gen6_masks[] = 73f8f235e5SZhenyu Wang { 74f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED, 75f8f235e5SZhenyu Wang .type = INTEL_AGP_UNCACHED_MEMORY }, 76f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC, 77f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC }, 78f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT, 79f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT }, 80f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC, 81f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC }, 82f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT, 83f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, 84f8f235e5SZhenyu Wang }; 85f8f235e5SZhenyu Wang 861a997ff2SDaniel Vetter struct intel_gtt_driver { 871a997ff2SDaniel Vetter unsigned int gen : 8; 881a997ff2SDaniel Vetter unsigned int is_g33 : 1; 891a997ff2SDaniel Vetter unsigned int is_pineview : 1; 901a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 9173800422SDaniel Vetter /* Chipset specific GTT setup */ 9273800422SDaniel Vetter int (*setup)(void); 931a997ff2SDaniel Vetter }; 941a997ff2SDaniel Vetter 95f51b7662SDaniel Vetter static struct _intel_private { 960ade6386SDaniel Vetter struct intel_gtt base; 971a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 98f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 99d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 100f51b7662SDaniel Vetter u8 __iomem *registers; 101f67eab66SDaniel Vetter phys_addr_t gtt_bus_addr; 10273800422SDaniel Vetter phys_addr_t gma_bus_addr; 1033f08e4efSChris Wilson phys_addr_t pte_bus_addr; 104f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 105f51b7662SDaniel Vetter int num_dcache_entries; 106f51b7662SDaniel Vetter union { 107f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 108f51b7662SDaniel Vetter void *i8xx_flush_page; 109f51b7662SDaniel Vetter }; 110f51b7662SDaniel Vetter struct page *i8xx_page; 111f51b7662SDaniel Vetter struct resource ifp_resource; 112f51b7662SDaniel Vetter int resource_valid; 1130e87d2b0SDaniel Vetter struct page *scratch_page; 1140e87d2b0SDaniel Vetter dma_addr_t scratch_page_dma; 115f51b7662SDaniel Vetter } intel_private; 116f51b7662SDaniel Vetter 1171a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 1181a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 1191a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 1201a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 1211a997ff2SDaniel Vetter 1220e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 123f51b7662SDaniel Vetter static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 124f51b7662SDaniel Vetter { 125f51b7662SDaniel Vetter *ret = pci_map_page(intel_private.pcidev, page, 0, 126f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 127f51b7662SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 128f51b7662SDaniel Vetter return -EINVAL; 129f51b7662SDaniel Vetter return 0; 130f51b7662SDaniel Vetter } 131f51b7662SDaniel Vetter 132f51b7662SDaniel Vetter static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 133f51b7662SDaniel Vetter { 134f51b7662SDaniel Vetter pci_unmap_page(intel_private.pcidev, dma, 135f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 136f51b7662SDaniel Vetter } 137f51b7662SDaniel Vetter 138f51b7662SDaniel Vetter static void intel_agp_free_sglist(struct agp_memory *mem) 139f51b7662SDaniel Vetter { 140f51b7662SDaniel Vetter struct sg_table st; 141f51b7662SDaniel Vetter 142f51b7662SDaniel Vetter st.sgl = mem->sg_list; 143f51b7662SDaniel Vetter st.orig_nents = st.nents = mem->page_count; 144f51b7662SDaniel Vetter 145f51b7662SDaniel Vetter sg_free_table(&st); 146f51b7662SDaniel Vetter 147f51b7662SDaniel Vetter mem->sg_list = NULL; 148f51b7662SDaniel Vetter mem->num_sg = 0; 149f51b7662SDaniel Vetter } 150f51b7662SDaniel Vetter 151f51b7662SDaniel Vetter static int intel_agp_map_memory(struct agp_memory *mem) 152f51b7662SDaniel Vetter { 153f51b7662SDaniel Vetter struct sg_table st; 154f51b7662SDaniel Vetter struct scatterlist *sg; 155f51b7662SDaniel Vetter int i; 156f51b7662SDaniel Vetter 157f51b7662SDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 158f51b7662SDaniel Vetter 159f51b7662SDaniel Vetter if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 160831cd445SChris Wilson goto err; 161f51b7662SDaniel Vetter 162f51b7662SDaniel Vetter mem->sg_list = sg = st.sgl; 163f51b7662SDaniel Vetter 164f51b7662SDaniel Vetter for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 165f51b7662SDaniel Vetter sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 166f51b7662SDaniel Vetter 167f51b7662SDaniel Vetter mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 168f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 169831cd445SChris Wilson if (unlikely(!mem->num_sg)) 170831cd445SChris Wilson goto err; 171831cd445SChris Wilson 172f51b7662SDaniel Vetter return 0; 173831cd445SChris Wilson 174831cd445SChris Wilson err: 175831cd445SChris Wilson sg_free_table(&st); 176831cd445SChris Wilson return -ENOMEM; 177f51b7662SDaniel Vetter } 178f51b7662SDaniel Vetter 179f51b7662SDaniel Vetter static void intel_agp_unmap_memory(struct agp_memory *mem) 180f51b7662SDaniel Vetter { 181f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 182f51b7662SDaniel Vetter 183f51b7662SDaniel Vetter pci_unmap_sg(intel_private.pcidev, mem->sg_list, 184f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 185f51b7662SDaniel Vetter intel_agp_free_sglist(mem); 186f51b7662SDaniel Vetter } 187f51b7662SDaniel Vetter 188f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 189f51b7662SDaniel Vetter off_t pg_start, int mask_type) 190f51b7662SDaniel Vetter { 191f51b7662SDaniel Vetter struct scatterlist *sg; 192f51b7662SDaniel Vetter int i, j; 193f51b7662SDaniel Vetter 194f51b7662SDaniel Vetter j = pg_start; 195f51b7662SDaniel Vetter 196f51b7662SDaniel Vetter WARN_ON(!mem->num_sg); 197f51b7662SDaniel Vetter 198f51b7662SDaniel Vetter if (mem->num_sg == mem->page_count) { 199f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->page_count, i) { 200f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 201f51b7662SDaniel Vetter sg_dma_address(sg), mask_type), 202f51b7662SDaniel Vetter intel_private.gtt+j); 203f51b7662SDaniel Vetter j++; 204f51b7662SDaniel Vetter } 205f51b7662SDaniel Vetter } else { 206f51b7662SDaniel Vetter /* sg may merge pages, but we have to separate 207f51b7662SDaniel Vetter * per-page addr for GTT */ 208f51b7662SDaniel Vetter unsigned int len, m; 209f51b7662SDaniel Vetter 210f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 211f51b7662SDaniel Vetter len = sg_dma_len(sg) / PAGE_SIZE; 212f51b7662SDaniel Vetter for (m = 0; m < len; m++) { 213f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 214f51b7662SDaniel Vetter sg_dma_address(sg) + m * PAGE_SIZE, 215f51b7662SDaniel Vetter mask_type), 216f51b7662SDaniel Vetter intel_private.gtt+j); 217f51b7662SDaniel Vetter j++; 218f51b7662SDaniel Vetter } 219f51b7662SDaniel Vetter } 220f51b7662SDaniel Vetter } 221f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 222f51b7662SDaniel Vetter } 223f51b7662SDaniel Vetter 224f51b7662SDaniel Vetter #else 225f51b7662SDaniel Vetter 226f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 227f51b7662SDaniel Vetter off_t pg_start, int mask_type) 228f51b7662SDaniel Vetter { 229f51b7662SDaniel Vetter int i, j; 230f51b7662SDaniel Vetter 231f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 232f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 233f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 234f51b7662SDaniel Vetter intel_private.gtt+j); 235f51b7662SDaniel Vetter } 236f51b7662SDaniel Vetter 237f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 238f51b7662SDaniel Vetter } 239f51b7662SDaniel Vetter 240f51b7662SDaniel Vetter #endif 241f51b7662SDaniel Vetter 242f51b7662SDaniel Vetter static int intel_i810_fetch_size(void) 243f51b7662SDaniel Vetter { 244f51b7662SDaniel Vetter u32 smram_miscc; 245f51b7662SDaniel Vetter struct aper_size_info_fixed *values; 246f51b7662SDaniel Vetter 247d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 248d7cca2f7SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 249f51b7662SDaniel Vetter values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 250f51b7662SDaniel Vetter 251f51b7662SDaniel Vetter if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 252d7cca2f7SDaniel Vetter dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); 253f51b7662SDaniel Vetter return 0; 254f51b7662SDaniel Vetter } 255f51b7662SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 256f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values + 1); 257f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 1; 258f51b7662SDaniel Vetter return values[1].size; 259f51b7662SDaniel Vetter } else { 260f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values); 261f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 262f51b7662SDaniel Vetter return values[0].size; 263f51b7662SDaniel Vetter } 264f51b7662SDaniel Vetter 265f51b7662SDaniel Vetter return 0; 266f51b7662SDaniel Vetter } 267f51b7662SDaniel Vetter 268f51b7662SDaniel Vetter static int intel_i810_configure(void) 269f51b7662SDaniel Vetter { 270f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 271f51b7662SDaniel Vetter u32 temp; 272f51b7662SDaniel Vetter int i; 273f51b7662SDaniel Vetter 274f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 275f51b7662SDaniel Vetter 276f51b7662SDaniel Vetter if (!intel_private.registers) { 277f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 278f51b7662SDaniel Vetter temp &= 0xfff80000; 279f51b7662SDaniel Vetter 280f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 281f51b7662SDaniel Vetter if (!intel_private.registers) { 282f51b7662SDaniel Vetter dev_err(&intel_private.pcidev->dev, 283f51b7662SDaniel Vetter "can't remap memory\n"); 284f51b7662SDaniel Vetter return -ENOMEM; 285f51b7662SDaniel Vetter } 286f51b7662SDaniel Vetter } 287f51b7662SDaniel Vetter 288f51b7662SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 289f51b7662SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 290f51b7662SDaniel Vetter /* This will need to be dynamically assigned */ 291f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 292f51b7662SDaniel Vetter "detected 4MB dedicated video ram\n"); 293f51b7662SDaniel Vetter intel_private.num_dcache_entries = 1024; 294f51b7662SDaniel Vetter } 295f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 296f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 297f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 298f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 299f51b7662SDaniel Vetter 300f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 301f51b7662SDaniel Vetter for (i = 0; i < current_size->num_entries; i++) { 302f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 303f51b7662SDaniel Vetter } 304f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 305f51b7662SDaniel Vetter } 306f51b7662SDaniel Vetter global_cache_flush(); 307f51b7662SDaniel Vetter return 0; 308f51b7662SDaniel Vetter } 309f51b7662SDaniel Vetter 310f51b7662SDaniel Vetter static void intel_i810_cleanup(void) 311f51b7662SDaniel Vetter { 312f51b7662SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 313f51b7662SDaniel Vetter readl(intel_private.registers); /* PCI Posting. */ 314f51b7662SDaniel Vetter iounmap(intel_private.registers); 315f51b7662SDaniel Vetter } 316f51b7662SDaniel Vetter 317ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 318f51b7662SDaniel Vetter { 319f51b7662SDaniel Vetter return; 320f51b7662SDaniel Vetter } 321f51b7662SDaniel Vetter 322f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 323f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 324f51b7662SDaniel Vetter { 325f51b7662SDaniel Vetter struct page *page; 326f51b7662SDaniel Vetter 327f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 328f51b7662SDaniel Vetter if (page == NULL) 329f51b7662SDaniel Vetter return NULL; 330f51b7662SDaniel Vetter 331f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 332f51b7662SDaniel Vetter set_pages_wb(page, 4); 333f51b7662SDaniel Vetter __free_pages(page, 2); 334f51b7662SDaniel Vetter return NULL; 335f51b7662SDaniel Vetter } 336f51b7662SDaniel Vetter get_page(page); 337f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 338f51b7662SDaniel Vetter return page; 339f51b7662SDaniel Vetter } 340f51b7662SDaniel Vetter 341f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 342f51b7662SDaniel Vetter { 343f51b7662SDaniel Vetter if (page == NULL) 344f51b7662SDaniel Vetter return; 345f51b7662SDaniel Vetter 346f51b7662SDaniel Vetter set_pages_wb(page, 4); 347f51b7662SDaniel Vetter put_page(page); 348f51b7662SDaniel Vetter __free_pages(page, 2); 349f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 350f51b7662SDaniel Vetter } 351f51b7662SDaniel Vetter 352f51b7662SDaniel Vetter static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 353f51b7662SDaniel Vetter int type) 354f51b7662SDaniel Vetter { 355f51b7662SDaniel Vetter if (type < AGP_USER_TYPES) 356f51b7662SDaniel Vetter return type; 357f51b7662SDaniel Vetter else if (type == AGP_USER_CACHED_MEMORY) 358f51b7662SDaniel Vetter return INTEL_AGP_CACHED_MEMORY; 359f51b7662SDaniel Vetter else 360f51b7662SDaniel Vetter return 0; 361f51b7662SDaniel Vetter } 362f51b7662SDaniel Vetter 363f8f235e5SZhenyu Wang static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge, 364f8f235e5SZhenyu Wang int type) 365f8f235e5SZhenyu Wang { 366f8f235e5SZhenyu Wang unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; 367f8f235e5SZhenyu Wang unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; 368f8f235e5SZhenyu Wang 369f8f235e5SZhenyu Wang if (type_mask == AGP_USER_UNCACHED_MEMORY) 370f8f235e5SZhenyu Wang return INTEL_AGP_UNCACHED_MEMORY; 371f8f235e5SZhenyu Wang else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) 372f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT : 373f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC_MLC; 374f8f235e5SZhenyu Wang else /* set 'normal'/'cached' to LLC by default */ 375f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT : 376f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC; 377f8f235e5SZhenyu Wang } 378f8f235e5SZhenyu Wang 379f8f235e5SZhenyu Wang 380f51b7662SDaniel Vetter static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 381f51b7662SDaniel Vetter int type) 382f51b7662SDaniel Vetter { 383f51b7662SDaniel Vetter int i, j, num_entries; 384f51b7662SDaniel Vetter void *temp; 385f51b7662SDaniel Vetter int ret = -EINVAL; 386f51b7662SDaniel Vetter int mask_type; 387f51b7662SDaniel Vetter 388f51b7662SDaniel Vetter if (mem->page_count == 0) 389f51b7662SDaniel Vetter goto out; 390f51b7662SDaniel Vetter 391f51b7662SDaniel Vetter temp = agp_bridge->current_size; 392f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 393f51b7662SDaniel Vetter 394f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 395f51b7662SDaniel Vetter goto out_err; 396f51b7662SDaniel Vetter 397f51b7662SDaniel Vetter 398f51b7662SDaniel Vetter for (j = pg_start; j < (pg_start + mem->page_count); j++) { 399f51b7662SDaniel Vetter if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 400f51b7662SDaniel Vetter ret = -EBUSY; 401f51b7662SDaniel Vetter goto out_err; 402f51b7662SDaniel Vetter } 403f51b7662SDaniel Vetter } 404f51b7662SDaniel Vetter 405f51b7662SDaniel Vetter if (type != mem->type) 406f51b7662SDaniel Vetter goto out_err; 407f51b7662SDaniel Vetter 408f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 409f51b7662SDaniel Vetter 410f51b7662SDaniel Vetter switch (mask_type) { 411f51b7662SDaniel Vetter case AGP_DCACHE_MEMORY: 412f51b7662SDaniel Vetter if (!mem->is_flushed) 413f51b7662SDaniel Vetter global_cache_flush(); 414f51b7662SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 415f51b7662SDaniel Vetter writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 416f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(i*4)); 417f51b7662SDaniel Vetter } 418f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 419f51b7662SDaniel Vetter break; 420f51b7662SDaniel Vetter case AGP_PHYS_MEMORY: 421f51b7662SDaniel Vetter case AGP_NORMAL_MEMORY: 422f51b7662SDaniel Vetter if (!mem->is_flushed) 423f51b7662SDaniel Vetter global_cache_flush(); 424f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 425f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 426f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 427f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(j*4)); 428f51b7662SDaniel Vetter } 429f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 430f51b7662SDaniel Vetter break; 431f51b7662SDaniel Vetter default: 432f51b7662SDaniel Vetter goto out_err; 433f51b7662SDaniel Vetter } 434f51b7662SDaniel Vetter 435f51b7662SDaniel Vetter out: 436f51b7662SDaniel Vetter ret = 0; 437f51b7662SDaniel Vetter out_err: 438f51b7662SDaniel Vetter mem->is_flushed = true; 439f51b7662SDaniel Vetter return ret; 440f51b7662SDaniel Vetter } 441f51b7662SDaniel Vetter 442f51b7662SDaniel Vetter static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 443f51b7662SDaniel Vetter int type) 444f51b7662SDaniel Vetter { 445f51b7662SDaniel Vetter int i; 446f51b7662SDaniel Vetter 447f51b7662SDaniel Vetter if (mem->page_count == 0) 448f51b7662SDaniel Vetter return 0; 449f51b7662SDaniel Vetter 450f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 451f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 452f51b7662SDaniel Vetter } 453f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 454f51b7662SDaniel Vetter 455f51b7662SDaniel Vetter return 0; 456f51b7662SDaniel Vetter } 457f51b7662SDaniel Vetter 458f51b7662SDaniel Vetter /* 459f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 460f51b7662SDaniel Vetter * pointer into hardware. 461f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 462f51b7662SDaniel Vetter */ 463f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 464f51b7662SDaniel Vetter { 465f51b7662SDaniel Vetter struct agp_memory *new; 466f51b7662SDaniel Vetter struct page *page; 467f51b7662SDaniel Vetter 468f51b7662SDaniel Vetter switch (pg_count) { 469f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 470f51b7662SDaniel Vetter break; 471f51b7662SDaniel Vetter case 4: 472f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 473f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 474f51b7662SDaniel Vetter break; 475f51b7662SDaniel Vetter default: 476f51b7662SDaniel Vetter return NULL; 477f51b7662SDaniel Vetter } 478f51b7662SDaniel Vetter 479f51b7662SDaniel Vetter if (page == NULL) 480f51b7662SDaniel Vetter return NULL; 481f51b7662SDaniel Vetter 482f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 483f51b7662SDaniel Vetter if (new == NULL) 484f51b7662SDaniel Vetter return NULL; 485f51b7662SDaniel Vetter 486f51b7662SDaniel Vetter new->pages[0] = page; 487f51b7662SDaniel Vetter if (pg_count == 4) { 488f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 489f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 490f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 491f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 492f51b7662SDaniel Vetter } 493f51b7662SDaniel Vetter new->page_count = pg_count; 494f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 495f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 496f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 497f51b7662SDaniel Vetter return new; 498f51b7662SDaniel Vetter } 499f51b7662SDaniel Vetter 500f51b7662SDaniel Vetter static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 501f51b7662SDaniel Vetter { 502f51b7662SDaniel Vetter struct agp_memory *new; 503f51b7662SDaniel Vetter 504f51b7662SDaniel Vetter if (type == AGP_DCACHE_MEMORY) { 505f51b7662SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 506f51b7662SDaniel Vetter return NULL; 507f51b7662SDaniel Vetter 508f51b7662SDaniel Vetter new = agp_create_memory(1); 509f51b7662SDaniel Vetter if (new == NULL) 510f51b7662SDaniel Vetter return NULL; 511f51b7662SDaniel Vetter 512f51b7662SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 513f51b7662SDaniel Vetter new->page_count = pg_count; 514f51b7662SDaniel Vetter new->num_scratch_pages = 0; 515f51b7662SDaniel Vetter agp_free_page_array(new); 516f51b7662SDaniel Vetter return new; 517f51b7662SDaniel Vetter } 518f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 519f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 520f51b7662SDaniel Vetter return NULL; 521f51b7662SDaniel Vetter } 522f51b7662SDaniel Vetter 523f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 524f51b7662SDaniel Vetter { 525f51b7662SDaniel Vetter agp_free_key(curr->key); 526f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 527f51b7662SDaniel Vetter if (curr->page_count == 4) 528f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 529f51b7662SDaniel Vetter else { 530f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 531f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 532f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 533f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 534f51b7662SDaniel Vetter } 535f51b7662SDaniel Vetter agp_free_page_array(curr); 536f51b7662SDaniel Vetter } 537f51b7662SDaniel Vetter kfree(curr); 538f51b7662SDaniel Vetter } 539f51b7662SDaniel Vetter 540f51b7662SDaniel Vetter static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 541f51b7662SDaniel Vetter dma_addr_t addr, int type) 542f51b7662SDaniel Vetter { 543f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 544f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 545f51b7662SDaniel Vetter } 546f51b7662SDaniel Vetter 5470e87d2b0SDaniel Vetter static int intel_gtt_setup_scratch_page(void) 5480e87d2b0SDaniel Vetter { 5490e87d2b0SDaniel Vetter struct page *page; 5500e87d2b0SDaniel Vetter dma_addr_t dma_addr; 5510e87d2b0SDaniel Vetter 5520e87d2b0SDaniel Vetter page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 5530e87d2b0SDaniel Vetter if (page == NULL) 5540e87d2b0SDaniel Vetter return -ENOMEM; 5550e87d2b0SDaniel Vetter get_page(page); 5560e87d2b0SDaniel Vetter set_pages_uc(page, 1); 5570e87d2b0SDaniel Vetter 5580e87d2b0SDaniel Vetter if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { 5590e87d2b0SDaniel Vetter dma_addr = pci_map_page(intel_private.pcidev, page, 0, 5600e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 5610e87d2b0SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 5620e87d2b0SDaniel Vetter return -EINVAL; 5630e87d2b0SDaniel Vetter 5640e87d2b0SDaniel Vetter intel_private.scratch_page_dma = dma_addr; 5650e87d2b0SDaniel Vetter } else 5660e87d2b0SDaniel Vetter intel_private.scratch_page_dma = page_to_phys(page); 5670e87d2b0SDaniel Vetter 5680e87d2b0SDaniel Vetter intel_private.scratch_page = page; 5690e87d2b0SDaniel Vetter 5700e87d2b0SDaniel Vetter return 0; 5710e87d2b0SDaniel Vetter } 5720e87d2b0SDaniel Vetter 5739e76e7b8SChris Wilson static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { 574f51b7662SDaniel Vetter {128, 32768, 5}, 575f51b7662SDaniel Vetter /* The 64M mode still requires a 128k gatt */ 576f51b7662SDaniel Vetter {64, 16384, 5}, 577f51b7662SDaniel Vetter {256, 65536, 6}, 578f51b7662SDaniel Vetter {512, 131072, 7}, 579f51b7662SDaniel Vetter }; 580f51b7662SDaniel Vetter 581bfde067bSDaniel Vetter static unsigned int intel_gtt_stolen_entries(void) 582f51b7662SDaniel Vetter { 583f51b7662SDaniel Vetter u16 gmch_ctrl; 584f51b7662SDaniel Vetter u8 rdct; 585f51b7662SDaniel Vetter int local = 0; 586f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 587d8d9abcdSDaniel Vetter unsigned int overhead_entries, stolen_entries; 588d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 589f51b7662SDaniel Vetter 590d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 591d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 592f51b7662SDaniel Vetter 5931a997ff2SDaniel Vetter if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) 594fbe40783SDaniel Vetter overhead_entries = 0; 595fbe40783SDaniel Vetter else 596fbe40783SDaniel Vetter overhead_entries = intel_private.base.gtt_mappable_entries 597fbe40783SDaniel Vetter / 1024; 598f51b7662SDaniel Vetter 599fbe40783SDaniel Vetter overhead_entries += 1; /* BIOS popup */ 600d8d9abcdSDaniel Vetter 601d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 602d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 603f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 604f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 605d8d9abcdSDaniel Vetter stolen_size = KB(512); 606f51b7662SDaniel Vetter break; 607f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 608d8d9abcdSDaniel Vetter stolen_size = MB(1); 609f51b7662SDaniel Vetter break; 610f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 611d8d9abcdSDaniel Vetter stolen_size = MB(8); 612f51b7662SDaniel Vetter break; 613f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 614f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 615d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 616f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 617f51b7662SDaniel Vetter local = 1; 618f51b7662SDaniel Vetter break; 619f51b7662SDaniel Vetter default: 620d8d9abcdSDaniel Vetter stolen_size = 0; 621f51b7662SDaniel Vetter break; 622f51b7662SDaniel Vetter } 6231a997ff2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 624f51b7662SDaniel Vetter /* 625f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 626f51b7662SDaniel Vetter */ 627f51b7662SDaniel Vetter u16 snb_gmch_ctl; 628f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 629f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 630f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 631d8d9abcdSDaniel Vetter stolen_size = MB(32); 632f51b7662SDaniel Vetter break; 633f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 634d8d9abcdSDaniel Vetter stolen_size = MB(64); 635f51b7662SDaniel Vetter break; 636f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 637d8d9abcdSDaniel Vetter stolen_size = MB(96); 638f51b7662SDaniel Vetter break; 639f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 640d8d9abcdSDaniel Vetter stolen_size = MB(128); 641f51b7662SDaniel Vetter break; 642f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 643d8d9abcdSDaniel Vetter stolen_size = MB(160); 644f51b7662SDaniel Vetter break; 645f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 646d8d9abcdSDaniel Vetter stolen_size = MB(192); 647f51b7662SDaniel Vetter break; 648f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 649d8d9abcdSDaniel Vetter stolen_size = MB(224); 650f51b7662SDaniel Vetter break; 651f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 652d8d9abcdSDaniel Vetter stolen_size = MB(256); 653f51b7662SDaniel Vetter break; 654f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 655d8d9abcdSDaniel Vetter stolen_size = MB(288); 656f51b7662SDaniel Vetter break; 657f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 658d8d9abcdSDaniel Vetter stolen_size = MB(320); 659f51b7662SDaniel Vetter break; 660f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 661d8d9abcdSDaniel Vetter stolen_size = MB(352); 662f51b7662SDaniel Vetter break; 663f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 664d8d9abcdSDaniel Vetter stolen_size = MB(384); 665f51b7662SDaniel Vetter break; 666f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 667d8d9abcdSDaniel Vetter stolen_size = MB(416); 668f51b7662SDaniel Vetter break; 669f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 670d8d9abcdSDaniel Vetter stolen_size = MB(448); 671f51b7662SDaniel Vetter break; 672f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 673d8d9abcdSDaniel Vetter stolen_size = MB(480); 674f51b7662SDaniel Vetter break; 675f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 676d8d9abcdSDaniel Vetter stolen_size = MB(512); 677f51b7662SDaniel Vetter break; 678f51b7662SDaniel Vetter } 679f51b7662SDaniel Vetter } else { 680f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 681f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 682d8d9abcdSDaniel Vetter stolen_size = MB(1); 683f51b7662SDaniel Vetter break; 684f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 685d8d9abcdSDaniel Vetter stolen_size = MB(4); 686f51b7662SDaniel Vetter break; 687f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 688d8d9abcdSDaniel Vetter stolen_size = MB(8); 689f51b7662SDaniel Vetter break; 690f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 691d8d9abcdSDaniel Vetter stolen_size = MB(16); 692f51b7662SDaniel Vetter break; 693f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 694d8d9abcdSDaniel Vetter stolen_size = MB(32); 695f51b7662SDaniel Vetter break; 696f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 697d8d9abcdSDaniel Vetter stolen_size = MB(48); 698f51b7662SDaniel Vetter break; 699f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 700d8d9abcdSDaniel Vetter stolen_size = MB(64); 701f51b7662SDaniel Vetter break; 702f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 703d8d9abcdSDaniel Vetter stolen_size = MB(128); 704f51b7662SDaniel Vetter break; 705f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 706d8d9abcdSDaniel Vetter stolen_size = MB(256); 707f51b7662SDaniel Vetter break; 708f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 709d8d9abcdSDaniel Vetter stolen_size = MB(96); 710f51b7662SDaniel Vetter break; 711f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 712d8d9abcdSDaniel Vetter stolen_size = MB(160); 713f51b7662SDaniel Vetter break; 714f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 715d8d9abcdSDaniel Vetter stolen_size = MB(224); 716f51b7662SDaniel Vetter break; 717f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 718d8d9abcdSDaniel Vetter stolen_size = MB(352); 719f51b7662SDaniel Vetter break; 720f51b7662SDaniel Vetter default: 721d8d9abcdSDaniel Vetter stolen_size = 0; 722f51b7662SDaniel Vetter break; 723f51b7662SDaniel Vetter } 724f51b7662SDaniel Vetter } 7251784a5fbSDaniel Vetter 726d8d9abcdSDaniel Vetter if (!local && stolen_size > intel_max_stolen) { 727d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 728d1d6ca73SJesse Barnes "detected %dK stolen memory, trimming to %dK\n", 729d8d9abcdSDaniel Vetter stolen_size / KB(1), intel_max_stolen / KB(1)); 730d8d9abcdSDaniel Vetter stolen_size = intel_max_stolen; 731d8d9abcdSDaniel Vetter } else if (stolen_size > 0) { 732d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 733d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 734f51b7662SDaniel Vetter } else { 735d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 736f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 737d8d9abcdSDaniel Vetter stolen_size = 0; 738f51b7662SDaniel Vetter } 739f51b7662SDaniel Vetter 740d8d9abcdSDaniel Vetter stolen_entries = stolen_size/KB(4) - overhead_entries; 741d8d9abcdSDaniel Vetter 742d8d9abcdSDaniel Vetter return stolen_entries; 743f51b7662SDaniel Vetter } 744f51b7662SDaniel Vetter 745fbe40783SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 746fbe40783SDaniel Vetter { 747fbe40783SDaniel Vetter int size; 748fbe40783SDaniel Vetter 749210b23c2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { 750fbe40783SDaniel Vetter u32 pgetbl_ctl; 751fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 752fbe40783SDaniel Vetter 753fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 754fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 755e5e408fcSDaniel Vetter size = KB(128); 756fbe40783SDaniel Vetter break; 757fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 758e5e408fcSDaniel Vetter size = KB(256); 759fbe40783SDaniel Vetter break; 760fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 761e5e408fcSDaniel Vetter size = KB(512); 762fbe40783SDaniel Vetter break; 763fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 764e5e408fcSDaniel Vetter size = KB(1024); 765fbe40783SDaniel Vetter break; 766fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 767e5e408fcSDaniel Vetter size = KB(2048); 768fbe40783SDaniel Vetter break; 769fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 770e5e408fcSDaniel Vetter size = KB(1024 + 512); 771fbe40783SDaniel Vetter break; 772fbe40783SDaniel Vetter default: 773fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 774fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 775e5e408fcSDaniel Vetter size = KB(512); 776fbe40783SDaniel Vetter } 777e5e408fcSDaniel Vetter 778e5e408fcSDaniel Vetter return size/4; 779210b23c2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 780210b23c2SDaniel Vetter u16 snb_gmch_ctl; 781210b23c2SDaniel Vetter 782210b23c2SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 783210b23c2SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 784210b23c2SDaniel Vetter default: 785210b23c2SDaniel Vetter case SNB_GTT_SIZE_0M: 786210b23c2SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 787210b23c2SDaniel Vetter size = MB(0); 788210b23c2SDaniel Vetter break; 789210b23c2SDaniel Vetter case SNB_GTT_SIZE_1M: 790210b23c2SDaniel Vetter size = MB(1); 791210b23c2SDaniel Vetter break; 792210b23c2SDaniel Vetter case SNB_GTT_SIZE_2M: 793210b23c2SDaniel Vetter size = MB(2); 794210b23c2SDaniel Vetter break; 795210b23c2SDaniel Vetter } 796210b23c2SDaniel Vetter return size/4; 797fbe40783SDaniel Vetter } else { 798fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 799fbe40783SDaniel Vetter * required to map the aperture. 800fbe40783SDaniel Vetter */ 801e5e408fcSDaniel Vetter return intel_private.base.gtt_mappable_entries; 802fbe40783SDaniel Vetter } 803fbe40783SDaniel Vetter } 804fbe40783SDaniel Vetter 8051784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 8061784a5fbSDaniel Vetter { 8071784a5fbSDaniel Vetter unsigned int aperture_size; 8081784a5fbSDaniel Vetter 809b1c5b0f8SChris Wilson if (INTEL_GTT_GEN == 2) { 810b1c5b0f8SChris Wilson u16 gmch_ctrl; 8111784a5fbSDaniel Vetter 8121784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 8131784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 8141784a5fbSDaniel Vetter 8151784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 816b1c5b0f8SChris Wilson aperture_size = MB(64); 8171784a5fbSDaniel Vetter else 818b1c5b0f8SChris Wilson aperture_size = MB(128); 819239918f7SDaniel Vetter } else { 8201784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 8211784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 8221784a5fbSDaniel Vetter } 8231784a5fbSDaniel Vetter 8241784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 8251784a5fbSDaniel Vetter } 8261784a5fbSDaniel Vetter 8270e87d2b0SDaniel Vetter static void intel_gtt_teardown_scratch_page(void) 8280e87d2b0SDaniel Vetter { 8290e87d2b0SDaniel Vetter set_pages_wb(intel_private.scratch_page, 1); 8300e87d2b0SDaniel Vetter pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 8310e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 8320e87d2b0SDaniel Vetter put_page(intel_private.scratch_page); 8330e87d2b0SDaniel Vetter __free_page(intel_private.scratch_page); 8340e87d2b0SDaniel Vetter } 8350e87d2b0SDaniel Vetter 8360e87d2b0SDaniel Vetter static void intel_gtt_cleanup(void) 8370e87d2b0SDaniel Vetter { 8380e87d2b0SDaniel Vetter if (intel_private.i9xx_flush_page) 8390e87d2b0SDaniel Vetter iounmap(intel_private.i9xx_flush_page); 8400e87d2b0SDaniel Vetter if (intel_private.resource_valid) 8410e87d2b0SDaniel Vetter release_resource(&intel_private.ifp_resource); 8420e87d2b0SDaniel Vetter intel_private.ifp_resource.start = 0; 8430e87d2b0SDaniel Vetter intel_private.resource_valid = 0; 8440e87d2b0SDaniel Vetter iounmap(intel_private.gtt); 8450e87d2b0SDaniel Vetter iounmap(intel_private.registers); 8460e87d2b0SDaniel Vetter 8470e87d2b0SDaniel Vetter intel_gtt_teardown_scratch_page(); 8480e87d2b0SDaniel Vetter } 8490e87d2b0SDaniel Vetter 8501784a5fbSDaniel Vetter static int intel_gtt_init(void) 8511784a5fbSDaniel Vetter { 852f67eab66SDaniel Vetter u32 gtt_map_size; 8533b15a9d7SDaniel Vetter int ret; 8543b15a9d7SDaniel Vetter 8553b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 8563b15a9d7SDaniel Vetter if (ret != 0) 8573b15a9d7SDaniel Vetter return ret; 858f67eab66SDaniel Vetter 859f67eab66SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 860f67eab66SDaniel Vetter intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 861f67eab66SDaniel Vetter 862f67eab66SDaniel Vetter gtt_map_size = intel_private.base.gtt_total_entries * 4; 863f67eab66SDaniel Vetter 864f67eab66SDaniel Vetter intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 865f67eab66SDaniel Vetter gtt_map_size); 866f67eab66SDaniel Vetter if (!intel_private.gtt) { 867f67eab66SDaniel Vetter iounmap(intel_private.registers); 868f67eab66SDaniel Vetter return -ENOMEM; 869f67eab66SDaniel Vetter } 870f67eab66SDaniel Vetter 871f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 872f67eab66SDaniel Vetter 8731784a5fbSDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 8741784a5fbSDaniel Vetter intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); 8751784a5fbSDaniel Vetter if (intel_private.base.gtt_stolen_entries == 0) { 8761784a5fbSDaniel Vetter iounmap(intel_private.registers); 877f67eab66SDaniel Vetter iounmap(intel_private.gtt); 8781784a5fbSDaniel Vetter return -ENOMEM; 8791784a5fbSDaniel Vetter } 8801784a5fbSDaniel Vetter 8810e87d2b0SDaniel Vetter ret = intel_gtt_setup_scratch_page(); 8820e87d2b0SDaniel Vetter if (ret != 0) { 8830e87d2b0SDaniel Vetter intel_gtt_cleanup(); 8840e87d2b0SDaniel Vetter return ret; 8850e87d2b0SDaniel Vetter } 8860e87d2b0SDaniel Vetter 8871784a5fbSDaniel Vetter return 0; 8881784a5fbSDaniel Vetter } 8891784a5fbSDaniel Vetter 8903e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 8913e921f98SDaniel Vetter { 8929e76e7b8SChris Wilson int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 8933e921f98SDaniel Vetter unsigned int aper_size; 8943e921f98SDaniel Vetter int i; 8953e921f98SDaniel Vetter 8963e921f98SDaniel Vetter aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 8973e921f98SDaniel Vetter / MB(1); 8983e921f98SDaniel Vetter 8993e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 900ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 9019e76e7b8SChris Wilson agp_bridge->current_size = 9029e76e7b8SChris Wilson (void *) (intel_fake_agp_sizes + i); 9033e921f98SDaniel Vetter return aper_size; 9043e921f98SDaniel Vetter } 9053e921f98SDaniel Vetter } 9063e921f98SDaniel Vetter 9073e921f98SDaniel Vetter return 0; 9083e921f98SDaniel Vetter } 9093e921f98SDaniel Vetter 910f51b7662SDaniel Vetter static void intel_i830_fini_flush(void) 911f51b7662SDaniel Vetter { 912f51b7662SDaniel Vetter kunmap(intel_private.i8xx_page); 913f51b7662SDaniel Vetter intel_private.i8xx_flush_page = NULL; 914f51b7662SDaniel Vetter unmap_page_from_agp(intel_private.i8xx_page); 915f51b7662SDaniel Vetter 916f51b7662SDaniel Vetter __free_page(intel_private.i8xx_page); 917f51b7662SDaniel Vetter intel_private.i8xx_page = NULL; 918f51b7662SDaniel Vetter } 919f51b7662SDaniel Vetter 920f51b7662SDaniel Vetter static void intel_i830_setup_flush(void) 921f51b7662SDaniel Vetter { 922f51b7662SDaniel Vetter /* return if we've already set the flush mechanism up */ 923f51b7662SDaniel Vetter if (intel_private.i8xx_page) 924f51b7662SDaniel Vetter return; 925f51b7662SDaniel Vetter 926f51b7662SDaniel Vetter intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 927f51b7662SDaniel Vetter if (!intel_private.i8xx_page) 928f51b7662SDaniel Vetter return; 929f51b7662SDaniel Vetter 930f51b7662SDaniel Vetter intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 931f51b7662SDaniel Vetter if (!intel_private.i8xx_flush_page) 932f51b7662SDaniel Vetter intel_i830_fini_flush(); 933f51b7662SDaniel Vetter } 934f51b7662SDaniel Vetter 935f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 936f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 937f51b7662SDaniel Vetter * doesn't snoop those buffers. 938f51b7662SDaniel Vetter * 939f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 940f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 941f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 942f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 943f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 944f51b7662SDaniel Vetter */ 945f51b7662SDaniel Vetter static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 946f51b7662SDaniel Vetter { 947f51b7662SDaniel Vetter unsigned int *pg = intel_private.i8xx_flush_page; 948f51b7662SDaniel Vetter 949f51b7662SDaniel Vetter memset(pg, 0, 1024); 950f51b7662SDaniel Vetter 951f51b7662SDaniel Vetter if (cpu_has_clflush) 952f51b7662SDaniel Vetter clflush_cache_range(pg, 1024); 953f51b7662SDaniel Vetter else if (wbinvd_on_all_cpus() != 0) 954f51b7662SDaniel Vetter printk(KERN_ERR "Timed out waiting for cache flush.\n"); 955f51b7662SDaniel Vetter } 956f51b7662SDaniel Vetter 95773800422SDaniel Vetter static void intel_enable_gtt(void) 95873800422SDaniel Vetter { 9593f08e4efSChris Wilson u32 gma_addr; 96073800422SDaniel Vetter u16 gmch_ctrl; 96173800422SDaniel Vetter 9622d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 2) 9632d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 9642d2430cfSDaniel Vetter &gma_addr); 9652d2430cfSDaniel Vetter else 9662d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 9672d2430cfSDaniel Vetter &gma_addr); 9682d2430cfSDaniel Vetter 96973800422SDaniel Vetter intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 97073800422SDaniel Vetter 97173800422SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); 97273800422SDaniel Vetter gmch_ctrl |= I830_GMCH_ENABLED; 97373800422SDaniel Vetter pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); 97473800422SDaniel Vetter 9753f08e4efSChris Wilson writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED, 9763f08e4efSChris Wilson intel_private.registers+I810_PGETBL_CTL); 97773800422SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 97873800422SDaniel Vetter } 97973800422SDaniel Vetter 98073800422SDaniel Vetter static int i830_setup(void) 98173800422SDaniel Vetter { 98273800422SDaniel Vetter u32 reg_addr; 98373800422SDaniel Vetter 98473800422SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 98573800422SDaniel Vetter reg_addr &= 0xfff80000; 98673800422SDaniel Vetter 98773800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 98873800422SDaniel Vetter if (!intel_private.registers) 98973800422SDaniel Vetter return -ENOMEM; 99073800422SDaniel Vetter 99173800422SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 9923f08e4efSChris Wilson intel_private.pte_bus_addr = 9933f08e4efSChris Wilson readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 99473800422SDaniel Vetter 99573800422SDaniel Vetter intel_i830_setup_flush(); 99673800422SDaniel Vetter 99773800422SDaniel Vetter return 0; 99873800422SDaniel Vetter } 99973800422SDaniel Vetter 10003b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 1001f51b7662SDaniel Vetter { 100273800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 1003f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 100473800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 1005f51b7662SDaniel Vetter 1006f51b7662SDaniel Vetter return 0; 1007f51b7662SDaniel Vetter } 1008f51b7662SDaniel Vetter 1009ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 1010f51b7662SDaniel Vetter { 1011f51b7662SDaniel Vetter return 0; 1012f51b7662SDaniel Vetter } 1013f51b7662SDaniel Vetter 1014f51b7662SDaniel Vetter static int intel_i830_configure(void) 1015f51b7662SDaniel Vetter { 1016f51b7662SDaniel Vetter int i; 1017f51b7662SDaniel Vetter 101873800422SDaniel Vetter intel_enable_gtt(); 1019f51b7662SDaniel Vetter 102073800422SDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1021f51b7662SDaniel Vetter 1022f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 102373800422SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; 102473800422SDaniel Vetter i < intel_private.base.gtt_total_entries; i++) { 1025fdfb58a9SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1026f51b7662SDaniel Vetter } 1027fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1028f51b7662SDaniel Vetter } 1029f51b7662SDaniel Vetter 1030f51b7662SDaniel Vetter global_cache_flush(); 1031f51b7662SDaniel Vetter 1032f51b7662SDaniel Vetter return 0; 1033f51b7662SDaniel Vetter } 1034f51b7662SDaniel Vetter 1035f51b7662SDaniel Vetter static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 1036f51b7662SDaniel Vetter int type) 1037f51b7662SDaniel Vetter { 1038f51b7662SDaniel Vetter int i, j, num_entries; 1039f51b7662SDaniel Vetter void *temp; 1040f51b7662SDaniel Vetter int ret = -EINVAL; 1041f51b7662SDaniel Vetter int mask_type; 1042f51b7662SDaniel Vetter 1043f51b7662SDaniel Vetter if (mem->page_count == 0) 1044f51b7662SDaniel Vetter goto out; 1045f51b7662SDaniel Vetter 1046f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1047f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1048f51b7662SDaniel Vetter 10490ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1050f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 10510ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 10520ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1053f51b7662SDaniel Vetter 1054f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1055f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1056f51b7662SDaniel Vetter goto out_err; 1057f51b7662SDaniel Vetter } 1058f51b7662SDaniel Vetter 1059f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1060f51b7662SDaniel Vetter goto out_err; 1061f51b7662SDaniel Vetter 1062f51b7662SDaniel Vetter /* The i830 can't check the GTT for entries since its read only, 1063f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1064f51b7662SDaniel Vetter */ 1065f51b7662SDaniel Vetter 1066f51b7662SDaniel Vetter if (type != mem->type) 1067f51b7662SDaniel Vetter goto out_err; 1068f51b7662SDaniel Vetter 1069f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1070f51b7662SDaniel Vetter 1071f51b7662SDaniel Vetter if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1072f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1073f51b7662SDaniel Vetter goto out_err; 1074f51b7662SDaniel Vetter 1075f51b7662SDaniel Vetter if (!mem->is_flushed) 1076f51b7662SDaniel Vetter global_cache_flush(); 1077f51b7662SDaniel Vetter 1078f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1079f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 1080f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 1081fdfb58a9SDaniel Vetter intel_private.gtt+j); 1082f51b7662SDaniel Vetter } 1083fdfb58a9SDaniel Vetter readl(intel_private.gtt+j-1); 1084f51b7662SDaniel Vetter 1085f51b7662SDaniel Vetter out: 1086f51b7662SDaniel Vetter ret = 0; 1087f51b7662SDaniel Vetter out_err: 1088f51b7662SDaniel Vetter mem->is_flushed = true; 1089f51b7662SDaniel Vetter return ret; 1090f51b7662SDaniel Vetter } 1091f51b7662SDaniel Vetter 1092f51b7662SDaniel Vetter static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1093f51b7662SDaniel Vetter int type) 1094f51b7662SDaniel Vetter { 1095f51b7662SDaniel Vetter int i; 1096f51b7662SDaniel Vetter 1097f51b7662SDaniel Vetter if (mem->page_count == 0) 1098f51b7662SDaniel Vetter return 0; 1099f51b7662SDaniel Vetter 11000ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1101f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1102f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1103f51b7662SDaniel Vetter return -EINVAL; 1104f51b7662SDaniel Vetter } 1105f51b7662SDaniel Vetter 1106f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1107fdfb58a9SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1108f51b7662SDaniel Vetter } 1109fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 1110f51b7662SDaniel Vetter 1111f51b7662SDaniel Vetter return 0; 1112f51b7662SDaniel Vetter } 1113f51b7662SDaniel Vetter 1114ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1115ffdd7510SDaniel Vetter int type) 1116f51b7662SDaniel Vetter { 1117f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 1118f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 1119f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 1120f51b7662SDaniel Vetter return NULL; 1121f51b7662SDaniel Vetter } 1122f51b7662SDaniel Vetter 1123f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 1124f51b7662SDaniel Vetter { 1125f51b7662SDaniel Vetter int ret; 1126d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1127f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1128d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 1129f51b7662SDaniel Vetter 1130f51b7662SDaniel Vetter return ret; 1131f51b7662SDaniel Vetter } 1132f51b7662SDaniel Vetter 1133f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 1134f51b7662SDaniel Vetter { 1135f51b7662SDaniel Vetter int ret; 1136f51b7662SDaniel Vetter u32 temp; 1137f51b7662SDaniel Vetter 1138d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1139f51b7662SDaniel Vetter if (!(temp & 0x1)) { 1140f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1141f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1142d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1143f51b7662SDaniel Vetter } else { 1144f51b7662SDaniel Vetter temp &= ~1; 1145f51b7662SDaniel Vetter 1146f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1147f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1148f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1149f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1150f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1151f51b7662SDaniel Vetter if (ret) 1152f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1153f51b7662SDaniel Vetter } 1154f51b7662SDaniel Vetter } 1155f51b7662SDaniel Vetter 1156f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1157f51b7662SDaniel Vetter { 1158f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1159f51b7662SDaniel Vetter int ret; 1160f51b7662SDaniel Vetter 1161d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1162d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1163f51b7662SDaniel Vetter 1164f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1165f51b7662SDaniel Vetter 1166f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1167f51b7662SDaniel Vetter 1168f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1169d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1170f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1171d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1172f51b7662SDaniel Vetter } else { 1173f51b7662SDaniel Vetter u64 l64; 1174f51b7662SDaniel Vetter 1175f51b7662SDaniel Vetter temp_lo &= ~0x1; 1176f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1177f51b7662SDaniel Vetter 1178f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1179f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1180f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1181f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1182f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1183f51b7662SDaniel Vetter if (ret) 1184f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1185f51b7662SDaniel Vetter } 1186f51b7662SDaniel Vetter } 1187f51b7662SDaniel Vetter 1188f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1189f51b7662SDaniel Vetter { 1190f51b7662SDaniel Vetter /* return if already configured */ 1191f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1192f51b7662SDaniel Vetter return; 1193f51b7662SDaniel Vetter 11941a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1195f51b7662SDaniel Vetter return; 1196f51b7662SDaniel Vetter 1197f51b7662SDaniel Vetter /* setup a resource for this object */ 1198f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1199f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1200f51b7662SDaniel Vetter 1201f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 12021a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1203f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1204f51b7662SDaniel Vetter } else { 1205f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1206f51b7662SDaniel Vetter } 1207f51b7662SDaniel Vetter 1208df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1209f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1210f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1211df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1212df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1213f51b7662SDaniel Vetter } 1214f51b7662SDaniel Vetter 1215f1befe71SChris Wilson static int intel_i9xx_configure(void) 1216f51b7662SDaniel Vetter { 1217f51b7662SDaniel Vetter int i; 1218f51b7662SDaniel Vetter 12192d2430cfSDaniel Vetter intel_enable_gtt(); 1220f51b7662SDaniel Vetter 12212d2430cfSDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1222f51b7662SDaniel Vetter 1223f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 12240ade6386SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; i < 12250ade6386SDaniel Vetter intel_private.base.gtt_total_entries; i++) { 1226f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1227f51b7662SDaniel Vetter } 1228f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1229f51b7662SDaniel Vetter } 1230f51b7662SDaniel Vetter 1231f51b7662SDaniel Vetter global_cache_flush(); 1232f51b7662SDaniel Vetter 1233f51b7662SDaniel Vetter return 0; 1234f51b7662SDaniel Vetter } 1235f51b7662SDaniel Vetter 1236f51b7662SDaniel Vetter static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1237f51b7662SDaniel Vetter { 1238f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1239f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1240f51b7662SDaniel Vetter } 1241f51b7662SDaniel Vetter 1242f51b7662SDaniel Vetter static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1243f51b7662SDaniel Vetter int type) 1244f51b7662SDaniel Vetter { 1245f51b7662SDaniel Vetter int num_entries; 1246f51b7662SDaniel Vetter void *temp; 1247f51b7662SDaniel Vetter int ret = -EINVAL; 1248f51b7662SDaniel Vetter int mask_type; 1249f51b7662SDaniel Vetter 1250f51b7662SDaniel Vetter if (mem->page_count == 0) 1251f51b7662SDaniel Vetter goto out; 1252f51b7662SDaniel Vetter 1253f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1254f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1255f51b7662SDaniel Vetter 12560ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1257f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 12580ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 12590ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1260f51b7662SDaniel Vetter 1261f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1262f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1263f51b7662SDaniel Vetter goto out_err; 1264f51b7662SDaniel Vetter } 1265f51b7662SDaniel Vetter 1266f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1267f51b7662SDaniel Vetter goto out_err; 1268f51b7662SDaniel Vetter 1269f51b7662SDaniel Vetter /* The i915 can't check the GTT for entries since it's read only; 1270f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1271f51b7662SDaniel Vetter */ 1272f51b7662SDaniel Vetter 1273f51b7662SDaniel Vetter if (type != mem->type) 1274f51b7662SDaniel Vetter goto out_err; 1275f51b7662SDaniel Vetter 1276f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1277f51b7662SDaniel Vetter 12781a997ff2SDaniel Vetter if (INTEL_GTT_GEN != 6 && mask_type != 0 && 12791a997ff2SDaniel Vetter mask_type != AGP_PHYS_MEMORY && 1280f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1281f51b7662SDaniel Vetter goto out_err; 1282f51b7662SDaniel Vetter 1283f51b7662SDaniel Vetter if (!mem->is_flushed) 1284f51b7662SDaniel Vetter global_cache_flush(); 1285f51b7662SDaniel Vetter 1286f51b7662SDaniel Vetter intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1287f51b7662SDaniel Vetter 1288f51b7662SDaniel Vetter out: 1289f51b7662SDaniel Vetter ret = 0; 1290f51b7662SDaniel Vetter out_err: 1291f51b7662SDaniel Vetter mem->is_flushed = true; 1292f51b7662SDaniel Vetter return ret; 1293f51b7662SDaniel Vetter } 1294f51b7662SDaniel Vetter 1295f51b7662SDaniel Vetter static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1296f51b7662SDaniel Vetter int type) 1297f51b7662SDaniel Vetter { 1298f51b7662SDaniel Vetter int i; 1299f51b7662SDaniel Vetter 1300f51b7662SDaniel Vetter if (mem->page_count == 0) 1301f51b7662SDaniel Vetter return 0; 1302f51b7662SDaniel Vetter 13030ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1304f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1305f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1306f51b7662SDaniel Vetter return -EINVAL; 1307f51b7662SDaniel Vetter } 1308f51b7662SDaniel Vetter 1309f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) 1310f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1311f51b7662SDaniel Vetter 1312f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); 1313f51b7662SDaniel Vetter 1314f51b7662SDaniel Vetter return 0; 1315f51b7662SDaniel Vetter } 1316f51b7662SDaniel Vetter 13172d2430cfSDaniel Vetter static int i9xx_setup(void) 13182d2430cfSDaniel Vetter { 13192d2430cfSDaniel Vetter u32 reg_addr; 13202d2430cfSDaniel Vetter 13212d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 13222d2430cfSDaniel Vetter 13232d2430cfSDaniel Vetter reg_addr &= 0xfff80000; 13242d2430cfSDaniel Vetter 13252d2430cfSDaniel Vetter intel_private.registers = ioremap(reg_addr, 128 * 4096); 13262d2430cfSDaniel Vetter if (!intel_private.registers) 13272d2430cfSDaniel Vetter return -ENOMEM; 13282d2430cfSDaniel Vetter 13292d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 3) { 13302d2430cfSDaniel Vetter u32 gtt_addr; 13313f08e4efSChris Wilson 13322d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, 13332d2430cfSDaniel Vetter I915_PTEADDR, >t_addr); 13342d2430cfSDaniel Vetter intel_private.gtt_bus_addr = gtt_addr; 13352d2430cfSDaniel Vetter } else { 13362d2430cfSDaniel Vetter u32 gtt_offset; 13372d2430cfSDaniel Vetter 13382d2430cfSDaniel Vetter switch (INTEL_GTT_GEN) { 13392d2430cfSDaniel Vetter case 5: 13402d2430cfSDaniel Vetter case 6: 13412d2430cfSDaniel Vetter gtt_offset = MB(2); 13422d2430cfSDaniel Vetter break; 13432d2430cfSDaniel Vetter case 4: 13442d2430cfSDaniel Vetter default: 13452d2430cfSDaniel Vetter gtt_offset = KB(512); 13462d2430cfSDaniel Vetter break; 13472d2430cfSDaniel Vetter } 13482d2430cfSDaniel Vetter intel_private.gtt_bus_addr = reg_addr + gtt_offset; 13492d2430cfSDaniel Vetter } 13502d2430cfSDaniel Vetter 13513f08e4efSChris Wilson intel_private.pte_bus_addr = 13523f08e4efSChris Wilson readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 13533f08e4efSChris Wilson 13542d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 13552d2430cfSDaniel Vetter 13562d2430cfSDaniel Vetter return 0; 13572d2430cfSDaniel Vetter } 13582d2430cfSDaniel Vetter 1359f51b7662SDaniel Vetter /* 1360f51b7662SDaniel Vetter * The i965 supports 36-bit physical addresses, but to keep 1361f51b7662SDaniel Vetter * the format of the GTT the same, the bits that don't fit 1362f51b7662SDaniel Vetter * in a 32-bit word are shifted down to bits 4..7. 1363f51b7662SDaniel Vetter * 1364f51b7662SDaniel Vetter * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1365f51b7662SDaniel Vetter * is always zero on 32-bit architectures, so no need to make 1366f51b7662SDaniel Vetter * this conditional. 1367f51b7662SDaniel Vetter */ 1368f51b7662SDaniel Vetter static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1369f51b7662SDaniel Vetter dma_addr_t addr, int type) 1370f51b7662SDaniel Vetter { 1371f51b7662SDaniel Vetter /* Shift high bits down */ 1372f51b7662SDaniel Vetter addr |= (addr >> 28) & 0xf0; 1373f51b7662SDaniel Vetter 1374f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 1375f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 1376f51b7662SDaniel Vetter } 1377f51b7662SDaniel Vetter 13783869d4a8SZhenyu Wang static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, 13793869d4a8SZhenyu Wang dma_addr_t addr, int type) 13803869d4a8SZhenyu Wang { 13818dfc2b14SZhenyu Wang /* gen6 has bit11-4 for physical addr bit39-32 */ 13828dfc2b14SZhenyu Wang addr |= (addr >> 28) & 0xff0; 13833869d4a8SZhenyu Wang 13843869d4a8SZhenyu Wang /* Type checking must be done elsewhere */ 13853869d4a8SZhenyu Wang return addr | bridge->driver->masks[type].mask; 13863869d4a8SZhenyu Wang } 13873869d4a8SZhenyu Wang 1388f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_810_driver = { 1389f51b7662SDaniel Vetter .owner = THIS_MODULE, 1390f51b7662SDaniel Vetter .aperture_sizes = intel_i810_sizes, 1391f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1392f51b7662SDaniel Vetter .num_aperture_sizes = 2, 1393f51b7662SDaniel Vetter .needs_scratch_page = true, 1394f51b7662SDaniel Vetter .configure = intel_i810_configure, 1395f51b7662SDaniel Vetter .fetch_size = intel_i810_fetch_size, 1396f51b7662SDaniel Vetter .cleanup = intel_i810_cleanup, 1397f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1398f51b7662SDaniel Vetter .masks = intel_i810_masks, 1399ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1400f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1401f51b7662SDaniel Vetter .create_gatt_table = agp_generic_create_gatt_table, 1402f51b7662SDaniel Vetter .free_gatt_table = agp_generic_free_gatt_table, 1403f51b7662SDaniel Vetter .insert_memory = intel_i810_insert_entries, 1404f51b7662SDaniel Vetter .remove_memory = intel_i810_remove_entries, 1405f51b7662SDaniel Vetter .alloc_by_type = intel_i810_alloc_by_type, 1406f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1407f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1408f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1409f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1410f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1411f51b7662SDaniel Vetter .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1412f51b7662SDaniel Vetter }; 1413f51b7662SDaniel Vetter 1414f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_830_driver = { 1415f51b7662SDaniel Vetter .owner = THIS_MODULE, 1416f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14179e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14189e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1419f51b7662SDaniel Vetter .needs_scratch_page = true, 1420f51b7662SDaniel Vetter .configure = intel_i830_configure, 14213e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1422fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1423f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1424f51b7662SDaniel Vetter .masks = intel_i810_masks, 1425ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1426f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14273b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1428ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1429f51b7662SDaniel Vetter .insert_memory = intel_i830_insert_entries, 1430f51b7662SDaniel Vetter .remove_memory = intel_i830_remove_entries, 1431ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1432f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1433f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1434f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1435f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1436f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1437f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1438f51b7662SDaniel Vetter .chipset_flush = intel_i830_chipset_flush, 1439f51b7662SDaniel Vetter }; 1440f51b7662SDaniel Vetter 1441f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_915_driver = { 1442f51b7662SDaniel Vetter .owner = THIS_MODULE, 1443f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14449e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14459e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1446f51b7662SDaniel Vetter .needs_scratch_page = true, 1447f1befe71SChris Wilson .configure = intel_i9xx_configure, 14483e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1449fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1450f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1451f51b7662SDaniel Vetter .masks = intel_i810_masks, 1452ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1453f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14543b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1455ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1456f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1457f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1458ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1459f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1460f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1461f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1462f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1463f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1464f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1465f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 14660e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1467f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1468f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1469f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1470f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1471f51b7662SDaniel Vetter #endif 1472f51b7662SDaniel Vetter }; 1473f51b7662SDaniel Vetter 1474f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_i965_driver = { 1475f51b7662SDaniel Vetter .owner = THIS_MODULE, 1476f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14779e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14789e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1479f51b7662SDaniel Vetter .needs_scratch_page = true, 1480f1befe71SChris Wilson .configure = intel_i9xx_configure, 14813e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1482fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1483f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1484f51b7662SDaniel Vetter .masks = intel_i810_masks, 1485ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1486f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14873b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1488ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1489f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1490f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1491ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1492f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1493f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1494f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1495f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1496f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1497f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1498f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 14990e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1500f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1501f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1502f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1503f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1504f51b7662SDaniel Vetter #endif 1505f51b7662SDaniel Vetter }; 1506f51b7662SDaniel Vetter 15073869d4a8SZhenyu Wang static const struct agp_bridge_driver intel_gen6_driver = { 15083869d4a8SZhenyu Wang .owner = THIS_MODULE, 15093869d4a8SZhenyu Wang .size_type = FIXED_APER_SIZE, 15109e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 15119e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 15123869d4a8SZhenyu Wang .needs_scratch_page = true, 15133869d4a8SZhenyu Wang .configure = intel_i9xx_configure, 15143e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1515fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 15163869d4a8SZhenyu Wang .mask_memory = intel_gen6_mask_memory, 1517f8f235e5SZhenyu Wang .masks = intel_gen6_masks, 1518ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 15193869d4a8SZhenyu Wang .cache_flush = global_cache_flush, 15203b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1521ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 15223869d4a8SZhenyu Wang .insert_memory = intel_i915_insert_entries, 15233869d4a8SZhenyu Wang .remove_memory = intel_i915_remove_entries, 1524ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 15253869d4a8SZhenyu Wang .free_by_type = intel_i810_free_by_type, 15263869d4a8SZhenyu Wang .agp_alloc_page = agp_generic_alloc_page, 15273869d4a8SZhenyu Wang .agp_alloc_pages = agp_generic_alloc_pages, 15283869d4a8SZhenyu Wang .agp_destroy_page = agp_generic_destroy_page, 15293869d4a8SZhenyu Wang .agp_destroy_pages = agp_generic_destroy_pages, 1530f8f235e5SZhenyu Wang .agp_type_to_mask_type = intel_gen6_type_to_mask_type, 15313869d4a8SZhenyu Wang .chipset_flush = intel_i915_chipset_flush, 15320e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 15333869d4a8SZhenyu Wang .agp_map_page = intel_agp_map_page, 15343869d4a8SZhenyu Wang .agp_unmap_page = intel_agp_unmap_page, 15353869d4a8SZhenyu Wang .agp_map_memory = intel_agp_map_memory, 15363869d4a8SZhenyu Wang .agp_unmap_memory = intel_agp_unmap_memory, 15373869d4a8SZhenyu Wang #endif 15383869d4a8SZhenyu Wang }; 15393869d4a8SZhenyu Wang 1540f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_g33_driver = { 1541f51b7662SDaniel Vetter .owner = THIS_MODULE, 1542f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 15439e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 15449e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1545f51b7662SDaniel Vetter .needs_scratch_page = true, 1546f1befe71SChris Wilson .configure = intel_i9xx_configure, 15473e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1548fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1549f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1550f51b7662SDaniel Vetter .masks = intel_i810_masks, 1551ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1552f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 15533b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1554ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1555f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1556f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1557ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1558f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1559f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1560f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1561f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1562f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1563f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1564f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 15650e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1566f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1567f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1568f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1569f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1570f51b7662SDaniel Vetter #endif 1571f51b7662SDaniel Vetter }; 157202c026ceSDaniel Vetter 15731a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 15741a997ff2SDaniel Vetter .gen = 2, 157573800422SDaniel Vetter .setup = i830_setup, 15761a997ff2SDaniel Vetter }; 15771a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 15781a997ff2SDaniel Vetter .gen = 3, 15792d2430cfSDaniel Vetter .setup = i9xx_setup, 15801a997ff2SDaniel Vetter }; 15811a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 15821a997ff2SDaniel Vetter .gen = 3, 15831a997ff2SDaniel Vetter .is_g33 = 1, 15842d2430cfSDaniel Vetter .setup = i9xx_setup, 15851a997ff2SDaniel Vetter }; 15861a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 15871a997ff2SDaniel Vetter .gen = 3, 15881a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 15892d2430cfSDaniel Vetter .setup = i9xx_setup, 15901a997ff2SDaniel Vetter }; 15911a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 15921a997ff2SDaniel Vetter .gen = 4, 15932d2430cfSDaniel Vetter .setup = i9xx_setup, 15941a997ff2SDaniel Vetter }; 15951a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 15961a997ff2SDaniel Vetter .gen = 5, 15972d2430cfSDaniel Vetter .setup = i9xx_setup, 15981a997ff2SDaniel Vetter }; 15991a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 16001a997ff2SDaniel Vetter .gen = 5, 16011a997ff2SDaniel Vetter .is_ironlake = 1, 16022d2430cfSDaniel Vetter .setup = i9xx_setup, 16031a997ff2SDaniel Vetter }; 16041a997ff2SDaniel Vetter static const struct intel_gtt_driver sandybridge_gtt_driver = { 16051a997ff2SDaniel Vetter .gen = 6, 16062d2430cfSDaniel Vetter .setup = i9xx_setup, 16071a997ff2SDaniel Vetter }; 16081a997ff2SDaniel Vetter 160902c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 161002c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 161102c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 161202c026ceSDaniel Vetter */ 161302c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 161402c026ceSDaniel Vetter unsigned int gmch_chip_id; 161502c026ceSDaniel Vetter char *name; 161602c026ceSDaniel Vetter const struct agp_bridge_driver *gmch_driver; 16171a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 161802c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 16191a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL}, 16201a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL}, 16211a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL}, 16221a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL}, 16231a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 16241a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16251a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 16261a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16271a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 16281a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16291a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 16301a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16311a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 16321a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16331a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 16341a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16351a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 16361a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16371a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 16381a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16391a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 16401a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16411a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 16421a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16431a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 16441a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16451a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 16461a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16471a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 16481a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16491a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 16501a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16511a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 16521a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16531a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 16541a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16551a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 16561a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16571a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 16581a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16591a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 16601a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16611a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 16621a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16631a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 16641a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16651a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 16661a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16671a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 16681a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16691a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 16701a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16711a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 16721a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16731a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 16741a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16751a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 16761a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 1677e9e5f8e8SChris Wilson { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1678e9e5f8e8SChris Wilson &intel_i965_driver , &g4x_gtt_driver }, 16791a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 16801a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 168102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 16821a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 168302c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 16841a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 168502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 16861a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 168702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 16881a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 168902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 16901a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 169102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 16921a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 169302c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 16941a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 169502c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 16961a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 169702c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 16981a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 169902c026ceSDaniel Vetter { 0, NULL, NULL } 170002c026ceSDaniel Vetter }; 170102c026ceSDaniel Vetter 170202c026ceSDaniel Vetter static int find_gmch(u16 device) 170302c026ceSDaniel Vetter { 170402c026ceSDaniel Vetter struct pci_dev *gmch_device; 170502c026ceSDaniel Vetter 170602c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 170702c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 170802c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 170902c026ceSDaniel Vetter device, gmch_device); 171002c026ceSDaniel Vetter } 171102c026ceSDaniel Vetter 171202c026ceSDaniel Vetter if (!gmch_device) 171302c026ceSDaniel Vetter return 0; 171402c026ceSDaniel Vetter 171502c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 171602c026ceSDaniel Vetter return 1; 171702c026ceSDaniel Vetter } 171802c026ceSDaniel Vetter 1719e2404e7cSDaniel Vetter int intel_gmch_probe(struct pci_dev *pdev, 172002c026ceSDaniel Vetter struct agp_bridge_data *bridge) 172102c026ceSDaniel Vetter { 172202c026ceSDaniel Vetter int i, mask; 172302c026ceSDaniel Vetter bridge->driver = NULL; 172402c026ceSDaniel Vetter 172502c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 172602c026ceSDaniel Vetter if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 172702c026ceSDaniel Vetter bridge->driver = 172802c026ceSDaniel Vetter intel_gtt_chipsets[i].gmch_driver; 17291a997ff2SDaniel Vetter intel_private.driver = 17301a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 173102c026ceSDaniel Vetter break; 173202c026ceSDaniel Vetter } 173302c026ceSDaniel Vetter } 173402c026ceSDaniel Vetter 173502c026ceSDaniel Vetter if (!bridge->driver) 173602c026ceSDaniel Vetter return 0; 173702c026ceSDaniel Vetter 173802c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 173902c026ceSDaniel Vetter bridge->dev = pdev; 174002c026ceSDaniel Vetter 1741d7cca2f7SDaniel Vetter intel_private.bridge_dev = pci_dev_get(pdev); 1742d7cca2f7SDaniel Vetter 174302c026ceSDaniel Vetter dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 174402c026ceSDaniel Vetter 174502c026ceSDaniel Vetter if (bridge->driver->mask_memory == intel_gen6_mask_memory) 174602c026ceSDaniel Vetter mask = 40; 174702c026ceSDaniel Vetter else if (bridge->driver->mask_memory == intel_i965_mask_memory) 174802c026ceSDaniel Vetter mask = 36; 174902c026ceSDaniel Vetter else 175002c026ceSDaniel Vetter mask = 32; 175102c026ceSDaniel Vetter 175202c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 175302c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 175402c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 175502c026ceSDaniel Vetter else 175602c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 175702c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 175802c026ceSDaniel Vetter 17591784a5fbSDaniel Vetter if (bridge->driver == &intel_810_driver) 17601784a5fbSDaniel Vetter return 1; 17611784a5fbSDaniel Vetter 17623b15a9d7SDaniel Vetter if (intel_gtt_init() != 0) 17633b15a9d7SDaniel Vetter return 0; 17641784a5fbSDaniel Vetter 176502c026ceSDaniel Vetter return 1; 176602c026ceSDaniel Vetter } 1767e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 176802c026ceSDaniel Vetter 176919966754SDaniel Vetter struct intel_gtt *intel_gtt_get(void) 177019966754SDaniel Vetter { 177119966754SDaniel Vetter return &intel_private.base; 177219966754SDaniel Vetter } 177319966754SDaniel Vetter EXPORT_SYMBOL(intel_gtt_get); 177419966754SDaniel Vetter 1775e2404e7cSDaniel Vetter void intel_gmch_remove(struct pci_dev *pdev) 177602c026ceSDaniel Vetter { 177702c026ceSDaniel Vetter if (intel_private.pcidev) 177802c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1779d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1780d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 178102c026ceSDaniel Vetter } 1782e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1783e2404e7cSDaniel Vetter 1784e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1785e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1786