1ff7cdd69SDaniel Vetter /* 2ff7cdd69SDaniel Vetter * Common Intel AGPGART and GTT definitions. 3ff7cdd69SDaniel Vetter */ 493f5f7f1SZhenyu Wang #ifndef _INTEL_AGP_H 593f5f7f1SZhenyu Wang #define _INTEL_AGP_H 6ff7cdd69SDaniel Vetter 7ff7cdd69SDaniel Vetter /* Intel registers */ 8ff7cdd69SDaniel Vetter #define INTEL_APSIZE 0xb4 9ff7cdd69SDaniel Vetter #define INTEL_ATTBASE 0xb8 10ff7cdd69SDaniel Vetter #define INTEL_AGPCTRL 0xb0 11ff7cdd69SDaniel Vetter #define INTEL_NBXCFG 0x50 12ff7cdd69SDaniel Vetter #define INTEL_ERRSTS 0x91 13ff7cdd69SDaniel Vetter 14ff7cdd69SDaniel Vetter /* Intel i830 registers */ 15ff7cdd69SDaniel Vetter #define I830_GMCH_CTRL 0x52 16ff7cdd69SDaniel Vetter #define I830_GMCH_ENABLED 0x4 17ff7cdd69SDaniel Vetter #define I830_GMCH_MEM_MASK 0x1 18ff7cdd69SDaniel Vetter #define I830_GMCH_MEM_64M 0x1 19ff7cdd69SDaniel Vetter #define I830_GMCH_MEM_128M 0 20ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_MASK 0x70 21ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_DISABLED 0x00 22ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_LOCAL 0x10 23ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_STOLEN_512 0x20 24ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_STOLEN_1024 0x30 25ff7cdd69SDaniel Vetter #define I830_GMCH_GMS_STOLEN_8192 0x40 26ff7cdd69SDaniel Vetter #define I830_RDRAM_CHANNEL_TYPE 0x03010 27ff7cdd69SDaniel Vetter #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) 28ff7cdd69SDaniel Vetter #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) 29ff7cdd69SDaniel Vetter 30ff7cdd69SDaniel Vetter /* This one is for I830MP w. an external graphic card */ 31ff7cdd69SDaniel Vetter #define INTEL_I830_ERRSTS 0x92 32ff7cdd69SDaniel Vetter 33ff7cdd69SDaniel Vetter /* Intel 855GM/852GM registers */ 34ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_MASK 0xF0 35ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_0M 0x0 36ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 37ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 38ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 39ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 40ff7cdd69SDaniel Vetter #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 41ff7cdd69SDaniel Vetter #define I85X_CAPID 0x44 42ff7cdd69SDaniel Vetter #define I85X_VARIANT_MASK 0x7 43ff7cdd69SDaniel Vetter #define I85X_VARIANT_SHIFT 5 44ff7cdd69SDaniel Vetter #define I855_GME 0x0 45ff7cdd69SDaniel Vetter #define I855_GM 0x4 46ff7cdd69SDaniel Vetter #define I852_GME 0x2 47ff7cdd69SDaniel Vetter #define I852_GM 0x5 48ff7cdd69SDaniel Vetter 49ff7cdd69SDaniel Vetter /* Intel i845 registers */ 50ff7cdd69SDaniel Vetter #define INTEL_I845_AGPM 0x51 51ff7cdd69SDaniel Vetter #define INTEL_I845_ERRSTS 0xc8 52ff7cdd69SDaniel Vetter 53ff7cdd69SDaniel Vetter /* Intel i860 registers */ 54ff7cdd69SDaniel Vetter #define INTEL_I860_MCHCFG 0x50 55ff7cdd69SDaniel Vetter #define INTEL_I860_ERRSTS 0xc8 56ff7cdd69SDaniel Vetter 57ff7cdd69SDaniel Vetter /* Intel i810 registers */ 58545b0a74SYinghai Lu #define I810_GMADR_BAR 0 59ff7cdd69SDaniel Vetter #define I810_MMADDR 0x14 60ff7cdd69SDaniel Vetter #define I810_PTE_BASE 0x10000 61ff7cdd69SDaniel Vetter #define I810_PTE_MAIN_UNCACHED 0x00000000 62ff7cdd69SDaniel Vetter #define I810_PTE_LOCAL 0x00000002 63ff7cdd69SDaniel Vetter #define I810_PTE_VALID 0x00000001 64ff7cdd69SDaniel Vetter #define I830_PTE_SYSTEM_CACHED 0x00000006 65a2757b6fSZhenyu Wang 66ff7cdd69SDaniel Vetter #define I810_SMRAM_MISCC 0x70 67ff7cdd69SDaniel Vetter #define I810_GFX_MEM_WIN_SIZE 0x00010000 68ff7cdd69SDaniel Vetter #define I810_GFX_MEM_WIN_32M 0x00010000 69ff7cdd69SDaniel Vetter #define I810_GMS 0x000000c0 70ff7cdd69SDaniel Vetter #define I810_GMS_DISABLE 0x00000000 71ff7cdd69SDaniel Vetter #define I810_PGETBL_CTL 0x2020 72ff7cdd69SDaniel Vetter #define I810_PGETBL_ENABLED 0x00000001 7320172842SDaniel Vetter /* Note: PGETBL_CTL2 has a different offset on G33. */ 7420172842SDaniel Vetter #define I965_PGETBL_CTL2 0x20c4 75ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_MASK 0x0000000e 76ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_512KB (0 << 1) 77ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_256KB (1 << 1) 78ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_128KB (2 << 1) 79ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_1MB (3 << 1) 80ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_2MB (4 << 1) 81ff7cdd69SDaniel Vetter #define I965_PGETBL_SIZE_1_5MB (5 << 1) 8220172842SDaniel Vetter #define G33_GMCH_SIZE_MASK (3 << 8) 8320172842SDaniel Vetter #define G33_GMCH_SIZE_1M (1 << 8) 8420172842SDaniel Vetter #define G33_GMCH_SIZE_2M (2 << 8) 8520172842SDaniel Vetter #define G4x_GMCH_SIZE_MASK (0xf << 8) 8620172842SDaniel Vetter #define G4x_GMCH_SIZE_1M (0x1 << 8) 8720172842SDaniel Vetter #define G4x_GMCH_SIZE_2M (0x3 << 8) 88780d7cc4SChris Wilson #define G4x_GMCH_SIZE_VT_EN (0x8 << 8) 89780d7cc4SChris Wilson #define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) 90780d7cc4SChris Wilson #define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) 91780d7cc4SChris Wilson #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) 92ff7cdd69SDaniel Vetter 93c97689d8SChris Wilson #define GFX_FLSH_CNTL 0x2170 /* 915+ */ 94c97689d8SChris Wilson 95ff7cdd69SDaniel Vetter #define I810_DRAM_CTL 0x3000 96ff7cdd69SDaniel Vetter #define I810_DRAM_ROW_0 0x00000001 97ff7cdd69SDaniel Vetter #define I810_DRAM_ROW_0_SDRAM 0x00000001 98ff7cdd69SDaniel Vetter 99ff7cdd69SDaniel Vetter /* Intel 815 register */ 100ff7cdd69SDaniel Vetter #define INTEL_815_APCONT 0x51 101ff7cdd69SDaniel Vetter #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 102ff7cdd69SDaniel Vetter 103ff7cdd69SDaniel Vetter /* Intel i820 registers */ 104ff7cdd69SDaniel Vetter #define INTEL_I820_RDCR 0x51 105ff7cdd69SDaniel Vetter #define INTEL_I820_ERRSTS 0xc8 106ff7cdd69SDaniel Vetter 107ff7cdd69SDaniel Vetter /* Intel i840 registers */ 108ff7cdd69SDaniel Vetter #define INTEL_I840_MCHCFG 0x50 109ff7cdd69SDaniel Vetter #define INTEL_I840_ERRSTS 0xc8 110ff7cdd69SDaniel Vetter 111ff7cdd69SDaniel Vetter /* Intel i850 registers */ 112ff7cdd69SDaniel Vetter #define INTEL_I850_MCHCFG 0x50 113ff7cdd69SDaniel Vetter #define INTEL_I850_ERRSTS 0xc8 114ff7cdd69SDaniel Vetter 115ff7cdd69SDaniel Vetter /* intel 915G registers */ 116545b0a74SYinghai Lu #define I915_GMADR_BAR 2 117ff7cdd69SDaniel Vetter #define I915_MMADDR 0x10 118ff7cdd69SDaniel Vetter #define I915_PTEADDR 0x1C 119ff7cdd69SDaniel Vetter #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 120ff7cdd69SDaniel Vetter #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 121ff7cdd69SDaniel Vetter #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 122ff7cdd69SDaniel Vetter #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 123ff7cdd69SDaniel Vetter #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 124ff7cdd69SDaniel Vetter #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 125ff7cdd69SDaniel Vetter #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 126ff7cdd69SDaniel Vetter #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 127ff7cdd69SDaniel Vetter 128ff7cdd69SDaniel Vetter #define I915_IFPADDR 0x60 129bdb8b975SChris Wilson #define I830_HIC 0x70 130ff7cdd69SDaniel Vetter 131ff7cdd69SDaniel Vetter /* Intel 965G registers */ 132ff7cdd69SDaniel Vetter #define I965_MSAC 0x62 133ff7cdd69SDaniel Vetter #define I965_IFPADDR 0x70 134ff7cdd69SDaniel Vetter 135ff7cdd69SDaniel Vetter /* Intel 7505 registers */ 136ff7cdd69SDaniel Vetter #define INTEL_I7505_APSIZE 0x74 137ff7cdd69SDaniel Vetter #define INTEL_I7505_NCAPID 0x60 138ff7cdd69SDaniel Vetter #define INTEL_I7505_NISTAT 0x6c 139ff7cdd69SDaniel Vetter #define INTEL_I7505_ATTBASE 0x78 140ff7cdd69SDaniel Vetter #define INTEL_I7505_ERRSTS 0x42 141ff7cdd69SDaniel Vetter #define INTEL_I7505_AGPCTRL 0x70 142ff7cdd69SDaniel Vetter #define INTEL_I7505_MCHCFG 0x50 143ff7cdd69SDaniel Vetter 144ff7cdd69SDaniel Vetter /* pci devices ids */ 145ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 146ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 147ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 148ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 149ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 150ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 151ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 152ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 153ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 154ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 155ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 156ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 157ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 158ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 159ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 160ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 161ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 162ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 163ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 164ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 165ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 166ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 167ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 168ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 169ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 170ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 171ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 172ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 17341a51428SChris Wilson #define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90 17441a51428SChris Wilson #define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92 175ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 176ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 177ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 178ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 179ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 180ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 181ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 182ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 183ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 184ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 185ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 18667384fe3SEugeni Dodonov #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069 187ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 188ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 189ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 190ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a 191ff7cdd69SDaniel Vetter #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 192ff7cdd69SDaniel Vetter 19393f5f7f1SZhenyu Wang #endif 194