1 /* 2 * Intel AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/pagemap.h> 10 #include <linux/agp_backend.h> 11 #include "agp.h" 12 13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 17 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 18 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 35 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 36 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 37 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 38 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 39 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 40 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 41 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 42 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 43 44 /* cover 915 and 945 variants */ 45 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 46 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 51 52 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 53 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 54 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 58 59 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 62 63 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ 64 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB) 67 68 extern int agp_memory_reserved; 69 70 71 /* Intel 815 register */ 72 #define INTEL_815_APCONT 0x51 73 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 74 75 /* Intel i820 registers */ 76 #define INTEL_I820_RDCR 0x51 77 #define INTEL_I820_ERRSTS 0xc8 78 79 /* Intel i840 registers */ 80 #define INTEL_I840_MCHCFG 0x50 81 #define INTEL_I840_ERRSTS 0xc8 82 83 /* Intel i850 registers */ 84 #define INTEL_I850_MCHCFG 0x50 85 #define INTEL_I850_ERRSTS 0xc8 86 87 /* intel 915G registers */ 88 #define I915_GMADDR 0x18 89 #define I915_MMADDR 0x10 90 #define I915_PTEADDR 0x1C 91 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 92 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 93 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 94 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 95 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 96 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 97 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 98 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 99 100 #define I915_IFPADDR 0x60 101 102 /* Intel 965G registers */ 103 #define I965_MSAC 0x62 104 #define I965_IFPADDR 0x70 105 106 /* Intel 7505 registers */ 107 #define INTEL_I7505_APSIZE 0x74 108 #define INTEL_I7505_NCAPID 0x60 109 #define INTEL_I7505_NISTAT 0x6c 110 #define INTEL_I7505_ATTBASE 0x78 111 #define INTEL_I7505_ERRSTS 0x42 112 #define INTEL_I7505_AGPCTRL 0x70 113 #define INTEL_I7505_MCHCFG 0x50 114 115 static const struct aper_size_info_fixed intel_i810_sizes[] = 116 { 117 {64, 16384, 4}, 118 /* The 32M mode still requires a 64k gatt */ 119 {32, 8192, 4} 120 }; 121 122 #define AGP_DCACHE_MEMORY 1 123 #define AGP_PHYS_MEMORY 2 124 #define INTEL_AGP_CACHED_MEMORY 3 125 126 static struct gatt_mask intel_i810_masks[] = 127 { 128 {.mask = I810_PTE_VALID, .type = 0}, 129 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 130 {.mask = I810_PTE_VALID, .type = 0}, 131 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 132 .type = INTEL_AGP_CACHED_MEMORY} 133 }; 134 135 static struct _intel_private { 136 struct pci_dev *pcidev; /* device one */ 137 u8 __iomem *registers; 138 u32 __iomem *gtt; /* I915G */ 139 int num_dcache_entries; 140 /* gtt_entries is the number of gtt entries that are already mapped 141 * to stolen memory. Stolen memory is larger than the memory mapped 142 * through gtt_entries, as it includes some reserved space for the BIOS 143 * popup and for the GTT. 144 */ 145 int gtt_entries; /* i830+ */ 146 union { 147 void __iomem *i9xx_flush_page; 148 void *i8xx_flush_page; 149 }; 150 struct page *i8xx_page; 151 struct resource ifp_resource; 152 int resource_valid; 153 } intel_private; 154 155 static int intel_i810_fetch_size(void) 156 { 157 u32 smram_miscc; 158 struct aper_size_info_fixed *values; 159 160 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 161 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 162 163 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 164 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 165 return 0; 166 } 167 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 168 agp_bridge->previous_size = 169 agp_bridge->current_size = (void *) (values + 1); 170 agp_bridge->aperture_size_idx = 1; 171 return values[1].size; 172 } else { 173 agp_bridge->previous_size = 174 agp_bridge->current_size = (void *) (values); 175 agp_bridge->aperture_size_idx = 0; 176 return values[0].size; 177 } 178 179 return 0; 180 } 181 182 static int intel_i810_configure(void) 183 { 184 struct aper_size_info_fixed *current_size; 185 u32 temp; 186 int i; 187 188 current_size = A_SIZE_FIX(agp_bridge->current_size); 189 190 if (!intel_private.registers) { 191 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 192 temp &= 0xfff80000; 193 194 intel_private.registers = ioremap(temp, 128 * 4096); 195 if (!intel_private.registers) { 196 dev_err(&intel_private.pcidev->dev, 197 "can't remap memory\n"); 198 return -ENOMEM; 199 } 200 } 201 202 if ((readl(intel_private.registers+I810_DRAM_CTL) 203 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 204 /* This will need to be dynamically assigned */ 205 dev_info(&intel_private.pcidev->dev, 206 "detected 4MB dedicated video ram\n"); 207 intel_private.num_dcache_entries = 1024; 208 } 209 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 210 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 211 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 212 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 213 214 if (agp_bridge->driver->needs_scratch_page) { 215 for (i = 0; i < current_size->num_entries; i++) { 216 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 217 } 218 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 219 } 220 global_cache_flush(); 221 return 0; 222 } 223 224 static void intel_i810_cleanup(void) 225 { 226 writel(0, intel_private.registers+I810_PGETBL_CTL); 227 readl(intel_private.registers); /* PCI Posting. */ 228 iounmap(intel_private.registers); 229 } 230 231 static void intel_i810_tlbflush(struct agp_memory *mem) 232 { 233 return; 234 } 235 236 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 237 { 238 return; 239 } 240 241 /* Exists to support ARGB cursors */ 242 static void *i8xx_alloc_pages(void) 243 { 244 struct page *page; 245 246 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 247 if (page == NULL) 248 return NULL; 249 250 if (set_pages_uc(page, 4) < 0) { 251 set_pages_wb(page, 4); 252 __free_pages(page, 2); 253 return NULL; 254 } 255 get_page(page); 256 atomic_inc(&agp_bridge->current_memory_agp); 257 return page_address(page); 258 } 259 260 static void i8xx_destroy_pages(void *addr) 261 { 262 struct page *page; 263 264 if (addr == NULL) 265 return; 266 267 page = virt_to_page(addr); 268 set_pages_wb(page, 4); 269 put_page(page); 270 __free_pages(page, 2); 271 atomic_dec(&agp_bridge->current_memory_agp); 272 } 273 274 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 275 int type) 276 { 277 if (type < AGP_USER_TYPES) 278 return type; 279 else if (type == AGP_USER_CACHED_MEMORY) 280 return INTEL_AGP_CACHED_MEMORY; 281 else 282 return 0; 283 } 284 285 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 286 int type) 287 { 288 int i, j, num_entries; 289 void *temp; 290 int ret = -EINVAL; 291 int mask_type; 292 293 if (mem->page_count == 0) 294 goto out; 295 296 temp = agp_bridge->current_size; 297 num_entries = A_SIZE_FIX(temp)->num_entries; 298 299 if ((pg_start + mem->page_count) > num_entries) 300 goto out_err; 301 302 303 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 304 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 305 ret = -EBUSY; 306 goto out_err; 307 } 308 } 309 310 if (type != mem->type) 311 goto out_err; 312 313 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 314 315 switch (mask_type) { 316 case AGP_DCACHE_MEMORY: 317 if (!mem->is_flushed) 318 global_cache_flush(); 319 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 320 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 321 intel_private.registers+I810_PTE_BASE+(i*4)); 322 } 323 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 324 break; 325 case AGP_PHYS_MEMORY: 326 case AGP_NORMAL_MEMORY: 327 if (!mem->is_flushed) 328 global_cache_flush(); 329 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 330 writel(agp_bridge->driver->mask_memory(agp_bridge, 331 mem->memory[i], 332 mask_type), 333 intel_private.registers+I810_PTE_BASE+(j*4)); 334 } 335 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 336 break; 337 default: 338 goto out_err; 339 } 340 341 agp_bridge->driver->tlb_flush(mem); 342 out: 343 ret = 0; 344 out_err: 345 mem->is_flushed = true; 346 return ret; 347 } 348 349 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 350 int type) 351 { 352 int i; 353 354 if (mem->page_count == 0) 355 return 0; 356 357 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 358 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 359 } 360 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 361 362 agp_bridge->driver->tlb_flush(mem); 363 return 0; 364 } 365 366 /* 367 * The i810/i830 requires a physical address to program its mouse 368 * pointer into hardware. 369 * However the Xserver still writes to it through the agp aperture. 370 */ 371 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 372 { 373 struct agp_memory *new; 374 void *addr; 375 376 switch (pg_count) { 377 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 378 break; 379 case 4: 380 /* kludge to get 4 physical pages for ARGB cursor */ 381 addr = i8xx_alloc_pages(); 382 break; 383 default: 384 return NULL; 385 } 386 387 if (addr == NULL) 388 return NULL; 389 390 new = agp_create_memory(pg_count); 391 if (new == NULL) 392 return NULL; 393 394 new->memory[0] = virt_to_gart(addr); 395 if (pg_count == 4) { 396 /* kludge to get 4 physical pages for ARGB cursor */ 397 new->memory[1] = new->memory[0] + PAGE_SIZE; 398 new->memory[2] = new->memory[1] + PAGE_SIZE; 399 new->memory[3] = new->memory[2] + PAGE_SIZE; 400 } 401 new->page_count = pg_count; 402 new->num_scratch_pages = pg_count; 403 new->type = AGP_PHYS_MEMORY; 404 new->physical = new->memory[0]; 405 return new; 406 } 407 408 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 409 { 410 struct agp_memory *new; 411 412 if (type == AGP_DCACHE_MEMORY) { 413 if (pg_count != intel_private.num_dcache_entries) 414 return NULL; 415 416 new = agp_create_memory(1); 417 if (new == NULL) 418 return NULL; 419 420 new->type = AGP_DCACHE_MEMORY; 421 new->page_count = pg_count; 422 new->num_scratch_pages = 0; 423 agp_free_page_array(new); 424 return new; 425 } 426 if (type == AGP_PHYS_MEMORY) 427 return alloc_agpphysmem_i8xx(pg_count, type); 428 return NULL; 429 } 430 431 static void intel_i810_free_by_type(struct agp_memory *curr) 432 { 433 agp_free_key(curr->key); 434 if (curr->type == AGP_PHYS_MEMORY) { 435 if (curr->page_count == 4) 436 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 437 else { 438 void *va = gart_to_virt(curr->memory[0]); 439 440 agp_bridge->driver->agp_destroy_page(va, 441 AGP_PAGE_DESTROY_UNMAP); 442 agp_bridge->driver->agp_destroy_page(va, 443 AGP_PAGE_DESTROY_FREE); 444 } 445 agp_free_page_array(curr); 446 } 447 kfree(curr); 448 } 449 450 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 451 unsigned long addr, int type) 452 { 453 /* Type checking must be done elsewhere */ 454 return addr | bridge->driver->masks[type].mask; 455 } 456 457 static struct aper_size_info_fixed intel_i830_sizes[] = 458 { 459 {128, 32768, 5}, 460 /* The 64M mode still requires a 128k gatt */ 461 {64, 16384, 5}, 462 {256, 65536, 6}, 463 {512, 131072, 7}, 464 }; 465 466 static void intel_i830_init_gtt_entries(void) 467 { 468 u16 gmch_ctrl; 469 int gtt_entries; 470 u8 rdct; 471 int local = 0; 472 static const int ddt[4] = { 0, 16, 32, 64 }; 473 int size; /* reserved space (in kb) at the top of stolen memory */ 474 475 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 476 477 if (IS_I965) { 478 u32 pgetbl_ctl; 479 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 480 481 /* The 965 has a field telling us the size of the GTT, 482 * which may be larger than what is necessary to map the 483 * aperture. 484 */ 485 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 486 case I965_PGETBL_SIZE_128KB: 487 size = 128; 488 break; 489 case I965_PGETBL_SIZE_256KB: 490 size = 256; 491 break; 492 case I965_PGETBL_SIZE_512KB: 493 size = 512; 494 break; 495 case I965_PGETBL_SIZE_1MB: 496 size = 1024; 497 break; 498 case I965_PGETBL_SIZE_2MB: 499 size = 2048; 500 break; 501 case I965_PGETBL_SIZE_1_5MB: 502 size = 1024 + 512; 503 break; 504 default: 505 dev_info(&intel_private.pcidev->dev, 506 "unknown page table size, assuming 512KB\n"); 507 size = 512; 508 } 509 size += 4; /* add in BIOS popup space */ 510 } else if (IS_G33) { 511 /* G33's GTT size defined in gmch_ctrl */ 512 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 513 case G33_PGETBL_SIZE_1M: 514 size = 1024; 515 break; 516 case G33_PGETBL_SIZE_2M: 517 size = 2048; 518 break; 519 default: 520 dev_info(&agp_bridge->dev->dev, 521 "unknown page table size 0x%x, assuming 512KB\n", 522 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 523 size = 512; 524 } 525 size += 4; 526 } else if (IS_G4X) { 527 /* On 4 series hardware, GTT stolen is separate from graphics 528 * stolen, ignore it in stolen gtt entries counting. However, 529 * 4KB of the stolen memory doesn't get mapped to the GTT. 530 */ 531 size = 4; 532 } else { 533 /* On previous hardware, the GTT size was just what was 534 * required to map the aperture. 535 */ 536 size = agp_bridge->driver->fetch_size() + 4; 537 } 538 539 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 540 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 541 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 542 case I830_GMCH_GMS_STOLEN_512: 543 gtt_entries = KB(512) - KB(size); 544 break; 545 case I830_GMCH_GMS_STOLEN_1024: 546 gtt_entries = MB(1) - KB(size); 547 break; 548 case I830_GMCH_GMS_STOLEN_8192: 549 gtt_entries = MB(8) - KB(size); 550 break; 551 case I830_GMCH_GMS_LOCAL: 552 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 553 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 554 MB(ddt[I830_RDRAM_DDT(rdct)]); 555 local = 1; 556 break; 557 default: 558 gtt_entries = 0; 559 break; 560 } 561 } else { 562 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 563 case I855_GMCH_GMS_STOLEN_1M: 564 gtt_entries = MB(1) - KB(size); 565 break; 566 case I855_GMCH_GMS_STOLEN_4M: 567 gtt_entries = MB(4) - KB(size); 568 break; 569 case I855_GMCH_GMS_STOLEN_8M: 570 gtt_entries = MB(8) - KB(size); 571 break; 572 case I855_GMCH_GMS_STOLEN_16M: 573 gtt_entries = MB(16) - KB(size); 574 break; 575 case I855_GMCH_GMS_STOLEN_32M: 576 gtt_entries = MB(32) - KB(size); 577 break; 578 case I915_GMCH_GMS_STOLEN_48M: 579 /* Check it's really I915G */ 580 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 581 gtt_entries = MB(48) - KB(size); 582 else 583 gtt_entries = 0; 584 break; 585 case I915_GMCH_GMS_STOLEN_64M: 586 /* Check it's really I915G */ 587 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 588 gtt_entries = MB(64) - KB(size); 589 else 590 gtt_entries = 0; 591 break; 592 case G33_GMCH_GMS_STOLEN_128M: 593 if (IS_G33 || IS_I965 || IS_G4X) 594 gtt_entries = MB(128) - KB(size); 595 else 596 gtt_entries = 0; 597 break; 598 case G33_GMCH_GMS_STOLEN_256M: 599 if (IS_G33 || IS_I965 || IS_G4X) 600 gtt_entries = MB(256) - KB(size); 601 else 602 gtt_entries = 0; 603 break; 604 case INTEL_GMCH_GMS_STOLEN_96M: 605 if (IS_I965 || IS_G4X) 606 gtt_entries = MB(96) - KB(size); 607 else 608 gtt_entries = 0; 609 break; 610 case INTEL_GMCH_GMS_STOLEN_160M: 611 if (IS_I965 || IS_G4X) 612 gtt_entries = MB(160) - KB(size); 613 else 614 gtt_entries = 0; 615 break; 616 case INTEL_GMCH_GMS_STOLEN_224M: 617 if (IS_I965 || IS_G4X) 618 gtt_entries = MB(224) - KB(size); 619 else 620 gtt_entries = 0; 621 break; 622 case INTEL_GMCH_GMS_STOLEN_352M: 623 if (IS_I965 || IS_G4X) 624 gtt_entries = MB(352) - KB(size); 625 else 626 gtt_entries = 0; 627 break; 628 default: 629 gtt_entries = 0; 630 break; 631 } 632 } 633 if (gtt_entries > 0) 634 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 635 gtt_entries / KB(1), local ? "local" : "stolen"); 636 else 637 dev_info(&agp_bridge->dev->dev, 638 "no pre-allocated video memory detected\n"); 639 gtt_entries /= KB(4); 640 641 intel_private.gtt_entries = gtt_entries; 642 } 643 644 static void intel_i830_fini_flush(void) 645 { 646 kunmap(intel_private.i8xx_page); 647 intel_private.i8xx_flush_page = NULL; 648 unmap_page_from_agp(intel_private.i8xx_page); 649 650 __free_page(intel_private.i8xx_page); 651 intel_private.i8xx_page = NULL; 652 } 653 654 static void intel_i830_setup_flush(void) 655 { 656 /* return if we've already set the flush mechanism up */ 657 if (intel_private.i8xx_page) 658 return; 659 660 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 661 if (!intel_private.i8xx_page) 662 return; 663 664 /* make page uncached */ 665 map_page_into_agp(intel_private.i8xx_page); 666 667 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 668 if (!intel_private.i8xx_flush_page) 669 intel_i830_fini_flush(); 670 } 671 672 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 673 { 674 unsigned int *pg = intel_private.i8xx_flush_page; 675 int i; 676 677 for (i = 0; i < 256; i += 2) 678 *(pg + i) = i; 679 680 wmb(); 681 } 682 683 /* The intel i830 automatically initializes the agp aperture during POST. 684 * Use the memory already set aside for in the GTT. 685 */ 686 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 687 { 688 int page_order; 689 struct aper_size_info_fixed *size; 690 int num_entries; 691 u32 temp; 692 693 size = agp_bridge->current_size; 694 page_order = size->page_order; 695 num_entries = size->num_entries; 696 agp_bridge->gatt_table_real = NULL; 697 698 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 699 temp &= 0xfff80000; 700 701 intel_private.registers = ioremap(temp, 128 * 4096); 702 if (!intel_private.registers) 703 return -ENOMEM; 704 705 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 706 global_cache_flush(); /* FIXME: ?? */ 707 708 /* we have to call this as early as possible after the MMIO base address is known */ 709 intel_i830_init_gtt_entries(); 710 711 agp_bridge->gatt_table = NULL; 712 713 agp_bridge->gatt_bus_addr = temp; 714 715 return 0; 716 } 717 718 /* Return the gatt table to a sane state. Use the top of stolen 719 * memory for the GTT. 720 */ 721 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 722 { 723 return 0; 724 } 725 726 static int intel_i830_fetch_size(void) 727 { 728 u16 gmch_ctrl; 729 struct aper_size_info_fixed *values; 730 731 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 732 733 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 734 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 735 /* 855GM/852GM/865G has 128MB aperture size */ 736 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 737 agp_bridge->aperture_size_idx = 0; 738 return values[0].size; 739 } 740 741 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 742 743 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 744 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 745 agp_bridge->aperture_size_idx = 0; 746 return values[0].size; 747 } else { 748 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 749 agp_bridge->aperture_size_idx = 1; 750 return values[1].size; 751 } 752 753 return 0; 754 } 755 756 static int intel_i830_configure(void) 757 { 758 struct aper_size_info_fixed *current_size; 759 u32 temp; 760 u16 gmch_ctrl; 761 int i; 762 763 current_size = A_SIZE_FIX(agp_bridge->current_size); 764 765 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 766 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 767 768 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 769 gmch_ctrl |= I830_GMCH_ENABLED; 770 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 771 772 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 773 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 774 775 if (agp_bridge->driver->needs_scratch_page) { 776 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 777 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 778 } 779 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 780 } 781 782 global_cache_flush(); 783 784 intel_i830_setup_flush(); 785 return 0; 786 } 787 788 static void intel_i830_cleanup(void) 789 { 790 iounmap(intel_private.registers); 791 } 792 793 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 794 int type) 795 { 796 int i, j, num_entries; 797 void *temp; 798 int ret = -EINVAL; 799 int mask_type; 800 801 if (mem->page_count == 0) 802 goto out; 803 804 temp = agp_bridge->current_size; 805 num_entries = A_SIZE_FIX(temp)->num_entries; 806 807 if (pg_start < intel_private.gtt_entries) { 808 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 809 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 810 pg_start, intel_private.gtt_entries); 811 812 dev_info(&intel_private.pcidev->dev, 813 "trying to insert into local/stolen memory\n"); 814 goto out_err; 815 } 816 817 if ((pg_start + mem->page_count) > num_entries) 818 goto out_err; 819 820 /* The i830 can't check the GTT for entries since its read only, 821 * depend on the caller to make the correct offset decisions. 822 */ 823 824 if (type != mem->type) 825 goto out_err; 826 827 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 828 829 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 830 mask_type != INTEL_AGP_CACHED_MEMORY) 831 goto out_err; 832 833 if (!mem->is_flushed) 834 global_cache_flush(); 835 836 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 837 writel(agp_bridge->driver->mask_memory(agp_bridge, 838 mem->memory[i], mask_type), 839 intel_private.registers+I810_PTE_BASE+(j*4)); 840 } 841 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 842 agp_bridge->driver->tlb_flush(mem); 843 844 out: 845 ret = 0; 846 out_err: 847 mem->is_flushed = true; 848 return ret; 849 } 850 851 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 852 int type) 853 { 854 int i; 855 856 if (mem->page_count == 0) 857 return 0; 858 859 if (pg_start < intel_private.gtt_entries) { 860 dev_info(&intel_private.pcidev->dev, 861 "trying to disable local/stolen memory\n"); 862 return -EINVAL; 863 } 864 865 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 866 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 867 } 868 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 869 870 agp_bridge->driver->tlb_flush(mem); 871 return 0; 872 } 873 874 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 875 { 876 if (type == AGP_PHYS_MEMORY) 877 return alloc_agpphysmem_i8xx(pg_count, type); 878 /* always return NULL for other allocation types for now */ 879 return NULL; 880 } 881 882 static int intel_alloc_chipset_flush_resource(void) 883 { 884 int ret; 885 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 886 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 887 pcibios_align_resource, agp_bridge->dev); 888 889 return ret; 890 } 891 892 static void intel_i915_setup_chipset_flush(void) 893 { 894 int ret; 895 u32 temp; 896 897 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 898 if (!(temp & 0x1)) { 899 intel_alloc_chipset_flush_resource(); 900 intel_private.resource_valid = 1; 901 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 902 } else { 903 temp &= ~1; 904 905 intel_private.resource_valid = 1; 906 intel_private.ifp_resource.start = temp; 907 intel_private.ifp_resource.end = temp + PAGE_SIZE; 908 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 909 /* some BIOSes reserve this area in a pnp some don't */ 910 if (ret) 911 intel_private.resource_valid = 0; 912 } 913 } 914 915 static void intel_i965_g33_setup_chipset_flush(void) 916 { 917 u32 temp_hi, temp_lo; 918 int ret; 919 920 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 921 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 922 923 if (!(temp_lo & 0x1)) { 924 925 intel_alloc_chipset_flush_resource(); 926 927 intel_private.resource_valid = 1; 928 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 929 upper_32_bits(intel_private.ifp_resource.start)); 930 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 931 } else { 932 u64 l64; 933 934 temp_lo &= ~0x1; 935 l64 = ((u64)temp_hi << 32) | temp_lo; 936 937 intel_private.resource_valid = 1; 938 intel_private.ifp_resource.start = l64; 939 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 940 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 941 /* some BIOSes reserve this area in a pnp some don't */ 942 if (ret) 943 intel_private.resource_valid = 0; 944 } 945 } 946 947 static void intel_i9xx_setup_flush(void) 948 { 949 /* return if already configured */ 950 if (intel_private.ifp_resource.start) 951 return; 952 953 /* setup a resource for this object */ 954 intel_private.ifp_resource.name = "Intel Flush Page"; 955 intel_private.ifp_resource.flags = IORESOURCE_MEM; 956 957 /* Setup chipset flush for 915 */ 958 if (IS_I965 || IS_G33 || IS_G4X) { 959 intel_i965_g33_setup_chipset_flush(); 960 } else { 961 intel_i915_setup_chipset_flush(); 962 } 963 964 if (intel_private.ifp_resource.start) { 965 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 966 if (!intel_private.i9xx_flush_page) 967 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 968 } 969 } 970 971 static int intel_i915_configure(void) 972 { 973 struct aper_size_info_fixed *current_size; 974 u32 temp; 975 u16 gmch_ctrl; 976 int i; 977 978 current_size = A_SIZE_FIX(agp_bridge->current_size); 979 980 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 981 982 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 983 984 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 985 gmch_ctrl |= I830_GMCH_ENABLED; 986 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 987 988 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 989 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 990 991 if (agp_bridge->driver->needs_scratch_page) { 992 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 993 writel(agp_bridge->scratch_page, intel_private.gtt+i); 994 } 995 readl(intel_private.gtt+i-1); /* PCI Posting. */ 996 } 997 998 global_cache_flush(); 999 1000 intel_i9xx_setup_flush(); 1001 1002 return 0; 1003 } 1004 1005 static void intel_i915_cleanup(void) 1006 { 1007 if (intel_private.i9xx_flush_page) 1008 iounmap(intel_private.i9xx_flush_page); 1009 if (intel_private.resource_valid) 1010 release_resource(&intel_private.ifp_resource); 1011 intel_private.ifp_resource.start = 0; 1012 intel_private.resource_valid = 0; 1013 iounmap(intel_private.gtt); 1014 iounmap(intel_private.registers); 1015 } 1016 1017 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1018 { 1019 if (intel_private.i9xx_flush_page) 1020 writel(1, intel_private.i9xx_flush_page); 1021 } 1022 1023 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1024 int type) 1025 { 1026 int i, j, num_entries; 1027 void *temp; 1028 int ret = -EINVAL; 1029 int mask_type; 1030 1031 if (mem->page_count == 0) 1032 goto out; 1033 1034 temp = agp_bridge->current_size; 1035 num_entries = A_SIZE_FIX(temp)->num_entries; 1036 1037 if (pg_start < intel_private.gtt_entries) { 1038 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1039 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1040 pg_start, intel_private.gtt_entries); 1041 1042 dev_info(&intel_private.pcidev->dev, 1043 "trying to insert into local/stolen memory\n"); 1044 goto out_err; 1045 } 1046 1047 if ((pg_start + mem->page_count) > num_entries) 1048 goto out_err; 1049 1050 /* The i915 can't check the GTT for entries since its read only, 1051 * depend on the caller to make the correct offset decisions. 1052 */ 1053 1054 if (type != mem->type) 1055 goto out_err; 1056 1057 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1058 1059 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1060 mask_type != INTEL_AGP_CACHED_MEMORY) 1061 goto out_err; 1062 1063 if (!mem->is_flushed) 1064 global_cache_flush(); 1065 1066 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1067 writel(agp_bridge->driver->mask_memory(agp_bridge, 1068 mem->memory[i], mask_type), intel_private.gtt+j); 1069 } 1070 1071 readl(intel_private.gtt+j-1); 1072 agp_bridge->driver->tlb_flush(mem); 1073 1074 out: 1075 ret = 0; 1076 out_err: 1077 mem->is_flushed = true; 1078 return ret; 1079 } 1080 1081 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1082 int type) 1083 { 1084 int i; 1085 1086 if (mem->page_count == 0) 1087 return 0; 1088 1089 if (pg_start < intel_private.gtt_entries) { 1090 dev_info(&intel_private.pcidev->dev, 1091 "trying to disable local/stolen memory\n"); 1092 return -EINVAL; 1093 } 1094 1095 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1096 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1097 1098 readl(intel_private.gtt+i-1); 1099 1100 agp_bridge->driver->tlb_flush(mem); 1101 return 0; 1102 } 1103 1104 /* Return the aperture size by just checking the resource length. The effect 1105 * described in the spec of the MSAC registers is just changing of the 1106 * resource size. 1107 */ 1108 static int intel_i9xx_fetch_size(void) 1109 { 1110 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1111 int aper_size; /* size in megabytes */ 1112 int i; 1113 1114 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1115 1116 for (i = 0; i < num_sizes; i++) { 1117 if (aper_size == intel_i830_sizes[i].size) { 1118 agp_bridge->current_size = intel_i830_sizes + i; 1119 agp_bridge->previous_size = agp_bridge->current_size; 1120 return aper_size; 1121 } 1122 } 1123 1124 return 0; 1125 } 1126 1127 /* The intel i915 automatically initializes the agp aperture during POST. 1128 * Use the memory already set aside for in the GTT. 1129 */ 1130 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1131 { 1132 int page_order; 1133 struct aper_size_info_fixed *size; 1134 int num_entries; 1135 u32 temp, temp2; 1136 int gtt_map_size = 256 * 1024; 1137 1138 size = agp_bridge->current_size; 1139 page_order = size->page_order; 1140 num_entries = size->num_entries; 1141 agp_bridge->gatt_table_real = NULL; 1142 1143 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1144 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1145 1146 if (IS_G33) 1147 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1148 intel_private.gtt = ioremap(temp2, gtt_map_size); 1149 if (!intel_private.gtt) 1150 return -ENOMEM; 1151 1152 temp &= 0xfff80000; 1153 1154 intel_private.registers = ioremap(temp, 128 * 4096); 1155 if (!intel_private.registers) { 1156 iounmap(intel_private.gtt); 1157 return -ENOMEM; 1158 } 1159 1160 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1161 global_cache_flush(); /* FIXME: ? */ 1162 1163 /* we have to call this as early as possible after the MMIO base address is known */ 1164 intel_i830_init_gtt_entries(); 1165 1166 agp_bridge->gatt_table = NULL; 1167 1168 agp_bridge->gatt_bus_addr = temp; 1169 1170 return 0; 1171 } 1172 1173 /* 1174 * The i965 supports 36-bit physical addresses, but to keep 1175 * the format of the GTT the same, the bits that don't fit 1176 * in a 32-bit word are shifted down to bits 4..7. 1177 * 1178 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1179 * is always zero on 32-bit architectures, so no need to make 1180 * this conditional. 1181 */ 1182 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1183 unsigned long addr, int type) 1184 { 1185 /* Shift high bits down */ 1186 addr |= (addr >> 28) & 0xf0; 1187 1188 /* Type checking must be done elsewhere */ 1189 return addr | bridge->driver->masks[type].mask; 1190 } 1191 1192 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1193 { 1194 switch (agp_bridge->dev->device) { 1195 case PCI_DEVICE_ID_INTEL_GM45_HB: 1196 case PCI_DEVICE_ID_INTEL_IGD_E_HB: 1197 case PCI_DEVICE_ID_INTEL_Q45_HB: 1198 case PCI_DEVICE_ID_INTEL_G45_HB: 1199 *gtt_offset = *gtt_size = MB(2); 1200 break; 1201 default: 1202 *gtt_offset = *gtt_size = KB(512); 1203 } 1204 } 1205 1206 /* The intel i965 automatically initializes the agp aperture during POST. 1207 * Use the memory already set aside for in the GTT. 1208 */ 1209 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1210 { 1211 int page_order; 1212 struct aper_size_info_fixed *size; 1213 int num_entries; 1214 u32 temp; 1215 int gtt_offset, gtt_size; 1216 1217 size = agp_bridge->current_size; 1218 page_order = size->page_order; 1219 num_entries = size->num_entries; 1220 agp_bridge->gatt_table_real = NULL; 1221 1222 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1223 1224 temp &= 0xfff00000; 1225 1226 intel_i965_get_gtt_range(>t_offset, >t_size); 1227 1228 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1229 1230 if (!intel_private.gtt) 1231 return -ENOMEM; 1232 1233 intel_private.registers = ioremap(temp, 128 * 4096); 1234 if (!intel_private.registers) { 1235 iounmap(intel_private.gtt); 1236 return -ENOMEM; 1237 } 1238 1239 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1240 global_cache_flush(); /* FIXME: ? */ 1241 1242 /* we have to call this as early as possible after the MMIO base address is known */ 1243 intel_i830_init_gtt_entries(); 1244 1245 agp_bridge->gatt_table = NULL; 1246 1247 agp_bridge->gatt_bus_addr = temp; 1248 1249 return 0; 1250 } 1251 1252 1253 static int intel_fetch_size(void) 1254 { 1255 int i; 1256 u16 temp; 1257 struct aper_size_info_16 *values; 1258 1259 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1260 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1261 1262 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1263 if (temp == values[i].size_value) { 1264 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1265 agp_bridge->aperture_size_idx = i; 1266 return values[i].size; 1267 } 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int __intel_8xx_fetch_size(u8 temp) 1274 { 1275 int i; 1276 struct aper_size_info_8 *values; 1277 1278 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1279 1280 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1281 if (temp == values[i].size_value) { 1282 agp_bridge->previous_size = 1283 agp_bridge->current_size = (void *) (values + i); 1284 agp_bridge->aperture_size_idx = i; 1285 return values[i].size; 1286 } 1287 } 1288 return 0; 1289 } 1290 1291 static int intel_8xx_fetch_size(void) 1292 { 1293 u8 temp; 1294 1295 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1296 return __intel_8xx_fetch_size(temp); 1297 } 1298 1299 static int intel_815_fetch_size(void) 1300 { 1301 u8 temp; 1302 1303 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1304 * one non-reserved bit, so mask the others out ... */ 1305 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1306 temp &= (1 << 3); 1307 1308 return __intel_8xx_fetch_size(temp); 1309 } 1310 1311 static void intel_tlbflush(struct agp_memory *mem) 1312 { 1313 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1314 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1315 } 1316 1317 1318 static void intel_8xx_tlbflush(struct agp_memory *mem) 1319 { 1320 u32 temp; 1321 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1322 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1323 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1324 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1325 } 1326 1327 1328 static void intel_cleanup(void) 1329 { 1330 u16 temp; 1331 struct aper_size_info_16 *previous_size; 1332 1333 previous_size = A_SIZE_16(agp_bridge->previous_size); 1334 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1335 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1336 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1337 } 1338 1339 1340 static void intel_8xx_cleanup(void) 1341 { 1342 u16 temp; 1343 struct aper_size_info_8 *previous_size; 1344 1345 previous_size = A_SIZE_8(agp_bridge->previous_size); 1346 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1347 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1348 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1349 } 1350 1351 1352 static int intel_configure(void) 1353 { 1354 u32 temp; 1355 u16 temp2; 1356 struct aper_size_info_16 *current_size; 1357 1358 current_size = A_SIZE_16(agp_bridge->current_size); 1359 1360 /* aperture size */ 1361 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1362 1363 /* address to map to */ 1364 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1365 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1366 1367 /* attbase - aperture base */ 1368 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1369 1370 /* agpctrl */ 1371 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1372 1373 /* paccfg/nbxcfg */ 1374 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1375 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1376 (temp2 & ~(1 << 10)) | (1 << 9)); 1377 /* clear any possible error conditions */ 1378 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1379 return 0; 1380 } 1381 1382 static int intel_815_configure(void) 1383 { 1384 u32 temp, addr; 1385 u8 temp2; 1386 struct aper_size_info_8 *current_size; 1387 1388 /* attbase - aperture base */ 1389 /* the Intel 815 chipset spec. says that bits 29-31 in the 1390 * ATTBASE register are reserved -> try not to write them */ 1391 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1392 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1393 return -EINVAL; 1394 } 1395 1396 current_size = A_SIZE_8(agp_bridge->current_size); 1397 1398 /* aperture size */ 1399 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1400 current_size->size_value); 1401 1402 /* address to map to */ 1403 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1404 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1405 1406 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1407 addr &= INTEL_815_ATTBASE_MASK; 1408 addr |= agp_bridge->gatt_bus_addr; 1409 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1410 1411 /* agpctrl */ 1412 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1413 1414 /* apcont */ 1415 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1416 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1417 1418 /* clear any possible error conditions */ 1419 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1420 return 0; 1421 } 1422 1423 static void intel_820_tlbflush(struct agp_memory *mem) 1424 { 1425 return; 1426 } 1427 1428 static void intel_820_cleanup(void) 1429 { 1430 u8 temp; 1431 struct aper_size_info_8 *previous_size; 1432 1433 previous_size = A_SIZE_8(agp_bridge->previous_size); 1434 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1435 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1436 temp & ~(1 << 1)); 1437 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1438 previous_size->size_value); 1439 } 1440 1441 1442 static int intel_820_configure(void) 1443 { 1444 u32 temp; 1445 u8 temp2; 1446 struct aper_size_info_8 *current_size; 1447 1448 current_size = A_SIZE_8(agp_bridge->current_size); 1449 1450 /* aperture size */ 1451 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1452 1453 /* address to map to */ 1454 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1455 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1456 1457 /* attbase - aperture base */ 1458 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1459 1460 /* agpctrl */ 1461 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1462 1463 /* global enable aperture access */ 1464 /* This flag is not accessed through MCHCFG register as in */ 1465 /* i850 chipset. */ 1466 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1467 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1468 /* clear any possible AGP-related error conditions */ 1469 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1470 return 0; 1471 } 1472 1473 static int intel_840_configure(void) 1474 { 1475 u32 temp; 1476 u16 temp2; 1477 struct aper_size_info_8 *current_size; 1478 1479 current_size = A_SIZE_8(agp_bridge->current_size); 1480 1481 /* aperture size */ 1482 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1483 1484 /* address to map to */ 1485 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1486 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1487 1488 /* attbase - aperture base */ 1489 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1490 1491 /* agpctrl */ 1492 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1493 1494 /* mcgcfg */ 1495 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1496 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1497 /* clear any possible error conditions */ 1498 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1499 return 0; 1500 } 1501 1502 static int intel_845_configure(void) 1503 { 1504 u32 temp; 1505 u8 temp2; 1506 struct aper_size_info_8 *current_size; 1507 1508 current_size = A_SIZE_8(agp_bridge->current_size); 1509 1510 /* aperture size */ 1511 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1512 1513 if (agp_bridge->apbase_config != 0) { 1514 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1515 agp_bridge->apbase_config); 1516 } else { 1517 /* address to map to */ 1518 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1519 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1520 agp_bridge->apbase_config = temp; 1521 } 1522 1523 /* attbase - aperture base */ 1524 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1525 1526 /* agpctrl */ 1527 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1528 1529 /* agpm */ 1530 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1531 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1532 /* clear any possible error conditions */ 1533 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1534 1535 intel_i830_setup_flush(); 1536 return 0; 1537 } 1538 1539 static int intel_850_configure(void) 1540 { 1541 u32 temp; 1542 u16 temp2; 1543 struct aper_size_info_8 *current_size; 1544 1545 current_size = A_SIZE_8(agp_bridge->current_size); 1546 1547 /* aperture size */ 1548 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1549 1550 /* address to map to */ 1551 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1552 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1553 1554 /* attbase - aperture base */ 1555 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1556 1557 /* agpctrl */ 1558 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1559 1560 /* mcgcfg */ 1561 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1562 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1563 /* clear any possible AGP-related error conditions */ 1564 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1565 return 0; 1566 } 1567 1568 static int intel_860_configure(void) 1569 { 1570 u32 temp; 1571 u16 temp2; 1572 struct aper_size_info_8 *current_size; 1573 1574 current_size = A_SIZE_8(agp_bridge->current_size); 1575 1576 /* aperture size */ 1577 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1578 1579 /* address to map to */ 1580 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1581 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1582 1583 /* attbase - aperture base */ 1584 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1585 1586 /* agpctrl */ 1587 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1588 1589 /* mcgcfg */ 1590 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1591 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1592 /* clear any possible AGP-related error conditions */ 1593 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1594 return 0; 1595 } 1596 1597 static int intel_830mp_configure(void) 1598 { 1599 u32 temp; 1600 u16 temp2; 1601 struct aper_size_info_8 *current_size; 1602 1603 current_size = A_SIZE_8(agp_bridge->current_size); 1604 1605 /* aperture size */ 1606 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1607 1608 /* address to map to */ 1609 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1610 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1611 1612 /* attbase - aperture base */ 1613 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1614 1615 /* agpctrl */ 1616 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1617 1618 /* gmch */ 1619 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1620 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1621 /* clear any possible AGP-related error conditions */ 1622 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1623 return 0; 1624 } 1625 1626 static int intel_7505_configure(void) 1627 { 1628 u32 temp; 1629 u16 temp2; 1630 struct aper_size_info_8 *current_size; 1631 1632 current_size = A_SIZE_8(agp_bridge->current_size); 1633 1634 /* aperture size */ 1635 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1636 1637 /* address to map to */ 1638 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1639 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1640 1641 /* attbase - aperture base */ 1642 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1643 1644 /* agpctrl */ 1645 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1646 1647 /* mchcfg */ 1648 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1649 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1650 1651 return 0; 1652 } 1653 1654 /* Setup function */ 1655 static const struct gatt_mask intel_generic_masks[] = 1656 { 1657 {.mask = 0x00000017, .type = 0} 1658 }; 1659 1660 static const struct aper_size_info_8 intel_815_sizes[2] = 1661 { 1662 {64, 16384, 4, 0}, 1663 {32, 8192, 3, 8}, 1664 }; 1665 1666 static const struct aper_size_info_8 intel_8xx_sizes[7] = 1667 { 1668 {256, 65536, 6, 0}, 1669 {128, 32768, 5, 32}, 1670 {64, 16384, 4, 48}, 1671 {32, 8192, 3, 56}, 1672 {16, 4096, 2, 60}, 1673 {8, 2048, 1, 62}, 1674 {4, 1024, 0, 63} 1675 }; 1676 1677 static const struct aper_size_info_16 intel_generic_sizes[7] = 1678 { 1679 {256, 65536, 6, 0}, 1680 {128, 32768, 5, 32}, 1681 {64, 16384, 4, 48}, 1682 {32, 8192, 3, 56}, 1683 {16, 4096, 2, 60}, 1684 {8, 2048, 1, 62}, 1685 {4, 1024, 0, 63} 1686 }; 1687 1688 static const struct aper_size_info_8 intel_830mp_sizes[4] = 1689 { 1690 {256, 65536, 6, 0}, 1691 {128, 32768, 5, 32}, 1692 {64, 16384, 4, 48}, 1693 {32, 8192, 3, 56} 1694 }; 1695 1696 static const struct agp_bridge_driver intel_generic_driver = { 1697 .owner = THIS_MODULE, 1698 .aperture_sizes = intel_generic_sizes, 1699 .size_type = U16_APER_SIZE, 1700 .num_aperture_sizes = 7, 1701 .configure = intel_configure, 1702 .fetch_size = intel_fetch_size, 1703 .cleanup = intel_cleanup, 1704 .tlb_flush = intel_tlbflush, 1705 .mask_memory = agp_generic_mask_memory, 1706 .masks = intel_generic_masks, 1707 .agp_enable = agp_generic_enable, 1708 .cache_flush = global_cache_flush, 1709 .create_gatt_table = agp_generic_create_gatt_table, 1710 .free_gatt_table = agp_generic_free_gatt_table, 1711 .insert_memory = agp_generic_insert_memory, 1712 .remove_memory = agp_generic_remove_memory, 1713 .alloc_by_type = agp_generic_alloc_by_type, 1714 .free_by_type = agp_generic_free_by_type, 1715 .agp_alloc_page = agp_generic_alloc_page, 1716 .agp_alloc_pages = agp_generic_alloc_pages, 1717 .agp_destroy_page = agp_generic_destroy_page, 1718 .agp_destroy_pages = agp_generic_destroy_pages, 1719 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1720 }; 1721 1722 static const struct agp_bridge_driver intel_810_driver = { 1723 .owner = THIS_MODULE, 1724 .aperture_sizes = intel_i810_sizes, 1725 .size_type = FIXED_APER_SIZE, 1726 .num_aperture_sizes = 2, 1727 .needs_scratch_page = true, 1728 .configure = intel_i810_configure, 1729 .fetch_size = intel_i810_fetch_size, 1730 .cleanup = intel_i810_cleanup, 1731 .tlb_flush = intel_i810_tlbflush, 1732 .mask_memory = intel_i810_mask_memory, 1733 .masks = intel_i810_masks, 1734 .agp_enable = intel_i810_agp_enable, 1735 .cache_flush = global_cache_flush, 1736 .create_gatt_table = agp_generic_create_gatt_table, 1737 .free_gatt_table = agp_generic_free_gatt_table, 1738 .insert_memory = intel_i810_insert_entries, 1739 .remove_memory = intel_i810_remove_entries, 1740 .alloc_by_type = intel_i810_alloc_by_type, 1741 .free_by_type = intel_i810_free_by_type, 1742 .agp_alloc_page = agp_generic_alloc_page, 1743 .agp_alloc_pages = agp_generic_alloc_pages, 1744 .agp_destroy_page = agp_generic_destroy_page, 1745 .agp_destroy_pages = agp_generic_destroy_pages, 1746 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1747 }; 1748 1749 static const struct agp_bridge_driver intel_815_driver = { 1750 .owner = THIS_MODULE, 1751 .aperture_sizes = intel_815_sizes, 1752 .size_type = U8_APER_SIZE, 1753 .num_aperture_sizes = 2, 1754 .configure = intel_815_configure, 1755 .fetch_size = intel_815_fetch_size, 1756 .cleanup = intel_8xx_cleanup, 1757 .tlb_flush = intel_8xx_tlbflush, 1758 .mask_memory = agp_generic_mask_memory, 1759 .masks = intel_generic_masks, 1760 .agp_enable = agp_generic_enable, 1761 .cache_flush = global_cache_flush, 1762 .create_gatt_table = agp_generic_create_gatt_table, 1763 .free_gatt_table = agp_generic_free_gatt_table, 1764 .insert_memory = agp_generic_insert_memory, 1765 .remove_memory = agp_generic_remove_memory, 1766 .alloc_by_type = agp_generic_alloc_by_type, 1767 .free_by_type = agp_generic_free_by_type, 1768 .agp_alloc_page = agp_generic_alloc_page, 1769 .agp_alloc_pages = agp_generic_alloc_pages, 1770 .agp_destroy_page = agp_generic_destroy_page, 1771 .agp_destroy_pages = agp_generic_destroy_pages, 1772 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1773 }; 1774 1775 static const struct agp_bridge_driver intel_830_driver = { 1776 .owner = THIS_MODULE, 1777 .aperture_sizes = intel_i830_sizes, 1778 .size_type = FIXED_APER_SIZE, 1779 .num_aperture_sizes = 4, 1780 .needs_scratch_page = true, 1781 .configure = intel_i830_configure, 1782 .fetch_size = intel_i830_fetch_size, 1783 .cleanup = intel_i830_cleanup, 1784 .tlb_flush = intel_i810_tlbflush, 1785 .mask_memory = intel_i810_mask_memory, 1786 .masks = intel_i810_masks, 1787 .agp_enable = intel_i810_agp_enable, 1788 .cache_flush = global_cache_flush, 1789 .create_gatt_table = intel_i830_create_gatt_table, 1790 .free_gatt_table = intel_i830_free_gatt_table, 1791 .insert_memory = intel_i830_insert_entries, 1792 .remove_memory = intel_i830_remove_entries, 1793 .alloc_by_type = intel_i830_alloc_by_type, 1794 .free_by_type = intel_i810_free_by_type, 1795 .agp_alloc_page = agp_generic_alloc_page, 1796 .agp_alloc_pages = agp_generic_alloc_pages, 1797 .agp_destroy_page = agp_generic_destroy_page, 1798 .agp_destroy_pages = agp_generic_destroy_pages, 1799 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1800 .chipset_flush = intel_i830_chipset_flush, 1801 }; 1802 1803 static const struct agp_bridge_driver intel_820_driver = { 1804 .owner = THIS_MODULE, 1805 .aperture_sizes = intel_8xx_sizes, 1806 .size_type = U8_APER_SIZE, 1807 .num_aperture_sizes = 7, 1808 .configure = intel_820_configure, 1809 .fetch_size = intel_8xx_fetch_size, 1810 .cleanup = intel_820_cleanup, 1811 .tlb_flush = intel_820_tlbflush, 1812 .mask_memory = agp_generic_mask_memory, 1813 .masks = intel_generic_masks, 1814 .agp_enable = agp_generic_enable, 1815 .cache_flush = global_cache_flush, 1816 .create_gatt_table = agp_generic_create_gatt_table, 1817 .free_gatt_table = agp_generic_free_gatt_table, 1818 .insert_memory = agp_generic_insert_memory, 1819 .remove_memory = agp_generic_remove_memory, 1820 .alloc_by_type = agp_generic_alloc_by_type, 1821 .free_by_type = agp_generic_free_by_type, 1822 .agp_alloc_page = agp_generic_alloc_page, 1823 .agp_alloc_pages = agp_generic_alloc_pages, 1824 .agp_destroy_page = agp_generic_destroy_page, 1825 .agp_destroy_pages = agp_generic_destroy_pages, 1826 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1827 }; 1828 1829 static const struct agp_bridge_driver intel_830mp_driver = { 1830 .owner = THIS_MODULE, 1831 .aperture_sizes = intel_830mp_sizes, 1832 .size_type = U8_APER_SIZE, 1833 .num_aperture_sizes = 4, 1834 .configure = intel_830mp_configure, 1835 .fetch_size = intel_8xx_fetch_size, 1836 .cleanup = intel_8xx_cleanup, 1837 .tlb_flush = intel_8xx_tlbflush, 1838 .mask_memory = agp_generic_mask_memory, 1839 .masks = intel_generic_masks, 1840 .agp_enable = agp_generic_enable, 1841 .cache_flush = global_cache_flush, 1842 .create_gatt_table = agp_generic_create_gatt_table, 1843 .free_gatt_table = agp_generic_free_gatt_table, 1844 .insert_memory = agp_generic_insert_memory, 1845 .remove_memory = agp_generic_remove_memory, 1846 .alloc_by_type = agp_generic_alloc_by_type, 1847 .free_by_type = agp_generic_free_by_type, 1848 .agp_alloc_page = agp_generic_alloc_page, 1849 .agp_alloc_pages = agp_generic_alloc_pages, 1850 .agp_destroy_page = agp_generic_destroy_page, 1851 .agp_destroy_pages = agp_generic_destroy_pages, 1852 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1853 }; 1854 1855 static const struct agp_bridge_driver intel_840_driver = { 1856 .owner = THIS_MODULE, 1857 .aperture_sizes = intel_8xx_sizes, 1858 .size_type = U8_APER_SIZE, 1859 .num_aperture_sizes = 7, 1860 .configure = intel_840_configure, 1861 .fetch_size = intel_8xx_fetch_size, 1862 .cleanup = intel_8xx_cleanup, 1863 .tlb_flush = intel_8xx_tlbflush, 1864 .mask_memory = agp_generic_mask_memory, 1865 .masks = intel_generic_masks, 1866 .agp_enable = agp_generic_enable, 1867 .cache_flush = global_cache_flush, 1868 .create_gatt_table = agp_generic_create_gatt_table, 1869 .free_gatt_table = agp_generic_free_gatt_table, 1870 .insert_memory = agp_generic_insert_memory, 1871 .remove_memory = agp_generic_remove_memory, 1872 .alloc_by_type = agp_generic_alloc_by_type, 1873 .free_by_type = agp_generic_free_by_type, 1874 .agp_alloc_page = agp_generic_alloc_page, 1875 .agp_alloc_pages = agp_generic_alloc_pages, 1876 .agp_destroy_page = agp_generic_destroy_page, 1877 .agp_destroy_pages = agp_generic_destroy_pages, 1878 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1879 }; 1880 1881 static const struct agp_bridge_driver intel_845_driver = { 1882 .owner = THIS_MODULE, 1883 .aperture_sizes = intel_8xx_sizes, 1884 .size_type = U8_APER_SIZE, 1885 .num_aperture_sizes = 7, 1886 .configure = intel_845_configure, 1887 .fetch_size = intel_8xx_fetch_size, 1888 .cleanup = intel_8xx_cleanup, 1889 .tlb_flush = intel_8xx_tlbflush, 1890 .mask_memory = agp_generic_mask_memory, 1891 .masks = intel_generic_masks, 1892 .agp_enable = agp_generic_enable, 1893 .cache_flush = global_cache_flush, 1894 .create_gatt_table = agp_generic_create_gatt_table, 1895 .free_gatt_table = agp_generic_free_gatt_table, 1896 .insert_memory = agp_generic_insert_memory, 1897 .remove_memory = agp_generic_remove_memory, 1898 .alloc_by_type = agp_generic_alloc_by_type, 1899 .free_by_type = agp_generic_free_by_type, 1900 .agp_alloc_page = agp_generic_alloc_page, 1901 .agp_alloc_pages = agp_generic_alloc_pages, 1902 .agp_destroy_page = agp_generic_destroy_page, 1903 .agp_destroy_pages = agp_generic_destroy_pages, 1904 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1905 .chipset_flush = intel_i830_chipset_flush, 1906 }; 1907 1908 static const struct agp_bridge_driver intel_850_driver = { 1909 .owner = THIS_MODULE, 1910 .aperture_sizes = intel_8xx_sizes, 1911 .size_type = U8_APER_SIZE, 1912 .num_aperture_sizes = 7, 1913 .configure = intel_850_configure, 1914 .fetch_size = intel_8xx_fetch_size, 1915 .cleanup = intel_8xx_cleanup, 1916 .tlb_flush = intel_8xx_tlbflush, 1917 .mask_memory = agp_generic_mask_memory, 1918 .masks = intel_generic_masks, 1919 .agp_enable = agp_generic_enable, 1920 .cache_flush = global_cache_flush, 1921 .create_gatt_table = agp_generic_create_gatt_table, 1922 .free_gatt_table = agp_generic_free_gatt_table, 1923 .insert_memory = agp_generic_insert_memory, 1924 .remove_memory = agp_generic_remove_memory, 1925 .alloc_by_type = agp_generic_alloc_by_type, 1926 .free_by_type = agp_generic_free_by_type, 1927 .agp_alloc_page = agp_generic_alloc_page, 1928 .agp_alloc_pages = agp_generic_alloc_pages, 1929 .agp_destroy_page = agp_generic_destroy_page, 1930 .agp_destroy_pages = agp_generic_destroy_pages, 1931 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1932 }; 1933 1934 static const struct agp_bridge_driver intel_860_driver = { 1935 .owner = THIS_MODULE, 1936 .aperture_sizes = intel_8xx_sizes, 1937 .size_type = U8_APER_SIZE, 1938 .num_aperture_sizes = 7, 1939 .configure = intel_860_configure, 1940 .fetch_size = intel_8xx_fetch_size, 1941 .cleanup = intel_8xx_cleanup, 1942 .tlb_flush = intel_8xx_tlbflush, 1943 .mask_memory = agp_generic_mask_memory, 1944 .masks = intel_generic_masks, 1945 .agp_enable = agp_generic_enable, 1946 .cache_flush = global_cache_flush, 1947 .create_gatt_table = agp_generic_create_gatt_table, 1948 .free_gatt_table = agp_generic_free_gatt_table, 1949 .insert_memory = agp_generic_insert_memory, 1950 .remove_memory = agp_generic_remove_memory, 1951 .alloc_by_type = agp_generic_alloc_by_type, 1952 .free_by_type = agp_generic_free_by_type, 1953 .agp_alloc_page = agp_generic_alloc_page, 1954 .agp_alloc_pages = agp_generic_alloc_pages, 1955 .agp_destroy_page = agp_generic_destroy_page, 1956 .agp_destroy_pages = agp_generic_destroy_pages, 1957 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1958 }; 1959 1960 static const struct agp_bridge_driver intel_915_driver = { 1961 .owner = THIS_MODULE, 1962 .aperture_sizes = intel_i830_sizes, 1963 .size_type = FIXED_APER_SIZE, 1964 .num_aperture_sizes = 4, 1965 .needs_scratch_page = true, 1966 .configure = intel_i915_configure, 1967 .fetch_size = intel_i9xx_fetch_size, 1968 .cleanup = intel_i915_cleanup, 1969 .tlb_flush = intel_i810_tlbflush, 1970 .mask_memory = intel_i810_mask_memory, 1971 .masks = intel_i810_masks, 1972 .agp_enable = intel_i810_agp_enable, 1973 .cache_flush = global_cache_flush, 1974 .create_gatt_table = intel_i915_create_gatt_table, 1975 .free_gatt_table = intel_i830_free_gatt_table, 1976 .insert_memory = intel_i915_insert_entries, 1977 .remove_memory = intel_i915_remove_entries, 1978 .alloc_by_type = intel_i830_alloc_by_type, 1979 .free_by_type = intel_i810_free_by_type, 1980 .agp_alloc_page = agp_generic_alloc_page, 1981 .agp_alloc_pages = agp_generic_alloc_pages, 1982 .agp_destroy_page = agp_generic_destroy_page, 1983 .agp_destroy_pages = agp_generic_destroy_pages, 1984 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1985 .chipset_flush = intel_i915_chipset_flush, 1986 }; 1987 1988 static const struct agp_bridge_driver intel_i965_driver = { 1989 .owner = THIS_MODULE, 1990 .aperture_sizes = intel_i830_sizes, 1991 .size_type = FIXED_APER_SIZE, 1992 .num_aperture_sizes = 4, 1993 .needs_scratch_page = true, 1994 .configure = intel_i915_configure, 1995 .fetch_size = intel_i9xx_fetch_size, 1996 .cleanup = intel_i915_cleanup, 1997 .tlb_flush = intel_i810_tlbflush, 1998 .mask_memory = intel_i965_mask_memory, 1999 .masks = intel_i810_masks, 2000 .agp_enable = intel_i810_agp_enable, 2001 .cache_flush = global_cache_flush, 2002 .create_gatt_table = intel_i965_create_gatt_table, 2003 .free_gatt_table = intel_i830_free_gatt_table, 2004 .insert_memory = intel_i915_insert_entries, 2005 .remove_memory = intel_i915_remove_entries, 2006 .alloc_by_type = intel_i830_alloc_by_type, 2007 .free_by_type = intel_i810_free_by_type, 2008 .agp_alloc_page = agp_generic_alloc_page, 2009 .agp_alloc_pages = agp_generic_alloc_pages, 2010 .agp_destroy_page = agp_generic_destroy_page, 2011 .agp_destroy_pages = agp_generic_destroy_pages, 2012 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2013 .chipset_flush = intel_i915_chipset_flush, 2014 }; 2015 2016 static const struct agp_bridge_driver intel_7505_driver = { 2017 .owner = THIS_MODULE, 2018 .aperture_sizes = intel_8xx_sizes, 2019 .size_type = U8_APER_SIZE, 2020 .num_aperture_sizes = 7, 2021 .configure = intel_7505_configure, 2022 .fetch_size = intel_8xx_fetch_size, 2023 .cleanup = intel_8xx_cleanup, 2024 .tlb_flush = intel_8xx_tlbflush, 2025 .mask_memory = agp_generic_mask_memory, 2026 .masks = intel_generic_masks, 2027 .agp_enable = agp_generic_enable, 2028 .cache_flush = global_cache_flush, 2029 .create_gatt_table = agp_generic_create_gatt_table, 2030 .free_gatt_table = agp_generic_free_gatt_table, 2031 .insert_memory = agp_generic_insert_memory, 2032 .remove_memory = agp_generic_remove_memory, 2033 .alloc_by_type = agp_generic_alloc_by_type, 2034 .free_by_type = agp_generic_free_by_type, 2035 .agp_alloc_page = agp_generic_alloc_page, 2036 .agp_alloc_pages = agp_generic_alloc_pages, 2037 .agp_destroy_page = agp_generic_destroy_page, 2038 .agp_destroy_pages = agp_generic_destroy_pages, 2039 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2040 }; 2041 2042 static const struct agp_bridge_driver intel_g33_driver = { 2043 .owner = THIS_MODULE, 2044 .aperture_sizes = intel_i830_sizes, 2045 .size_type = FIXED_APER_SIZE, 2046 .num_aperture_sizes = 4, 2047 .needs_scratch_page = true, 2048 .configure = intel_i915_configure, 2049 .fetch_size = intel_i9xx_fetch_size, 2050 .cleanup = intel_i915_cleanup, 2051 .tlb_flush = intel_i810_tlbflush, 2052 .mask_memory = intel_i965_mask_memory, 2053 .masks = intel_i810_masks, 2054 .agp_enable = intel_i810_agp_enable, 2055 .cache_flush = global_cache_flush, 2056 .create_gatt_table = intel_i915_create_gatt_table, 2057 .free_gatt_table = intel_i830_free_gatt_table, 2058 .insert_memory = intel_i915_insert_entries, 2059 .remove_memory = intel_i915_remove_entries, 2060 .alloc_by_type = intel_i830_alloc_by_type, 2061 .free_by_type = intel_i810_free_by_type, 2062 .agp_alloc_page = agp_generic_alloc_page, 2063 .agp_alloc_pages = agp_generic_alloc_pages, 2064 .agp_destroy_page = agp_generic_destroy_page, 2065 .agp_destroy_pages = agp_generic_destroy_pages, 2066 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2067 .chipset_flush = intel_i915_chipset_flush, 2068 }; 2069 2070 static int find_gmch(u16 device) 2071 { 2072 struct pci_dev *gmch_device; 2073 2074 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2075 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2076 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2077 device, gmch_device); 2078 } 2079 2080 if (!gmch_device) 2081 return 0; 2082 2083 intel_private.pcidev = gmch_device; 2084 return 1; 2085 } 2086 2087 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2088 * driver and gmch_driver must be non-null, and find_gmch will determine 2089 * which one should be used if a gmch_chip_id is present. 2090 */ 2091 static const struct intel_driver_description { 2092 unsigned int chip_id; 2093 unsigned int gmch_chip_id; 2094 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2095 char *name; 2096 const struct agp_bridge_driver *driver; 2097 const struct agp_bridge_driver *gmch_driver; 2098 } intel_agp_chipsets[] = { 2099 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2100 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2101 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2102 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2103 NULL, &intel_810_driver }, 2104 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2105 NULL, &intel_810_driver }, 2106 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2107 NULL, &intel_810_driver }, 2108 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2109 &intel_815_driver, &intel_810_driver }, 2110 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2111 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2112 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2113 &intel_830mp_driver, &intel_830_driver }, 2114 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2115 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2116 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2117 &intel_845_driver, &intel_830_driver }, 2118 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2119 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2120 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2121 &intel_845_driver, &intel_830_driver }, 2122 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2123 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2124 &intel_845_driver, &intel_830_driver }, 2125 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2126 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2127 NULL, &intel_915_driver }, 2128 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2129 NULL, &intel_915_driver }, 2130 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2131 NULL, &intel_915_driver }, 2132 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2133 NULL, &intel_915_driver }, 2134 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2135 NULL, &intel_915_driver }, 2136 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2137 NULL, &intel_915_driver }, 2138 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2139 NULL, &intel_i965_driver }, 2140 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2141 NULL, &intel_i965_driver }, 2142 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2143 NULL, &intel_i965_driver }, 2144 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2145 NULL, &intel_i965_driver }, 2146 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2147 NULL, &intel_i965_driver }, 2148 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2149 NULL, &intel_i965_driver }, 2150 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2151 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2152 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2153 NULL, &intel_g33_driver }, 2154 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2155 NULL, &intel_g33_driver }, 2156 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2157 NULL, &intel_g33_driver }, 2158 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2159 "Mobile Intel? GM45 Express", NULL, &intel_i965_driver }, 2160 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, 2161 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2162 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2163 "Q45/Q43", NULL, &intel_i965_driver }, 2164 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2165 "G45/G43", NULL, &intel_i965_driver }, 2166 { 0, 0, 0, NULL, NULL, NULL } 2167 }; 2168 2169 static int __devinit agp_intel_probe(struct pci_dev *pdev, 2170 const struct pci_device_id *ent) 2171 { 2172 struct agp_bridge_data *bridge; 2173 u8 cap_ptr = 0; 2174 struct resource *r; 2175 int i; 2176 2177 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2178 2179 bridge = agp_alloc_bridge(); 2180 if (!bridge) 2181 return -ENOMEM; 2182 2183 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2184 /* In case that multiple models of gfx chip may 2185 stand on same host bridge type, this can be 2186 sure we detect the right IGD. */ 2187 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2188 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2189 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2190 bridge->driver = 2191 intel_agp_chipsets[i].gmch_driver; 2192 break; 2193 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2194 continue; 2195 } else { 2196 bridge->driver = intel_agp_chipsets[i].driver; 2197 break; 2198 } 2199 } 2200 } 2201 2202 if (intel_agp_chipsets[i].name == NULL) { 2203 if (cap_ptr) 2204 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2205 pdev->vendor, pdev->device); 2206 agp_put_bridge(bridge); 2207 return -ENODEV; 2208 } 2209 2210 if (bridge->driver == NULL) { 2211 /* bridge has no AGP and no IGD detected */ 2212 if (cap_ptr) 2213 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2214 intel_agp_chipsets[i].gmch_chip_id); 2215 agp_put_bridge(bridge); 2216 return -ENODEV; 2217 } 2218 2219 bridge->dev = pdev; 2220 bridge->capndx = cap_ptr; 2221 bridge->dev_private_data = &intel_private; 2222 2223 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2224 2225 /* 2226 * The following fixes the case where the BIOS has "forgotten" to 2227 * provide an address range for the GART. 2228 * 20030610 - hamish@zot.org 2229 */ 2230 r = &pdev->resource[0]; 2231 if (!r->start && r->end) { 2232 if (pci_assign_resource(pdev, 0)) { 2233 dev_err(&pdev->dev, "can't assign resource 0\n"); 2234 agp_put_bridge(bridge); 2235 return -ENODEV; 2236 } 2237 } 2238 2239 /* 2240 * If the device has not been properly setup, the following will catch 2241 * the problem and should stop the system from crashing. 2242 * 20030610 - hamish@zot.org 2243 */ 2244 if (pci_enable_device(pdev)) { 2245 dev_err(&pdev->dev, "can't enable PCI device\n"); 2246 agp_put_bridge(bridge); 2247 return -ENODEV; 2248 } 2249 2250 /* Fill in the mode register */ 2251 if (cap_ptr) { 2252 pci_read_config_dword(pdev, 2253 bridge->capndx+PCI_AGP_STATUS, 2254 &bridge->mode); 2255 } 2256 2257 pci_set_drvdata(pdev, bridge); 2258 return agp_add_bridge(bridge); 2259 } 2260 2261 static void __devexit agp_intel_remove(struct pci_dev *pdev) 2262 { 2263 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2264 2265 agp_remove_bridge(bridge); 2266 2267 if (intel_private.pcidev) 2268 pci_dev_put(intel_private.pcidev); 2269 2270 agp_put_bridge(bridge); 2271 } 2272 2273 #ifdef CONFIG_PM 2274 static int agp_intel_resume(struct pci_dev *pdev) 2275 { 2276 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2277 int ret_val; 2278 2279 pci_restore_state(pdev); 2280 2281 /* We should restore our graphics device's config space, 2282 * as host bridge (00:00) resumes before graphics device (02:00), 2283 * then our access to its pci space can work right. 2284 */ 2285 if (intel_private.pcidev) 2286 pci_restore_state(intel_private.pcidev); 2287 2288 if (bridge->driver == &intel_generic_driver) 2289 intel_configure(); 2290 else if (bridge->driver == &intel_850_driver) 2291 intel_850_configure(); 2292 else if (bridge->driver == &intel_845_driver) 2293 intel_845_configure(); 2294 else if (bridge->driver == &intel_830mp_driver) 2295 intel_830mp_configure(); 2296 else if (bridge->driver == &intel_915_driver) 2297 intel_i915_configure(); 2298 else if (bridge->driver == &intel_830_driver) 2299 intel_i830_configure(); 2300 else if (bridge->driver == &intel_810_driver) 2301 intel_i810_configure(); 2302 else if (bridge->driver == &intel_i965_driver) 2303 intel_i915_configure(); 2304 2305 ret_val = agp_rebind_memory(); 2306 if (ret_val != 0) 2307 return ret_val; 2308 2309 return 0; 2310 } 2311 #endif 2312 2313 static struct pci_device_id agp_intel_pci_table[] = { 2314 #define ID(x) \ 2315 { \ 2316 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2317 .class_mask = ~0, \ 2318 .vendor = PCI_VENDOR_ID_INTEL, \ 2319 .device = x, \ 2320 .subvendor = PCI_ANY_ID, \ 2321 .subdevice = PCI_ANY_ID, \ 2322 } 2323 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2324 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2325 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2326 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2327 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2328 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2329 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2330 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2331 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2332 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2333 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2334 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2335 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2336 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2337 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2338 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2339 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2340 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2341 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2342 ID(PCI_DEVICE_ID_INTEL_7505_0), 2343 ID(PCI_DEVICE_ID_INTEL_7205_0), 2344 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2345 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2346 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2347 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2348 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2349 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2350 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2351 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2352 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2353 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2354 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2355 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2356 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2357 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2358 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2359 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2360 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), 2361 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2362 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2363 { } 2364 }; 2365 2366 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2367 2368 static struct pci_driver agp_intel_pci_driver = { 2369 .name = "agpgart-intel", 2370 .id_table = agp_intel_pci_table, 2371 .probe = agp_intel_probe, 2372 .remove = __devexit_p(agp_intel_remove), 2373 #ifdef CONFIG_PM 2374 .resume = agp_intel_resume, 2375 #endif 2376 }; 2377 2378 static int __init agp_intel_init(void) 2379 { 2380 if (agp_off) 2381 return -EINVAL; 2382 return pci_register_driver(&agp_intel_pci_driver); 2383 } 2384 2385 static void __exit agp_intel_cleanup(void) 2386 { 2387 pci_unregister_driver(&agp_intel_pci_driver); 2388 } 2389 2390 module_init(agp_intel_init); 2391 module_exit(agp_intel_cleanup); 2392 2393 MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 2394 MODULE_LICENSE("GPL and additional rights"); 2395