1 /* 2 * Copyright 2001-2003 SuSE Labs. 3 * Distributed under the GNU public license, v2. 4 * 5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. 6 * It also includes support for the AMD 8151 AGP bridge, 7 * although it doesn't actually do much, as all the real 8 * work is done in the northbridge(s). 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/init.h> 14 #include <linux/agp_backend.h> 15 #include <linux/mmzone.h> 16 #include <asm/page.h> /* PAGE_SIZE */ 17 #include <asm/e820.h> 18 #include <asm/k8.h> 19 #include <asm/gart.h> 20 #include "agp.h" 21 22 /* NVIDIA K8 registers */ 23 #define NVIDIA_X86_64_0_APBASE 0x10 24 #define NVIDIA_X86_64_1_APBASE1 0x50 25 #define NVIDIA_X86_64_1_APLIMIT1 0x54 26 #define NVIDIA_X86_64_1_APSIZE 0xa8 27 #define NVIDIA_X86_64_1_APBASE2 0xd8 28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc 29 30 /* ULi K8 registers */ 31 #define ULI_X86_64_BASE_ADDR 0x10 32 #define ULI_X86_64_HTT_FEA_REG 0x50 33 #define ULI_X86_64_ENU_SCR_REG 0x54 34 35 static struct resource *aperture_resource; 36 static int __initdata agp_try_unsupported = 1; 37 static int agp_bridges_found; 38 39 static void amd64_tlbflush(struct agp_memory *temp) 40 { 41 k8_flush_garts(); 42 } 43 44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 45 { 46 int i, j, num_entries; 47 long long tmp; 48 int mask_type; 49 struct agp_bridge_data *bridge = mem->bridge; 50 u32 pte; 51 52 num_entries = agp_num_entries(); 53 54 if (type != mem->type) 55 return -EINVAL; 56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); 57 if (mask_type != 0) 58 return -EINVAL; 59 60 61 /* Make sure we can fit the range in the gatt table. */ 62 /* FIXME: could wrap */ 63 if (((unsigned long)pg_start + mem->page_count) > num_entries) 64 return -EINVAL; 65 66 j = pg_start; 67 68 /* gatt table should be empty. */ 69 while (j < (pg_start + mem->page_count)) { 70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 71 return -EBUSY; 72 j++; 73 } 74 75 if (!mem->is_flushed) { 76 global_cache_flush(); 77 mem->is_flushed = true; 78 } 79 80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 81 tmp = agp_bridge->driver->mask_memory(agp_bridge, 82 mem->memory[i], mask_type); 83 84 BUG_ON(tmp & 0xffffff0000000ffcULL); 85 pte = (tmp & 0x000000ff00000000ULL) >> 28; 86 pte |=(tmp & 0x00000000fffff000ULL); 87 pte |= GPTE_VALID | GPTE_COHERENT; 88 89 writel(pte, agp_bridge->gatt_table+j); 90 readl(agp_bridge->gatt_table+j); /* PCI Posting. */ 91 } 92 amd64_tlbflush(mem); 93 return 0; 94 } 95 96 /* 97 * This hack alters the order element according 98 * to the size of a long. It sucks. I totally disown this, even 99 * though it does appear to work for the most part. 100 */ 101 static struct aper_size_info_32 amd64_aperture_sizes[7] = 102 { 103 {32, 8192, 3+(sizeof(long)/8), 0 }, 104 {64, 16384, 4+(sizeof(long)/8), 1<<1 }, 105 {128, 32768, 5+(sizeof(long)/8), 1<<2 }, 106 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, 107 {512, 131072, 7+(sizeof(long)/8), 1<<3 }, 108 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, 109 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} 110 }; 111 112 113 /* 114 * Get the current Aperture size from the x86-64. 115 * Note, that there may be multiple x86-64's, but we just return 116 * the value from the first one we find. The set_size functions 117 * keep the rest coherent anyway. Or at least should do. 118 */ 119 static int amd64_fetch_size(void) 120 { 121 struct pci_dev *dev; 122 int i; 123 u32 temp; 124 struct aper_size_info_32 *values; 125 126 dev = k8_northbridges[0]; 127 if (dev==NULL) 128 return 0; 129 130 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); 131 temp = (temp & 0xe); 132 values = A_SIZE_32(amd64_aperture_sizes); 133 134 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 135 if (temp == values[i].size_value) { 136 agp_bridge->previous_size = 137 agp_bridge->current_size = (void *) (values + i); 138 139 agp_bridge->aperture_size_idx = i; 140 return values[i].size; 141 } 142 } 143 return 0; 144 } 145 146 /* 147 * In a multiprocessor x86-64 system, this function gets 148 * called once for each CPU. 149 */ 150 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table) 151 { 152 u64 aperturebase; 153 u32 tmp; 154 u64 aper_base; 155 156 /* Address to map to */ 157 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp); 158 aperturebase = tmp << 25; 159 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 160 161 enable_gart_translation(hammer, gatt_table); 162 163 return aper_base; 164 } 165 166 167 static const struct aper_size_info_32 amd_8151_sizes[7] = 168 { 169 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ 170 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ 171 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ 172 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ 173 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ 174 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ 175 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ 176 }; 177 178 static int amd_8151_configure(void) 179 { 180 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); 181 int i; 182 183 /* Configure AGP regs in each x86-64 host bridge. */ 184 for (i = 0; i < num_k8_northbridges; i++) { 185 agp_bridge->gart_bus_addr = 186 amd64_configure(k8_northbridges[i], gatt_bus); 187 } 188 k8_flush_garts(); 189 return 0; 190 } 191 192 193 static void amd64_cleanup(void) 194 { 195 u32 tmp; 196 int i; 197 for (i = 0; i < num_k8_northbridges; i++) { 198 struct pci_dev *dev = k8_northbridges[i]; 199 /* disable gart translation */ 200 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp); 201 tmp &= ~AMD64_GARTEN; 202 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp); 203 } 204 } 205 206 207 static const struct agp_bridge_driver amd_8151_driver = { 208 .owner = THIS_MODULE, 209 .aperture_sizes = amd_8151_sizes, 210 .size_type = U32_APER_SIZE, 211 .num_aperture_sizes = 7, 212 .configure = amd_8151_configure, 213 .fetch_size = amd64_fetch_size, 214 .cleanup = amd64_cleanup, 215 .tlb_flush = amd64_tlbflush, 216 .mask_memory = agp_generic_mask_memory, 217 .masks = NULL, 218 .agp_enable = agp_generic_enable, 219 .cache_flush = global_cache_flush, 220 .create_gatt_table = agp_generic_create_gatt_table, 221 .free_gatt_table = agp_generic_free_gatt_table, 222 .insert_memory = amd64_insert_memory, 223 .remove_memory = agp_generic_remove_memory, 224 .alloc_by_type = agp_generic_alloc_by_type, 225 .free_by_type = agp_generic_free_by_type, 226 .agp_alloc_page = agp_generic_alloc_page, 227 .agp_alloc_pages = agp_generic_alloc_pages, 228 .agp_destroy_page = agp_generic_destroy_page, 229 .agp_destroy_pages = agp_generic_destroy_pages, 230 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 231 }; 232 233 /* Some basic sanity checks for the aperture. */ 234 static int __devinit agp_aperture_valid(u64 aper, u32 size) 235 { 236 if (!aperture_valid(aper, size, 32*1024*1024)) 237 return 0; 238 239 /* Request the Aperture. This catches cases when someone else 240 already put a mapping in there - happens with some very broken BIOS 241 242 Maybe better to use pci_assign_resource/pci_enable_device instead 243 trusting the bridges? */ 244 if (!aperture_resource && 245 !(aperture_resource = request_mem_region(aper, size, "aperture"))) { 246 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); 247 return 0; 248 } 249 return 1; 250 } 251 252 /* 253 * W*s centric BIOS sometimes only set up the aperture in the AGP 254 * bridge, not the northbridge. On AMD64 this is handled early 255 * in aperture.c, but when IOMMU is not enabled or we run 256 * on a 32bit kernel this needs to be redone. 257 * Unfortunately it is impossible to fix the aperture here because it's too late 258 * to allocate that much memory. But at least error out cleanly instead of 259 * crashing. 260 */ 261 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, 262 u16 cap) 263 { 264 u32 aper_low, aper_hi; 265 u64 aper, nb_aper; 266 int order = 0; 267 u32 nb_order, nb_base; 268 u16 apsize; 269 270 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order); 271 nb_order = (nb_order >> 1) & 7; 272 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base); 273 nb_aper = nb_base << 25; 274 275 /* Northbridge seems to contain crap. Try the AGP bridge. */ 276 277 pci_read_config_word(agp, cap+0x14, &apsize); 278 if (apsize == 0xffff) { 279 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) 280 return 0; 281 return -1; 282 } 283 284 apsize &= 0xfff; 285 /* Some BIOS use weird encodings not in the AGPv3 table. */ 286 if (apsize & 0xff) 287 apsize |= 0xf00; 288 order = 7 - hweight16(apsize); 289 290 pci_read_config_dword(agp, 0x10, &aper_low); 291 pci_read_config_dword(agp, 0x14, &aper_hi); 292 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 293 294 /* 295 * On some sick chips APSIZE is 0. This means it wants 4G 296 * so let double check that order, and lets trust the AMD NB settings 297 */ 298 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) { 299 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n", 300 32 << order); 301 order = nb_order; 302 } 303 304 if (nb_order >= order) { 305 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) 306 return 0; 307 } 308 309 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n", 310 aper, 32 << order); 311 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) 312 return -1; 313 314 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1); 315 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25); 316 317 return 0; 318 } 319 320 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 321 { 322 int i; 323 324 if (cache_k8_northbridges() < 0) 325 return -ENODEV; 326 327 i = 0; 328 for (i = 0; i < num_k8_northbridges; i++) { 329 struct pci_dev *dev = k8_northbridges[i]; 330 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 331 dev_err(&dev->dev, "no usable aperture found\n"); 332 #ifdef __x86_64__ 333 /* should port this to i386 */ 334 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n"); 335 #endif 336 return -1; 337 } 338 } 339 return 0; 340 } 341 342 /* Handle AMD 8151 quirks */ 343 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) 344 { 345 char *revstring; 346 347 switch (pdev->revision) { 348 case 0x01: revstring="A0"; break; 349 case 0x02: revstring="A1"; break; 350 case 0x11: revstring="B0"; break; 351 case 0x12: revstring="B1"; break; 352 case 0x13: revstring="B2"; break; 353 case 0x14: revstring="B3"; break; 354 default: revstring="??"; break; 355 } 356 357 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring); 358 359 /* 360 * Work around errata. 361 * Chips before B2 stepping incorrectly reporting v3.5 362 */ 363 if (pdev->revision < 0x13) { 364 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n"); 365 bridge->major_version = 3; 366 bridge->minor_version = 0; 367 } 368 } 369 370 371 static const struct aper_size_info_32 uli_sizes[7] = 372 { 373 {256, 65536, 6, 10}, 374 {128, 32768, 5, 9}, 375 {64, 16384, 4, 8}, 376 {32, 8192, 3, 7}, 377 {16, 4096, 2, 6}, 378 {8, 2048, 1, 4}, 379 {4, 1024, 0, 3} 380 }; 381 static int __devinit uli_agp_init(struct pci_dev *pdev) 382 { 383 u32 httfea,baseaddr,enuscr; 384 struct pci_dev *dev1; 385 int i; 386 unsigned size = amd64_fetch_size(); 387 388 dev_info(&pdev->dev, "setting up ULi AGP\n"); 389 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); 390 if (dev1 == NULL) { 391 dev_info(&pdev->dev, "can't find ULi secondary device\n"); 392 return -ENODEV; 393 } 394 395 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) 396 if (uli_sizes[i].size == size) 397 break; 398 399 if (i == ARRAY_SIZE(uli_sizes)) { 400 dev_info(&pdev->dev, "no ULi size found for %d\n", size); 401 return -ENODEV; 402 } 403 404 /* shadow x86-64 registers into ULi registers */ 405 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 406 407 /* if x86-64 aperture base is beyond 4G, exit here */ 408 if ((httfea & 0x7fff) >> (32 - 25)) 409 return -ENODEV; 410 411 httfea = (httfea& 0x7fff) << 25; 412 413 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); 414 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; 415 baseaddr|= httfea; 416 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); 417 418 enuscr= httfea+ (size * 1024 * 1024) - 1; 419 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); 420 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); 421 422 pci_dev_put(dev1); 423 return 0; 424 } 425 426 427 static const struct aper_size_info_32 nforce3_sizes[5] = 428 { 429 {512, 131072, 7, 0x00000000 }, 430 {256, 65536, 6, 0x00000008 }, 431 {128, 32768, 5, 0x0000000C }, 432 {64, 16384, 4, 0x0000000E }, 433 {32, 8192, 3, 0x0000000F } 434 }; 435 436 /* Handle shadow device of the Nvidia NForce3 */ 437 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ 438 static int nforce3_agp_init(struct pci_dev *pdev) 439 { 440 u32 tmp, apbase, apbar, aplimit; 441 struct pci_dev *dev1; 442 int i; 443 unsigned size = amd64_fetch_size(); 444 445 dev_info(&pdev->dev, "setting up Nforce3 AGP\n"); 446 447 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); 448 if (dev1 == NULL) { 449 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n"); 450 return -ENODEV; 451 } 452 453 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) 454 if (nforce3_sizes[i].size == size) 455 break; 456 457 if (i == ARRAY_SIZE(nforce3_sizes)) { 458 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size); 459 return -ENODEV; 460 } 461 462 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); 463 tmp &= ~(0xf); 464 tmp |= nforce3_sizes[i].size_value; 465 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 466 467 /* shadow x86-64 registers into NVIDIA registers */ 468 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 469 470 /* if x86-64 aperture base is beyond 4G, exit here */ 471 if ( (apbase & 0x7fff) >> (32 - 25) ) { 472 dev_info(&pdev->dev, "aperture base > 4G\n"); 473 return -ENODEV; 474 } 475 476 apbase = (apbase & 0x7fff) << 25; 477 478 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); 479 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; 480 apbar |= apbase; 481 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); 482 483 aplimit = apbase + (size * 1024 * 1024) - 1; 484 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); 485 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); 486 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); 487 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); 488 489 pci_dev_put(dev1); 490 491 return 0; 492 } 493 494 static int __devinit agp_amd64_probe(struct pci_dev *pdev, 495 const struct pci_device_id *ent) 496 { 497 struct agp_bridge_data *bridge; 498 u8 cap_ptr; 499 int err; 500 501 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 502 if (!cap_ptr) 503 return -ENODEV; 504 505 /* Could check for AGPv3 here */ 506 507 bridge = agp_alloc_bridge(); 508 if (!bridge) 509 return -ENOMEM; 510 511 if (pdev->vendor == PCI_VENDOR_ID_AMD && 512 pdev->device == PCI_DEVICE_ID_AMD_8151_0) { 513 amd8151_init(pdev, bridge); 514 } else { 515 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n", 516 pdev->vendor, pdev->device); 517 } 518 519 bridge->driver = &amd_8151_driver; 520 bridge->dev = pdev; 521 bridge->capndx = cap_ptr; 522 523 /* Fill in the mode register */ 524 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 525 526 if (cache_nbs(pdev, cap_ptr) == -1) { 527 agp_put_bridge(bridge); 528 return -ENODEV; 529 } 530 531 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { 532 int ret = nforce3_agp_init(pdev); 533 if (ret) { 534 agp_put_bridge(bridge); 535 return ret; 536 } 537 } 538 539 if (pdev->vendor == PCI_VENDOR_ID_AL) { 540 int ret = uli_agp_init(pdev); 541 if (ret) { 542 agp_put_bridge(bridge); 543 return ret; 544 } 545 } 546 547 pci_set_drvdata(pdev, bridge); 548 err = agp_add_bridge(bridge); 549 if (err < 0) 550 return err; 551 552 agp_bridges_found++; 553 return 0; 554 } 555 556 static void __devexit agp_amd64_remove(struct pci_dev *pdev) 557 { 558 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 559 560 release_mem_region(virt_to_gart(bridge->gatt_table_real), 561 amd64_aperture_sizes[bridge->aperture_size_idx].size); 562 agp_remove_bridge(bridge); 563 agp_put_bridge(bridge); 564 } 565 566 #ifdef CONFIG_PM 567 568 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) 569 { 570 pci_save_state(pdev); 571 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 572 573 return 0; 574 } 575 576 static int agp_amd64_resume(struct pci_dev *pdev) 577 { 578 pci_set_power_state(pdev, PCI_D0); 579 pci_restore_state(pdev); 580 581 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) 582 nforce3_agp_init(pdev); 583 584 return amd_8151_configure(); 585 } 586 587 #endif /* CONFIG_PM */ 588 589 static struct pci_device_id agp_amd64_pci_table[] = { 590 { 591 .class = (PCI_CLASS_BRIDGE_HOST << 8), 592 .class_mask = ~0, 593 .vendor = PCI_VENDOR_ID_AMD, 594 .device = PCI_DEVICE_ID_AMD_8151_0, 595 .subvendor = PCI_ANY_ID, 596 .subdevice = PCI_ANY_ID, 597 }, 598 /* ULi M1689 */ 599 { 600 .class = (PCI_CLASS_BRIDGE_HOST << 8), 601 .class_mask = ~0, 602 .vendor = PCI_VENDOR_ID_AL, 603 .device = PCI_DEVICE_ID_AL_M1689, 604 .subvendor = PCI_ANY_ID, 605 .subdevice = PCI_ANY_ID, 606 }, 607 /* VIA K8T800Pro */ 608 { 609 .class = (PCI_CLASS_BRIDGE_HOST << 8), 610 .class_mask = ~0, 611 .vendor = PCI_VENDOR_ID_VIA, 612 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, 613 .subvendor = PCI_ANY_ID, 614 .subdevice = PCI_ANY_ID, 615 }, 616 /* VIA K8T800 */ 617 { 618 .class = (PCI_CLASS_BRIDGE_HOST << 8), 619 .class_mask = ~0, 620 .vendor = PCI_VENDOR_ID_VIA, 621 .device = PCI_DEVICE_ID_VIA_8385_0, 622 .subvendor = PCI_ANY_ID, 623 .subdevice = PCI_ANY_ID, 624 }, 625 /* VIA K8M800 / K8N800 */ 626 { 627 .class = (PCI_CLASS_BRIDGE_HOST << 8), 628 .class_mask = ~0, 629 .vendor = PCI_VENDOR_ID_VIA, 630 .device = PCI_DEVICE_ID_VIA_8380_0, 631 .subvendor = PCI_ANY_ID, 632 .subdevice = PCI_ANY_ID, 633 }, 634 /* VIA K8M890 / K8N890 */ 635 { 636 .class = (PCI_CLASS_BRIDGE_HOST << 8), 637 .class_mask = ~0, 638 .vendor = PCI_VENDOR_ID_VIA, 639 .device = PCI_DEVICE_ID_VIA_VT3336, 640 .subvendor = PCI_ANY_ID, 641 .subdevice = PCI_ANY_ID, 642 }, 643 /* VIA K8T890 */ 644 { 645 .class = (PCI_CLASS_BRIDGE_HOST << 8), 646 .class_mask = ~0, 647 .vendor = PCI_VENDOR_ID_VIA, 648 .device = PCI_DEVICE_ID_VIA_3238_0, 649 .subvendor = PCI_ANY_ID, 650 .subdevice = PCI_ANY_ID, 651 }, 652 /* VIA K8T800/K8M800/K8N800 */ 653 { 654 .class = (PCI_CLASS_BRIDGE_HOST << 8), 655 .class_mask = ~0, 656 .vendor = PCI_VENDOR_ID_VIA, 657 .device = PCI_DEVICE_ID_VIA_838X_1, 658 .subvendor = PCI_ANY_ID, 659 .subdevice = PCI_ANY_ID, 660 }, 661 /* NForce3 */ 662 { 663 .class = (PCI_CLASS_BRIDGE_HOST << 8), 664 .class_mask = ~0, 665 .vendor = PCI_VENDOR_ID_NVIDIA, 666 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, 667 .subvendor = PCI_ANY_ID, 668 .subdevice = PCI_ANY_ID, 669 }, 670 { 671 .class = (PCI_CLASS_BRIDGE_HOST << 8), 672 .class_mask = ~0, 673 .vendor = PCI_VENDOR_ID_NVIDIA, 674 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, 675 .subvendor = PCI_ANY_ID, 676 .subdevice = PCI_ANY_ID, 677 }, 678 /* SIS 755 */ 679 { 680 .class = (PCI_CLASS_BRIDGE_HOST << 8), 681 .class_mask = ~0, 682 .vendor = PCI_VENDOR_ID_SI, 683 .device = PCI_DEVICE_ID_SI_755, 684 .subvendor = PCI_ANY_ID, 685 .subdevice = PCI_ANY_ID, 686 }, 687 /* SIS 760 */ 688 { 689 .class = (PCI_CLASS_BRIDGE_HOST << 8), 690 .class_mask = ~0, 691 .vendor = PCI_VENDOR_ID_SI, 692 .device = PCI_DEVICE_ID_SI_760, 693 .subvendor = PCI_ANY_ID, 694 .subdevice = PCI_ANY_ID, 695 }, 696 /* ALI/ULI M1695 */ 697 { 698 .class = (PCI_CLASS_BRIDGE_HOST << 8), 699 .class_mask = ~0, 700 .vendor = PCI_VENDOR_ID_AL, 701 .device = 0x1695, 702 .subvendor = PCI_ANY_ID, 703 .subdevice = PCI_ANY_ID, 704 }, 705 706 { } 707 }; 708 709 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); 710 711 static struct pci_driver agp_amd64_pci_driver = { 712 .name = "agpgart-amd64", 713 .id_table = agp_amd64_pci_table, 714 .probe = agp_amd64_probe, 715 .remove = agp_amd64_remove, 716 #ifdef CONFIG_PM 717 .suspend = agp_amd64_suspend, 718 .resume = agp_amd64_resume, 719 #endif 720 }; 721 722 723 /* Not static due to IOMMU code calling it early. */ 724 int __init agp_amd64_init(void) 725 { 726 int err = 0; 727 728 if (agp_off) 729 return -EINVAL; 730 err = pci_register_driver(&agp_amd64_pci_driver); 731 if (err < 0) 732 return err; 733 734 if (agp_bridges_found == 0) { 735 struct pci_dev *dev; 736 if (!agp_try_unsupported && !agp_try_unsupported_boot) { 737 printk(KERN_INFO PFX "No supported AGP bridge found.\n"); 738 #ifdef MODULE 739 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); 740 #else 741 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 742 #endif 743 return -ENODEV; 744 } 745 746 /* First check that we have at least one AMD64 NB */ 747 if (!pci_dev_present(k8_nb_ids)) 748 return -ENODEV; 749 750 /* Look for any AGP bridge */ 751 dev = NULL; 752 err = -ENODEV; 753 for_each_pci_dev(dev) { 754 if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) 755 continue; 756 /* Only one bridge supported right now */ 757 if (agp_amd64_probe(dev, NULL) == 0) { 758 err = 0; 759 break; 760 } 761 } 762 } 763 return err; 764 } 765 766 static void __exit agp_amd64_cleanup(void) 767 { 768 if (aperture_resource) 769 release_resource(aperture_resource); 770 pci_unregister_driver(&agp_amd64_pci_driver); 771 } 772 773 /* On AMD64 the PCI driver needs to initialize this driver early 774 for the IOMMU, so it has to be called via a backdoor. */ 775 #ifndef CONFIG_GART_IOMMU 776 module_init(agp_amd64_init); 777 module_exit(agp_amd64_cleanup); 778 #endif 779 780 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen"); 781 module_param(agp_try_unsupported, bool, 0); 782 MODULE_LICENSE("GPL"); 783