1 /* 2 * Copyright 2001-2003 SuSE Labs. 3 * Distributed under the GNU public license, v2. 4 * 5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. 6 * It also includes support for the AMD 8151 AGP bridge, 7 * although it doesn't actually do much, as all the real 8 * work is done in the northbridge(s). 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/init.h> 14 #include <linux/agp_backend.h> 15 #include <linux/mmzone.h> 16 #include <asm/page.h> /* PAGE_SIZE */ 17 #include <asm/e820.h> 18 #include <asm/k8.h> 19 #include <asm/gart.h> 20 #include "agp.h" 21 22 /* NVIDIA K8 registers */ 23 #define NVIDIA_X86_64_0_APBASE 0x10 24 #define NVIDIA_X86_64_1_APBASE1 0x50 25 #define NVIDIA_X86_64_1_APLIMIT1 0x54 26 #define NVIDIA_X86_64_1_APSIZE 0xa8 27 #define NVIDIA_X86_64_1_APBASE2 0xd8 28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc 29 30 /* ULi K8 registers */ 31 #define ULI_X86_64_BASE_ADDR 0x10 32 #define ULI_X86_64_HTT_FEA_REG 0x50 33 #define ULI_X86_64_ENU_SCR_REG 0x54 34 35 static struct resource *aperture_resource; 36 static int __initdata agp_try_unsupported = 1; 37 static int agp_bridges_found; 38 39 static void amd64_tlbflush(struct agp_memory *temp) 40 { 41 k8_flush_garts(); 42 } 43 44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 45 { 46 int i, j, num_entries; 47 long long tmp; 48 int mask_type; 49 struct agp_bridge_data *bridge = mem->bridge; 50 u32 pte; 51 52 num_entries = agp_num_entries(); 53 54 if (type != mem->type) 55 return -EINVAL; 56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); 57 if (mask_type != 0) 58 return -EINVAL; 59 60 61 /* Make sure we can fit the range in the gatt table. */ 62 /* FIXME: could wrap */ 63 if (((unsigned long)pg_start + mem->page_count) > num_entries) 64 return -EINVAL; 65 66 j = pg_start; 67 68 /* gatt table should be empty. */ 69 while (j < (pg_start + mem->page_count)) { 70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 71 return -EBUSY; 72 j++; 73 } 74 75 if (!mem->is_flushed) { 76 global_cache_flush(); 77 mem->is_flushed = true; 78 } 79 80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 81 tmp = agp_bridge->driver->mask_memory(agp_bridge, 82 page_to_phys(mem->pages[i]), 83 mask_type); 84 85 BUG_ON(tmp & 0xffffff0000000ffcULL); 86 pte = (tmp & 0x000000ff00000000ULL) >> 28; 87 pte |=(tmp & 0x00000000fffff000ULL); 88 pte |= GPTE_VALID | GPTE_COHERENT; 89 90 writel(pte, agp_bridge->gatt_table+j); 91 readl(agp_bridge->gatt_table+j); /* PCI Posting. */ 92 } 93 amd64_tlbflush(mem); 94 return 0; 95 } 96 97 /* 98 * This hack alters the order element according 99 * to the size of a long. It sucks. I totally disown this, even 100 * though it does appear to work for the most part. 101 */ 102 static struct aper_size_info_32 amd64_aperture_sizes[7] = 103 { 104 {32, 8192, 3+(sizeof(long)/8), 0 }, 105 {64, 16384, 4+(sizeof(long)/8), 1<<1 }, 106 {128, 32768, 5+(sizeof(long)/8), 1<<2 }, 107 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, 108 {512, 131072, 7+(sizeof(long)/8), 1<<3 }, 109 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, 110 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} 111 }; 112 113 114 /* 115 * Get the current Aperture size from the x86-64. 116 * Note, that there may be multiple x86-64's, but we just return 117 * the value from the first one we find. The set_size functions 118 * keep the rest coherent anyway. Or at least should do. 119 */ 120 static int amd64_fetch_size(void) 121 { 122 struct pci_dev *dev; 123 int i; 124 u32 temp; 125 struct aper_size_info_32 *values; 126 127 dev = k8_northbridges[0]; 128 if (dev==NULL) 129 return 0; 130 131 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); 132 temp = (temp & 0xe); 133 values = A_SIZE_32(amd64_aperture_sizes); 134 135 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 136 if (temp == values[i].size_value) { 137 agp_bridge->previous_size = 138 agp_bridge->current_size = (void *) (values + i); 139 140 agp_bridge->aperture_size_idx = i; 141 return values[i].size; 142 } 143 } 144 return 0; 145 } 146 147 /* 148 * In a multiprocessor x86-64 system, this function gets 149 * called once for each CPU. 150 */ 151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table) 152 { 153 u64 aperturebase; 154 u32 tmp; 155 u64 aper_base; 156 157 /* Address to map to */ 158 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp); 159 aperturebase = tmp << 25; 160 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 161 162 enable_gart_translation(hammer, gatt_table); 163 164 return aper_base; 165 } 166 167 168 static const struct aper_size_info_32 amd_8151_sizes[7] = 169 { 170 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ 171 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ 172 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ 173 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ 174 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ 175 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ 176 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ 177 }; 178 179 static int amd_8151_configure(void) 180 { 181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real); 182 int i; 183 184 /* Configure AGP regs in each x86-64 host bridge. */ 185 for (i = 0; i < num_k8_northbridges; i++) { 186 agp_bridge->gart_bus_addr = 187 amd64_configure(k8_northbridges[i], gatt_bus); 188 } 189 k8_flush_garts(); 190 return 0; 191 } 192 193 194 static void amd64_cleanup(void) 195 { 196 u32 tmp; 197 int i; 198 for (i = 0; i < num_k8_northbridges; i++) { 199 struct pci_dev *dev = k8_northbridges[i]; 200 /* disable gart translation */ 201 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp); 202 tmp &= ~AMD64_GARTEN; 203 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp); 204 } 205 } 206 207 208 static const struct agp_bridge_driver amd_8151_driver = { 209 .owner = THIS_MODULE, 210 .aperture_sizes = amd_8151_sizes, 211 .size_type = U32_APER_SIZE, 212 .num_aperture_sizes = 7, 213 .configure = amd_8151_configure, 214 .fetch_size = amd64_fetch_size, 215 .cleanup = amd64_cleanup, 216 .tlb_flush = amd64_tlbflush, 217 .mask_memory = agp_generic_mask_memory, 218 .masks = NULL, 219 .agp_enable = agp_generic_enable, 220 .cache_flush = global_cache_flush, 221 .create_gatt_table = agp_generic_create_gatt_table, 222 .free_gatt_table = agp_generic_free_gatt_table, 223 .insert_memory = amd64_insert_memory, 224 .remove_memory = agp_generic_remove_memory, 225 .alloc_by_type = agp_generic_alloc_by_type, 226 .free_by_type = agp_generic_free_by_type, 227 .agp_alloc_page = agp_generic_alloc_page, 228 .agp_alloc_pages = agp_generic_alloc_pages, 229 .agp_destroy_page = agp_generic_destroy_page, 230 .agp_destroy_pages = agp_generic_destroy_pages, 231 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 232 }; 233 234 /* Some basic sanity checks for the aperture. */ 235 static int __devinit agp_aperture_valid(u64 aper, u32 size) 236 { 237 if (!aperture_valid(aper, size, 32*1024*1024)) 238 return 0; 239 240 /* Request the Aperture. This catches cases when someone else 241 already put a mapping in there - happens with some very broken BIOS 242 243 Maybe better to use pci_assign_resource/pci_enable_device instead 244 trusting the bridges? */ 245 if (!aperture_resource && 246 !(aperture_resource = request_mem_region(aper, size, "aperture"))) { 247 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); 248 return 0; 249 } 250 return 1; 251 } 252 253 /* 254 * W*s centric BIOS sometimes only set up the aperture in the AGP 255 * bridge, not the northbridge. On AMD64 this is handled early 256 * in aperture.c, but when IOMMU is not enabled or we run 257 * on a 32bit kernel this needs to be redone. 258 * Unfortunately it is impossible to fix the aperture here because it's too late 259 * to allocate that much memory. But at least error out cleanly instead of 260 * crashing. 261 */ 262 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, 263 u16 cap) 264 { 265 u32 aper_low, aper_hi; 266 u64 aper, nb_aper; 267 int order = 0; 268 u32 nb_order, nb_base; 269 u16 apsize; 270 271 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order); 272 nb_order = (nb_order >> 1) & 7; 273 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base); 274 nb_aper = nb_base << 25; 275 276 /* Northbridge seems to contain crap. Try the AGP bridge. */ 277 278 pci_read_config_word(agp, cap+0x14, &apsize); 279 if (apsize == 0xffff) { 280 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) 281 return 0; 282 return -1; 283 } 284 285 apsize &= 0xfff; 286 /* Some BIOS use weird encodings not in the AGPv3 table. */ 287 if (apsize & 0xff) 288 apsize |= 0xf00; 289 order = 7 - hweight16(apsize); 290 291 pci_read_config_dword(agp, 0x10, &aper_low); 292 pci_read_config_dword(agp, 0x14, &aper_hi); 293 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 294 295 /* 296 * On some sick chips APSIZE is 0. This means it wants 4G 297 * so let double check that order, and lets trust the AMD NB settings 298 */ 299 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) { 300 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n", 301 32 << order); 302 order = nb_order; 303 } 304 305 if (nb_order >= order) { 306 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) 307 return 0; 308 } 309 310 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n", 311 aper, 32 << order); 312 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) 313 return -1; 314 315 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1); 316 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25); 317 318 return 0; 319 } 320 321 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 322 { 323 int i; 324 325 if (cache_k8_northbridges() < 0) 326 return -ENODEV; 327 328 i = 0; 329 for (i = 0; i < num_k8_northbridges; i++) { 330 struct pci_dev *dev = k8_northbridges[i]; 331 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 332 dev_err(&dev->dev, "no usable aperture found\n"); 333 #ifdef __x86_64__ 334 /* should port this to i386 */ 335 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n"); 336 #endif 337 return -1; 338 } 339 } 340 return 0; 341 } 342 343 /* Handle AMD 8151 quirks */ 344 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) 345 { 346 char *revstring; 347 348 switch (pdev->revision) { 349 case 0x01: revstring="A0"; break; 350 case 0x02: revstring="A1"; break; 351 case 0x11: revstring="B0"; break; 352 case 0x12: revstring="B1"; break; 353 case 0x13: revstring="B2"; break; 354 case 0x14: revstring="B3"; break; 355 default: revstring="??"; break; 356 } 357 358 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring); 359 360 /* 361 * Work around errata. 362 * Chips before B2 stepping incorrectly reporting v3.5 363 */ 364 if (pdev->revision < 0x13) { 365 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n"); 366 bridge->major_version = 3; 367 bridge->minor_version = 0; 368 } 369 } 370 371 372 static const struct aper_size_info_32 uli_sizes[7] = 373 { 374 {256, 65536, 6, 10}, 375 {128, 32768, 5, 9}, 376 {64, 16384, 4, 8}, 377 {32, 8192, 3, 7}, 378 {16, 4096, 2, 6}, 379 {8, 2048, 1, 4}, 380 {4, 1024, 0, 3} 381 }; 382 static int __devinit uli_agp_init(struct pci_dev *pdev) 383 { 384 u32 httfea,baseaddr,enuscr; 385 struct pci_dev *dev1; 386 int i; 387 unsigned size = amd64_fetch_size(); 388 389 dev_info(&pdev->dev, "setting up ULi AGP\n"); 390 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); 391 if (dev1 == NULL) { 392 dev_info(&pdev->dev, "can't find ULi secondary device\n"); 393 return -ENODEV; 394 } 395 396 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) 397 if (uli_sizes[i].size == size) 398 break; 399 400 if (i == ARRAY_SIZE(uli_sizes)) { 401 dev_info(&pdev->dev, "no ULi size found for %d\n", size); 402 return -ENODEV; 403 } 404 405 /* shadow x86-64 registers into ULi registers */ 406 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 407 408 /* if x86-64 aperture base is beyond 4G, exit here */ 409 if ((httfea & 0x7fff) >> (32 - 25)) 410 return -ENODEV; 411 412 httfea = (httfea& 0x7fff) << 25; 413 414 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); 415 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; 416 baseaddr|= httfea; 417 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); 418 419 enuscr= httfea+ (size * 1024 * 1024) - 1; 420 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); 421 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); 422 423 pci_dev_put(dev1); 424 return 0; 425 } 426 427 428 static const struct aper_size_info_32 nforce3_sizes[5] = 429 { 430 {512, 131072, 7, 0x00000000 }, 431 {256, 65536, 6, 0x00000008 }, 432 {128, 32768, 5, 0x0000000C }, 433 {64, 16384, 4, 0x0000000E }, 434 {32, 8192, 3, 0x0000000F } 435 }; 436 437 /* Handle shadow device of the Nvidia NForce3 */ 438 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ 439 static int nforce3_agp_init(struct pci_dev *pdev) 440 { 441 u32 tmp, apbase, apbar, aplimit; 442 struct pci_dev *dev1; 443 int i; 444 unsigned size = amd64_fetch_size(); 445 446 dev_info(&pdev->dev, "setting up Nforce3 AGP\n"); 447 448 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); 449 if (dev1 == NULL) { 450 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n"); 451 return -ENODEV; 452 } 453 454 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) 455 if (nforce3_sizes[i].size == size) 456 break; 457 458 if (i == ARRAY_SIZE(nforce3_sizes)) { 459 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size); 460 return -ENODEV; 461 } 462 463 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); 464 tmp &= ~(0xf); 465 tmp |= nforce3_sizes[i].size_value; 466 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 467 468 /* shadow x86-64 registers into NVIDIA registers */ 469 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 470 471 /* if x86-64 aperture base is beyond 4G, exit here */ 472 if ( (apbase & 0x7fff) >> (32 - 25) ) { 473 dev_info(&pdev->dev, "aperture base > 4G\n"); 474 return -ENODEV; 475 } 476 477 apbase = (apbase & 0x7fff) << 25; 478 479 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); 480 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; 481 apbar |= apbase; 482 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); 483 484 aplimit = apbase + (size * 1024 * 1024) - 1; 485 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); 486 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); 487 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); 488 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); 489 490 pci_dev_put(dev1); 491 492 return 0; 493 } 494 495 static int __devinit agp_amd64_probe(struct pci_dev *pdev, 496 const struct pci_device_id *ent) 497 { 498 struct agp_bridge_data *bridge; 499 u8 cap_ptr; 500 int err; 501 502 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 503 if (!cap_ptr) 504 return -ENODEV; 505 506 /* Could check for AGPv3 here */ 507 508 bridge = agp_alloc_bridge(); 509 if (!bridge) 510 return -ENOMEM; 511 512 if (pdev->vendor == PCI_VENDOR_ID_AMD && 513 pdev->device == PCI_DEVICE_ID_AMD_8151_0) { 514 amd8151_init(pdev, bridge); 515 } else { 516 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n", 517 pdev->vendor, pdev->device); 518 } 519 520 bridge->driver = &amd_8151_driver; 521 bridge->dev = pdev; 522 bridge->capndx = cap_ptr; 523 524 /* Fill in the mode register */ 525 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 526 527 if (cache_nbs(pdev, cap_ptr) == -1) { 528 agp_put_bridge(bridge); 529 return -ENODEV; 530 } 531 532 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { 533 int ret = nforce3_agp_init(pdev); 534 if (ret) { 535 agp_put_bridge(bridge); 536 return ret; 537 } 538 } 539 540 if (pdev->vendor == PCI_VENDOR_ID_AL) { 541 int ret = uli_agp_init(pdev); 542 if (ret) { 543 agp_put_bridge(bridge); 544 return ret; 545 } 546 } 547 548 pci_set_drvdata(pdev, bridge); 549 err = agp_add_bridge(bridge); 550 if (err < 0) 551 return err; 552 553 agp_bridges_found++; 554 return 0; 555 } 556 557 static void __devexit agp_amd64_remove(struct pci_dev *pdev) 558 { 559 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 560 561 release_mem_region(virt_to_phys(bridge->gatt_table_real), 562 amd64_aperture_sizes[bridge->aperture_size_idx].size); 563 agp_remove_bridge(bridge); 564 agp_put_bridge(bridge); 565 } 566 567 #ifdef CONFIG_PM 568 569 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) 570 { 571 pci_save_state(pdev); 572 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 573 574 return 0; 575 } 576 577 static int agp_amd64_resume(struct pci_dev *pdev) 578 { 579 pci_set_power_state(pdev, PCI_D0); 580 pci_restore_state(pdev); 581 582 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) 583 nforce3_agp_init(pdev); 584 585 return amd_8151_configure(); 586 } 587 588 #endif /* CONFIG_PM */ 589 590 static struct pci_device_id agp_amd64_pci_table[] = { 591 { 592 .class = (PCI_CLASS_BRIDGE_HOST << 8), 593 .class_mask = ~0, 594 .vendor = PCI_VENDOR_ID_AMD, 595 .device = PCI_DEVICE_ID_AMD_8151_0, 596 .subvendor = PCI_ANY_ID, 597 .subdevice = PCI_ANY_ID, 598 }, 599 /* ULi M1689 */ 600 { 601 .class = (PCI_CLASS_BRIDGE_HOST << 8), 602 .class_mask = ~0, 603 .vendor = PCI_VENDOR_ID_AL, 604 .device = PCI_DEVICE_ID_AL_M1689, 605 .subvendor = PCI_ANY_ID, 606 .subdevice = PCI_ANY_ID, 607 }, 608 /* VIA K8T800Pro */ 609 { 610 .class = (PCI_CLASS_BRIDGE_HOST << 8), 611 .class_mask = ~0, 612 .vendor = PCI_VENDOR_ID_VIA, 613 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, 614 .subvendor = PCI_ANY_ID, 615 .subdevice = PCI_ANY_ID, 616 }, 617 /* VIA K8T800 */ 618 { 619 .class = (PCI_CLASS_BRIDGE_HOST << 8), 620 .class_mask = ~0, 621 .vendor = PCI_VENDOR_ID_VIA, 622 .device = PCI_DEVICE_ID_VIA_8385_0, 623 .subvendor = PCI_ANY_ID, 624 .subdevice = PCI_ANY_ID, 625 }, 626 /* VIA K8M800 / K8N800 */ 627 { 628 .class = (PCI_CLASS_BRIDGE_HOST << 8), 629 .class_mask = ~0, 630 .vendor = PCI_VENDOR_ID_VIA, 631 .device = PCI_DEVICE_ID_VIA_8380_0, 632 .subvendor = PCI_ANY_ID, 633 .subdevice = PCI_ANY_ID, 634 }, 635 /* VIA K8M890 / K8N890 */ 636 { 637 .class = (PCI_CLASS_BRIDGE_HOST << 8), 638 .class_mask = ~0, 639 .vendor = PCI_VENDOR_ID_VIA, 640 .device = PCI_DEVICE_ID_VIA_VT3336, 641 .subvendor = PCI_ANY_ID, 642 .subdevice = PCI_ANY_ID, 643 }, 644 /* VIA K8T890 */ 645 { 646 .class = (PCI_CLASS_BRIDGE_HOST << 8), 647 .class_mask = ~0, 648 .vendor = PCI_VENDOR_ID_VIA, 649 .device = PCI_DEVICE_ID_VIA_3238_0, 650 .subvendor = PCI_ANY_ID, 651 .subdevice = PCI_ANY_ID, 652 }, 653 /* VIA K8T800/K8M800/K8N800 */ 654 { 655 .class = (PCI_CLASS_BRIDGE_HOST << 8), 656 .class_mask = ~0, 657 .vendor = PCI_VENDOR_ID_VIA, 658 .device = PCI_DEVICE_ID_VIA_838X_1, 659 .subvendor = PCI_ANY_ID, 660 .subdevice = PCI_ANY_ID, 661 }, 662 /* NForce3 */ 663 { 664 .class = (PCI_CLASS_BRIDGE_HOST << 8), 665 .class_mask = ~0, 666 .vendor = PCI_VENDOR_ID_NVIDIA, 667 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, 668 .subvendor = PCI_ANY_ID, 669 .subdevice = PCI_ANY_ID, 670 }, 671 { 672 .class = (PCI_CLASS_BRIDGE_HOST << 8), 673 .class_mask = ~0, 674 .vendor = PCI_VENDOR_ID_NVIDIA, 675 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, 676 .subvendor = PCI_ANY_ID, 677 .subdevice = PCI_ANY_ID, 678 }, 679 /* SIS 755 */ 680 { 681 .class = (PCI_CLASS_BRIDGE_HOST << 8), 682 .class_mask = ~0, 683 .vendor = PCI_VENDOR_ID_SI, 684 .device = PCI_DEVICE_ID_SI_755, 685 .subvendor = PCI_ANY_ID, 686 .subdevice = PCI_ANY_ID, 687 }, 688 /* SIS 760 */ 689 { 690 .class = (PCI_CLASS_BRIDGE_HOST << 8), 691 .class_mask = ~0, 692 .vendor = PCI_VENDOR_ID_SI, 693 .device = PCI_DEVICE_ID_SI_760, 694 .subvendor = PCI_ANY_ID, 695 .subdevice = PCI_ANY_ID, 696 }, 697 /* ALI/ULI M1695 */ 698 { 699 .class = (PCI_CLASS_BRIDGE_HOST << 8), 700 .class_mask = ~0, 701 .vendor = PCI_VENDOR_ID_AL, 702 .device = 0x1695, 703 .subvendor = PCI_ANY_ID, 704 .subdevice = PCI_ANY_ID, 705 }, 706 707 { } 708 }; 709 710 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); 711 712 static struct pci_driver agp_amd64_pci_driver = { 713 .name = "agpgart-amd64", 714 .id_table = agp_amd64_pci_table, 715 .probe = agp_amd64_probe, 716 .remove = agp_amd64_remove, 717 #ifdef CONFIG_PM 718 .suspend = agp_amd64_suspend, 719 .resume = agp_amd64_resume, 720 #endif 721 }; 722 723 724 /* Not static due to IOMMU code calling it early. */ 725 int __init agp_amd64_init(void) 726 { 727 int err = 0; 728 static int done = 0; 729 730 if (agp_off) 731 return -EINVAL; 732 733 if (done++) 734 return agp_bridges_found ? 0 : -ENODEV; 735 736 err = pci_register_driver(&agp_amd64_pci_driver); 737 if (err < 0) 738 return err; 739 740 if (agp_bridges_found == 0) { 741 struct pci_dev *dev; 742 if (!agp_try_unsupported && !agp_try_unsupported_boot) { 743 printk(KERN_INFO PFX "No supported AGP bridge found.\n"); 744 #ifdef MODULE 745 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); 746 #else 747 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 748 #endif 749 return -ENODEV; 750 } 751 752 /* First check that we have at least one AMD64 NB */ 753 if (!pci_dev_present(k8_nb_ids)) 754 return -ENODEV; 755 756 /* Look for any AGP bridge */ 757 dev = NULL; 758 err = -ENODEV; 759 for_each_pci_dev(dev) { 760 if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) 761 continue; 762 /* Only one bridge supported right now */ 763 if (agp_amd64_probe(dev, NULL) == 0) { 764 err = 0; 765 break; 766 } 767 } 768 } 769 return err; 770 } 771 772 static void __exit agp_amd64_cleanup(void) 773 { 774 if (aperture_resource) 775 release_resource(aperture_resource); 776 pci_unregister_driver(&agp_amd64_pci_driver); 777 } 778 779 module_init(agp_amd64_init); 780 module_exit(agp_amd64_cleanup); 781 782 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen"); 783 module_param(agp_try_unsupported, bool, 0); 784 MODULE_LICENSE("GPL"); 785