xref: /openbmc/linux/drivers/char/agp/amd64-agp.c (revision 22246614)
1 /*
2  * Copyright 2001-2003 SuSE Labs.
3  * Distributed under the GNU public license, v2.
4  *
5  * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6  * It also includes support for the AMD 8151 AGP bridge,
7  * although it doesn't actually do much, as all the real
8  * work is done in the northbridge(s).
9  */
10 
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h>		/* PAGE_SIZE */
17 #include <asm/e820.h>
18 #include <asm/k8.h>
19 #include "agp.h"
20 
21 /* PTE bits. */
22 #define GPTE_VALID	1
23 #define GPTE_COHERENT	2
24 
25 /* Aperture control register bits. */
26 #define GARTEN		(1<<0)
27 #define DISGARTCPU	(1<<4)
28 #define DISGARTIO	(1<<5)
29 
30 /* GART cache control register bits. */
31 #define INVGART		(1<<0)
32 #define GARTPTEERR	(1<<1)
33 
34 /* K8 On-cpu GART registers */
35 #define AMD64_GARTAPERTURECTL	0x90
36 #define AMD64_GARTAPERTUREBASE	0x94
37 #define AMD64_GARTTABLEBASE	0x98
38 #define AMD64_GARTCACHECTL	0x9c
39 #define AMD64_GARTEN		(1<<0)
40 
41 /* NVIDIA K8 registers */
42 #define NVIDIA_X86_64_0_APBASE		0x10
43 #define NVIDIA_X86_64_1_APBASE1		0x50
44 #define NVIDIA_X86_64_1_APLIMIT1	0x54
45 #define NVIDIA_X86_64_1_APSIZE		0xa8
46 #define NVIDIA_X86_64_1_APBASE2		0xd8
47 #define NVIDIA_X86_64_1_APLIMIT2	0xdc
48 
49 /* ULi K8 registers */
50 #define ULI_X86_64_BASE_ADDR		0x10
51 #define ULI_X86_64_HTT_FEA_REG		0x50
52 #define ULI_X86_64_ENU_SCR_REG		0x54
53 
54 static struct resource *aperture_resource;
55 static int __initdata agp_try_unsupported = 1;
56 
57 static void amd64_tlbflush(struct agp_memory *temp)
58 {
59 	k8_flush_garts();
60 }
61 
62 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
63 {
64 	int i, j, num_entries;
65 	long long tmp;
66 	int mask_type;
67 	struct agp_bridge_data *bridge = mem->bridge;
68 	u32 pte;
69 
70 	num_entries = agp_num_entries();
71 
72 	if (type != mem->type)
73 		return -EINVAL;
74 	mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
75 	if (mask_type != 0)
76 		return -EINVAL;
77 
78 
79 	/* Make sure we can fit the range in the gatt table. */
80 	/* FIXME: could wrap */
81 	if (((unsigned long)pg_start + mem->page_count) > num_entries)
82 		return -EINVAL;
83 
84 	j = pg_start;
85 
86 	/* gatt table should be empty. */
87 	while (j < (pg_start + mem->page_count)) {
88 		if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
89 			return -EBUSY;
90 		j++;
91 	}
92 
93 	if (mem->is_flushed == FALSE) {
94 		global_cache_flush();
95 		mem->is_flushed = TRUE;
96 	}
97 
98 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
99 		tmp = agp_bridge->driver->mask_memory(agp_bridge,
100 			mem->memory[i], mask_type);
101 
102 		BUG_ON(tmp & 0xffffff0000000ffcULL);
103 		pte = (tmp & 0x000000ff00000000ULL) >> 28;
104 		pte |=(tmp & 0x00000000fffff000ULL);
105 		pte |= GPTE_VALID | GPTE_COHERENT;
106 
107 		writel(pte, agp_bridge->gatt_table+j);
108 		readl(agp_bridge->gatt_table+j);	/* PCI Posting. */
109 	}
110 	amd64_tlbflush(mem);
111 	return 0;
112 }
113 
114 /*
115  * This hack alters the order element according
116  * to the size of a long. It sucks. I totally disown this, even
117  * though it does appear to work for the most part.
118  */
119 static struct aper_size_info_32 amd64_aperture_sizes[7] =
120 {
121 	{32,   8192,   3+(sizeof(long)/8), 0 },
122 	{64,   16384,  4+(sizeof(long)/8), 1<<1 },
123 	{128,  32768,  5+(sizeof(long)/8), 1<<2 },
124 	{256,  65536,  6+(sizeof(long)/8), 1<<1 | 1<<2 },
125 	{512,  131072, 7+(sizeof(long)/8), 1<<3 },
126 	{1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
127 	{2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
128 };
129 
130 
131 /*
132  * Get the current Aperture size from the x86-64.
133  * Note, that there may be multiple x86-64's, but we just return
134  * the value from the first one we find. The set_size functions
135  * keep the rest coherent anyway. Or at least should do.
136  */
137 static int amd64_fetch_size(void)
138 {
139 	struct pci_dev *dev;
140 	int i;
141 	u32 temp;
142 	struct aper_size_info_32 *values;
143 
144 	dev = k8_northbridges[0];
145 	if (dev==NULL)
146 		return 0;
147 
148 	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
149 	temp = (temp & 0xe);
150 	values = A_SIZE_32(amd64_aperture_sizes);
151 
152 	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
153 		if (temp == values[i].size_value) {
154 			agp_bridge->previous_size =
155 			    agp_bridge->current_size = (void *) (values + i);
156 
157 			agp_bridge->aperture_size_idx = i;
158 			return values[i].size;
159 		}
160 	}
161 	return 0;
162 }
163 
164 /*
165  * In a multiprocessor x86-64 system, this function gets
166  * called once for each CPU.
167  */
168 static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
169 {
170 	u64 aperturebase;
171 	u32 tmp;
172 	u64 addr, aper_base;
173 
174 	/* Address to map to */
175 	pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
176 	aperturebase = tmp << 25;
177 	aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
178 
179 	/* address of the mappings table */
180 	addr = (u64) gatt_table;
181 	addr >>= 12;
182 	tmp = (u32) addr<<4;
183 	tmp &= ~0xf;
184 	pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
185 
186 	/* Enable GART translation for this hammer. */
187 	pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
188 	tmp |= GARTEN;
189 	tmp &= ~(DISGARTCPU | DISGARTIO);
190 	pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
191 
192 	return aper_base;
193 }
194 
195 
196 static const struct aper_size_info_32 amd_8151_sizes[7] =
197 {
198 	{2048, 524288, 9, 0x00000000 },	/* 0 0 0 0 0 0 */
199 	{1024, 262144, 8, 0x00000400 },	/* 1 0 0 0 0 0 */
200 	{512,  131072, 7, 0x00000600 },	/* 1 1 0 0 0 0 */
201 	{256,  65536,  6, 0x00000700 },	/* 1 1 1 0 0 0 */
202 	{128,  32768,  5, 0x00000720 },	/* 1 1 1 1 0 0 */
203 	{64,   16384,  4, 0x00000730 },	/* 1 1 1 1 1 0 */
204 	{32,   8192,   3, 0x00000738 }	/* 1 1 1 1 1 1 */
205 };
206 
207 static int amd_8151_configure(void)
208 {
209 	unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
210 	int i;
211 
212 	/* Configure AGP regs in each x86-64 host bridge. */
213         for (i = 0; i < num_k8_northbridges; i++) {
214 		agp_bridge->gart_bus_addr =
215 				amd64_configure(k8_northbridges[i], gatt_bus);
216 	}
217 	k8_flush_garts();
218 	return 0;
219 }
220 
221 
222 static void amd64_cleanup(void)
223 {
224 	u32 tmp;
225 	int i;
226         for (i = 0; i < num_k8_northbridges; i++) {
227 		struct pci_dev *dev = k8_northbridges[i];
228 		/* disable gart translation */
229 		pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
230 		tmp &= ~AMD64_GARTEN;
231 		pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
232 	}
233 }
234 
235 
236 static const struct agp_bridge_driver amd_8151_driver = {
237 	.owner			= THIS_MODULE,
238 	.aperture_sizes		= amd_8151_sizes,
239 	.size_type		= U32_APER_SIZE,
240 	.num_aperture_sizes	= 7,
241 	.configure		= amd_8151_configure,
242 	.fetch_size		= amd64_fetch_size,
243 	.cleanup		= amd64_cleanup,
244 	.tlb_flush		= amd64_tlbflush,
245 	.mask_memory		= agp_generic_mask_memory,
246 	.masks			= NULL,
247 	.agp_enable		= agp_generic_enable,
248 	.cache_flush		= global_cache_flush,
249 	.create_gatt_table	= agp_generic_create_gatt_table,
250 	.free_gatt_table	= agp_generic_free_gatt_table,
251 	.insert_memory		= amd64_insert_memory,
252 	.remove_memory		= agp_generic_remove_memory,
253 	.alloc_by_type		= agp_generic_alloc_by_type,
254 	.free_by_type		= agp_generic_free_by_type,
255 	.agp_alloc_page		= agp_generic_alloc_page,
256 	.agp_destroy_page	= agp_generic_destroy_page,
257 	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
258 };
259 
260 /* Some basic sanity checks for the aperture. */
261 static int __devinit aperture_valid(u64 aper, u32 size)
262 {
263 	if (aper == 0) {
264 		printk(KERN_ERR PFX "No aperture\n");
265 		return 0;
266 	}
267 	if (size < 32*1024*1024) {
268 		printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
269 		return 0;
270 	}
271        if ((u64)aper + size > 0x100000000ULL) {
272 		printk(KERN_ERR PFX "Aperture out of bounds\n");
273 		return 0;
274 	}
275 	if (e820_any_mapped(aper, aper + size, E820_RAM)) {
276 		printk(KERN_ERR PFX "Aperture pointing to RAM\n");
277 		return 0;
278 	}
279 
280 	/* Request the Aperture. This catches cases when someone else
281 	   already put a mapping in there - happens with some very broken BIOS
282 
283 	   Maybe better to use pci_assign_resource/pci_enable_device instead
284 	   trusting the bridges? */
285 	if (!aperture_resource &&
286 	    !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
287 		printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
288 		return 0;
289 	}
290 	return 1;
291 }
292 
293 /*
294  * W*s centric BIOS sometimes only set up the aperture in the AGP
295  * bridge, not the northbridge. On AMD64 this is handled early
296  * in aperture.c, but when IOMMU is not enabled or we run
297  * on a 32bit kernel this needs to be redone.
298  * Unfortunately it is impossible to fix the aperture here because it's too late
299  * to allocate that much memory. But at least error out cleanly instead of
300  * crashing.
301  */
302 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
303 								 u16 cap)
304 {
305 	u32 aper_low, aper_hi;
306 	u64 aper, nb_aper;
307 	int order = 0;
308 	u32 nb_order, nb_base;
309 	u16 apsize;
310 
311 	pci_read_config_dword(nb, 0x90, &nb_order);
312 	nb_order = (nb_order >> 1) & 7;
313 	pci_read_config_dword(nb, 0x94, &nb_base);
314 	nb_aper = nb_base << 25;
315 	if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
316 		return 0;
317 	}
318 
319 	/* Northbridge seems to contain crap. Try the AGP bridge. */
320 
321 	pci_read_config_word(agp, cap+0x14, &apsize);
322 	if (apsize == 0xffff)
323 		return -1;
324 
325 	apsize &= 0xfff;
326 	/* Some BIOS use weird encodings not in the AGPv3 table. */
327 	if (apsize & 0xff)
328 		apsize |= 0xf00;
329 	order = 7 - hweight16(apsize);
330 
331 	pci_read_config_dword(agp, 0x10, &aper_low);
332 	pci_read_config_dword(agp, 0x14, &aper_hi);
333 	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
334 	printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
335 	if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
336 		return -1;
337 
338 	pci_write_config_dword(nb, 0x90, order << 1);
339 	pci_write_config_dword(nb, 0x94, aper >> 25);
340 
341 	return 0;
342 }
343 
344 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
345 {
346 	int i;
347 
348 	if (cache_k8_northbridges() < 0)
349 		return -ENODEV;
350 
351 	i = 0;
352 	for (i = 0; i < num_k8_northbridges; i++) {
353 		struct pci_dev *dev = k8_northbridges[i];
354 		if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
355 			printk(KERN_ERR PFX "No usable aperture found.\n");
356 #ifdef __x86_64__
357 			/* should port this to i386 */
358 			printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
359 #endif
360 			return -1;
361 		}
362 	}
363 	return 0;
364 }
365 
366 /* Handle AMD 8151 quirks */
367 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
368 {
369 	char *revstring;
370 
371 	switch (pdev->revision) {
372 	case 0x01: revstring="A0"; break;
373 	case 0x02: revstring="A1"; break;
374 	case 0x11: revstring="B0"; break;
375 	case 0x12: revstring="B1"; break;
376 	case 0x13: revstring="B2"; break;
377 	case 0x14: revstring="B3"; break;
378 	default:   revstring="??"; break;
379 	}
380 
381 	printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
382 
383 	/*
384 	 * Work around errata.
385 	 * Chips before B2 stepping incorrectly reporting v3.5
386 	 */
387 	if (pdev->revision < 0x13) {
388 		printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
389 		bridge->major_version = 3;
390 		bridge->minor_version = 0;
391 	}
392 }
393 
394 
395 static const struct aper_size_info_32 uli_sizes[7] =
396 {
397 	{256, 65536, 6, 10},
398 	{128, 32768, 5, 9},
399 	{64, 16384, 4, 8},
400 	{32, 8192, 3, 7},
401 	{16, 4096, 2, 6},
402 	{8, 2048, 1, 4},
403 	{4, 1024, 0, 3}
404 };
405 static int __devinit uli_agp_init(struct pci_dev *pdev)
406 {
407 	u32 httfea,baseaddr,enuscr;
408 	struct pci_dev *dev1;
409 	int i;
410 	unsigned size = amd64_fetch_size();
411 	printk(KERN_INFO "Setting up ULi AGP.\n");
412 	dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
413 	if (dev1 == NULL) {
414 		printk(KERN_INFO PFX "Detected a ULi chipset, "
415 			"but could not fine the secondary device.\n");
416 		return -ENODEV;
417 	}
418 
419 	for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
420 		if (uli_sizes[i].size == size)
421 			break;
422 
423 	if (i == ARRAY_SIZE(uli_sizes)) {
424 		printk(KERN_INFO PFX "No ULi size found for %d\n", size);
425 		return -ENODEV;
426 	}
427 
428 	/* shadow x86-64 registers into ULi registers */
429 	pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
430 
431 	/* if x86-64 aperture base is beyond 4G, exit here */
432 	if ((httfea & 0x7fff) >> (32 - 25))
433 		return -ENODEV;
434 
435 	httfea = (httfea& 0x7fff) << 25;
436 
437 	pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
438 	baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
439 	baseaddr|= httfea;
440 	pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
441 
442 	enuscr= httfea+ (size * 1024 * 1024) - 1;
443 	pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
444 	pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
445 
446 	pci_dev_put(dev1);
447 	return 0;
448 }
449 
450 
451 static const struct aper_size_info_32 nforce3_sizes[5] =
452 {
453 	{512,  131072, 7, 0x00000000 },
454 	{256,  65536,  6, 0x00000008 },
455 	{128,  32768,  5, 0x0000000C },
456 	{64,   16384,  4, 0x0000000E },
457 	{32,   8192,   3, 0x0000000F }
458 };
459 
460 /* Handle shadow device of the Nvidia NForce3 */
461 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
462 static int nforce3_agp_init(struct pci_dev *pdev)
463 {
464 	u32 tmp, apbase, apbar, aplimit;
465 	struct pci_dev *dev1;
466 	int i;
467 	unsigned size = amd64_fetch_size();
468 
469 	printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
470 
471 	dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
472 	if (dev1 == NULL) {
473 		printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
474 			"nForce3 chipset, but could not find "
475 			"the secondary device.\n");
476 		return -ENODEV;
477 	}
478 
479 	for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
480 		if (nforce3_sizes[i].size == size)
481 			break;
482 
483 	if (i == ARRAY_SIZE(nforce3_sizes)) {
484 		printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
485 		return -ENODEV;
486 	}
487 
488 	pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
489 	tmp &= ~(0xf);
490 	tmp |= nforce3_sizes[i].size_value;
491 	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
492 
493 	/* shadow x86-64 registers into NVIDIA registers */
494 	pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
495 
496 	/* if x86-64 aperture base is beyond 4G, exit here */
497 	if ( (apbase & 0x7fff) >> (32 - 25) ) {
498 		printk(KERN_INFO PFX "aperture base > 4G\n");
499 		return -ENODEV;
500 	}
501 
502 	apbase = (apbase & 0x7fff) << 25;
503 
504 	pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
505 	apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
506 	apbar |= apbase;
507 	pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
508 
509 	aplimit = apbase + (size * 1024 * 1024) - 1;
510 	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
511 	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
512 	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
513 	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
514 
515 	pci_dev_put(dev1);
516 
517 	return 0;
518 }
519 
520 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
521 				     const struct pci_device_id *ent)
522 {
523 	struct agp_bridge_data *bridge;
524 	u8 cap_ptr;
525 
526 	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
527 	if (!cap_ptr)
528 		return -ENODEV;
529 
530 	/* Could check for AGPv3 here */
531 
532 	bridge = agp_alloc_bridge();
533 	if (!bridge)
534 		return -ENOMEM;
535 
536 	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
537 	    pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
538 		amd8151_init(pdev, bridge);
539 	} else {
540 		printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
541 	}
542 
543 	bridge->driver = &amd_8151_driver;
544 	bridge->dev = pdev;
545 	bridge->capndx = cap_ptr;
546 
547 	/* Fill in the mode register */
548 	pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
549 
550 	if (cache_nbs(pdev, cap_ptr) == -1) {
551 		agp_put_bridge(bridge);
552 		return -ENODEV;
553 	}
554 
555 	if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
556 		int ret = nforce3_agp_init(pdev);
557 		if (ret) {
558 			agp_put_bridge(bridge);
559 			return ret;
560 		}
561 	}
562 
563 	if (pdev->vendor == PCI_VENDOR_ID_AL) {
564 		int ret = uli_agp_init(pdev);
565 		if (ret) {
566 			agp_put_bridge(bridge);
567 			return ret;
568 		}
569 	}
570 
571 	pci_set_drvdata(pdev, bridge);
572 	return agp_add_bridge(bridge);
573 }
574 
575 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
576 {
577 	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
578 
579 	release_mem_region(virt_to_gart(bridge->gatt_table_real),
580 			   amd64_aperture_sizes[bridge->aperture_size_idx].size);
581 	agp_remove_bridge(bridge);
582 	agp_put_bridge(bridge);
583 }
584 
585 #ifdef CONFIG_PM
586 
587 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
588 {
589 	pci_save_state(pdev);
590 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
591 
592 	return 0;
593 }
594 
595 static int agp_amd64_resume(struct pci_dev *pdev)
596 {
597 	pci_set_power_state(pdev, PCI_D0);
598 	pci_restore_state(pdev);
599 
600 	if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
601 		nforce3_agp_init(pdev);
602 
603 	return amd_8151_configure();
604 }
605 
606 #endif /* CONFIG_PM */
607 
608 static struct pci_device_id agp_amd64_pci_table[] = {
609 	{
610 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
611 	.class_mask	= ~0,
612 	.vendor		= PCI_VENDOR_ID_AMD,
613 	.device		= PCI_DEVICE_ID_AMD_8151_0,
614 	.subvendor	= PCI_ANY_ID,
615 	.subdevice	= PCI_ANY_ID,
616 	},
617 	/* ULi M1689 */
618 	{
619 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
620 	.class_mask	= ~0,
621 	.vendor		= PCI_VENDOR_ID_AL,
622 	.device		= PCI_DEVICE_ID_AL_M1689,
623 	.subvendor	= PCI_ANY_ID,
624 	.subdevice	= PCI_ANY_ID,
625 	},
626 	/* VIA K8T800Pro */
627 	{
628 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
629 	.class_mask	= ~0,
630 	.vendor		= PCI_VENDOR_ID_VIA,
631 	.device		= PCI_DEVICE_ID_VIA_K8T800PRO_0,
632 	.subvendor	= PCI_ANY_ID,
633 	.subdevice	= PCI_ANY_ID,
634 	},
635 	/* VIA K8T800 */
636 	{
637 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
638 	.class_mask	= ~0,
639 	.vendor		= PCI_VENDOR_ID_VIA,
640 	.device		= PCI_DEVICE_ID_VIA_8385_0,
641 	.subvendor	= PCI_ANY_ID,
642 	.subdevice	= PCI_ANY_ID,
643 	},
644 	/* VIA K8M800 / K8N800 */
645 	{
646 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
647 	.class_mask	= ~0,
648 	.vendor		= PCI_VENDOR_ID_VIA,
649 	.device		= PCI_DEVICE_ID_VIA_8380_0,
650 	.subvendor	= PCI_ANY_ID,
651 	.subdevice	= PCI_ANY_ID,
652 	},
653 	/* VIA K8M890 / K8N890 */
654 	{
655 	.class          = (PCI_CLASS_BRIDGE_HOST << 8),
656 	.class_mask     = ~0,
657 	.vendor         = PCI_VENDOR_ID_VIA,
658 	.device         = PCI_DEVICE_ID_VIA_VT3336,
659 	.subvendor      = PCI_ANY_ID,
660 	.subdevice      = PCI_ANY_ID,
661 	},
662 	/* VIA K8T890 */
663 	{
664 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
665 	.class_mask	= ~0,
666 	.vendor		= PCI_VENDOR_ID_VIA,
667 	.device		= PCI_DEVICE_ID_VIA_3238_0,
668 	.subvendor	= PCI_ANY_ID,
669 	.subdevice	= PCI_ANY_ID,
670 	},
671 	/* VIA K8T800/K8M800/K8N800 */
672 	{
673 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
674 	.class_mask	= ~0,
675 	.vendor		= PCI_VENDOR_ID_VIA,
676 	.device		= PCI_DEVICE_ID_VIA_838X_1,
677 	.subvendor	= PCI_ANY_ID,
678 	.subdevice	= PCI_ANY_ID,
679 	},
680 	/* NForce3 */
681 	{
682 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
683 	.class_mask	= ~0,
684 	.vendor		= PCI_VENDOR_ID_NVIDIA,
685 	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE3,
686 	.subvendor	= PCI_ANY_ID,
687 	.subdevice	= PCI_ANY_ID,
688 	},
689 	{
690 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
691 	.class_mask	= ~0,
692 	.vendor		= PCI_VENDOR_ID_NVIDIA,
693 	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE3S,
694 	.subvendor	= PCI_ANY_ID,
695 	.subdevice	= PCI_ANY_ID,
696 	},
697 	/* SIS 755 */
698 	{
699 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
700 	.class_mask	= ~0,
701 	.vendor		= PCI_VENDOR_ID_SI,
702 	.device		= PCI_DEVICE_ID_SI_755,
703 	.subvendor	= PCI_ANY_ID,
704 	.subdevice	= PCI_ANY_ID,
705 	},
706 	/* SIS 760 */
707 	{
708 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
709 	.class_mask	= ~0,
710 	.vendor		= PCI_VENDOR_ID_SI,
711 	.device		= PCI_DEVICE_ID_SI_760,
712 	.subvendor	= PCI_ANY_ID,
713 	.subdevice	= PCI_ANY_ID,
714 	},
715 	/* ALI/ULI M1695 */
716 	{
717 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
718 	.class_mask	= ~0,
719 	.vendor		= PCI_VENDOR_ID_AL,
720 	.device		= 0x1695,
721 	.subvendor	= PCI_ANY_ID,
722 	.subdevice	= PCI_ANY_ID,
723 	},
724 
725 	{ }
726 };
727 
728 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
729 
730 static struct pci_driver agp_amd64_pci_driver = {
731 	.name		= "agpgart-amd64",
732 	.id_table	= agp_amd64_pci_table,
733 	.probe		= agp_amd64_probe,
734 	.remove		= agp_amd64_remove,
735 #ifdef CONFIG_PM
736 	.suspend	= agp_amd64_suspend,
737 	.resume		= agp_amd64_resume,
738 #endif
739 };
740 
741 
742 /* Not static due to IOMMU code calling it early. */
743 int __init agp_amd64_init(void)
744 {
745 	int err = 0;
746 
747 	if (agp_off)
748 		return -EINVAL;
749 	if (pci_register_driver(&agp_amd64_pci_driver) < 0) {
750 		struct pci_dev *dev;
751 		if (!agp_try_unsupported && !agp_try_unsupported_boot) {
752 			printk(KERN_INFO PFX "No supported AGP bridge found.\n");
753 #ifdef MODULE
754 			printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
755 #else
756 			printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
757 #endif
758 			return -ENODEV;
759 		}
760 
761 		/* First check that we have at least one AMD64 NB */
762 		if (!pci_dev_present(k8_nb_ids))
763 			return -ENODEV;
764 
765 		/* Look for any AGP bridge */
766 		dev = NULL;
767 		err = -ENODEV;
768 		for_each_pci_dev(dev) {
769 			if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
770 				continue;
771 			/* Only one bridge supported right now */
772 			if (agp_amd64_probe(dev, NULL) == 0) {
773 				err = 0;
774 				break;
775 			}
776 		}
777 	}
778 	return err;
779 }
780 
781 static void __exit agp_amd64_cleanup(void)
782 {
783 	if (aperture_resource)
784 		release_resource(aperture_resource);
785 	pci_unregister_driver(&agp_amd64_pci_driver);
786 }
787 
788 /* On AMD64 the PCI driver needs to initialize this driver early
789    for the IOMMU, so it has to be called via a backdoor. */
790 #ifndef CONFIG_GART_IOMMU
791 module_init(agp_amd64_init);
792 module_exit(agp_amd64_cleanup);
793 #endif
794 
795 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
796 module_param(agp_try_unsupported, bool, 0);
797 MODULE_LICENSE("GPL");
798