1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/delay.h> 10 #include <linux/list.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_domain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/slab.h> 19 #include <linux/sys_soc.h> 20 #include <linux/iopoll.h> 21 22 #include <linux/platform_data/ti-sysc.h> 23 24 #include <dt-bindings/bus/ti-sysc.h> 25 26 #define DIS_ISP BIT(2) 27 #define DIS_IVA BIT(1) 28 #define DIS_SGX BIT(0) 29 30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 enum sysc_soc { 35 SOC_UNKNOWN, 36 SOC_2420, 37 SOC_2430, 38 SOC_3430, 39 SOC_3630, 40 SOC_4430, 41 SOC_4460, 42 SOC_4470, 43 SOC_5430, 44 SOC_AM3, 45 SOC_AM4, 46 SOC_DRA7, 47 }; 48 49 struct sysc_address { 50 unsigned long base; 51 struct list_head node; 52 }; 53 54 struct sysc_soc_info { 55 unsigned long general_purpose:1; 56 enum sysc_soc soc; 57 struct mutex list_lock; /* disabled modules list lock */ 58 struct list_head disabled_modules; 59 }; 60 61 enum sysc_clocks { 62 SYSC_FCK, 63 SYSC_ICK, 64 SYSC_OPTFCK0, 65 SYSC_OPTFCK1, 66 SYSC_OPTFCK2, 67 SYSC_OPTFCK3, 68 SYSC_OPTFCK4, 69 SYSC_OPTFCK5, 70 SYSC_OPTFCK6, 71 SYSC_OPTFCK7, 72 SYSC_MAX_CLOCKS, 73 }; 74 75 static struct sysc_soc_info *sysc_soc; 76 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 77 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 79 "opt5", "opt6", "opt7", 80 }; 81 82 #define SYSC_IDLEMODE_MASK 3 83 #define SYSC_CLOCKACTIVITY_MASK 3 84 85 /** 86 * struct sysc - TI sysc interconnect target module registers and capabilities 87 * @dev: struct device pointer 88 * @module_pa: physical address of the interconnect target module 89 * @module_size: size of the interconnect target module 90 * @module_va: virtual address of the interconnect target module 91 * @offsets: register offsets from module base 92 * @mdata: ti-sysc to hwmod translation data for a module 93 * @clocks: clocks used by the interconnect target module 94 * @clock_roles: clock role names for the found clocks 95 * @nr_clocks: number of clocks used by the interconnect target module 96 * @rsts: resets used by the interconnect target module 97 * @legacy_mode: configured for legacy mode if set 98 * @cap: interconnect target module capabilities 99 * @cfg: interconnect target module configuration 100 * @cookie: data used by legacy platform callbacks 101 * @name: name if available 102 * @revision: interconnect target module revision 103 * @reserved: target module is reserved and already in use 104 * @enabled: sysc runtime enabled status 105 * @needs_resume: runtime resume needed on resume from suspend 106 * @child_needs_resume: runtime resume needed for child on resume from suspend 107 * @disable_on_idle: status flag used for disabling modules with resets 108 * @idle_work: work structure used to perform delayed idle on a module 109 * @pre_reset_quirk: module specific pre-reset quirk 110 * @post_reset_quirk: module specific post-reset quirk 111 * @reset_done_quirk: module specific reset done quirk 112 * @module_enable_quirk: module specific enable quirk 113 * @module_disable_quirk: module specific disable quirk 114 * @module_unlock_quirk: module specific sysconfig unlock quirk 115 * @module_lock_quirk: module specific sysconfig lock quirk 116 */ 117 struct sysc { 118 struct device *dev; 119 u64 module_pa; 120 u32 module_size; 121 void __iomem *module_va; 122 int offsets[SYSC_MAX_REGS]; 123 struct ti_sysc_module_data *mdata; 124 struct clk **clocks; 125 const char **clock_roles; 126 int nr_clocks; 127 struct reset_control *rsts; 128 const char *legacy_mode; 129 const struct sysc_capabilities *cap; 130 struct sysc_config cfg; 131 struct ti_sysc_cookie cookie; 132 const char *name; 133 u32 revision; 134 unsigned int reserved:1; 135 unsigned int enabled:1; 136 unsigned int needs_resume:1; 137 unsigned int child_needs_resume:1; 138 struct delayed_work idle_work; 139 void (*pre_reset_quirk)(struct sysc *sysc); 140 void (*post_reset_quirk)(struct sysc *sysc); 141 void (*reset_done_quirk)(struct sysc *sysc); 142 void (*module_enable_quirk)(struct sysc *sysc); 143 void (*module_disable_quirk)(struct sysc *sysc); 144 void (*module_unlock_quirk)(struct sysc *sysc); 145 void (*module_lock_quirk)(struct sysc *sysc); 146 }; 147 148 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 149 bool is_child); 150 151 static void sysc_write(struct sysc *ddata, int offset, u32 value) 152 { 153 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 154 writew_relaxed(value & 0xffff, ddata->module_va + offset); 155 156 /* Only i2c revision has LO and HI register with stride of 4 */ 157 if (ddata->offsets[SYSC_REVISION] >= 0 && 158 offset == ddata->offsets[SYSC_REVISION]) { 159 u16 hi = value >> 16; 160 161 writew_relaxed(hi, ddata->module_va + offset + 4); 162 } 163 164 return; 165 } 166 167 writel_relaxed(value, ddata->module_va + offset); 168 } 169 170 static u32 sysc_read(struct sysc *ddata, int offset) 171 { 172 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 173 u32 val; 174 175 val = readw_relaxed(ddata->module_va + offset); 176 177 /* Only i2c revision has LO and HI register with stride of 4 */ 178 if (ddata->offsets[SYSC_REVISION] >= 0 && 179 offset == ddata->offsets[SYSC_REVISION]) { 180 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 181 182 val |= tmp << 16; 183 } 184 185 return val; 186 } 187 188 return readl_relaxed(ddata->module_va + offset); 189 } 190 191 static bool sysc_opt_clks_needed(struct sysc *ddata) 192 { 193 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 194 } 195 196 static u32 sysc_read_revision(struct sysc *ddata) 197 { 198 int offset = ddata->offsets[SYSC_REVISION]; 199 200 if (offset < 0) 201 return 0; 202 203 return sysc_read(ddata, offset); 204 } 205 206 static u32 sysc_read_sysconfig(struct sysc *ddata) 207 { 208 int offset = ddata->offsets[SYSC_SYSCONFIG]; 209 210 if (offset < 0) 211 return 0; 212 213 return sysc_read(ddata, offset); 214 } 215 216 static u32 sysc_read_sysstatus(struct sysc *ddata) 217 { 218 int offset = ddata->offsets[SYSC_SYSSTATUS]; 219 220 if (offset < 0) 221 return 0; 222 223 return sysc_read(ddata, offset); 224 } 225 226 /* Poll on reset status */ 227 static int sysc_wait_softreset(struct sysc *ddata) 228 { 229 u32 sysc_mask, syss_done, rstval; 230 int syss_offset, error = 0; 231 232 if (ddata->cap->regbits->srst_shift < 0) 233 return 0; 234 235 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 236 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 237 238 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 239 syss_done = 0; 240 else 241 syss_done = ddata->cfg.syss_mask; 242 243 if (syss_offset >= 0) { 244 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 245 rstval, (rstval & ddata->cfg.syss_mask) == 246 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 247 248 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 249 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 250 rstval, !(rstval & sysc_mask), 251 100, MAX_MODULE_SOFTRESET_WAIT); 252 } 253 254 return error; 255 } 256 257 static int sysc_add_named_clock_from_child(struct sysc *ddata, 258 const char *name, 259 const char *optfck_name) 260 { 261 struct device_node *np = ddata->dev->of_node; 262 struct device_node *child; 263 struct clk_lookup *cl; 264 struct clk *clock; 265 const char *n; 266 267 if (name) 268 n = name; 269 else 270 n = optfck_name; 271 272 /* Does the clock alias already exist? */ 273 clock = of_clk_get_by_name(np, n); 274 if (!IS_ERR(clock)) { 275 clk_put(clock); 276 277 return 0; 278 } 279 280 child = of_get_next_available_child(np, NULL); 281 if (!child) 282 return -ENODEV; 283 284 clock = devm_get_clk_from_child(ddata->dev, child, name); 285 if (IS_ERR(clock)) 286 return PTR_ERR(clock); 287 288 /* 289 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 290 * limit for clk_get(). If cl ever needs to be freed, it should be done 291 * with clkdev_drop(). 292 */ 293 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 294 if (!cl) 295 return -ENOMEM; 296 297 cl->con_id = n; 298 cl->dev_id = dev_name(ddata->dev); 299 cl->clk = clock; 300 clkdev_add(cl); 301 302 clk_put(clock); 303 304 return 0; 305 } 306 307 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 308 { 309 const char *optfck_name; 310 int error, index; 311 312 if (ddata->nr_clocks < SYSC_OPTFCK0) 313 index = SYSC_OPTFCK0; 314 else 315 index = ddata->nr_clocks; 316 317 if (name) 318 optfck_name = name; 319 else 320 optfck_name = clock_names[index]; 321 322 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 323 if (error) 324 return error; 325 326 ddata->clock_roles[index] = optfck_name; 327 ddata->nr_clocks++; 328 329 return 0; 330 } 331 332 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 333 { 334 int error, i, index = -ENODEV; 335 336 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 337 index = SYSC_FCK; 338 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 339 index = SYSC_ICK; 340 341 if (index < 0) { 342 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 343 if (!ddata->clocks[i]) { 344 index = i; 345 break; 346 } 347 } 348 } 349 350 if (index < 0) { 351 dev_err(ddata->dev, "clock %s not added\n", name); 352 return index; 353 } 354 355 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 356 if (IS_ERR(ddata->clocks[index])) { 357 dev_err(ddata->dev, "clock get error for %s: %li\n", 358 name, PTR_ERR(ddata->clocks[index])); 359 360 return PTR_ERR(ddata->clocks[index]); 361 } 362 363 error = clk_prepare(ddata->clocks[index]); 364 if (error) { 365 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 366 name, error); 367 368 return error; 369 } 370 371 return 0; 372 } 373 374 static int sysc_get_clocks(struct sysc *ddata) 375 { 376 struct device_node *np = ddata->dev->of_node; 377 struct property *prop; 378 const char *name; 379 int nr_fck = 0, nr_ick = 0, i, error = 0; 380 381 ddata->clock_roles = devm_kcalloc(ddata->dev, 382 SYSC_MAX_CLOCKS, 383 sizeof(*ddata->clock_roles), 384 GFP_KERNEL); 385 if (!ddata->clock_roles) 386 return -ENOMEM; 387 388 of_property_for_each_string(np, "clock-names", prop, name) { 389 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 390 nr_fck++; 391 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 392 nr_ick++; 393 ddata->clock_roles[ddata->nr_clocks] = name; 394 ddata->nr_clocks++; 395 } 396 397 if (ddata->nr_clocks < 1) 398 return 0; 399 400 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 401 error = sysc_init_ext_opt_clock(ddata, NULL); 402 if (error) 403 return error; 404 } 405 406 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 407 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 408 409 return -EINVAL; 410 } 411 412 if (nr_fck > 1 || nr_ick > 1) { 413 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 414 415 return -EINVAL; 416 } 417 418 /* Always add a slot for main clocks fck and ick even if unused */ 419 if (!nr_fck) 420 ddata->nr_clocks++; 421 if (!nr_ick) 422 ddata->nr_clocks++; 423 424 ddata->clocks = devm_kcalloc(ddata->dev, 425 ddata->nr_clocks, sizeof(*ddata->clocks), 426 GFP_KERNEL); 427 if (!ddata->clocks) 428 return -ENOMEM; 429 430 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 431 const char *name = ddata->clock_roles[i]; 432 433 if (!name) 434 continue; 435 436 error = sysc_get_one_clock(ddata, name); 437 if (error) 438 return error; 439 } 440 441 return 0; 442 } 443 444 static int sysc_enable_main_clocks(struct sysc *ddata) 445 { 446 struct clk *clock; 447 int i, error; 448 449 if (!ddata->clocks) 450 return 0; 451 452 for (i = 0; i < SYSC_OPTFCK0; i++) { 453 clock = ddata->clocks[i]; 454 455 /* Main clocks may not have ick */ 456 if (IS_ERR_OR_NULL(clock)) 457 continue; 458 459 error = clk_enable(clock); 460 if (error) 461 goto err_disable; 462 } 463 464 return 0; 465 466 err_disable: 467 for (i--; i >= 0; i--) { 468 clock = ddata->clocks[i]; 469 470 /* Main clocks may not have ick */ 471 if (IS_ERR_OR_NULL(clock)) 472 continue; 473 474 clk_disable(clock); 475 } 476 477 return error; 478 } 479 480 static void sysc_disable_main_clocks(struct sysc *ddata) 481 { 482 struct clk *clock; 483 int i; 484 485 if (!ddata->clocks) 486 return; 487 488 for (i = 0; i < SYSC_OPTFCK0; i++) { 489 clock = ddata->clocks[i]; 490 if (IS_ERR_OR_NULL(clock)) 491 continue; 492 493 clk_disable(clock); 494 } 495 } 496 497 static int sysc_enable_opt_clocks(struct sysc *ddata) 498 { 499 struct clk *clock; 500 int i, error; 501 502 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 503 return 0; 504 505 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 506 clock = ddata->clocks[i]; 507 508 /* Assume no holes for opt clocks */ 509 if (IS_ERR_OR_NULL(clock)) 510 return 0; 511 512 error = clk_enable(clock); 513 if (error) 514 goto err_disable; 515 } 516 517 return 0; 518 519 err_disable: 520 for (i--; i >= 0; i--) { 521 clock = ddata->clocks[i]; 522 if (IS_ERR_OR_NULL(clock)) 523 continue; 524 525 clk_disable(clock); 526 } 527 528 return error; 529 } 530 531 static void sysc_disable_opt_clocks(struct sysc *ddata) 532 { 533 struct clk *clock; 534 int i; 535 536 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 537 return; 538 539 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 540 clock = ddata->clocks[i]; 541 542 /* Assume no holes for opt clocks */ 543 if (IS_ERR_OR_NULL(clock)) 544 return; 545 546 clk_disable(clock); 547 } 548 } 549 550 static void sysc_clkdm_deny_idle(struct sysc *ddata) 551 { 552 struct ti_sysc_platform_data *pdata; 553 554 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 555 return; 556 557 pdata = dev_get_platdata(ddata->dev); 558 if (pdata && pdata->clkdm_deny_idle) 559 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 560 } 561 562 static void sysc_clkdm_allow_idle(struct sysc *ddata) 563 { 564 struct ti_sysc_platform_data *pdata; 565 566 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 567 return; 568 569 pdata = dev_get_platdata(ddata->dev); 570 if (pdata && pdata->clkdm_allow_idle) 571 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 572 } 573 574 /** 575 * sysc_init_resets - init rstctrl reset line if configured 576 * @ddata: device driver data 577 * 578 * See sysc_rstctrl_reset_deassert(). 579 */ 580 static int sysc_init_resets(struct sysc *ddata) 581 { 582 ddata->rsts = 583 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 584 585 return PTR_ERR_OR_ZERO(ddata->rsts); 586 } 587 588 /** 589 * sysc_parse_and_check_child_range - parses module IO region from ranges 590 * @ddata: device driver data 591 * 592 * In general we only need rev, syss, and sysc registers and not the whole 593 * module range. But we do want the offsets for these registers from the 594 * module base. This allows us to check them against the legacy hwmod 595 * platform data. Let's also check the ranges are configured properly. 596 */ 597 static int sysc_parse_and_check_child_range(struct sysc *ddata) 598 { 599 struct device_node *np = ddata->dev->of_node; 600 const __be32 *ranges; 601 u32 nr_addr, nr_size; 602 int len, error; 603 604 ranges = of_get_property(np, "ranges", &len); 605 if (!ranges) { 606 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 607 608 return -ENOENT; 609 } 610 611 len /= sizeof(*ranges); 612 613 if (len < 3) { 614 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 615 616 return -EINVAL; 617 } 618 619 error = of_property_read_u32(np, "#address-cells", &nr_addr); 620 if (error) 621 return -ENOENT; 622 623 error = of_property_read_u32(np, "#size-cells", &nr_size); 624 if (error) 625 return -ENOENT; 626 627 if (nr_addr != 1 || nr_size != 1) { 628 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 629 630 return -EINVAL; 631 } 632 633 ranges++; 634 ddata->module_pa = of_translate_address(np, ranges++); 635 ddata->module_size = be32_to_cpup(ranges); 636 637 return 0; 638 } 639 640 /* Interconnect instances to probe before l4_per instances */ 641 static struct resource early_bus_ranges[] = { 642 /* am3/4 l4_wkup */ 643 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, 644 /* omap4/5 and dra7 l4_cfg */ 645 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, 646 /* omap4 l4_wkup */ 647 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, 648 /* omap5 and dra7 l4_wkup without dra7 dcan segment */ 649 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, 650 }; 651 652 static atomic_t sysc_defer = ATOMIC_INIT(10); 653 654 /** 655 * sysc_defer_non_critical - defer non_critical interconnect probing 656 * @ddata: device driver data 657 * 658 * We want to probe l4_cfg and l4_wkup interconnect instances before any 659 * l4_per instances as l4_per instances depend on resources on l4_cfg and 660 * l4_wkup interconnects. 661 */ 662 static int sysc_defer_non_critical(struct sysc *ddata) 663 { 664 struct resource *res; 665 int i; 666 667 if (!atomic_read(&sysc_defer)) 668 return 0; 669 670 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { 671 res = &early_bus_ranges[i]; 672 if (ddata->module_pa >= res->start && 673 ddata->module_pa <= res->end) { 674 atomic_set(&sysc_defer, 0); 675 676 return 0; 677 } 678 } 679 680 atomic_dec_if_positive(&sysc_defer); 681 682 return -EPROBE_DEFER; 683 } 684 685 static struct device_node *stdout_path; 686 687 static void sysc_init_stdout_path(struct sysc *ddata) 688 { 689 struct device_node *np = NULL; 690 const char *uart; 691 692 if (IS_ERR(stdout_path)) 693 return; 694 695 if (stdout_path) 696 return; 697 698 np = of_find_node_by_path("/chosen"); 699 if (!np) 700 goto err; 701 702 uart = of_get_property(np, "stdout-path", NULL); 703 if (!uart) 704 goto err; 705 706 np = of_find_node_by_path(uart); 707 if (!np) 708 goto err; 709 710 stdout_path = np; 711 712 return; 713 714 err: 715 stdout_path = ERR_PTR(-ENODEV); 716 } 717 718 static void sysc_check_quirk_stdout(struct sysc *ddata, 719 struct device_node *np) 720 { 721 sysc_init_stdout_path(ddata); 722 if (np != stdout_path) 723 return; 724 725 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 726 SYSC_QUIRK_NO_RESET_ON_INIT; 727 } 728 729 /** 730 * sysc_check_one_child - check child configuration 731 * @ddata: device driver data 732 * @np: child device node 733 * 734 * Let's avoid messy situations where we have new interconnect target 735 * node but children have "ti,hwmods". These belong to the interconnect 736 * target node and are managed by this driver. 737 */ 738 static void sysc_check_one_child(struct sysc *ddata, 739 struct device_node *np) 740 { 741 const char *name; 742 743 name = of_get_property(np, "ti,hwmods", NULL); 744 if (name && !of_device_is_compatible(np, "ti,sysc")) 745 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 746 747 sysc_check_quirk_stdout(ddata, np); 748 sysc_parse_dts_quirks(ddata, np, true); 749 } 750 751 static void sysc_check_children(struct sysc *ddata) 752 { 753 struct device_node *child; 754 755 for_each_child_of_node(ddata->dev->of_node, child) 756 sysc_check_one_child(ddata, child); 757 } 758 759 /* 760 * So far only I2C uses 16-bit read access with clockactivity with revision 761 * in two registers with stride of 4. We can detect this based on the rev 762 * register size to configure things far enough to be able to properly read 763 * the revision register. 764 */ 765 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 766 { 767 if (resource_size(res) == 8) 768 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 769 } 770 771 /** 772 * sysc_parse_one - parses the interconnect target module registers 773 * @ddata: device driver data 774 * @reg: register to parse 775 */ 776 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 777 { 778 struct resource *res; 779 const char *name; 780 781 switch (reg) { 782 case SYSC_REVISION: 783 case SYSC_SYSCONFIG: 784 case SYSC_SYSSTATUS: 785 name = reg_names[reg]; 786 break; 787 default: 788 return -EINVAL; 789 } 790 791 res = platform_get_resource_byname(to_platform_device(ddata->dev), 792 IORESOURCE_MEM, name); 793 if (!res) { 794 ddata->offsets[reg] = -ENODEV; 795 796 return 0; 797 } 798 799 ddata->offsets[reg] = res->start - ddata->module_pa; 800 if (reg == SYSC_REVISION) 801 sysc_check_quirk_16bit(ddata, res); 802 803 return 0; 804 } 805 806 static int sysc_parse_registers(struct sysc *ddata) 807 { 808 int i, error; 809 810 for (i = 0; i < SYSC_MAX_REGS; i++) { 811 error = sysc_parse_one(ddata, i); 812 if (error) 813 return error; 814 } 815 816 return 0; 817 } 818 819 /** 820 * sysc_check_registers - check for misconfigured register overlaps 821 * @ddata: device driver data 822 */ 823 static int sysc_check_registers(struct sysc *ddata) 824 { 825 int i, j, nr_regs = 0, nr_matches = 0; 826 827 for (i = 0; i < SYSC_MAX_REGS; i++) { 828 if (ddata->offsets[i] < 0) 829 continue; 830 831 if (ddata->offsets[i] > (ddata->module_size - 4)) { 832 dev_err(ddata->dev, "register outside module range"); 833 834 return -EINVAL; 835 } 836 837 for (j = 0; j < SYSC_MAX_REGS; j++) { 838 if (ddata->offsets[j] < 0) 839 continue; 840 841 if (ddata->offsets[i] == ddata->offsets[j]) 842 nr_matches++; 843 } 844 nr_regs++; 845 } 846 847 if (nr_matches > nr_regs) { 848 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 849 nr_regs, nr_matches); 850 851 return -EINVAL; 852 } 853 854 return 0; 855 } 856 857 /** 858 * sysc_ioremap - ioremap register space for the interconnect target module 859 * @ddata: device driver data 860 * 861 * Note that the interconnect target module registers can be anywhere 862 * within the interconnect target module range. For example, SGX has 863 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 864 * has them at offset 0x1200 in the CPSW_WR child. Usually the 865 * the interconnect target module registers are at the beginning of 866 * the module range though. 867 */ 868 static int sysc_ioremap(struct sysc *ddata) 869 { 870 int size; 871 872 if (ddata->offsets[SYSC_REVISION] < 0 && 873 ddata->offsets[SYSC_SYSCONFIG] < 0 && 874 ddata->offsets[SYSC_SYSSTATUS] < 0) { 875 size = ddata->module_size; 876 } else { 877 size = max3(ddata->offsets[SYSC_REVISION], 878 ddata->offsets[SYSC_SYSCONFIG], 879 ddata->offsets[SYSC_SYSSTATUS]); 880 881 if (size < SZ_1K) 882 size = SZ_1K; 883 884 if ((size + sizeof(u32)) > ddata->module_size) 885 size = ddata->module_size; 886 } 887 888 ddata->module_va = devm_ioremap(ddata->dev, 889 ddata->module_pa, 890 size + sizeof(u32)); 891 if (!ddata->module_va) 892 return -EIO; 893 894 return 0; 895 } 896 897 /** 898 * sysc_map_and_check_registers - ioremap and check device registers 899 * @ddata: device driver data 900 */ 901 static int sysc_map_and_check_registers(struct sysc *ddata) 902 { 903 struct device_node *np = ddata->dev->of_node; 904 int error; 905 906 error = sysc_parse_and_check_child_range(ddata); 907 if (error) 908 return error; 909 910 error = sysc_defer_non_critical(ddata); 911 if (error) 912 return error; 913 914 sysc_check_children(ddata); 915 916 if (!of_get_property(np, "reg", NULL)) 917 return 0; 918 919 error = sysc_parse_registers(ddata); 920 if (error) 921 return error; 922 923 error = sysc_ioremap(ddata); 924 if (error) 925 return error; 926 927 error = sysc_check_registers(ddata); 928 if (error) 929 return error; 930 931 return 0; 932 } 933 934 /** 935 * sysc_show_rev - read and show interconnect target module revision 936 * @bufp: buffer to print the information to 937 * @ddata: device driver data 938 */ 939 static int sysc_show_rev(char *bufp, struct sysc *ddata) 940 { 941 int len; 942 943 if (ddata->offsets[SYSC_REVISION] < 0) 944 return sprintf(bufp, ":NA"); 945 946 len = sprintf(bufp, ":%08x", ddata->revision); 947 948 return len; 949 } 950 951 static int sysc_show_reg(struct sysc *ddata, 952 char *bufp, enum sysc_registers reg) 953 { 954 if (ddata->offsets[reg] < 0) 955 return sprintf(bufp, ":NA"); 956 957 return sprintf(bufp, ":%x", ddata->offsets[reg]); 958 } 959 960 static int sysc_show_name(char *bufp, struct sysc *ddata) 961 { 962 if (!ddata->name) 963 return 0; 964 965 return sprintf(bufp, ":%s", ddata->name); 966 } 967 968 /** 969 * sysc_show_registers - show information about interconnect target module 970 * @ddata: device driver data 971 */ 972 static void sysc_show_registers(struct sysc *ddata) 973 { 974 char buf[128]; 975 char *bufp = buf; 976 int i; 977 978 for (i = 0; i < SYSC_MAX_REGS; i++) 979 bufp += sysc_show_reg(ddata, bufp, i); 980 981 bufp += sysc_show_rev(bufp, ddata); 982 bufp += sysc_show_name(bufp, ddata); 983 984 dev_dbg(ddata->dev, "%llx:%x%s\n", 985 ddata->module_pa, ddata->module_size, 986 buf); 987 } 988 989 /** 990 * sysc_write_sysconfig - handle sysconfig quirks for register write 991 * @ddata: device driver data 992 * @value: register value 993 */ 994 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 995 { 996 if (ddata->module_unlock_quirk) 997 ddata->module_unlock_quirk(ddata); 998 999 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 1000 1001 if (ddata->module_lock_quirk) 1002 ddata->module_lock_quirk(ddata); 1003 } 1004 1005 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 1006 #define SYSC_CLOCACT_ICK 2 1007 1008 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1009 static int sysc_enable_module(struct device *dev) 1010 { 1011 struct sysc *ddata; 1012 const struct sysc_regbits *regbits; 1013 u32 reg, idlemodes, best_mode; 1014 int error; 1015 1016 ddata = dev_get_drvdata(dev); 1017 1018 /* 1019 * Some modules like DSS reset automatically on idle. Enable optional 1020 * reset clocks and wait for OCP softreset to complete. 1021 */ 1022 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1023 error = sysc_enable_opt_clocks(ddata); 1024 if (error) { 1025 dev_err(ddata->dev, 1026 "Optional clocks failed for enable: %i\n", 1027 error); 1028 return error; 1029 } 1030 } 1031 /* 1032 * Some modules like i2c and hdq1w have unusable reset status unless 1033 * the module reset quirk is enabled. Skip status check on enable. 1034 */ 1035 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1036 error = sysc_wait_softreset(ddata); 1037 if (error) 1038 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1039 } 1040 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1041 sysc_disable_opt_clocks(ddata); 1042 1043 /* 1044 * Some subsystem private interconnects, like DSS top level module, 1045 * need only the automatic OCP softreset handling with no sysconfig 1046 * register bits to configure. 1047 */ 1048 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1049 return 0; 1050 1051 regbits = ddata->cap->regbits; 1052 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1053 1054 /* 1055 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1056 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1057 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1058 */ 1059 if (regbits->clkact_shift >= 0 && 1060 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1061 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1062 1063 /* Set SIDLE mode */ 1064 idlemodes = ddata->cfg.sidlemodes; 1065 if (!idlemodes || regbits->sidle_shift < 0) 1066 goto set_midle; 1067 1068 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1069 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1070 best_mode = SYSC_IDLE_NO; 1071 } else { 1072 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1073 if (best_mode > SYSC_IDLE_MASK) { 1074 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1075 return -EINVAL; 1076 } 1077 1078 /* Set WAKEUP */ 1079 if (regbits->enwkup_shift >= 0 && 1080 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1081 reg |= BIT(regbits->enwkup_shift); 1082 } 1083 1084 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1085 reg |= best_mode << regbits->sidle_shift; 1086 sysc_write_sysconfig(ddata, reg); 1087 1088 set_midle: 1089 /* Set MIDLE mode */ 1090 idlemodes = ddata->cfg.midlemodes; 1091 if (!idlemodes || regbits->midle_shift < 0) 1092 goto set_autoidle; 1093 1094 best_mode = fls(ddata->cfg.midlemodes) - 1; 1095 if (best_mode > SYSC_IDLE_MASK) { 1096 dev_err(dev, "%s: invalid midlemode\n", __func__); 1097 return -EINVAL; 1098 } 1099 1100 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1101 best_mode = SYSC_IDLE_NO; 1102 1103 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1104 reg |= best_mode << regbits->midle_shift; 1105 sysc_write_sysconfig(ddata, reg); 1106 1107 set_autoidle: 1108 /* Autoidle bit must enabled separately if available */ 1109 if (regbits->autoidle_shift >= 0 && 1110 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1111 reg |= 1 << regbits->autoidle_shift; 1112 sysc_write_sysconfig(ddata, reg); 1113 } 1114 1115 /* Flush posted write */ 1116 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1117 1118 if (ddata->module_enable_quirk) 1119 ddata->module_enable_quirk(ddata); 1120 1121 return 0; 1122 } 1123 1124 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1125 { 1126 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1127 *best_mode = SYSC_IDLE_SMART_WKUP; 1128 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1129 *best_mode = SYSC_IDLE_SMART; 1130 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1131 *best_mode = SYSC_IDLE_FORCE; 1132 else 1133 return -EINVAL; 1134 1135 return 0; 1136 } 1137 1138 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1139 static int sysc_disable_module(struct device *dev) 1140 { 1141 struct sysc *ddata; 1142 const struct sysc_regbits *regbits; 1143 u32 reg, idlemodes, best_mode; 1144 int ret; 1145 1146 ddata = dev_get_drvdata(dev); 1147 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1148 return 0; 1149 1150 if (ddata->module_disable_quirk) 1151 ddata->module_disable_quirk(ddata); 1152 1153 regbits = ddata->cap->regbits; 1154 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1155 1156 /* Set MIDLE mode */ 1157 idlemodes = ddata->cfg.midlemodes; 1158 if (!idlemodes || regbits->midle_shift < 0) 1159 goto set_sidle; 1160 1161 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1162 if (ret) { 1163 dev_err(dev, "%s: invalid midlemode\n", __func__); 1164 return ret; 1165 } 1166 1167 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1168 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1169 best_mode = SYSC_IDLE_FORCE; 1170 1171 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1172 reg |= best_mode << regbits->midle_shift; 1173 sysc_write_sysconfig(ddata, reg); 1174 1175 set_sidle: 1176 /* Set SIDLE mode */ 1177 idlemodes = ddata->cfg.sidlemodes; 1178 if (!idlemodes || regbits->sidle_shift < 0) 1179 return 0; 1180 1181 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1182 best_mode = SYSC_IDLE_FORCE; 1183 } else { 1184 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1185 if (ret) { 1186 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1187 return ret; 1188 } 1189 } 1190 1191 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1192 reg |= best_mode << regbits->sidle_shift; 1193 if (regbits->autoidle_shift >= 0 && 1194 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1195 reg |= 1 << regbits->autoidle_shift; 1196 sysc_write_sysconfig(ddata, reg); 1197 1198 /* Flush posted write */ 1199 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1200 1201 return 0; 1202 } 1203 1204 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1205 struct sysc *ddata) 1206 { 1207 struct ti_sysc_platform_data *pdata; 1208 int error; 1209 1210 pdata = dev_get_platdata(ddata->dev); 1211 if (!pdata) 1212 return 0; 1213 1214 if (!pdata->idle_module) 1215 return -ENODEV; 1216 1217 error = pdata->idle_module(dev, &ddata->cookie); 1218 if (error) 1219 dev_err(dev, "%s: could not idle: %i\n", 1220 __func__, error); 1221 1222 reset_control_assert(ddata->rsts); 1223 1224 return 0; 1225 } 1226 1227 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1228 struct sysc *ddata) 1229 { 1230 struct ti_sysc_platform_data *pdata; 1231 int error; 1232 1233 pdata = dev_get_platdata(ddata->dev); 1234 if (!pdata) 1235 return 0; 1236 1237 if (!pdata->enable_module) 1238 return -ENODEV; 1239 1240 error = pdata->enable_module(dev, &ddata->cookie); 1241 if (error) 1242 dev_err(dev, "%s: could not enable: %i\n", 1243 __func__, error); 1244 1245 reset_control_deassert(ddata->rsts); 1246 1247 return 0; 1248 } 1249 1250 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1251 { 1252 struct sysc *ddata; 1253 int error = 0; 1254 1255 ddata = dev_get_drvdata(dev); 1256 1257 if (!ddata->enabled) 1258 return 0; 1259 1260 sysc_clkdm_deny_idle(ddata); 1261 1262 if (ddata->legacy_mode) { 1263 error = sysc_runtime_suspend_legacy(dev, ddata); 1264 if (error) 1265 goto err_allow_idle; 1266 } else { 1267 error = sysc_disable_module(dev); 1268 if (error) 1269 goto err_allow_idle; 1270 } 1271 1272 sysc_disable_main_clocks(ddata); 1273 1274 if (sysc_opt_clks_needed(ddata)) 1275 sysc_disable_opt_clocks(ddata); 1276 1277 ddata->enabled = false; 1278 1279 err_allow_idle: 1280 sysc_clkdm_allow_idle(ddata); 1281 1282 reset_control_assert(ddata->rsts); 1283 1284 return error; 1285 } 1286 1287 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1288 { 1289 struct sysc *ddata; 1290 int error = 0; 1291 1292 ddata = dev_get_drvdata(dev); 1293 1294 if (ddata->enabled) 1295 return 0; 1296 1297 1298 sysc_clkdm_deny_idle(ddata); 1299 1300 if (sysc_opt_clks_needed(ddata)) { 1301 error = sysc_enable_opt_clocks(ddata); 1302 if (error) 1303 goto err_allow_idle; 1304 } 1305 1306 error = sysc_enable_main_clocks(ddata); 1307 if (error) 1308 goto err_opt_clocks; 1309 1310 reset_control_deassert(ddata->rsts); 1311 1312 if (ddata->legacy_mode) { 1313 error = sysc_runtime_resume_legacy(dev, ddata); 1314 if (error) 1315 goto err_main_clocks; 1316 } else { 1317 error = sysc_enable_module(dev); 1318 if (error) 1319 goto err_main_clocks; 1320 } 1321 1322 ddata->enabled = true; 1323 1324 sysc_clkdm_allow_idle(ddata); 1325 1326 return 0; 1327 1328 err_main_clocks: 1329 sysc_disable_main_clocks(ddata); 1330 err_opt_clocks: 1331 if (sysc_opt_clks_needed(ddata)) 1332 sysc_disable_opt_clocks(ddata); 1333 err_allow_idle: 1334 sysc_clkdm_allow_idle(ddata); 1335 1336 return error; 1337 } 1338 1339 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1340 { 1341 struct device *dev = ddata->dev; 1342 int error; 1343 1344 /* Disable target module if it is enabled */ 1345 if (ddata->enabled) { 1346 error = sysc_runtime_suspend(dev); 1347 if (error) 1348 dev_warn(dev, "reinit suspend failed: %i\n", error); 1349 } 1350 1351 /* Enable target module */ 1352 error = sysc_runtime_resume(dev); 1353 if (error) 1354 dev_warn(dev, "reinit resume failed: %i\n", error); 1355 1356 if (leave_enabled) 1357 return error; 1358 1359 /* Disable target module if no leave_enabled was set */ 1360 error = sysc_runtime_suspend(dev); 1361 if (error) 1362 dev_warn(dev, "reinit suspend failed: %i\n", error); 1363 1364 return error; 1365 } 1366 1367 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1368 { 1369 struct sysc *ddata; 1370 1371 ddata = dev_get_drvdata(dev); 1372 1373 if (ddata->cfg.quirks & 1374 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1375 return 0; 1376 1377 if (!ddata->enabled) 1378 return 0; 1379 1380 ddata->needs_resume = 1; 1381 1382 return sysc_runtime_suspend(dev); 1383 } 1384 1385 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1386 { 1387 struct sysc *ddata; 1388 int error = 0; 1389 1390 ddata = dev_get_drvdata(dev); 1391 1392 if (ddata->cfg.quirks & 1393 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1394 return 0; 1395 1396 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1397 error = sysc_reinit_module(ddata, ddata->needs_resume); 1398 if (error) 1399 dev_warn(dev, "noirq_resume failed: %i\n", error); 1400 } else if (ddata->needs_resume) { 1401 error = sysc_runtime_resume(dev); 1402 if (error) 1403 dev_warn(dev, "noirq_resume failed: %i\n", error); 1404 } 1405 1406 ddata->needs_resume = 0; 1407 1408 return error; 1409 } 1410 1411 static const struct dev_pm_ops sysc_pm_ops = { 1412 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1413 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1414 sysc_runtime_resume, 1415 NULL) 1416 }; 1417 1418 /* Module revision register based quirks */ 1419 struct sysc_revision_quirk { 1420 const char *name; 1421 u32 base; 1422 int rev_offset; 1423 int sysc_offset; 1424 int syss_offset; 1425 u32 revision; 1426 u32 revision_mask; 1427 u32 quirks; 1428 }; 1429 1430 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1431 optrev_val, optrevmask, optquirkmask) \ 1432 { \ 1433 .name = (optname), \ 1434 .base = (optbase), \ 1435 .rev_offset = (optrev), \ 1436 .sysc_offset = (optsysc), \ 1437 .syss_offset = (optsyss), \ 1438 .revision = (optrev_val), \ 1439 .revision_mask = (optrevmask), \ 1440 .quirks = (optquirkmask), \ 1441 } 1442 1443 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1444 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1445 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1446 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1447 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1448 SYSC_QUIRK_LEGACY_IDLE), 1449 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1450 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1451 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1452 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1453 /* Uarts on omap4 and later */ 1454 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1455 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1456 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1457 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1458 1459 /* Quirks that need to be set based on the module address */ 1460 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1461 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1462 SYSC_QUIRK_SWSUP_SIDLE), 1463 1464 /* Quirks that need to be set based on detected module */ 1465 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1466 SYSC_MODULE_QUIRK_AESS), 1467 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1468 SYSC_QUIRK_CLKDM_NOAUTO), 1469 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1470 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1471 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1472 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1473 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1474 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1475 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1476 SYSC_QUIRK_CLKDM_NOAUTO), 1477 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1478 SYSC_QUIRK_CLKDM_NOAUTO), 1479 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1480 SYSC_QUIRK_GPMC_DEBUG), 1481 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1482 SYSC_QUIRK_OPT_CLKS_NEEDED), 1483 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1484 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1485 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1486 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1487 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1488 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1489 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1490 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1491 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1492 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1493 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1494 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1495 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1496 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1497 SYSC_MODULE_QUIRK_SGX), 1498 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1499 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1500 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 1501 SYSC_QUIRK_SWSUP_SIDLE), 1502 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1503 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1504 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1505 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1506 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1507 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1508 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1509 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1510 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1511 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1512 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1513 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1514 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1515 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1516 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1517 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1518 SYSC_QUIRK_REINIT_ON_RESUME), 1519 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1520 SYSC_MODULE_QUIRK_WDT), 1521 /* PRUSS on am3, am4 and am5 */ 1522 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1523 SYSC_MODULE_QUIRK_PRUSS), 1524 /* Watchdog on am3 and am4 */ 1525 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1526 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1527 1528 #ifdef DEBUG 1529 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1530 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1531 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1532 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1533 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1534 0xffff00f0, 0), 1535 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1536 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1537 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1538 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1539 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1540 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1541 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1542 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1543 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1544 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1545 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1546 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1547 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1548 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1549 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1550 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1551 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1552 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1553 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1554 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1555 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1556 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1557 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1558 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1559 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1560 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1561 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1562 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1563 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1564 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1565 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1566 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1567 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1568 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1569 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1570 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1571 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1572 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1573 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1574 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1575 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1576 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1577 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1578 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1579 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1580 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1581 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1582 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1583 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1584 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1585 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), 1586 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), 1587 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1588 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1589 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1590 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1591 /* Some timers on omap4 and later */ 1592 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1593 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1594 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1595 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1596 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1597 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1598 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1599 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1600 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1601 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1602 #endif 1603 }; 1604 1605 /* 1606 * Early quirks based on module base and register offsets only that are 1607 * needed before the module revision can be read 1608 */ 1609 static void sysc_init_early_quirks(struct sysc *ddata) 1610 { 1611 const struct sysc_revision_quirk *q; 1612 int i; 1613 1614 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1615 q = &sysc_revision_quirks[i]; 1616 1617 if (!q->base) 1618 continue; 1619 1620 if (q->base != ddata->module_pa) 1621 continue; 1622 1623 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1624 continue; 1625 1626 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1627 continue; 1628 1629 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1630 continue; 1631 1632 ddata->name = q->name; 1633 ddata->cfg.quirks |= q->quirks; 1634 } 1635 } 1636 1637 /* Quirks that also consider the revision register value */ 1638 static void sysc_init_revision_quirks(struct sysc *ddata) 1639 { 1640 const struct sysc_revision_quirk *q; 1641 int i; 1642 1643 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1644 q = &sysc_revision_quirks[i]; 1645 1646 if (q->base && q->base != ddata->module_pa) 1647 continue; 1648 1649 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1650 continue; 1651 1652 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1653 continue; 1654 1655 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1656 continue; 1657 1658 if (q->revision == ddata->revision || 1659 (q->revision & q->revision_mask) == 1660 (ddata->revision & q->revision_mask)) { 1661 ddata->name = q->name; 1662 ddata->cfg.quirks |= q->quirks; 1663 } 1664 } 1665 } 1666 1667 /* 1668 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1669 * enabled DSS interrupts. Eventually we may be able to do this on 1670 * dispc init rather than top-level DSS init. 1671 */ 1672 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1673 bool disable) 1674 { 1675 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1676 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1677 int manager_count; 1678 bool framedonetv_irq = true; 1679 u32 val, irq_mask = 0; 1680 1681 switch (sysc_soc->soc) { 1682 case SOC_2420 ... SOC_3630: 1683 manager_count = 2; 1684 framedonetv_irq = false; 1685 break; 1686 case SOC_4430 ... SOC_4470: 1687 manager_count = 3; 1688 break; 1689 case SOC_5430: 1690 case SOC_DRA7: 1691 manager_count = 4; 1692 break; 1693 case SOC_AM4: 1694 manager_count = 1; 1695 framedonetv_irq = false; 1696 break; 1697 case SOC_UNKNOWN: 1698 default: 1699 return 0; 1700 } 1701 1702 /* Remap the whole module range to be able to reset dispc outputs */ 1703 devm_iounmap(ddata->dev, ddata->module_va); 1704 ddata->module_va = devm_ioremap(ddata->dev, 1705 ddata->module_pa, 1706 ddata->module_size); 1707 if (!ddata->module_va) 1708 return -EIO; 1709 1710 /* DISP_CONTROL */ 1711 val = sysc_read(ddata, dispc_offset + 0x40); 1712 lcd_en = val & lcd_en_mask; 1713 digit_en = val & digit_en_mask; 1714 if (lcd_en) 1715 irq_mask |= BIT(0); /* FRAMEDONE */ 1716 if (digit_en) { 1717 if (framedonetv_irq) 1718 irq_mask |= BIT(24); /* FRAMEDONETV */ 1719 else 1720 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1721 } 1722 if (disable & (lcd_en | digit_en)) 1723 sysc_write(ddata, dispc_offset + 0x40, 1724 val & ~(lcd_en_mask | digit_en_mask)); 1725 1726 if (manager_count <= 2) 1727 return irq_mask; 1728 1729 /* DISPC_CONTROL2 */ 1730 val = sysc_read(ddata, dispc_offset + 0x238); 1731 lcd2_en = val & lcd_en_mask; 1732 if (lcd2_en) 1733 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1734 if (disable && lcd2_en) 1735 sysc_write(ddata, dispc_offset + 0x238, 1736 val & ~lcd_en_mask); 1737 1738 if (manager_count <= 3) 1739 return irq_mask; 1740 1741 /* DISPC_CONTROL3 */ 1742 val = sysc_read(ddata, dispc_offset + 0x848); 1743 lcd3_en = val & lcd_en_mask; 1744 if (lcd3_en) 1745 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1746 if (disable && lcd3_en) 1747 sysc_write(ddata, dispc_offset + 0x848, 1748 val & ~lcd_en_mask); 1749 1750 return irq_mask; 1751 } 1752 1753 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1754 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1755 { 1756 const int dispc_offset = 0x1000; 1757 int error; 1758 u32 irq_mask, val; 1759 1760 /* Get enabled outputs */ 1761 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1762 if (!irq_mask) 1763 return; 1764 1765 /* Clear IRQSTATUS */ 1766 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1767 1768 /* Disable outputs */ 1769 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1770 1771 /* Poll IRQSTATUS */ 1772 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1773 val, val != irq_mask, 100, 50); 1774 if (error) 1775 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1776 __func__, val, irq_mask); 1777 1778 if (sysc_soc->soc == SOC_3430) { 1779 /* Clear DSS_SDI_CONTROL */ 1780 sysc_write(ddata, 0x44, 0); 1781 1782 /* Clear DSS_PLL_CONTROL */ 1783 sysc_write(ddata, 0x48, 0); 1784 } 1785 1786 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1787 sysc_write(ddata, 0x40, 0); 1788 } 1789 1790 /* 1-wire needs module's internal clocks enabled for reset */ 1791 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1792 { 1793 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1794 u16 val; 1795 1796 val = sysc_read(ddata, offset); 1797 val |= BIT(5); 1798 sysc_write(ddata, offset, val); 1799 } 1800 1801 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1802 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1803 { 1804 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1805 1806 sysc_write(ddata, offset, 1); 1807 } 1808 1809 /* I2C needs to be disabled for reset */ 1810 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1811 { 1812 int offset; 1813 u16 val; 1814 1815 /* I2C_CON, omap2/3 is different from omap4 and later */ 1816 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1817 offset = 0x24; 1818 else 1819 offset = 0xa4; 1820 1821 /* I2C_EN */ 1822 val = sysc_read(ddata, offset); 1823 if (enable) 1824 val |= BIT(15); 1825 else 1826 val &= ~BIT(15); 1827 sysc_write(ddata, offset, val); 1828 } 1829 1830 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1831 { 1832 sysc_clk_quirk_i2c(ddata, false); 1833 } 1834 1835 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1836 { 1837 sysc_clk_quirk_i2c(ddata, true); 1838 } 1839 1840 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1841 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1842 { 1843 u32 val, kick0_val = 0, kick1_val = 0; 1844 unsigned long flags; 1845 int error; 1846 1847 if (!lock) { 1848 kick0_val = 0x83e70b13; 1849 kick1_val = 0x95a4f1e0; 1850 } 1851 1852 local_irq_save(flags); 1853 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1854 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1855 !(val & BIT(0)), 100, 50); 1856 if (error) 1857 dev_warn(ddata->dev, "rtc busy timeout\n"); 1858 /* Now we have ~15 microseconds to read/write various registers */ 1859 sysc_write(ddata, 0x6c, kick0_val); 1860 sysc_write(ddata, 0x70, kick1_val); 1861 local_irq_restore(flags); 1862 } 1863 1864 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1865 { 1866 sysc_quirk_rtc(ddata, false); 1867 } 1868 1869 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1870 { 1871 sysc_quirk_rtc(ddata, true); 1872 } 1873 1874 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1875 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1876 { 1877 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1878 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1879 1880 sysc_write(ddata, offset, val); 1881 } 1882 1883 /* Watchdog timer needs a disable sequence after reset */ 1884 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1885 { 1886 int wps, spr, error; 1887 u32 val; 1888 1889 wps = 0x34; 1890 spr = 0x48; 1891 1892 sysc_write(ddata, spr, 0xaaaa); 1893 error = readl_poll_timeout(ddata->module_va + wps, val, 1894 !(val & 0x10), 100, 1895 MAX_MODULE_SOFTRESET_WAIT); 1896 if (error) 1897 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1898 1899 sysc_write(ddata, spr, 0x5555); 1900 error = readl_poll_timeout(ddata->module_va + wps, val, 1901 !(val & 0x10), 100, 1902 MAX_MODULE_SOFTRESET_WAIT); 1903 if (error) 1904 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1905 } 1906 1907 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1908 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1909 { 1910 u32 reg; 1911 1912 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1913 reg |= SYSC_PRUSS_STANDBY_INIT; 1914 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1915 } 1916 1917 static void sysc_init_module_quirks(struct sysc *ddata) 1918 { 1919 if (ddata->legacy_mode || !ddata->name) 1920 return; 1921 1922 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1923 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 1924 1925 return; 1926 } 1927 1928 #ifdef CONFIG_OMAP_GPMC_DEBUG 1929 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 1930 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 1931 1932 return; 1933 } 1934 #endif 1935 1936 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1937 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 1938 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 1939 1940 return; 1941 } 1942 1943 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 1944 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 1945 1946 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 1947 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 1948 1949 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 1950 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 1951 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 1952 1953 return; 1954 } 1955 1956 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 1957 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 1958 1959 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 1960 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1961 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 1962 } 1963 1964 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 1965 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 1966 } 1967 1968 static int sysc_clockdomain_init(struct sysc *ddata) 1969 { 1970 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1971 struct clk *fck = NULL, *ick = NULL; 1972 int error; 1973 1974 if (!pdata || !pdata->init_clockdomain) 1975 return 0; 1976 1977 switch (ddata->nr_clocks) { 1978 case 2: 1979 ick = ddata->clocks[SYSC_ICK]; 1980 fallthrough; 1981 case 1: 1982 fck = ddata->clocks[SYSC_FCK]; 1983 break; 1984 case 0: 1985 return 0; 1986 } 1987 1988 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1989 if (!error || error == -ENODEV) 1990 return 0; 1991 1992 return error; 1993 } 1994 1995 /* 1996 * Note that pdata->init_module() typically does a reset first. After 1997 * pdata->init_module() is done, PM runtime can be used for the interconnect 1998 * target module. 1999 */ 2000 static int sysc_legacy_init(struct sysc *ddata) 2001 { 2002 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2003 int error; 2004 2005 if (!pdata || !pdata->init_module) 2006 return 0; 2007 2008 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2009 if (error == -EEXIST) 2010 error = 0; 2011 2012 return error; 2013 } 2014 2015 /* 2016 * Note that the caller must ensure the interconnect target module is enabled 2017 * before calling reset. Otherwise reset will not complete. 2018 */ 2019 static int sysc_reset(struct sysc *ddata) 2020 { 2021 int sysc_offset, sysc_val, error; 2022 u32 sysc_mask; 2023 2024 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2025 2026 if (ddata->legacy_mode || 2027 ddata->cap->regbits->srst_shift < 0 || 2028 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 2029 return 0; 2030 2031 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2032 2033 if (ddata->pre_reset_quirk) 2034 ddata->pre_reset_quirk(ddata); 2035 2036 if (sysc_offset >= 0) { 2037 sysc_val = sysc_read_sysconfig(ddata); 2038 sysc_val |= sysc_mask; 2039 sysc_write(ddata, sysc_offset, sysc_val); 2040 } 2041 2042 if (ddata->cfg.srst_udelay) 2043 usleep_range(ddata->cfg.srst_udelay, 2044 ddata->cfg.srst_udelay * 2); 2045 2046 if (ddata->post_reset_quirk) 2047 ddata->post_reset_quirk(ddata); 2048 2049 error = sysc_wait_softreset(ddata); 2050 if (error) 2051 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2052 2053 if (ddata->reset_done_quirk) 2054 ddata->reset_done_quirk(ddata); 2055 2056 return error; 2057 } 2058 2059 /* 2060 * At this point the module is configured enough to read the revision but 2061 * module may not be completely configured yet to use PM runtime. Enable 2062 * all clocks directly during init to configure the quirks needed for PM 2063 * runtime based on the revision register. 2064 */ 2065 static int sysc_init_module(struct sysc *ddata) 2066 { 2067 bool rstctrl_deasserted = false; 2068 int error = 0; 2069 2070 error = sysc_clockdomain_init(ddata); 2071 if (error) 2072 return error; 2073 2074 sysc_clkdm_deny_idle(ddata); 2075 2076 /* 2077 * Always enable clocks. The bootloader may or may not have enabled 2078 * the related clocks. 2079 */ 2080 error = sysc_enable_opt_clocks(ddata); 2081 if (error) 2082 return error; 2083 2084 error = sysc_enable_main_clocks(ddata); 2085 if (error) 2086 goto err_opt_clocks; 2087 2088 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2089 error = reset_control_deassert(ddata->rsts); 2090 if (error) 2091 goto err_main_clocks; 2092 rstctrl_deasserted = true; 2093 } 2094 2095 ddata->revision = sysc_read_revision(ddata); 2096 sysc_init_revision_quirks(ddata); 2097 sysc_init_module_quirks(ddata); 2098 2099 if (ddata->legacy_mode) { 2100 error = sysc_legacy_init(ddata); 2101 if (error) 2102 goto err_main_clocks; 2103 } 2104 2105 if (!ddata->legacy_mode) { 2106 error = sysc_enable_module(ddata->dev); 2107 if (error) 2108 goto err_main_clocks; 2109 } 2110 2111 error = sysc_reset(ddata); 2112 if (error) 2113 dev_err(ddata->dev, "Reset failed with %d\n", error); 2114 2115 if (error && !ddata->legacy_mode) 2116 sysc_disable_module(ddata->dev); 2117 2118 err_main_clocks: 2119 if (error) 2120 sysc_disable_main_clocks(ddata); 2121 err_opt_clocks: 2122 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2123 if (error) { 2124 sysc_disable_opt_clocks(ddata); 2125 sysc_clkdm_allow_idle(ddata); 2126 } 2127 2128 if (error && rstctrl_deasserted && 2129 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2130 reset_control_assert(ddata->rsts); 2131 2132 return error; 2133 } 2134 2135 static int sysc_init_sysc_mask(struct sysc *ddata) 2136 { 2137 struct device_node *np = ddata->dev->of_node; 2138 int error; 2139 u32 val; 2140 2141 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2142 if (error) 2143 return 0; 2144 2145 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2146 2147 return 0; 2148 } 2149 2150 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2151 const char *name) 2152 { 2153 struct device_node *np = ddata->dev->of_node; 2154 struct property *prop; 2155 const __be32 *p; 2156 u32 val; 2157 2158 of_property_for_each_u32(np, name, prop, p, val) { 2159 if (val >= SYSC_NR_IDLEMODES) { 2160 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2161 return -EINVAL; 2162 } 2163 *idlemodes |= (1 << val); 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int sysc_init_idlemodes(struct sysc *ddata) 2170 { 2171 int error; 2172 2173 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2174 "ti,sysc-midle"); 2175 if (error) 2176 return error; 2177 2178 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2179 "ti,sysc-sidle"); 2180 if (error) 2181 return error; 2182 2183 return 0; 2184 } 2185 2186 /* 2187 * Only some devices on omap4 and later have SYSCONFIG reset done 2188 * bit. We can detect this if there is no SYSSTATUS at all, or the 2189 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2190 * have multiple bits for the child devices like OHCI and EHCI. 2191 * Depends on SYSC being parsed first. 2192 */ 2193 static int sysc_init_syss_mask(struct sysc *ddata) 2194 { 2195 struct device_node *np = ddata->dev->of_node; 2196 int error; 2197 u32 val; 2198 2199 error = of_property_read_u32(np, "ti,syss-mask", &val); 2200 if (error) { 2201 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2202 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2203 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2204 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2205 2206 return 0; 2207 } 2208 2209 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2210 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2211 2212 ddata->cfg.syss_mask = val; 2213 2214 return 0; 2215 } 2216 2217 /* 2218 * Many child device drivers need to have fck and opt clocks available 2219 * to get the clock rate for device internal configuration etc. 2220 */ 2221 static int sysc_child_add_named_clock(struct sysc *ddata, 2222 struct device *child, 2223 const char *name) 2224 { 2225 struct clk *clk; 2226 struct clk_lookup *l; 2227 int error = 0; 2228 2229 if (!name) 2230 return 0; 2231 2232 clk = clk_get(child, name); 2233 if (!IS_ERR(clk)) { 2234 error = -EEXIST; 2235 goto put_clk; 2236 } 2237 2238 clk = clk_get(ddata->dev, name); 2239 if (IS_ERR(clk)) 2240 return -ENODEV; 2241 2242 l = clkdev_create(clk, name, dev_name(child)); 2243 if (!l) 2244 error = -ENOMEM; 2245 put_clk: 2246 clk_put(clk); 2247 2248 return error; 2249 } 2250 2251 static int sysc_child_add_clocks(struct sysc *ddata, 2252 struct device *child) 2253 { 2254 int i, error; 2255 2256 for (i = 0; i < ddata->nr_clocks; i++) { 2257 error = sysc_child_add_named_clock(ddata, 2258 child, 2259 ddata->clock_roles[i]); 2260 if (error && error != -EEXIST) { 2261 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2262 ddata->clock_roles[i], error); 2263 2264 return error; 2265 } 2266 } 2267 2268 return 0; 2269 } 2270 2271 static struct device_type sysc_device_type = { 2272 }; 2273 2274 static struct sysc *sysc_child_to_parent(struct device *dev) 2275 { 2276 struct device *parent = dev->parent; 2277 2278 if (!parent || parent->type != &sysc_device_type) 2279 return NULL; 2280 2281 return dev_get_drvdata(parent); 2282 } 2283 2284 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2285 { 2286 struct sysc *ddata; 2287 int error; 2288 2289 ddata = sysc_child_to_parent(dev); 2290 2291 error = pm_generic_runtime_suspend(dev); 2292 if (error) 2293 return error; 2294 2295 if (!ddata->enabled) 2296 return 0; 2297 2298 return sysc_runtime_suspend(ddata->dev); 2299 } 2300 2301 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2302 { 2303 struct sysc *ddata; 2304 int error; 2305 2306 ddata = sysc_child_to_parent(dev); 2307 2308 if (!ddata->enabled) { 2309 error = sysc_runtime_resume(ddata->dev); 2310 if (error < 0) 2311 dev_err(ddata->dev, 2312 "%s error: %i\n", __func__, error); 2313 } 2314 2315 return pm_generic_runtime_resume(dev); 2316 } 2317 2318 #ifdef CONFIG_PM_SLEEP 2319 static int sysc_child_suspend_noirq(struct device *dev) 2320 { 2321 struct sysc *ddata; 2322 int error; 2323 2324 ddata = sysc_child_to_parent(dev); 2325 2326 dev_dbg(ddata->dev, "%s %s\n", __func__, 2327 ddata->name ? ddata->name : ""); 2328 2329 error = pm_generic_suspend_noirq(dev); 2330 if (error) { 2331 dev_err(dev, "%s error at %i: %i\n", 2332 __func__, __LINE__, error); 2333 2334 return error; 2335 } 2336 2337 if (!pm_runtime_status_suspended(dev)) { 2338 error = pm_generic_runtime_suspend(dev); 2339 if (error) { 2340 dev_dbg(dev, "%s busy at %i: %i\n", 2341 __func__, __LINE__, error); 2342 2343 return 0; 2344 } 2345 2346 error = sysc_runtime_suspend(ddata->dev); 2347 if (error) { 2348 dev_err(dev, "%s error at %i: %i\n", 2349 __func__, __LINE__, error); 2350 2351 return error; 2352 } 2353 2354 ddata->child_needs_resume = true; 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int sysc_child_resume_noirq(struct device *dev) 2361 { 2362 struct sysc *ddata; 2363 int error; 2364 2365 ddata = sysc_child_to_parent(dev); 2366 2367 dev_dbg(ddata->dev, "%s %s\n", __func__, 2368 ddata->name ? ddata->name : ""); 2369 2370 if (ddata->child_needs_resume) { 2371 ddata->child_needs_resume = false; 2372 2373 error = sysc_runtime_resume(ddata->dev); 2374 if (error) 2375 dev_err(ddata->dev, 2376 "%s runtime resume error: %i\n", 2377 __func__, error); 2378 2379 error = pm_generic_runtime_resume(dev); 2380 if (error) 2381 dev_err(ddata->dev, 2382 "%s generic runtime resume: %i\n", 2383 __func__, error); 2384 } 2385 2386 return pm_generic_resume_noirq(dev); 2387 } 2388 #endif 2389 2390 static struct dev_pm_domain sysc_child_pm_domain = { 2391 .ops = { 2392 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2393 sysc_child_runtime_resume, 2394 NULL) 2395 USE_PLATFORM_PM_SLEEP_OPS 2396 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2397 sysc_child_resume_noirq) 2398 } 2399 }; 2400 2401 /** 2402 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2403 * @ddata: device driver data 2404 * @child: child device driver 2405 * 2406 * Allow idle for child devices as done with _od_runtime_suspend(). 2407 * Otherwise many child devices will not idle because of the permanent 2408 * parent usecount set in pm_runtime_irq_safe(). 2409 * 2410 * Note that the long term solution is to just modify the child device 2411 * drivers to not set pm_runtime_irq_safe() and then this can be just 2412 * dropped. 2413 */ 2414 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2415 { 2416 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2417 dev_pm_domain_set(child, &sysc_child_pm_domain); 2418 } 2419 2420 static int sysc_notifier_call(struct notifier_block *nb, 2421 unsigned long event, void *device) 2422 { 2423 struct device *dev = device; 2424 struct sysc *ddata; 2425 int error; 2426 2427 ddata = sysc_child_to_parent(dev); 2428 if (!ddata) 2429 return NOTIFY_DONE; 2430 2431 switch (event) { 2432 case BUS_NOTIFY_ADD_DEVICE: 2433 error = sysc_child_add_clocks(ddata, dev); 2434 if (error) 2435 return error; 2436 sysc_legacy_idle_quirk(ddata, dev); 2437 break; 2438 default: 2439 break; 2440 } 2441 2442 return NOTIFY_DONE; 2443 } 2444 2445 static struct notifier_block sysc_nb = { 2446 .notifier_call = sysc_notifier_call, 2447 }; 2448 2449 /* Device tree configured quirks */ 2450 struct sysc_dts_quirk { 2451 const char *name; 2452 u32 mask; 2453 }; 2454 2455 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2456 { .name = "ti,no-idle-on-init", 2457 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2458 { .name = "ti,no-reset-on-init", 2459 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2460 { .name = "ti,no-idle", 2461 .mask = SYSC_QUIRK_NO_IDLE, }, 2462 }; 2463 2464 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2465 bool is_child) 2466 { 2467 const struct property *prop; 2468 int i, len; 2469 2470 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2471 const char *name = sysc_dts_quirks[i].name; 2472 2473 prop = of_get_property(np, name, &len); 2474 if (!prop) 2475 continue; 2476 2477 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2478 if (is_child) { 2479 dev_warn(ddata->dev, 2480 "dts flag should be at module level for %s\n", 2481 name); 2482 } 2483 } 2484 } 2485 2486 static int sysc_init_dts_quirks(struct sysc *ddata) 2487 { 2488 struct device_node *np = ddata->dev->of_node; 2489 int error; 2490 u32 val; 2491 2492 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2493 2494 sysc_parse_dts_quirks(ddata, np, false); 2495 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2496 if (!error) { 2497 if (val > 255) { 2498 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2499 val); 2500 } 2501 2502 ddata->cfg.srst_udelay = (u8)val; 2503 } 2504 2505 return 0; 2506 } 2507 2508 static void sysc_unprepare(struct sysc *ddata) 2509 { 2510 int i; 2511 2512 if (!ddata->clocks) 2513 return; 2514 2515 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2516 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2517 clk_unprepare(ddata->clocks[i]); 2518 } 2519 } 2520 2521 /* 2522 * Common sysc register bits found on omap2, also known as type1 2523 */ 2524 static const struct sysc_regbits sysc_regbits_omap2 = { 2525 .dmadisable_shift = -ENODEV, 2526 .midle_shift = 12, 2527 .sidle_shift = 3, 2528 .clkact_shift = 8, 2529 .emufree_shift = 5, 2530 .enwkup_shift = 2, 2531 .srst_shift = 1, 2532 .autoidle_shift = 0, 2533 }; 2534 2535 static const struct sysc_capabilities sysc_omap2 = { 2536 .type = TI_SYSC_OMAP2, 2537 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2538 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2539 SYSC_OMAP2_AUTOIDLE, 2540 .regbits = &sysc_regbits_omap2, 2541 }; 2542 2543 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2544 static const struct sysc_capabilities sysc_omap2_timer = { 2545 .type = TI_SYSC_OMAP2_TIMER, 2546 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2547 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2548 SYSC_OMAP2_AUTOIDLE, 2549 .regbits = &sysc_regbits_omap2, 2550 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2551 }; 2552 2553 /* 2554 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2555 * with different sidle position 2556 */ 2557 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2558 .dmadisable_shift = -ENODEV, 2559 .midle_shift = -ENODEV, 2560 .sidle_shift = 4, 2561 .clkact_shift = -ENODEV, 2562 .enwkup_shift = -ENODEV, 2563 .srst_shift = 1, 2564 .autoidle_shift = 0, 2565 .emufree_shift = -ENODEV, 2566 }; 2567 2568 static const struct sysc_capabilities sysc_omap3_sham = { 2569 .type = TI_SYSC_OMAP3_SHAM, 2570 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2571 .regbits = &sysc_regbits_omap3_sham, 2572 }; 2573 2574 /* 2575 * AES register bits found on omap3 and later, a variant of 2576 * sysc_regbits_omap2 with different sidle position 2577 */ 2578 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2579 .dmadisable_shift = -ENODEV, 2580 .midle_shift = -ENODEV, 2581 .sidle_shift = 6, 2582 .clkact_shift = -ENODEV, 2583 .enwkup_shift = -ENODEV, 2584 .srst_shift = 1, 2585 .autoidle_shift = 0, 2586 .emufree_shift = -ENODEV, 2587 }; 2588 2589 static const struct sysc_capabilities sysc_omap3_aes = { 2590 .type = TI_SYSC_OMAP3_AES, 2591 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2592 .regbits = &sysc_regbits_omap3_aes, 2593 }; 2594 2595 /* 2596 * Common sysc register bits found on omap4, also known as type2 2597 */ 2598 static const struct sysc_regbits sysc_regbits_omap4 = { 2599 .dmadisable_shift = 16, 2600 .midle_shift = 4, 2601 .sidle_shift = 2, 2602 .clkact_shift = -ENODEV, 2603 .enwkup_shift = -ENODEV, 2604 .emufree_shift = 1, 2605 .srst_shift = 0, 2606 .autoidle_shift = -ENODEV, 2607 }; 2608 2609 static const struct sysc_capabilities sysc_omap4 = { 2610 .type = TI_SYSC_OMAP4, 2611 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2612 SYSC_OMAP4_SOFTRESET, 2613 .regbits = &sysc_regbits_omap4, 2614 }; 2615 2616 static const struct sysc_capabilities sysc_omap4_timer = { 2617 .type = TI_SYSC_OMAP4_TIMER, 2618 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2619 SYSC_OMAP4_SOFTRESET, 2620 .regbits = &sysc_regbits_omap4, 2621 }; 2622 2623 /* 2624 * Common sysc register bits found on omap4, also known as type3 2625 */ 2626 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2627 .dmadisable_shift = -ENODEV, 2628 .midle_shift = 2, 2629 .sidle_shift = 0, 2630 .clkact_shift = -ENODEV, 2631 .enwkup_shift = -ENODEV, 2632 .srst_shift = -ENODEV, 2633 .emufree_shift = -ENODEV, 2634 .autoidle_shift = -ENODEV, 2635 }; 2636 2637 static const struct sysc_capabilities sysc_omap4_simple = { 2638 .type = TI_SYSC_OMAP4_SIMPLE, 2639 .regbits = &sysc_regbits_omap4_simple, 2640 }; 2641 2642 /* 2643 * SmartReflex sysc found on omap34xx 2644 */ 2645 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2646 .dmadisable_shift = -ENODEV, 2647 .midle_shift = -ENODEV, 2648 .sidle_shift = -ENODEV, 2649 .clkact_shift = 20, 2650 .enwkup_shift = -ENODEV, 2651 .srst_shift = -ENODEV, 2652 .emufree_shift = -ENODEV, 2653 .autoidle_shift = -ENODEV, 2654 }; 2655 2656 static const struct sysc_capabilities sysc_34xx_sr = { 2657 .type = TI_SYSC_OMAP34XX_SR, 2658 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2659 .regbits = &sysc_regbits_omap34xx_sr, 2660 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2661 SYSC_QUIRK_LEGACY_IDLE, 2662 }; 2663 2664 /* 2665 * SmartReflex sysc found on omap36xx and later 2666 */ 2667 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2668 .dmadisable_shift = -ENODEV, 2669 .midle_shift = -ENODEV, 2670 .sidle_shift = 24, 2671 .clkact_shift = -ENODEV, 2672 .enwkup_shift = 26, 2673 .srst_shift = -ENODEV, 2674 .emufree_shift = -ENODEV, 2675 .autoidle_shift = -ENODEV, 2676 }; 2677 2678 static const struct sysc_capabilities sysc_36xx_sr = { 2679 .type = TI_SYSC_OMAP36XX_SR, 2680 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2681 .regbits = &sysc_regbits_omap36xx_sr, 2682 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2683 }; 2684 2685 static const struct sysc_capabilities sysc_omap4_sr = { 2686 .type = TI_SYSC_OMAP4_SR, 2687 .regbits = &sysc_regbits_omap36xx_sr, 2688 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2689 }; 2690 2691 /* 2692 * McASP register bits found on omap4 and later 2693 */ 2694 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2695 .dmadisable_shift = -ENODEV, 2696 .midle_shift = -ENODEV, 2697 .sidle_shift = 0, 2698 .clkact_shift = -ENODEV, 2699 .enwkup_shift = -ENODEV, 2700 .srst_shift = -ENODEV, 2701 .emufree_shift = -ENODEV, 2702 .autoidle_shift = -ENODEV, 2703 }; 2704 2705 static const struct sysc_capabilities sysc_omap4_mcasp = { 2706 .type = TI_SYSC_OMAP4_MCASP, 2707 .regbits = &sysc_regbits_omap4_mcasp, 2708 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2709 }; 2710 2711 /* 2712 * McASP found on dra7 and later 2713 */ 2714 static const struct sysc_capabilities sysc_dra7_mcasp = { 2715 .type = TI_SYSC_OMAP4_SIMPLE, 2716 .regbits = &sysc_regbits_omap4_simple, 2717 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2718 }; 2719 2720 /* 2721 * FS USB host found on omap4 and later 2722 */ 2723 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2724 .dmadisable_shift = -ENODEV, 2725 .midle_shift = -ENODEV, 2726 .sidle_shift = 24, 2727 .clkact_shift = -ENODEV, 2728 .enwkup_shift = 26, 2729 .srst_shift = -ENODEV, 2730 .emufree_shift = -ENODEV, 2731 .autoidle_shift = -ENODEV, 2732 }; 2733 2734 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2735 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2736 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2737 .regbits = &sysc_regbits_omap4_usb_host_fs, 2738 }; 2739 2740 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2741 .dmadisable_shift = -ENODEV, 2742 .midle_shift = -ENODEV, 2743 .sidle_shift = -ENODEV, 2744 .clkact_shift = -ENODEV, 2745 .enwkup_shift = 4, 2746 .srst_shift = 0, 2747 .emufree_shift = -ENODEV, 2748 .autoidle_shift = -ENODEV, 2749 }; 2750 2751 static const struct sysc_capabilities sysc_dra7_mcan = { 2752 .type = TI_SYSC_DRA7_MCAN, 2753 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2754 .regbits = &sysc_regbits_dra7_mcan, 2755 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2756 }; 2757 2758 /* 2759 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2760 */ 2761 static const struct sysc_capabilities sysc_pruss = { 2762 .type = TI_SYSC_PRUSS, 2763 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2764 .regbits = &sysc_regbits_omap4_simple, 2765 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2766 }; 2767 2768 static int sysc_init_pdata(struct sysc *ddata) 2769 { 2770 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2771 struct ti_sysc_module_data *mdata; 2772 2773 if (!pdata) 2774 return 0; 2775 2776 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2777 if (!mdata) 2778 return -ENOMEM; 2779 2780 if (ddata->legacy_mode) { 2781 mdata->name = ddata->legacy_mode; 2782 mdata->module_pa = ddata->module_pa; 2783 mdata->module_size = ddata->module_size; 2784 mdata->offsets = ddata->offsets; 2785 mdata->nr_offsets = SYSC_MAX_REGS; 2786 mdata->cap = ddata->cap; 2787 mdata->cfg = &ddata->cfg; 2788 } 2789 2790 ddata->mdata = mdata; 2791 2792 return 0; 2793 } 2794 2795 static int sysc_init_match(struct sysc *ddata) 2796 { 2797 const struct sysc_capabilities *cap; 2798 2799 cap = of_device_get_match_data(ddata->dev); 2800 if (!cap) 2801 return -EINVAL; 2802 2803 ddata->cap = cap; 2804 if (ddata->cap) 2805 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2806 2807 return 0; 2808 } 2809 2810 static void ti_sysc_idle(struct work_struct *work) 2811 { 2812 struct sysc *ddata; 2813 2814 ddata = container_of(work, struct sysc, idle_work.work); 2815 2816 /* 2817 * One time decrement of clock usage counts if left on from init. 2818 * Note that we disable opt clocks unconditionally in this case 2819 * as they are enabled unconditionally during init without 2820 * considering sysc_opt_clks_needed() at that point. 2821 */ 2822 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2823 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2824 sysc_disable_main_clocks(ddata); 2825 sysc_disable_opt_clocks(ddata); 2826 sysc_clkdm_allow_idle(ddata); 2827 } 2828 2829 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2830 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2831 return; 2832 2833 /* 2834 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2835 * and SYSC_QUIRK_NO_RESET_ON_INIT 2836 */ 2837 if (pm_runtime_active(ddata->dev)) 2838 pm_runtime_put_sync(ddata->dev); 2839 } 2840 2841 /* 2842 * SoC model and features detection. Only needed for SoCs that need 2843 * special handling for quirks, no need to list others. 2844 */ 2845 static const struct soc_device_attribute sysc_soc_match[] = { 2846 SOC_FLAG("OMAP242*", SOC_2420), 2847 SOC_FLAG("OMAP243*", SOC_2430), 2848 SOC_FLAG("OMAP3[45]*", SOC_3430), 2849 SOC_FLAG("OMAP3[67]*", SOC_3630), 2850 SOC_FLAG("OMAP443*", SOC_4430), 2851 SOC_FLAG("OMAP446*", SOC_4460), 2852 SOC_FLAG("OMAP447*", SOC_4470), 2853 SOC_FLAG("OMAP54*", SOC_5430), 2854 SOC_FLAG("AM433", SOC_AM3), 2855 SOC_FLAG("AM43*", SOC_AM4), 2856 SOC_FLAG("DRA7*", SOC_DRA7), 2857 2858 { /* sentinel */ }, 2859 }; 2860 2861 /* 2862 * List of SoCs variants with disabled features. By default we assume all 2863 * devices in the device tree are available so no need to list those SoCs. 2864 */ 2865 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2866 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2867 SOC_FLAG("AM3505", DIS_SGX), 2868 SOC_FLAG("OMAP3525", DIS_SGX), 2869 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2870 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2871 2872 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2873 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2874 SOC_FLAG("DM3725", DIS_SGX), 2875 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2876 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2877 SOC_FLAG("OMAP3621", DIS_ISP), 2878 2879 { /* sentinel */ }, 2880 }; 2881 2882 static int sysc_add_disabled(unsigned long base) 2883 { 2884 struct sysc_address *disabled_module; 2885 2886 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2887 if (!disabled_module) 2888 return -ENOMEM; 2889 2890 disabled_module->base = base; 2891 2892 mutex_lock(&sysc_soc->list_lock); 2893 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2894 mutex_unlock(&sysc_soc->list_lock); 2895 2896 return 0; 2897 } 2898 2899 /* 2900 * One time init to detect the booted SoC and disable unavailable features. 2901 * Note that we initialize static data shared across all ti-sysc instances 2902 * so ddata is only used for SoC type. This can be called from module_init 2903 * once we no longer need to rely on platform data. 2904 */ 2905 static int sysc_init_soc(struct sysc *ddata) 2906 { 2907 const struct soc_device_attribute *match; 2908 struct ti_sysc_platform_data *pdata; 2909 unsigned long features = 0; 2910 struct device_node *np; 2911 2912 if (sysc_soc) 2913 return 0; 2914 2915 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2916 if (!sysc_soc) 2917 return -ENOMEM; 2918 2919 mutex_init(&sysc_soc->list_lock); 2920 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2921 sysc_soc->general_purpose = true; 2922 2923 pdata = dev_get_platdata(ddata->dev); 2924 if (pdata && pdata->soc_type_gp) 2925 sysc_soc->general_purpose = pdata->soc_type_gp(); 2926 2927 match = soc_device_match(sysc_soc_match); 2928 if (match && match->data) 2929 sysc_soc->soc = (int)match->data; 2930 2931 /* 2932 * Check and warn about possible old incomplete dtb. We now want to see 2933 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 2934 */ 2935 switch (sysc_soc->soc) { 2936 case SOC_AM3: 2937 case SOC_AM4: 2938 case SOC_4430 ... SOC_4470: 2939 case SOC_5430: 2940 case SOC_DRA7: 2941 np = of_find_node_by_path("/ocp"); 2942 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 2943 "ti-sysc: Incomplete old dtb, please update\n"); 2944 break; 2945 default: 2946 break; 2947 } 2948 2949 /* Ignore devices that are not available on HS and EMU SoCs */ 2950 if (!sysc_soc->general_purpose) { 2951 switch (sysc_soc->soc) { 2952 case SOC_3430 ... SOC_3630: 2953 sysc_add_disabled(0x48304000); /* timer12 */ 2954 break; 2955 case SOC_AM3: 2956 sysc_add_disabled(0x48310000); /* rng */ 2957 default: 2958 break; 2959 } 2960 } 2961 2962 match = soc_device_match(sysc_soc_feat_match); 2963 if (!match) 2964 return 0; 2965 2966 if (match->data) 2967 features = (unsigned long)match->data; 2968 2969 /* 2970 * Add disabled devices to the list based on the module base. 2971 * Note that this must be done before we attempt to access the 2972 * device and have module revision checks working. 2973 */ 2974 if (features & DIS_ISP) 2975 sysc_add_disabled(0x480bd400); 2976 if (features & DIS_IVA) 2977 sysc_add_disabled(0x5d000000); 2978 if (features & DIS_SGX) 2979 sysc_add_disabled(0x50000000); 2980 2981 return 0; 2982 } 2983 2984 static void sysc_cleanup_soc(void) 2985 { 2986 struct sysc_address *disabled_module; 2987 struct list_head *pos, *tmp; 2988 2989 if (!sysc_soc) 2990 return; 2991 2992 mutex_lock(&sysc_soc->list_lock); 2993 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 2994 disabled_module = list_entry(pos, struct sysc_address, node); 2995 list_del(pos); 2996 kfree(disabled_module); 2997 } 2998 mutex_unlock(&sysc_soc->list_lock); 2999 } 3000 3001 static int sysc_check_disabled_devices(struct sysc *ddata) 3002 { 3003 struct sysc_address *disabled_module; 3004 struct list_head *pos; 3005 int error = 0; 3006 3007 mutex_lock(&sysc_soc->list_lock); 3008 list_for_each(pos, &sysc_soc->disabled_modules) { 3009 disabled_module = list_entry(pos, struct sysc_address, node); 3010 if (ddata->module_pa == disabled_module->base) { 3011 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3012 error = -ENODEV; 3013 break; 3014 } 3015 } 3016 mutex_unlock(&sysc_soc->list_lock); 3017 3018 return error; 3019 } 3020 3021 /* 3022 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3023 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3024 * are needed, we could also look at the timer register configuration. 3025 */ 3026 static int sysc_check_active_timer(struct sysc *ddata) 3027 { 3028 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3029 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3030 return 0; 3031 3032 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3033 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3034 return -ENXIO; 3035 3036 return 0; 3037 } 3038 3039 static const struct of_device_id sysc_match_table[] = { 3040 { .compatible = "simple-bus", }, 3041 { /* sentinel */ }, 3042 }; 3043 3044 static int sysc_probe(struct platform_device *pdev) 3045 { 3046 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3047 struct sysc *ddata; 3048 int error; 3049 3050 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3051 if (!ddata) 3052 return -ENOMEM; 3053 3054 ddata->offsets[SYSC_REVISION] = -ENODEV; 3055 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3056 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3057 ddata->dev = &pdev->dev; 3058 platform_set_drvdata(pdev, ddata); 3059 3060 error = sysc_init_soc(ddata); 3061 if (error) 3062 return error; 3063 3064 error = sysc_init_match(ddata); 3065 if (error) 3066 return error; 3067 3068 error = sysc_init_dts_quirks(ddata); 3069 if (error) 3070 return error; 3071 3072 error = sysc_map_and_check_registers(ddata); 3073 if (error) 3074 return error; 3075 3076 error = sysc_init_sysc_mask(ddata); 3077 if (error) 3078 return error; 3079 3080 error = sysc_init_idlemodes(ddata); 3081 if (error) 3082 return error; 3083 3084 error = sysc_init_syss_mask(ddata); 3085 if (error) 3086 return error; 3087 3088 error = sysc_init_pdata(ddata); 3089 if (error) 3090 return error; 3091 3092 sysc_init_early_quirks(ddata); 3093 3094 error = sysc_check_disabled_devices(ddata); 3095 if (error) 3096 return error; 3097 3098 error = sysc_check_active_timer(ddata); 3099 if (error == -ENXIO) 3100 ddata->reserved = true; 3101 else if (error) 3102 return error; 3103 3104 error = sysc_get_clocks(ddata); 3105 if (error) 3106 return error; 3107 3108 error = sysc_init_resets(ddata); 3109 if (error) 3110 goto unprepare; 3111 3112 error = sysc_init_module(ddata); 3113 if (error) 3114 goto unprepare; 3115 3116 pm_runtime_enable(ddata->dev); 3117 error = pm_runtime_resume_and_get(ddata->dev); 3118 if (error < 0) { 3119 pm_runtime_disable(ddata->dev); 3120 goto unprepare; 3121 } 3122 3123 /* Balance use counts as PM runtime should have enabled these all */ 3124 if (!(ddata->cfg.quirks & 3125 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3126 sysc_disable_main_clocks(ddata); 3127 sysc_disable_opt_clocks(ddata); 3128 sysc_clkdm_allow_idle(ddata); 3129 } 3130 3131 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3132 reset_control_assert(ddata->rsts); 3133 3134 sysc_show_registers(ddata); 3135 3136 ddata->dev->type = &sysc_device_type; 3137 3138 if (!ddata->reserved) { 3139 error = of_platform_populate(ddata->dev->of_node, 3140 sysc_match_table, 3141 pdata ? pdata->auxdata : NULL, 3142 ddata->dev); 3143 if (error) 3144 goto err; 3145 } 3146 3147 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3148 3149 /* At least earlycon won't survive without deferred idle */ 3150 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3151 SYSC_QUIRK_NO_IDLE_ON_INIT | 3152 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3153 schedule_delayed_work(&ddata->idle_work, 3000); 3154 } else { 3155 pm_runtime_put(&pdev->dev); 3156 } 3157 3158 return 0; 3159 3160 err: 3161 pm_runtime_put_sync(&pdev->dev); 3162 pm_runtime_disable(&pdev->dev); 3163 unprepare: 3164 sysc_unprepare(ddata); 3165 3166 return error; 3167 } 3168 3169 static int sysc_remove(struct platform_device *pdev) 3170 { 3171 struct sysc *ddata = platform_get_drvdata(pdev); 3172 int error; 3173 3174 cancel_delayed_work_sync(&ddata->idle_work); 3175 3176 error = pm_runtime_resume_and_get(ddata->dev); 3177 if (error < 0) { 3178 pm_runtime_disable(ddata->dev); 3179 goto unprepare; 3180 } 3181 3182 of_platform_depopulate(&pdev->dev); 3183 3184 pm_runtime_put_sync(&pdev->dev); 3185 pm_runtime_disable(&pdev->dev); 3186 3187 if (!reset_control_status(ddata->rsts)) 3188 reset_control_assert(ddata->rsts); 3189 3190 unprepare: 3191 sysc_unprepare(ddata); 3192 3193 return 0; 3194 } 3195 3196 static const struct of_device_id sysc_match[] = { 3197 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3198 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3199 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3200 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3201 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3202 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3203 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3204 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3205 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3206 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3207 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3208 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3209 { .compatible = "ti,sysc-usb-host-fs", 3210 .data = &sysc_omap4_usb_host_fs, }, 3211 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3212 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3213 { }, 3214 }; 3215 MODULE_DEVICE_TABLE(of, sysc_match); 3216 3217 static struct platform_driver sysc_driver = { 3218 .probe = sysc_probe, 3219 .remove = sysc_remove, 3220 .driver = { 3221 .name = "ti-sysc", 3222 .of_match_table = sysc_match, 3223 .pm = &sysc_pm_ops, 3224 }, 3225 }; 3226 3227 static int __init sysc_init(void) 3228 { 3229 bus_register_notifier(&platform_bus_type, &sysc_nb); 3230 3231 return platform_driver_register(&sysc_driver); 3232 } 3233 module_init(sysc_init); 3234 3235 static void __exit sysc_exit(void) 3236 { 3237 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3238 platform_driver_unregister(&sysc_driver); 3239 sysc_cleanup_soc(); 3240 } 3241 module_exit(sysc_exit); 3242 3243 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3244 MODULE_LICENSE("GPL v2"); 3245