1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/cpu_pm.h> 10 #include <linux/delay.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/slab.h> 20 #include <linux/sys_soc.h> 21 #include <linux/timekeeping.h> 22 #include <linux/iopoll.h> 23 24 #include <linux/platform_data/ti-sysc.h> 25 26 #include <dt-bindings/bus/ti-sysc.h> 27 28 #define DIS_ISP BIT(2) 29 #define DIS_IVA BIT(1) 30 #define DIS_SGX BIT(0) 31 32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 33 34 #define MAX_MODULE_SOFTRESET_WAIT 10000 35 36 enum sysc_soc { 37 SOC_UNKNOWN, 38 SOC_2420, 39 SOC_2430, 40 SOC_3430, 41 SOC_3630, 42 SOC_4430, 43 SOC_4460, 44 SOC_4470, 45 SOC_5430, 46 SOC_AM3, 47 SOC_AM4, 48 SOC_DRA7, 49 }; 50 51 struct sysc_address { 52 unsigned long base; 53 struct list_head node; 54 }; 55 56 struct sysc_module { 57 struct sysc *ddata; 58 struct list_head node; 59 }; 60 61 struct sysc_soc_info { 62 unsigned long general_purpose:1; 63 enum sysc_soc soc; 64 struct mutex list_lock; /* disabled and restored modules list lock */ 65 struct list_head disabled_modules; 66 struct list_head restored_modules; 67 struct notifier_block nb; 68 }; 69 70 enum sysc_clocks { 71 SYSC_FCK, 72 SYSC_ICK, 73 SYSC_OPTFCK0, 74 SYSC_OPTFCK1, 75 SYSC_OPTFCK2, 76 SYSC_OPTFCK3, 77 SYSC_OPTFCK4, 78 SYSC_OPTFCK5, 79 SYSC_OPTFCK6, 80 SYSC_OPTFCK7, 81 SYSC_MAX_CLOCKS, 82 }; 83 84 static struct sysc_soc_info *sysc_soc; 85 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 86 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 88 "opt5", "opt6", "opt7", 89 }; 90 91 #define SYSC_IDLEMODE_MASK 3 92 #define SYSC_CLOCKACTIVITY_MASK 3 93 94 /** 95 * struct sysc - TI sysc interconnect target module registers and capabilities 96 * @dev: struct device pointer 97 * @module_pa: physical address of the interconnect target module 98 * @module_size: size of the interconnect target module 99 * @module_va: virtual address of the interconnect target module 100 * @offsets: register offsets from module base 101 * @mdata: ti-sysc to hwmod translation data for a module 102 * @clocks: clocks used by the interconnect target module 103 * @clock_roles: clock role names for the found clocks 104 * @nr_clocks: number of clocks used by the interconnect target module 105 * @rsts: resets used by the interconnect target module 106 * @legacy_mode: configured for legacy mode if set 107 * @cap: interconnect target module capabilities 108 * @cfg: interconnect target module configuration 109 * @cookie: data used by legacy platform callbacks 110 * @name: name if available 111 * @revision: interconnect target module revision 112 * @reserved: target module is reserved and already in use 113 * @enabled: sysc runtime enabled status 114 * @needs_resume: runtime resume needed on resume from suspend 115 * @child_needs_resume: runtime resume needed for child on resume from suspend 116 * @disable_on_idle: status flag used for disabling modules with resets 117 * @idle_work: work structure used to perform delayed idle on a module 118 * @pre_reset_quirk: module specific pre-reset quirk 119 * @post_reset_quirk: module specific post-reset quirk 120 * @reset_done_quirk: module specific reset done quirk 121 * @module_enable_quirk: module specific enable quirk 122 * @module_disable_quirk: module specific disable quirk 123 * @module_unlock_quirk: module specific sysconfig unlock quirk 124 * @module_lock_quirk: module specific sysconfig lock quirk 125 */ 126 struct sysc { 127 struct device *dev; 128 u64 module_pa; 129 u32 module_size; 130 void __iomem *module_va; 131 int offsets[SYSC_MAX_REGS]; 132 struct ti_sysc_module_data *mdata; 133 struct clk **clocks; 134 const char **clock_roles; 135 int nr_clocks; 136 struct reset_control *rsts; 137 const char *legacy_mode; 138 const struct sysc_capabilities *cap; 139 struct sysc_config cfg; 140 struct ti_sysc_cookie cookie; 141 const char *name; 142 u32 revision; 143 u32 sysconfig; 144 unsigned int reserved:1; 145 unsigned int enabled:1; 146 unsigned int needs_resume:1; 147 unsigned int child_needs_resume:1; 148 struct delayed_work idle_work; 149 void (*pre_reset_quirk)(struct sysc *sysc); 150 void (*post_reset_quirk)(struct sysc *sysc); 151 void (*reset_done_quirk)(struct sysc *sysc); 152 void (*module_enable_quirk)(struct sysc *sysc); 153 void (*module_disable_quirk)(struct sysc *sysc); 154 void (*module_unlock_quirk)(struct sysc *sysc); 155 void (*module_lock_quirk)(struct sysc *sysc); 156 }; 157 158 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 159 bool is_child); 160 static int sysc_reset(struct sysc *ddata); 161 162 static void sysc_write(struct sysc *ddata, int offset, u32 value) 163 { 164 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 165 writew_relaxed(value & 0xffff, ddata->module_va + offset); 166 167 /* Only i2c revision has LO and HI register with stride of 4 */ 168 if (ddata->offsets[SYSC_REVISION] >= 0 && 169 offset == ddata->offsets[SYSC_REVISION]) { 170 u16 hi = value >> 16; 171 172 writew_relaxed(hi, ddata->module_va + offset + 4); 173 } 174 175 return; 176 } 177 178 writel_relaxed(value, ddata->module_va + offset); 179 } 180 181 static u32 sysc_read(struct sysc *ddata, int offset) 182 { 183 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 184 u32 val; 185 186 val = readw_relaxed(ddata->module_va + offset); 187 188 /* Only i2c revision has LO and HI register with stride of 4 */ 189 if (ddata->offsets[SYSC_REVISION] >= 0 && 190 offset == ddata->offsets[SYSC_REVISION]) { 191 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 192 193 val |= tmp << 16; 194 } 195 196 return val; 197 } 198 199 return readl_relaxed(ddata->module_va + offset); 200 } 201 202 static bool sysc_opt_clks_needed(struct sysc *ddata) 203 { 204 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 205 } 206 207 static u32 sysc_read_revision(struct sysc *ddata) 208 { 209 int offset = ddata->offsets[SYSC_REVISION]; 210 211 if (offset < 0) 212 return 0; 213 214 return sysc_read(ddata, offset); 215 } 216 217 static u32 sysc_read_sysconfig(struct sysc *ddata) 218 { 219 int offset = ddata->offsets[SYSC_SYSCONFIG]; 220 221 if (offset < 0) 222 return 0; 223 224 return sysc_read(ddata, offset); 225 } 226 227 static u32 sysc_read_sysstatus(struct sysc *ddata) 228 { 229 int offset = ddata->offsets[SYSC_SYSSTATUS]; 230 231 if (offset < 0) 232 return 0; 233 234 return sysc_read(ddata, offset); 235 } 236 237 static int sysc_poll_reset_sysstatus(struct sysc *ddata) 238 { 239 int error, retries; 240 u32 syss_done, rstval; 241 242 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 243 syss_done = 0; 244 else 245 syss_done = ddata->cfg.syss_mask; 246 247 if (likely(!timekeeping_suspended)) { 248 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 249 rstval, (rstval & ddata->cfg.syss_mask) == 250 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 251 } else { 252 retries = MAX_MODULE_SOFTRESET_WAIT; 253 while (retries--) { 254 rstval = sysc_read_sysstatus(ddata); 255 if ((rstval & ddata->cfg.syss_mask) == syss_done) 256 return 0; 257 udelay(2); /* Account for udelay flakeyness */ 258 } 259 error = -ETIMEDOUT; 260 } 261 262 return error; 263 } 264 265 static int sysc_poll_reset_sysconfig(struct sysc *ddata) 266 { 267 int error, retries; 268 u32 sysc_mask, rstval; 269 270 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 271 272 if (likely(!timekeeping_suspended)) { 273 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 274 rstval, !(rstval & sysc_mask), 275 100, MAX_MODULE_SOFTRESET_WAIT); 276 } else { 277 retries = MAX_MODULE_SOFTRESET_WAIT; 278 while (retries--) { 279 rstval = sysc_read_sysconfig(ddata); 280 if (!(rstval & sysc_mask)) 281 return 0; 282 udelay(2); /* Account for udelay flakeyness */ 283 } 284 error = -ETIMEDOUT; 285 } 286 287 return error; 288 } 289 290 /* Poll on reset status */ 291 static int sysc_wait_softreset(struct sysc *ddata) 292 { 293 int syss_offset, error = 0; 294 295 if (ddata->cap->regbits->srst_shift < 0) 296 return 0; 297 298 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 299 300 if (syss_offset >= 0) 301 error = sysc_poll_reset_sysstatus(ddata); 302 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) 303 error = sysc_poll_reset_sysconfig(ddata); 304 305 return error; 306 } 307 308 static int sysc_add_named_clock_from_child(struct sysc *ddata, 309 const char *name, 310 const char *optfck_name) 311 { 312 struct device_node *np = ddata->dev->of_node; 313 struct device_node *child; 314 struct clk_lookup *cl; 315 struct clk *clock; 316 const char *n; 317 318 if (name) 319 n = name; 320 else 321 n = optfck_name; 322 323 /* Does the clock alias already exist? */ 324 clock = of_clk_get_by_name(np, n); 325 if (!IS_ERR(clock)) { 326 clk_put(clock); 327 328 return 0; 329 } 330 331 child = of_get_next_available_child(np, NULL); 332 if (!child) 333 return -ENODEV; 334 335 clock = devm_get_clk_from_child(ddata->dev, child, name); 336 if (IS_ERR(clock)) 337 return PTR_ERR(clock); 338 339 /* 340 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 341 * limit for clk_get(). If cl ever needs to be freed, it should be done 342 * with clkdev_drop(). 343 */ 344 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 345 if (!cl) 346 return -ENOMEM; 347 348 cl->con_id = n; 349 cl->dev_id = dev_name(ddata->dev); 350 cl->clk = clock; 351 clkdev_add(cl); 352 353 clk_put(clock); 354 355 return 0; 356 } 357 358 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 359 { 360 const char *optfck_name; 361 int error, index; 362 363 if (ddata->nr_clocks < SYSC_OPTFCK0) 364 index = SYSC_OPTFCK0; 365 else 366 index = ddata->nr_clocks; 367 368 if (name) 369 optfck_name = name; 370 else 371 optfck_name = clock_names[index]; 372 373 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 374 if (error) 375 return error; 376 377 ddata->clock_roles[index] = optfck_name; 378 ddata->nr_clocks++; 379 380 return 0; 381 } 382 383 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 384 { 385 int error, i, index = -ENODEV; 386 387 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 388 index = SYSC_FCK; 389 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 390 index = SYSC_ICK; 391 392 if (index < 0) { 393 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 394 if (!ddata->clocks[i]) { 395 index = i; 396 break; 397 } 398 } 399 } 400 401 if (index < 0) { 402 dev_err(ddata->dev, "clock %s not added\n", name); 403 return index; 404 } 405 406 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 407 if (IS_ERR(ddata->clocks[index])) { 408 dev_err(ddata->dev, "clock get error for %s: %li\n", 409 name, PTR_ERR(ddata->clocks[index])); 410 411 return PTR_ERR(ddata->clocks[index]); 412 } 413 414 error = clk_prepare(ddata->clocks[index]); 415 if (error) { 416 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 417 name, error); 418 419 return error; 420 } 421 422 return 0; 423 } 424 425 static int sysc_get_clocks(struct sysc *ddata) 426 { 427 struct device_node *np = ddata->dev->of_node; 428 struct property *prop; 429 const char *name; 430 int nr_fck = 0, nr_ick = 0, i, error = 0; 431 432 ddata->clock_roles = devm_kcalloc(ddata->dev, 433 SYSC_MAX_CLOCKS, 434 sizeof(*ddata->clock_roles), 435 GFP_KERNEL); 436 if (!ddata->clock_roles) 437 return -ENOMEM; 438 439 of_property_for_each_string(np, "clock-names", prop, name) { 440 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 441 nr_fck++; 442 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 443 nr_ick++; 444 ddata->clock_roles[ddata->nr_clocks] = name; 445 ddata->nr_clocks++; 446 } 447 448 if (ddata->nr_clocks < 1) 449 return 0; 450 451 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 452 error = sysc_init_ext_opt_clock(ddata, NULL); 453 if (error) 454 return error; 455 } 456 457 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 458 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 459 460 return -EINVAL; 461 } 462 463 if (nr_fck > 1 || nr_ick > 1) { 464 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 465 466 return -EINVAL; 467 } 468 469 /* Always add a slot for main clocks fck and ick even if unused */ 470 if (!nr_fck) 471 ddata->nr_clocks++; 472 if (!nr_ick) 473 ddata->nr_clocks++; 474 475 ddata->clocks = devm_kcalloc(ddata->dev, 476 ddata->nr_clocks, sizeof(*ddata->clocks), 477 GFP_KERNEL); 478 if (!ddata->clocks) 479 return -ENOMEM; 480 481 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 482 const char *name = ddata->clock_roles[i]; 483 484 if (!name) 485 continue; 486 487 error = sysc_get_one_clock(ddata, name); 488 if (error) 489 return error; 490 } 491 492 return 0; 493 } 494 495 static int sysc_enable_main_clocks(struct sysc *ddata) 496 { 497 struct clk *clock; 498 int i, error; 499 500 if (!ddata->clocks) 501 return 0; 502 503 for (i = 0; i < SYSC_OPTFCK0; i++) { 504 clock = ddata->clocks[i]; 505 506 /* Main clocks may not have ick */ 507 if (IS_ERR_OR_NULL(clock)) 508 continue; 509 510 error = clk_enable(clock); 511 if (error) 512 goto err_disable; 513 } 514 515 return 0; 516 517 err_disable: 518 for (i--; i >= 0; i--) { 519 clock = ddata->clocks[i]; 520 521 /* Main clocks may not have ick */ 522 if (IS_ERR_OR_NULL(clock)) 523 continue; 524 525 clk_disable(clock); 526 } 527 528 return error; 529 } 530 531 static void sysc_disable_main_clocks(struct sysc *ddata) 532 { 533 struct clk *clock; 534 int i; 535 536 if (!ddata->clocks) 537 return; 538 539 for (i = 0; i < SYSC_OPTFCK0; i++) { 540 clock = ddata->clocks[i]; 541 if (IS_ERR_OR_NULL(clock)) 542 continue; 543 544 clk_disable(clock); 545 } 546 } 547 548 static int sysc_enable_opt_clocks(struct sysc *ddata) 549 { 550 struct clk *clock; 551 int i, error; 552 553 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 554 return 0; 555 556 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 557 clock = ddata->clocks[i]; 558 559 /* Assume no holes for opt clocks */ 560 if (IS_ERR_OR_NULL(clock)) 561 return 0; 562 563 error = clk_enable(clock); 564 if (error) 565 goto err_disable; 566 } 567 568 return 0; 569 570 err_disable: 571 for (i--; i >= 0; i--) { 572 clock = ddata->clocks[i]; 573 if (IS_ERR_OR_NULL(clock)) 574 continue; 575 576 clk_disable(clock); 577 } 578 579 return error; 580 } 581 582 static void sysc_disable_opt_clocks(struct sysc *ddata) 583 { 584 struct clk *clock; 585 int i; 586 587 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 588 return; 589 590 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 591 clock = ddata->clocks[i]; 592 593 /* Assume no holes for opt clocks */ 594 if (IS_ERR_OR_NULL(clock)) 595 return; 596 597 clk_disable(clock); 598 } 599 } 600 601 static void sysc_clkdm_deny_idle(struct sysc *ddata) 602 { 603 struct ti_sysc_platform_data *pdata; 604 605 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 606 return; 607 608 pdata = dev_get_platdata(ddata->dev); 609 if (pdata && pdata->clkdm_deny_idle) 610 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 611 } 612 613 static void sysc_clkdm_allow_idle(struct sysc *ddata) 614 { 615 struct ti_sysc_platform_data *pdata; 616 617 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 618 return; 619 620 pdata = dev_get_platdata(ddata->dev); 621 if (pdata && pdata->clkdm_allow_idle) 622 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 623 } 624 625 /** 626 * sysc_init_resets - init rstctrl reset line if configured 627 * @ddata: device driver data 628 * 629 * See sysc_rstctrl_reset_deassert(). 630 */ 631 static int sysc_init_resets(struct sysc *ddata) 632 { 633 ddata->rsts = 634 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 635 636 return PTR_ERR_OR_ZERO(ddata->rsts); 637 } 638 639 /** 640 * sysc_parse_and_check_child_range - parses module IO region from ranges 641 * @ddata: device driver data 642 * 643 * In general we only need rev, syss, and sysc registers and not the whole 644 * module range. But we do want the offsets for these registers from the 645 * module base. This allows us to check them against the legacy hwmod 646 * platform data. Let's also check the ranges are configured properly. 647 */ 648 static int sysc_parse_and_check_child_range(struct sysc *ddata) 649 { 650 struct device_node *np = ddata->dev->of_node; 651 const __be32 *ranges; 652 u32 nr_addr, nr_size; 653 int len, error; 654 655 ranges = of_get_property(np, "ranges", &len); 656 if (!ranges) { 657 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 658 659 return -ENOENT; 660 } 661 662 len /= sizeof(*ranges); 663 664 if (len < 3) { 665 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 666 667 return -EINVAL; 668 } 669 670 error = of_property_read_u32(np, "#address-cells", &nr_addr); 671 if (error) 672 return -ENOENT; 673 674 error = of_property_read_u32(np, "#size-cells", &nr_size); 675 if (error) 676 return -ENOENT; 677 678 if (nr_addr != 1 || nr_size != 1) { 679 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 680 681 return -EINVAL; 682 } 683 684 ranges++; 685 ddata->module_pa = of_translate_address(np, ranges++); 686 ddata->module_size = be32_to_cpup(ranges); 687 688 return 0; 689 } 690 691 /* Interconnect instances to probe before l4_per instances */ 692 static struct resource early_bus_ranges[] = { 693 /* am3/4 l4_wkup */ 694 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, 695 /* omap4/5 and dra7 l4_cfg */ 696 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, 697 /* omap4 l4_wkup */ 698 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, 699 /* omap5 and dra7 l4_wkup without dra7 dcan segment */ 700 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, 701 }; 702 703 static atomic_t sysc_defer = ATOMIC_INIT(10); 704 705 /** 706 * sysc_defer_non_critical - defer non_critical interconnect probing 707 * @ddata: device driver data 708 * 709 * We want to probe l4_cfg and l4_wkup interconnect instances before any 710 * l4_per instances as l4_per instances depend on resources on l4_cfg and 711 * l4_wkup interconnects. 712 */ 713 static int sysc_defer_non_critical(struct sysc *ddata) 714 { 715 struct resource *res; 716 int i; 717 718 if (!atomic_read(&sysc_defer)) 719 return 0; 720 721 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { 722 res = &early_bus_ranges[i]; 723 if (ddata->module_pa >= res->start && 724 ddata->module_pa <= res->end) { 725 atomic_set(&sysc_defer, 0); 726 727 return 0; 728 } 729 } 730 731 atomic_dec_if_positive(&sysc_defer); 732 733 return -EPROBE_DEFER; 734 } 735 736 static struct device_node *stdout_path; 737 738 static void sysc_init_stdout_path(struct sysc *ddata) 739 { 740 struct device_node *np = NULL; 741 const char *uart; 742 743 if (IS_ERR(stdout_path)) 744 return; 745 746 if (stdout_path) 747 return; 748 749 np = of_find_node_by_path("/chosen"); 750 if (!np) 751 goto err; 752 753 uart = of_get_property(np, "stdout-path", NULL); 754 if (!uart) 755 goto err; 756 757 np = of_find_node_by_path(uart); 758 if (!np) 759 goto err; 760 761 stdout_path = np; 762 763 return; 764 765 err: 766 stdout_path = ERR_PTR(-ENODEV); 767 } 768 769 static void sysc_check_quirk_stdout(struct sysc *ddata, 770 struct device_node *np) 771 { 772 sysc_init_stdout_path(ddata); 773 if (np != stdout_path) 774 return; 775 776 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 777 SYSC_QUIRK_NO_RESET_ON_INIT; 778 } 779 780 /** 781 * sysc_check_one_child - check child configuration 782 * @ddata: device driver data 783 * @np: child device node 784 * 785 * Let's avoid messy situations where we have new interconnect target 786 * node but children have "ti,hwmods". These belong to the interconnect 787 * target node and are managed by this driver. 788 */ 789 static void sysc_check_one_child(struct sysc *ddata, 790 struct device_node *np) 791 { 792 const char *name; 793 794 name = of_get_property(np, "ti,hwmods", NULL); 795 if (name && !of_device_is_compatible(np, "ti,sysc")) 796 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 797 798 sysc_check_quirk_stdout(ddata, np); 799 sysc_parse_dts_quirks(ddata, np, true); 800 } 801 802 static void sysc_check_children(struct sysc *ddata) 803 { 804 struct device_node *child; 805 806 for_each_child_of_node(ddata->dev->of_node, child) 807 sysc_check_one_child(ddata, child); 808 } 809 810 /* 811 * So far only I2C uses 16-bit read access with clockactivity with revision 812 * in two registers with stride of 4. We can detect this based on the rev 813 * register size to configure things far enough to be able to properly read 814 * the revision register. 815 */ 816 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 817 { 818 if (resource_size(res) == 8) 819 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 820 } 821 822 /** 823 * sysc_parse_one - parses the interconnect target module registers 824 * @ddata: device driver data 825 * @reg: register to parse 826 */ 827 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 828 { 829 struct resource *res; 830 const char *name; 831 832 switch (reg) { 833 case SYSC_REVISION: 834 case SYSC_SYSCONFIG: 835 case SYSC_SYSSTATUS: 836 name = reg_names[reg]; 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 res = platform_get_resource_byname(to_platform_device(ddata->dev), 843 IORESOURCE_MEM, name); 844 if (!res) { 845 ddata->offsets[reg] = -ENODEV; 846 847 return 0; 848 } 849 850 ddata->offsets[reg] = res->start - ddata->module_pa; 851 if (reg == SYSC_REVISION) 852 sysc_check_quirk_16bit(ddata, res); 853 854 return 0; 855 } 856 857 static int sysc_parse_registers(struct sysc *ddata) 858 { 859 int i, error; 860 861 for (i = 0; i < SYSC_MAX_REGS; i++) { 862 error = sysc_parse_one(ddata, i); 863 if (error) 864 return error; 865 } 866 867 return 0; 868 } 869 870 /** 871 * sysc_check_registers - check for misconfigured register overlaps 872 * @ddata: device driver data 873 */ 874 static int sysc_check_registers(struct sysc *ddata) 875 { 876 int i, j, nr_regs = 0, nr_matches = 0; 877 878 for (i = 0; i < SYSC_MAX_REGS; i++) { 879 if (ddata->offsets[i] < 0) 880 continue; 881 882 if (ddata->offsets[i] > (ddata->module_size - 4)) { 883 dev_err(ddata->dev, "register outside module range"); 884 885 return -EINVAL; 886 } 887 888 for (j = 0; j < SYSC_MAX_REGS; j++) { 889 if (ddata->offsets[j] < 0) 890 continue; 891 892 if (ddata->offsets[i] == ddata->offsets[j]) 893 nr_matches++; 894 } 895 nr_regs++; 896 } 897 898 if (nr_matches > nr_regs) { 899 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 900 nr_regs, nr_matches); 901 902 return -EINVAL; 903 } 904 905 return 0; 906 } 907 908 /** 909 * sysc_ioremap - ioremap register space for the interconnect target module 910 * @ddata: device driver data 911 * 912 * Note that the interconnect target module registers can be anywhere 913 * within the interconnect target module range. For example, SGX has 914 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 915 * has them at offset 0x1200 in the CPSW_WR child. Usually the 916 * the interconnect target module registers are at the beginning of 917 * the module range though. 918 */ 919 static int sysc_ioremap(struct sysc *ddata) 920 { 921 int size; 922 923 if (ddata->offsets[SYSC_REVISION] < 0 && 924 ddata->offsets[SYSC_SYSCONFIG] < 0 && 925 ddata->offsets[SYSC_SYSSTATUS] < 0) { 926 size = ddata->module_size; 927 } else { 928 size = max3(ddata->offsets[SYSC_REVISION], 929 ddata->offsets[SYSC_SYSCONFIG], 930 ddata->offsets[SYSC_SYSSTATUS]); 931 932 if (size < SZ_1K) 933 size = SZ_1K; 934 935 if ((size + sizeof(u32)) > ddata->module_size) 936 size = ddata->module_size; 937 } 938 939 ddata->module_va = devm_ioremap(ddata->dev, 940 ddata->module_pa, 941 size + sizeof(u32)); 942 if (!ddata->module_va) 943 return -EIO; 944 945 return 0; 946 } 947 948 /** 949 * sysc_map_and_check_registers - ioremap and check device registers 950 * @ddata: device driver data 951 */ 952 static int sysc_map_and_check_registers(struct sysc *ddata) 953 { 954 struct device_node *np = ddata->dev->of_node; 955 int error; 956 957 error = sysc_parse_and_check_child_range(ddata); 958 if (error) 959 return error; 960 961 error = sysc_defer_non_critical(ddata); 962 if (error) 963 return error; 964 965 sysc_check_children(ddata); 966 967 if (!of_get_property(np, "reg", NULL)) 968 return 0; 969 970 error = sysc_parse_registers(ddata); 971 if (error) 972 return error; 973 974 error = sysc_ioremap(ddata); 975 if (error) 976 return error; 977 978 error = sysc_check_registers(ddata); 979 if (error) 980 return error; 981 982 return 0; 983 } 984 985 /** 986 * sysc_show_rev - read and show interconnect target module revision 987 * @bufp: buffer to print the information to 988 * @ddata: device driver data 989 */ 990 static int sysc_show_rev(char *bufp, struct sysc *ddata) 991 { 992 int len; 993 994 if (ddata->offsets[SYSC_REVISION] < 0) 995 return sprintf(bufp, ":NA"); 996 997 len = sprintf(bufp, ":%08x", ddata->revision); 998 999 return len; 1000 } 1001 1002 static int sysc_show_reg(struct sysc *ddata, 1003 char *bufp, enum sysc_registers reg) 1004 { 1005 if (ddata->offsets[reg] < 0) 1006 return sprintf(bufp, ":NA"); 1007 1008 return sprintf(bufp, ":%x", ddata->offsets[reg]); 1009 } 1010 1011 static int sysc_show_name(char *bufp, struct sysc *ddata) 1012 { 1013 if (!ddata->name) 1014 return 0; 1015 1016 return sprintf(bufp, ":%s", ddata->name); 1017 } 1018 1019 /** 1020 * sysc_show_registers - show information about interconnect target module 1021 * @ddata: device driver data 1022 */ 1023 static void sysc_show_registers(struct sysc *ddata) 1024 { 1025 char buf[128]; 1026 char *bufp = buf; 1027 int i; 1028 1029 for (i = 0; i < SYSC_MAX_REGS; i++) 1030 bufp += sysc_show_reg(ddata, bufp, i); 1031 1032 bufp += sysc_show_rev(bufp, ddata); 1033 bufp += sysc_show_name(bufp, ddata); 1034 1035 dev_dbg(ddata->dev, "%llx:%x%s\n", 1036 ddata->module_pa, ddata->module_size, 1037 buf); 1038 } 1039 1040 /** 1041 * sysc_write_sysconfig - handle sysconfig quirks for register write 1042 * @ddata: device driver data 1043 * @value: register value 1044 */ 1045 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 1046 { 1047 if (ddata->module_unlock_quirk) 1048 ddata->module_unlock_quirk(ddata); 1049 1050 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 1051 1052 if (ddata->module_lock_quirk) 1053 ddata->module_lock_quirk(ddata); 1054 } 1055 1056 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 1057 #define SYSC_CLOCACT_ICK 2 1058 1059 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1060 static int sysc_enable_module(struct device *dev) 1061 { 1062 struct sysc *ddata; 1063 const struct sysc_regbits *regbits; 1064 u32 reg, idlemodes, best_mode; 1065 int error; 1066 1067 ddata = dev_get_drvdata(dev); 1068 1069 /* 1070 * Some modules like DSS reset automatically on idle. Enable optional 1071 * reset clocks and wait for OCP softreset to complete. 1072 */ 1073 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1074 error = sysc_enable_opt_clocks(ddata); 1075 if (error) { 1076 dev_err(ddata->dev, 1077 "Optional clocks failed for enable: %i\n", 1078 error); 1079 return error; 1080 } 1081 } 1082 /* 1083 * Some modules like i2c and hdq1w have unusable reset status unless 1084 * the module reset quirk is enabled. Skip status check on enable. 1085 */ 1086 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1087 error = sysc_wait_softreset(ddata); 1088 if (error) 1089 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1090 } 1091 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1092 sysc_disable_opt_clocks(ddata); 1093 1094 /* 1095 * Some subsystem private interconnects, like DSS top level module, 1096 * need only the automatic OCP softreset handling with no sysconfig 1097 * register bits to configure. 1098 */ 1099 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1100 return 0; 1101 1102 regbits = ddata->cap->regbits; 1103 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1104 1105 /* 1106 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1107 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1108 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1109 */ 1110 if (regbits->clkact_shift >= 0 && 1111 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1112 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1113 1114 /* Set SIDLE mode */ 1115 idlemodes = ddata->cfg.sidlemodes; 1116 if (!idlemodes || regbits->sidle_shift < 0) 1117 goto set_midle; 1118 1119 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1120 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1121 best_mode = SYSC_IDLE_NO; 1122 } else { 1123 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1124 if (best_mode > SYSC_IDLE_MASK) { 1125 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1126 return -EINVAL; 1127 } 1128 1129 /* Set WAKEUP */ 1130 if (regbits->enwkup_shift >= 0 && 1131 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1132 reg |= BIT(regbits->enwkup_shift); 1133 } 1134 1135 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1136 reg |= best_mode << regbits->sidle_shift; 1137 sysc_write_sysconfig(ddata, reg); 1138 1139 set_midle: 1140 /* Set MIDLE mode */ 1141 idlemodes = ddata->cfg.midlemodes; 1142 if (!idlemodes || regbits->midle_shift < 0) 1143 goto set_autoidle; 1144 1145 best_mode = fls(ddata->cfg.midlemodes) - 1; 1146 if (best_mode > SYSC_IDLE_MASK) { 1147 dev_err(dev, "%s: invalid midlemode\n", __func__); 1148 error = -EINVAL; 1149 goto save_context; 1150 } 1151 1152 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1153 best_mode = SYSC_IDLE_NO; 1154 1155 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1156 reg |= best_mode << regbits->midle_shift; 1157 sysc_write_sysconfig(ddata, reg); 1158 1159 set_autoidle: 1160 /* Autoidle bit must enabled separately if available */ 1161 if (regbits->autoidle_shift >= 0 && 1162 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1163 reg |= 1 << regbits->autoidle_shift; 1164 sysc_write_sysconfig(ddata, reg); 1165 } 1166 1167 error = 0; 1168 1169 save_context: 1170 /* Save context and flush posted write */ 1171 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1172 1173 if (ddata->module_enable_quirk) 1174 ddata->module_enable_quirk(ddata); 1175 1176 return error; 1177 } 1178 1179 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1180 { 1181 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1182 *best_mode = SYSC_IDLE_SMART_WKUP; 1183 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1184 *best_mode = SYSC_IDLE_SMART; 1185 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1186 *best_mode = SYSC_IDLE_FORCE; 1187 else 1188 return -EINVAL; 1189 1190 return 0; 1191 } 1192 1193 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1194 static int sysc_disable_module(struct device *dev) 1195 { 1196 struct sysc *ddata; 1197 const struct sysc_regbits *regbits; 1198 u32 reg, idlemodes, best_mode; 1199 int ret; 1200 1201 ddata = dev_get_drvdata(dev); 1202 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1203 return 0; 1204 1205 if (ddata->module_disable_quirk) 1206 ddata->module_disable_quirk(ddata); 1207 1208 regbits = ddata->cap->regbits; 1209 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1210 1211 /* Set MIDLE mode */ 1212 idlemodes = ddata->cfg.midlemodes; 1213 if (!idlemodes || regbits->midle_shift < 0) 1214 goto set_sidle; 1215 1216 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1217 if (ret) { 1218 dev_err(dev, "%s: invalid midlemode\n", __func__); 1219 return ret; 1220 } 1221 1222 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1223 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1224 best_mode = SYSC_IDLE_FORCE; 1225 1226 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1227 reg |= best_mode << regbits->midle_shift; 1228 sysc_write_sysconfig(ddata, reg); 1229 1230 set_sidle: 1231 /* Set SIDLE mode */ 1232 idlemodes = ddata->cfg.sidlemodes; 1233 if (!idlemodes || regbits->sidle_shift < 0) { 1234 ret = 0; 1235 goto save_context; 1236 } 1237 1238 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1239 best_mode = SYSC_IDLE_FORCE; 1240 } else { 1241 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1242 if (ret) { 1243 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1244 ret = -EINVAL; 1245 goto save_context; 1246 } 1247 } 1248 1249 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1250 reg |= best_mode << regbits->sidle_shift; 1251 if (regbits->autoidle_shift >= 0 && 1252 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1253 reg |= 1 << regbits->autoidle_shift; 1254 sysc_write_sysconfig(ddata, reg); 1255 1256 ret = 0; 1257 1258 save_context: 1259 /* Save context and flush posted write */ 1260 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1261 1262 return ret; 1263 } 1264 1265 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1266 struct sysc *ddata) 1267 { 1268 struct ti_sysc_platform_data *pdata; 1269 int error; 1270 1271 pdata = dev_get_platdata(ddata->dev); 1272 if (!pdata) 1273 return 0; 1274 1275 if (!pdata->idle_module) 1276 return -ENODEV; 1277 1278 error = pdata->idle_module(dev, &ddata->cookie); 1279 if (error) 1280 dev_err(dev, "%s: could not idle: %i\n", 1281 __func__, error); 1282 1283 reset_control_assert(ddata->rsts); 1284 1285 return 0; 1286 } 1287 1288 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1289 struct sysc *ddata) 1290 { 1291 struct ti_sysc_platform_data *pdata; 1292 int error; 1293 1294 pdata = dev_get_platdata(ddata->dev); 1295 if (!pdata) 1296 return 0; 1297 1298 if (!pdata->enable_module) 1299 return -ENODEV; 1300 1301 error = pdata->enable_module(dev, &ddata->cookie); 1302 if (error) 1303 dev_err(dev, "%s: could not enable: %i\n", 1304 __func__, error); 1305 1306 reset_control_deassert(ddata->rsts); 1307 1308 return 0; 1309 } 1310 1311 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1312 { 1313 struct sysc *ddata; 1314 int error = 0; 1315 1316 ddata = dev_get_drvdata(dev); 1317 1318 if (!ddata->enabled) 1319 return 0; 1320 1321 sysc_clkdm_deny_idle(ddata); 1322 1323 if (ddata->legacy_mode) { 1324 error = sysc_runtime_suspend_legacy(dev, ddata); 1325 if (error) 1326 goto err_allow_idle; 1327 } else { 1328 error = sysc_disable_module(dev); 1329 if (error) 1330 goto err_allow_idle; 1331 } 1332 1333 sysc_disable_main_clocks(ddata); 1334 1335 if (sysc_opt_clks_needed(ddata)) 1336 sysc_disable_opt_clocks(ddata); 1337 1338 ddata->enabled = false; 1339 1340 err_allow_idle: 1341 sysc_clkdm_allow_idle(ddata); 1342 1343 reset_control_assert(ddata->rsts); 1344 1345 return error; 1346 } 1347 1348 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1349 { 1350 struct sysc *ddata; 1351 int error = 0; 1352 1353 ddata = dev_get_drvdata(dev); 1354 1355 if (ddata->enabled) 1356 return 0; 1357 1358 1359 sysc_clkdm_deny_idle(ddata); 1360 1361 if (sysc_opt_clks_needed(ddata)) { 1362 error = sysc_enable_opt_clocks(ddata); 1363 if (error) 1364 goto err_allow_idle; 1365 } 1366 1367 error = sysc_enable_main_clocks(ddata); 1368 if (error) 1369 goto err_opt_clocks; 1370 1371 reset_control_deassert(ddata->rsts); 1372 1373 if (ddata->legacy_mode) { 1374 error = sysc_runtime_resume_legacy(dev, ddata); 1375 if (error) 1376 goto err_main_clocks; 1377 } else { 1378 error = sysc_enable_module(dev); 1379 if (error) 1380 goto err_main_clocks; 1381 } 1382 1383 ddata->enabled = true; 1384 1385 sysc_clkdm_allow_idle(ddata); 1386 1387 return 0; 1388 1389 err_main_clocks: 1390 sysc_disable_main_clocks(ddata); 1391 err_opt_clocks: 1392 if (sysc_opt_clks_needed(ddata)) 1393 sysc_disable_opt_clocks(ddata); 1394 err_allow_idle: 1395 sysc_clkdm_allow_idle(ddata); 1396 1397 return error; 1398 } 1399 1400 /* 1401 * Checks if device context was lost. Assumes the sysconfig register value 1402 * after lost context is different from the configured value. Only works for 1403 * enabled devices. 1404 * 1405 * Eventually we may want to also add support to using the context lost 1406 * registers that some SoCs have. 1407 */ 1408 static int sysc_check_context(struct sysc *ddata) 1409 { 1410 u32 reg; 1411 1412 if (!ddata->enabled) 1413 return -ENODATA; 1414 1415 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1416 if (reg == ddata->sysconfig) 1417 return 0; 1418 1419 return -EACCES; 1420 } 1421 1422 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1423 { 1424 struct device *dev = ddata->dev; 1425 int error; 1426 1427 if (ddata->enabled) { 1428 /* Nothing to do if enabled and context not lost */ 1429 error = sysc_check_context(ddata); 1430 if (!error) 1431 return 0; 1432 1433 /* Disable target module if it is enabled */ 1434 error = sysc_runtime_suspend(dev); 1435 if (error) 1436 dev_warn(dev, "reinit suspend failed: %i\n", error); 1437 } 1438 1439 /* Enable target module */ 1440 error = sysc_runtime_resume(dev); 1441 if (error) 1442 dev_warn(dev, "reinit resume failed: %i\n", error); 1443 1444 /* Some modules like am335x gpmc need reset and restore of sysconfig */ 1445 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) { 1446 error = sysc_reset(ddata); 1447 if (error) 1448 dev_warn(dev, "reinit reset failed: %i\n", error); 1449 1450 sysc_write_sysconfig(ddata, ddata->sysconfig); 1451 } 1452 1453 if (leave_enabled) 1454 return error; 1455 1456 /* Disable target module if no leave_enabled was set */ 1457 error = sysc_runtime_suspend(dev); 1458 if (error) 1459 dev_warn(dev, "reinit suspend failed: %i\n", error); 1460 1461 return error; 1462 } 1463 1464 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1465 { 1466 struct sysc *ddata; 1467 1468 ddata = dev_get_drvdata(dev); 1469 1470 if (ddata->cfg.quirks & 1471 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1472 return 0; 1473 1474 if (!ddata->enabled) 1475 return 0; 1476 1477 ddata->needs_resume = 1; 1478 1479 return sysc_runtime_suspend(dev); 1480 } 1481 1482 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1483 { 1484 struct sysc *ddata; 1485 int error = 0; 1486 1487 ddata = dev_get_drvdata(dev); 1488 1489 if (ddata->cfg.quirks & 1490 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1491 return 0; 1492 1493 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1494 error = sysc_reinit_module(ddata, ddata->needs_resume); 1495 if (error) 1496 dev_warn(dev, "noirq_resume failed: %i\n", error); 1497 } else if (ddata->needs_resume) { 1498 error = sysc_runtime_resume(dev); 1499 if (error) 1500 dev_warn(dev, "noirq_resume failed: %i\n", error); 1501 } 1502 1503 ddata->needs_resume = 0; 1504 1505 return error; 1506 } 1507 1508 static const struct dev_pm_ops sysc_pm_ops = { 1509 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1510 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1511 sysc_runtime_resume, 1512 NULL) 1513 }; 1514 1515 /* Module revision register based quirks */ 1516 struct sysc_revision_quirk { 1517 const char *name; 1518 u32 base; 1519 int rev_offset; 1520 int sysc_offset; 1521 int syss_offset; 1522 u32 revision; 1523 u32 revision_mask; 1524 u32 quirks; 1525 }; 1526 1527 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1528 optrev_val, optrevmask, optquirkmask) \ 1529 { \ 1530 .name = (optname), \ 1531 .base = (optbase), \ 1532 .rev_offset = (optrev), \ 1533 .sysc_offset = (optsysc), \ 1534 .syss_offset = (optsyss), \ 1535 .revision = (optrev_val), \ 1536 .revision_mask = (optrevmask), \ 1537 .quirks = (optquirkmask), \ 1538 } 1539 1540 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1541 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1542 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1543 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1544 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1545 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1546 /* Uarts on omap4 and later */ 1547 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1548 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1549 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1550 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1551 1552 /* Quirks that need to be set based on the module address */ 1553 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1554 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1555 SYSC_QUIRK_SWSUP_SIDLE), 1556 1557 /* Quirks that need to be set based on detected module */ 1558 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1559 SYSC_MODULE_QUIRK_AESS), 1560 /* Errata i893 handling for dra7 dcan1 and 2 */ 1561 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1562 SYSC_QUIRK_CLKDM_NOAUTO), 1563 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1564 SYSC_QUIRK_CLKDM_NOAUTO), 1565 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1566 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1567 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1568 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1569 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1570 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1571 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1572 SYSC_QUIRK_CLKDM_NOAUTO), 1573 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1574 SYSC_QUIRK_CLKDM_NOAUTO), 1575 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1576 SYSC_QUIRK_OPT_CLKS_IN_RESET), 1577 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1578 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST | 1579 SYSC_QUIRK_GPMC_DEBUG), 1580 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1581 SYSC_QUIRK_OPT_CLKS_NEEDED), 1582 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1583 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1584 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1585 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1586 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1587 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1588 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1589 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1590 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1591 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1592 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1593 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1594 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1595 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1596 SYSC_MODULE_QUIRK_SGX), 1597 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1598 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1599 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 1600 SYSC_QUIRK_SWSUP_SIDLE), 1601 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1602 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1603 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1604 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1605 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1606 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1607 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1608 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1609 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1610 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1611 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1612 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1613 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033, 1614 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1615 SYSC_MODULE_QUIRK_OTG), 1616 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040, 1617 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1618 SYSC_MODULE_QUIRK_OTG), 1619 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1620 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1621 SYSC_MODULE_QUIRK_OTG), 1622 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1623 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1624 SYSC_QUIRK_REINIT_ON_CTX_LOST), 1625 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1626 SYSC_MODULE_QUIRK_WDT), 1627 /* PRUSS on am3, am4 and am5 */ 1628 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1629 SYSC_MODULE_QUIRK_PRUSS), 1630 /* Watchdog on am3 and am4 */ 1631 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1632 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1633 1634 #ifdef DEBUG 1635 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1636 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1637 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1638 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1639 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1640 0xffff00f0, 0), 1641 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1642 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1643 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1644 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1645 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1646 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1647 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1648 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1649 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1650 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1651 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1652 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1653 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1654 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1655 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1656 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1657 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1658 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1659 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1660 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1661 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1662 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1663 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1664 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1665 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1666 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1667 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1668 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1669 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1670 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1671 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1672 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1673 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1674 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1675 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1676 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1677 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1678 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1679 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1680 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1681 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1682 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1683 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1684 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1685 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1686 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1687 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1688 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1689 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0), 1690 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1691 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1692 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), 1693 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), 1694 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1695 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1696 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1697 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1698 /* Some timers on omap4 and later */ 1699 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1700 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1701 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1702 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1703 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1704 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1705 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1706 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1707 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1708 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1709 #endif 1710 }; 1711 1712 /* 1713 * Early quirks based on module base and register offsets only that are 1714 * needed before the module revision can be read 1715 */ 1716 static void sysc_init_early_quirks(struct sysc *ddata) 1717 { 1718 const struct sysc_revision_quirk *q; 1719 int i; 1720 1721 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1722 q = &sysc_revision_quirks[i]; 1723 1724 if (!q->base) 1725 continue; 1726 1727 if (q->base != ddata->module_pa) 1728 continue; 1729 1730 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1731 continue; 1732 1733 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1734 continue; 1735 1736 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1737 continue; 1738 1739 ddata->name = q->name; 1740 ddata->cfg.quirks |= q->quirks; 1741 } 1742 } 1743 1744 /* Quirks that also consider the revision register value */ 1745 static void sysc_init_revision_quirks(struct sysc *ddata) 1746 { 1747 const struct sysc_revision_quirk *q; 1748 int i; 1749 1750 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1751 q = &sysc_revision_quirks[i]; 1752 1753 if (q->base && q->base != ddata->module_pa) 1754 continue; 1755 1756 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1757 continue; 1758 1759 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1760 continue; 1761 1762 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1763 continue; 1764 1765 if (q->revision == ddata->revision || 1766 (q->revision & q->revision_mask) == 1767 (ddata->revision & q->revision_mask)) { 1768 ddata->name = q->name; 1769 ddata->cfg.quirks |= q->quirks; 1770 } 1771 } 1772 } 1773 1774 /* 1775 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1776 * enabled DSS interrupts. Eventually we may be able to do this on 1777 * dispc init rather than top-level DSS init. 1778 */ 1779 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1780 bool disable) 1781 { 1782 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1783 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1784 int manager_count; 1785 bool framedonetv_irq = true; 1786 u32 val, irq_mask = 0; 1787 1788 switch (sysc_soc->soc) { 1789 case SOC_2420 ... SOC_3630: 1790 manager_count = 2; 1791 framedonetv_irq = false; 1792 break; 1793 case SOC_4430 ... SOC_4470: 1794 manager_count = 3; 1795 break; 1796 case SOC_5430: 1797 case SOC_DRA7: 1798 manager_count = 4; 1799 break; 1800 case SOC_AM4: 1801 manager_count = 1; 1802 framedonetv_irq = false; 1803 break; 1804 case SOC_UNKNOWN: 1805 default: 1806 return 0; 1807 } 1808 1809 /* Remap the whole module range to be able to reset dispc outputs */ 1810 devm_iounmap(ddata->dev, ddata->module_va); 1811 ddata->module_va = devm_ioremap(ddata->dev, 1812 ddata->module_pa, 1813 ddata->module_size); 1814 if (!ddata->module_va) 1815 return -EIO; 1816 1817 /* DISP_CONTROL */ 1818 val = sysc_read(ddata, dispc_offset + 0x40); 1819 lcd_en = val & lcd_en_mask; 1820 digit_en = val & digit_en_mask; 1821 if (lcd_en) 1822 irq_mask |= BIT(0); /* FRAMEDONE */ 1823 if (digit_en) { 1824 if (framedonetv_irq) 1825 irq_mask |= BIT(24); /* FRAMEDONETV */ 1826 else 1827 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1828 } 1829 if (disable & (lcd_en | digit_en)) 1830 sysc_write(ddata, dispc_offset + 0x40, 1831 val & ~(lcd_en_mask | digit_en_mask)); 1832 1833 if (manager_count <= 2) 1834 return irq_mask; 1835 1836 /* DISPC_CONTROL2 */ 1837 val = sysc_read(ddata, dispc_offset + 0x238); 1838 lcd2_en = val & lcd_en_mask; 1839 if (lcd2_en) 1840 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1841 if (disable && lcd2_en) 1842 sysc_write(ddata, dispc_offset + 0x238, 1843 val & ~lcd_en_mask); 1844 1845 if (manager_count <= 3) 1846 return irq_mask; 1847 1848 /* DISPC_CONTROL3 */ 1849 val = sysc_read(ddata, dispc_offset + 0x848); 1850 lcd3_en = val & lcd_en_mask; 1851 if (lcd3_en) 1852 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1853 if (disable && lcd3_en) 1854 sysc_write(ddata, dispc_offset + 0x848, 1855 val & ~lcd_en_mask); 1856 1857 return irq_mask; 1858 } 1859 1860 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1861 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1862 { 1863 const int dispc_offset = 0x1000; 1864 int error; 1865 u32 irq_mask, val; 1866 1867 /* Get enabled outputs */ 1868 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1869 if (!irq_mask) 1870 return; 1871 1872 /* Clear IRQSTATUS */ 1873 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1874 1875 /* Disable outputs */ 1876 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1877 1878 /* Poll IRQSTATUS */ 1879 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1880 val, val != irq_mask, 100, 50); 1881 if (error) 1882 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1883 __func__, val, irq_mask); 1884 1885 if (sysc_soc->soc == SOC_3430) { 1886 /* Clear DSS_SDI_CONTROL */ 1887 sysc_write(ddata, 0x44, 0); 1888 1889 /* Clear DSS_PLL_CONTROL */ 1890 sysc_write(ddata, 0x48, 0); 1891 } 1892 1893 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1894 sysc_write(ddata, 0x40, 0); 1895 } 1896 1897 /* 1-wire needs module's internal clocks enabled for reset */ 1898 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1899 { 1900 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1901 u16 val; 1902 1903 val = sysc_read(ddata, offset); 1904 val |= BIT(5); 1905 sysc_write(ddata, offset, val); 1906 } 1907 1908 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1909 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1910 { 1911 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1912 1913 sysc_write(ddata, offset, 1); 1914 } 1915 1916 /* I2C needs to be disabled for reset */ 1917 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1918 { 1919 int offset; 1920 u16 val; 1921 1922 /* I2C_CON, omap2/3 is different from omap4 and later */ 1923 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1924 offset = 0x24; 1925 else 1926 offset = 0xa4; 1927 1928 /* I2C_EN */ 1929 val = sysc_read(ddata, offset); 1930 if (enable) 1931 val |= BIT(15); 1932 else 1933 val &= ~BIT(15); 1934 sysc_write(ddata, offset, val); 1935 } 1936 1937 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1938 { 1939 sysc_clk_quirk_i2c(ddata, false); 1940 } 1941 1942 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1943 { 1944 sysc_clk_quirk_i2c(ddata, true); 1945 } 1946 1947 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1948 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1949 { 1950 u32 val, kick0_val = 0, kick1_val = 0; 1951 unsigned long flags; 1952 int error; 1953 1954 if (!lock) { 1955 kick0_val = 0x83e70b13; 1956 kick1_val = 0x95a4f1e0; 1957 } 1958 1959 local_irq_save(flags); 1960 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1961 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1962 !(val & BIT(0)), 100, 50); 1963 if (error) 1964 dev_warn(ddata->dev, "rtc busy timeout\n"); 1965 /* Now we have ~15 microseconds to read/write various registers */ 1966 sysc_write(ddata, 0x6c, kick0_val); 1967 sysc_write(ddata, 0x70, kick1_val); 1968 local_irq_restore(flags); 1969 } 1970 1971 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1972 { 1973 sysc_quirk_rtc(ddata, false); 1974 } 1975 1976 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1977 { 1978 sysc_quirk_rtc(ddata, true); 1979 } 1980 1981 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */ 1982 static void sysc_module_enable_quirk_otg(struct sysc *ddata) 1983 { 1984 int offset = 0x414; /* OTG_FORCESTDBY */ 1985 1986 sysc_write(ddata, offset, 0); 1987 } 1988 1989 static void sysc_module_disable_quirk_otg(struct sysc *ddata) 1990 { 1991 int offset = 0x414; /* OTG_FORCESTDBY */ 1992 u32 val = BIT(0); /* ENABLEFORCE */ 1993 1994 sysc_write(ddata, offset, val); 1995 } 1996 1997 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1998 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1999 { 2000 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 2001 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 2002 2003 sysc_write(ddata, offset, val); 2004 } 2005 2006 /* Watchdog timer needs a disable sequence after reset */ 2007 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 2008 { 2009 int wps, spr, error; 2010 u32 val; 2011 2012 wps = 0x34; 2013 spr = 0x48; 2014 2015 sysc_write(ddata, spr, 0xaaaa); 2016 error = readl_poll_timeout(ddata->module_va + wps, val, 2017 !(val & 0x10), 100, 2018 MAX_MODULE_SOFTRESET_WAIT); 2019 if (error) 2020 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 2021 2022 sysc_write(ddata, spr, 0x5555); 2023 error = readl_poll_timeout(ddata->module_va + wps, val, 2024 !(val & 0x10), 100, 2025 MAX_MODULE_SOFTRESET_WAIT); 2026 if (error) 2027 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 2028 } 2029 2030 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 2031 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 2032 { 2033 u32 reg; 2034 2035 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 2036 reg |= SYSC_PRUSS_STANDBY_INIT; 2037 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 2038 } 2039 2040 static void sysc_init_module_quirks(struct sysc *ddata) 2041 { 2042 if (ddata->legacy_mode || !ddata->name) 2043 return; 2044 2045 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 2046 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 2047 2048 return; 2049 } 2050 2051 #ifdef CONFIG_OMAP_GPMC_DEBUG 2052 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 2053 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 2054 2055 return; 2056 } 2057 #endif 2058 2059 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 2060 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 2061 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 2062 2063 return; 2064 } 2065 2066 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 2067 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 2068 2069 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 2070 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 2071 2072 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 2073 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 2074 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 2075 2076 return; 2077 } 2078 2079 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) { 2080 ddata->module_enable_quirk = sysc_module_enable_quirk_otg; 2081 ddata->module_disable_quirk = sysc_module_disable_quirk_otg; 2082 } 2083 2084 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 2085 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 2086 2087 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 2088 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 2089 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 2090 } 2091 2092 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 2093 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 2094 } 2095 2096 static int sysc_clockdomain_init(struct sysc *ddata) 2097 { 2098 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2099 struct clk *fck = NULL, *ick = NULL; 2100 int error; 2101 2102 if (!pdata || !pdata->init_clockdomain) 2103 return 0; 2104 2105 switch (ddata->nr_clocks) { 2106 case 2: 2107 ick = ddata->clocks[SYSC_ICK]; 2108 fallthrough; 2109 case 1: 2110 fck = ddata->clocks[SYSC_FCK]; 2111 break; 2112 case 0: 2113 return 0; 2114 } 2115 2116 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 2117 if (!error || error == -ENODEV) 2118 return 0; 2119 2120 return error; 2121 } 2122 2123 /* 2124 * Note that pdata->init_module() typically does a reset first. After 2125 * pdata->init_module() is done, PM runtime can be used for the interconnect 2126 * target module. 2127 */ 2128 static int sysc_legacy_init(struct sysc *ddata) 2129 { 2130 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2131 int error; 2132 2133 if (!pdata || !pdata->init_module) 2134 return 0; 2135 2136 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2137 if (error == -EEXIST) 2138 error = 0; 2139 2140 return error; 2141 } 2142 2143 /* 2144 * Note that the caller must ensure the interconnect target module is enabled 2145 * before calling reset. Otherwise reset will not complete. 2146 */ 2147 static int sysc_reset(struct sysc *ddata) 2148 { 2149 int sysc_offset, sysc_val, error; 2150 u32 sysc_mask; 2151 2152 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2153 2154 if (ddata->legacy_mode || 2155 ddata->cap->regbits->srst_shift < 0 || 2156 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 2157 return 0; 2158 2159 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2160 2161 if (ddata->pre_reset_quirk) 2162 ddata->pre_reset_quirk(ddata); 2163 2164 if (sysc_offset >= 0) { 2165 sysc_val = sysc_read_sysconfig(ddata); 2166 sysc_val |= sysc_mask; 2167 sysc_write(ddata, sysc_offset, sysc_val); 2168 } 2169 2170 if (ddata->cfg.srst_udelay) 2171 usleep_range(ddata->cfg.srst_udelay, 2172 ddata->cfg.srst_udelay * 2); 2173 2174 if (ddata->post_reset_quirk) 2175 ddata->post_reset_quirk(ddata); 2176 2177 error = sysc_wait_softreset(ddata); 2178 if (error) 2179 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2180 2181 if (ddata->reset_done_quirk) 2182 ddata->reset_done_quirk(ddata); 2183 2184 return error; 2185 } 2186 2187 /* 2188 * At this point the module is configured enough to read the revision but 2189 * module may not be completely configured yet to use PM runtime. Enable 2190 * all clocks directly during init to configure the quirks needed for PM 2191 * runtime based on the revision register. 2192 */ 2193 static int sysc_init_module(struct sysc *ddata) 2194 { 2195 bool rstctrl_deasserted = false; 2196 int error = 0; 2197 2198 error = sysc_clockdomain_init(ddata); 2199 if (error) 2200 return error; 2201 2202 sysc_clkdm_deny_idle(ddata); 2203 2204 /* 2205 * Always enable clocks. The bootloader may or may not have enabled 2206 * the related clocks. 2207 */ 2208 error = sysc_enable_opt_clocks(ddata); 2209 if (error) 2210 return error; 2211 2212 error = sysc_enable_main_clocks(ddata); 2213 if (error) 2214 goto err_opt_clocks; 2215 2216 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2217 error = reset_control_deassert(ddata->rsts); 2218 if (error) 2219 goto err_main_clocks; 2220 rstctrl_deasserted = true; 2221 } 2222 2223 ddata->revision = sysc_read_revision(ddata); 2224 sysc_init_revision_quirks(ddata); 2225 sysc_init_module_quirks(ddata); 2226 2227 if (ddata->legacy_mode) { 2228 error = sysc_legacy_init(ddata); 2229 if (error) 2230 goto err_main_clocks; 2231 } 2232 2233 if (!ddata->legacy_mode) { 2234 error = sysc_enable_module(ddata->dev); 2235 if (error) 2236 goto err_main_clocks; 2237 } 2238 2239 error = sysc_reset(ddata); 2240 if (error) 2241 dev_err(ddata->dev, "Reset failed with %d\n", error); 2242 2243 if (error && !ddata->legacy_mode) 2244 sysc_disable_module(ddata->dev); 2245 2246 err_main_clocks: 2247 if (error) 2248 sysc_disable_main_clocks(ddata); 2249 err_opt_clocks: 2250 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2251 if (error) { 2252 sysc_disable_opt_clocks(ddata); 2253 sysc_clkdm_allow_idle(ddata); 2254 } 2255 2256 if (error && rstctrl_deasserted && 2257 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2258 reset_control_assert(ddata->rsts); 2259 2260 return error; 2261 } 2262 2263 static int sysc_init_sysc_mask(struct sysc *ddata) 2264 { 2265 struct device_node *np = ddata->dev->of_node; 2266 int error; 2267 u32 val; 2268 2269 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2270 if (error) 2271 return 0; 2272 2273 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2274 2275 return 0; 2276 } 2277 2278 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2279 const char *name) 2280 { 2281 struct device_node *np = ddata->dev->of_node; 2282 struct property *prop; 2283 const __be32 *p; 2284 u32 val; 2285 2286 of_property_for_each_u32(np, name, prop, p, val) { 2287 if (val >= SYSC_NR_IDLEMODES) { 2288 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2289 return -EINVAL; 2290 } 2291 *idlemodes |= (1 << val); 2292 } 2293 2294 return 0; 2295 } 2296 2297 static int sysc_init_idlemodes(struct sysc *ddata) 2298 { 2299 int error; 2300 2301 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2302 "ti,sysc-midle"); 2303 if (error) 2304 return error; 2305 2306 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2307 "ti,sysc-sidle"); 2308 if (error) 2309 return error; 2310 2311 return 0; 2312 } 2313 2314 /* 2315 * Only some devices on omap4 and later have SYSCONFIG reset done 2316 * bit. We can detect this if there is no SYSSTATUS at all, or the 2317 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2318 * have multiple bits for the child devices like OHCI and EHCI. 2319 * Depends on SYSC being parsed first. 2320 */ 2321 static int sysc_init_syss_mask(struct sysc *ddata) 2322 { 2323 struct device_node *np = ddata->dev->of_node; 2324 int error; 2325 u32 val; 2326 2327 error = of_property_read_u32(np, "ti,syss-mask", &val); 2328 if (error) { 2329 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2330 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2331 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2332 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2333 2334 return 0; 2335 } 2336 2337 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2338 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2339 2340 ddata->cfg.syss_mask = val; 2341 2342 return 0; 2343 } 2344 2345 /* 2346 * Many child device drivers need to have fck and opt clocks available 2347 * to get the clock rate for device internal configuration etc. 2348 */ 2349 static int sysc_child_add_named_clock(struct sysc *ddata, 2350 struct device *child, 2351 const char *name) 2352 { 2353 struct clk *clk; 2354 struct clk_lookup *l; 2355 int error = 0; 2356 2357 if (!name) 2358 return 0; 2359 2360 clk = clk_get(child, name); 2361 if (!IS_ERR(clk)) { 2362 error = -EEXIST; 2363 goto put_clk; 2364 } 2365 2366 clk = clk_get(ddata->dev, name); 2367 if (IS_ERR(clk)) 2368 return -ENODEV; 2369 2370 l = clkdev_create(clk, name, dev_name(child)); 2371 if (!l) 2372 error = -ENOMEM; 2373 put_clk: 2374 clk_put(clk); 2375 2376 return error; 2377 } 2378 2379 static int sysc_child_add_clocks(struct sysc *ddata, 2380 struct device *child) 2381 { 2382 int i, error; 2383 2384 for (i = 0; i < ddata->nr_clocks; i++) { 2385 error = sysc_child_add_named_clock(ddata, 2386 child, 2387 ddata->clock_roles[i]); 2388 if (error && error != -EEXIST) { 2389 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2390 ddata->clock_roles[i], error); 2391 2392 return error; 2393 } 2394 } 2395 2396 return 0; 2397 } 2398 2399 static struct device_type sysc_device_type = { 2400 }; 2401 2402 static struct sysc *sysc_child_to_parent(struct device *dev) 2403 { 2404 struct device *parent = dev->parent; 2405 2406 if (!parent || parent->type != &sysc_device_type) 2407 return NULL; 2408 2409 return dev_get_drvdata(parent); 2410 } 2411 2412 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2413 { 2414 struct sysc *ddata; 2415 int error; 2416 2417 ddata = sysc_child_to_parent(dev); 2418 2419 error = pm_generic_runtime_suspend(dev); 2420 if (error) 2421 return error; 2422 2423 if (!ddata->enabled) 2424 return 0; 2425 2426 return sysc_runtime_suspend(ddata->dev); 2427 } 2428 2429 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2430 { 2431 struct sysc *ddata; 2432 int error; 2433 2434 ddata = sysc_child_to_parent(dev); 2435 2436 if (!ddata->enabled) { 2437 error = sysc_runtime_resume(ddata->dev); 2438 if (error < 0) 2439 dev_err(ddata->dev, 2440 "%s error: %i\n", __func__, error); 2441 } 2442 2443 return pm_generic_runtime_resume(dev); 2444 } 2445 2446 #ifdef CONFIG_PM_SLEEP 2447 static int sysc_child_suspend_noirq(struct device *dev) 2448 { 2449 struct sysc *ddata; 2450 int error; 2451 2452 ddata = sysc_child_to_parent(dev); 2453 2454 dev_dbg(ddata->dev, "%s %s\n", __func__, 2455 ddata->name ? ddata->name : ""); 2456 2457 error = pm_generic_suspend_noirq(dev); 2458 if (error) { 2459 dev_err(dev, "%s error at %i: %i\n", 2460 __func__, __LINE__, error); 2461 2462 return error; 2463 } 2464 2465 if (!pm_runtime_status_suspended(dev)) { 2466 error = pm_generic_runtime_suspend(dev); 2467 if (error) { 2468 dev_dbg(dev, "%s busy at %i: %i\n", 2469 __func__, __LINE__, error); 2470 2471 return 0; 2472 } 2473 2474 error = sysc_runtime_suspend(ddata->dev); 2475 if (error) { 2476 dev_err(dev, "%s error at %i: %i\n", 2477 __func__, __LINE__, error); 2478 2479 return error; 2480 } 2481 2482 ddata->child_needs_resume = true; 2483 } 2484 2485 return 0; 2486 } 2487 2488 static int sysc_child_resume_noirq(struct device *dev) 2489 { 2490 struct sysc *ddata; 2491 int error; 2492 2493 ddata = sysc_child_to_parent(dev); 2494 2495 dev_dbg(ddata->dev, "%s %s\n", __func__, 2496 ddata->name ? ddata->name : ""); 2497 2498 if (ddata->child_needs_resume) { 2499 ddata->child_needs_resume = false; 2500 2501 error = sysc_runtime_resume(ddata->dev); 2502 if (error) 2503 dev_err(ddata->dev, 2504 "%s runtime resume error: %i\n", 2505 __func__, error); 2506 2507 error = pm_generic_runtime_resume(dev); 2508 if (error) 2509 dev_err(ddata->dev, 2510 "%s generic runtime resume: %i\n", 2511 __func__, error); 2512 } 2513 2514 return pm_generic_resume_noirq(dev); 2515 } 2516 #endif 2517 2518 static struct dev_pm_domain sysc_child_pm_domain = { 2519 .ops = { 2520 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2521 sysc_child_runtime_resume, 2522 NULL) 2523 USE_PLATFORM_PM_SLEEP_OPS 2524 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2525 sysc_child_resume_noirq) 2526 } 2527 }; 2528 2529 /* Caller needs to take list_lock if ever used outside of cpu_pm */ 2530 static void sysc_reinit_modules(struct sysc_soc_info *soc) 2531 { 2532 struct sysc_module *module; 2533 struct list_head *pos; 2534 struct sysc *ddata; 2535 2536 list_for_each(pos, &sysc_soc->restored_modules) { 2537 module = list_entry(pos, struct sysc_module, node); 2538 ddata = module->ddata; 2539 sysc_reinit_module(ddata, ddata->enabled); 2540 } 2541 } 2542 2543 /** 2544 * sysc_context_notifier - optionally reset and restore module after idle 2545 * @nb: notifier block 2546 * @cmd: unused 2547 * @v: unused 2548 * 2549 * Some interconnect target modules need to be restored, or reset and restored 2550 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x 2551 * OTG and GPMC target modules even if the modules are unused. 2552 */ 2553 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, 2554 void *v) 2555 { 2556 struct sysc_soc_info *soc; 2557 2558 soc = container_of(nb, struct sysc_soc_info, nb); 2559 2560 switch (cmd) { 2561 case CPU_CLUSTER_PM_ENTER: 2562 break; 2563 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2564 break; 2565 case CPU_CLUSTER_PM_EXIT: 2566 sysc_reinit_modules(soc); 2567 break; 2568 } 2569 2570 return NOTIFY_OK; 2571 } 2572 2573 /** 2574 * sysc_add_restored - optionally add reset and restore quirk hanlling 2575 * @ddata: device data 2576 */ 2577 static void sysc_add_restored(struct sysc *ddata) 2578 { 2579 struct sysc_module *restored_module; 2580 2581 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); 2582 if (!restored_module) 2583 return; 2584 2585 restored_module->ddata = ddata; 2586 2587 mutex_lock(&sysc_soc->list_lock); 2588 2589 list_add(&restored_module->node, &sysc_soc->restored_modules); 2590 2591 if (sysc_soc->nb.notifier_call) 2592 goto out_unlock; 2593 2594 sysc_soc->nb.notifier_call = sysc_context_notifier; 2595 cpu_pm_register_notifier(&sysc_soc->nb); 2596 2597 out_unlock: 2598 mutex_unlock(&sysc_soc->list_lock); 2599 } 2600 2601 /** 2602 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2603 * @ddata: device driver data 2604 * @child: child device driver 2605 * 2606 * Allow idle for child devices as done with _od_runtime_suspend(). 2607 * Otherwise many child devices will not idle because of the permanent 2608 * parent usecount set in pm_runtime_irq_safe(). 2609 * 2610 * Note that the long term solution is to just modify the child device 2611 * drivers to not set pm_runtime_irq_safe() and then this can be just 2612 * dropped. 2613 */ 2614 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2615 { 2616 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2617 dev_pm_domain_set(child, &sysc_child_pm_domain); 2618 } 2619 2620 static int sysc_notifier_call(struct notifier_block *nb, 2621 unsigned long event, void *device) 2622 { 2623 struct device *dev = device; 2624 struct sysc *ddata; 2625 int error; 2626 2627 ddata = sysc_child_to_parent(dev); 2628 if (!ddata) 2629 return NOTIFY_DONE; 2630 2631 switch (event) { 2632 case BUS_NOTIFY_ADD_DEVICE: 2633 error = sysc_child_add_clocks(ddata, dev); 2634 if (error) 2635 return error; 2636 sysc_legacy_idle_quirk(ddata, dev); 2637 break; 2638 default: 2639 break; 2640 } 2641 2642 return NOTIFY_DONE; 2643 } 2644 2645 static struct notifier_block sysc_nb = { 2646 .notifier_call = sysc_notifier_call, 2647 }; 2648 2649 /* Device tree configured quirks */ 2650 struct sysc_dts_quirk { 2651 const char *name; 2652 u32 mask; 2653 }; 2654 2655 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2656 { .name = "ti,no-idle-on-init", 2657 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2658 { .name = "ti,no-reset-on-init", 2659 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2660 { .name = "ti,no-idle", 2661 .mask = SYSC_QUIRK_NO_IDLE, }, 2662 }; 2663 2664 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2665 bool is_child) 2666 { 2667 const struct property *prop; 2668 int i, len; 2669 2670 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2671 const char *name = sysc_dts_quirks[i].name; 2672 2673 prop = of_get_property(np, name, &len); 2674 if (!prop) 2675 continue; 2676 2677 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2678 if (is_child) { 2679 dev_warn(ddata->dev, 2680 "dts flag should be at module level for %s\n", 2681 name); 2682 } 2683 } 2684 } 2685 2686 static int sysc_init_dts_quirks(struct sysc *ddata) 2687 { 2688 struct device_node *np = ddata->dev->of_node; 2689 int error; 2690 u32 val; 2691 2692 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2693 2694 sysc_parse_dts_quirks(ddata, np, false); 2695 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2696 if (!error) { 2697 if (val > 255) { 2698 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2699 val); 2700 } 2701 2702 ddata->cfg.srst_udelay = (u8)val; 2703 } 2704 2705 return 0; 2706 } 2707 2708 static void sysc_unprepare(struct sysc *ddata) 2709 { 2710 int i; 2711 2712 if (!ddata->clocks) 2713 return; 2714 2715 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2716 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2717 clk_unprepare(ddata->clocks[i]); 2718 } 2719 } 2720 2721 /* 2722 * Common sysc register bits found on omap2, also known as type1 2723 */ 2724 static const struct sysc_regbits sysc_regbits_omap2 = { 2725 .dmadisable_shift = -ENODEV, 2726 .midle_shift = 12, 2727 .sidle_shift = 3, 2728 .clkact_shift = 8, 2729 .emufree_shift = 5, 2730 .enwkup_shift = 2, 2731 .srst_shift = 1, 2732 .autoidle_shift = 0, 2733 }; 2734 2735 static const struct sysc_capabilities sysc_omap2 = { 2736 .type = TI_SYSC_OMAP2, 2737 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2738 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2739 SYSC_OMAP2_AUTOIDLE, 2740 .regbits = &sysc_regbits_omap2, 2741 }; 2742 2743 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2744 static const struct sysc_capabilities sysc_omap2_timer = { 2745 .type = TI_SYSC_OMAP2_TIMER, 2746 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2747 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2748 SYSC_OMAP2_AUTOIDLE, 2749 .regbits = &sysc_regbits_omap2, 2750 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2751 }; 2752 2753 /* 2754 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2755 * with different sidle position 2756 */ 2757 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2758 .dmadisable_shift = -ENODEV, 2759 .midle_shift = -ENODEV, 2760 .sidle_shift = 4, 2761 .clkact_shift = -ENODEV, 2762 .enwkup_shift = -ENODEV, 2763 .srst_shift = 1, 2764 .autoidle_shift = 0, 2765 .emufree_shift = -ENODEV, 2766 }; 2767 2768 static const struct sysc_capabilities sysc_omap3_sham = { 2769 .type = TI_SYSC_OMAP3_SHAM, 2770 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2771 .regbits = &sysc_regbits_omap3_sham, 2772 }; 2773 2774 /* 2775 * AES register bits found on omap3 and later, a variant of 2776 * sysc_regbits_omap2 with different sidle position 2777 */ 2778 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2779 .dmadisable_shift = -ENODEV, 2780 .midle_shift = -ENODEV, 2781 .sidle_shift = 6, 2782 .clkact_shift = -ENODEV, 2783 .enwkup_shift = -ENODEV, 2784 .srst_shift = 1, 2785 .autoidle_shift = 0, 2786 .emufree_shift = -ENODEV, 2787 }; 2788 2789 static const struct sysc_capabilities sysc_omap3_aes = { 2790 .type = TI_SYSC_OMAP3_AES, 2791 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2792 .regbits = &sysc_regbits_omap3_aes, 2793 }; 2794 2795 /* 2796 * Common sysc register bits found on omap4, also known as type2 2797 */ 2798 static const struct sysc_regbits sysc_regbits_omap4 = { 2799 .dmadisable_shift = 16, 2800 .midle_shift = 4, 2801 .sidle_shift = 2, 2802 .clkact_shift = -ENODEV, 2803 .enwkup_shift = -ENODEV, 2804 .emufree_shift = 1, 2805 .srst_shift = 0, 2806 .autoidle_shift = -ENODEV, 2807 }; 2808 2809 static const struct sysc_capabilities sysc_omap4 = { 2810 .type = TI_SYSC_OMAP4, 2811 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2812 SYSC_OMAP4_SOFTRESET, 2813 .regbits = &sysc_regbits_omap4, 2814 }; 2815 2816 static const struct sysc_capabilities sysc_omap4_timer = { 2817 .type = TI_SYSC_OMAP4_TIMER, 2818 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2819 SYSC_OMAP4_SOFTRESET, 2820 .regbits = &sysc_regbits_omap4, 2821 }; 2822 2823 /* 2824 * Common sysc register bits found on omap4, also known as type3 2825 */ 2826 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2827 .dmadisable_shift = -ENODEV, 2828 .midle_shift = 2, 2829 .sidle_shift = 0, 2830 .clkact_shift = -ENODEV, 2831 .enwkup_shift = -ENODEV, 2832 .srst_shift = -ENODEV, 2833 .emufree_shift = -ENODEV, 2834 .autoidle_shift = -ENODEV, 2835 }; 2836 2837 static const struct sysc_capabilities sysc_omap4_simple = { 2838 .type = TI_SYSC_OMAP4_SIMPLE, 2839 .regbits = &sysc_regbits_omap4_simple, 2840 }; 2841 2842 /* 2843 * SmartReflex sysc found on omap34xx 2844 */ 2845 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2846 .dmadisable_shift = -ENODEV, 2847 .midle_shift = -ENODEV, 2848 .sidle_shift = -ENODEV, 2849 .clkact_shift = 20, 2850 .enwkup_shift = -ENODEV, 2851 .srst_shift = -ENODEV, 2852 .emufree_shift = -ENODEV, 2853 .autoidle_shift = -ENODEV, 2854 }; 2855 2856 static const struct sysc_capabilities sysc_34xx_sr = { 2857 .type = TI_SYSC_OMAP34XX_SR, 2858 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2859 .regbits = &sysc_regbits_omap34xx_sr, 2860 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2861 SYSC_QUIRK_LEGACY_IDLE, 2862 }; 2863 2864 /* 2865 * SmartReflex sysc found on omap36xx and later 2866 */ 2867 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2868 .dmadisable_shift = -ENODEV, 2869 .midle_shift = -ENODEV, 2870 .sidle_shift = 24, 2871 .clkact_shift = -ENODEV, 2872 .enwkup_shift = 26, 2873 .srst_shift = -ENODEV, 2874 .emufree_shift = -ENODEV, 2875 .autoidle_shift = -ENODEV, 2876 }; 2877 2878 static const struct sysc_capabilities sysc_36xx_sr = { 2879 .type = TI_SYSC_OMAP36XX_SR, 2880 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2881 .regbits = &sysc_regbits_omap36xx_sr, 2882 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2883 }; 2884 2885 static const struct sysc_capabilities sysc_omap4_sr = { 2886 .type = TI_SYSC_OMAP4_SR, 2887 .regbits = &sysc_regbits_omap36xx_sr, 2888 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2889 }; 2890 2891 /* 2892 * McASP register bits found on omap4 and later 2893 */ 2894 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2895 .dmadisable_shift = -ENODEV, 2896 .midle_shift = -ENODEV, 2897 .sidle_shift = 0, 2898 .clkact_shift = -ENODEV, 2899 .enwkup_shift = -ENODEV, 2900 .srst_shift = -ENODEV, 2901 .emufree_shift = -ENODEV, 2902 .autoidle_shift = -ENODEV, 2903 }; 2904 2905 static const struct sysc_capabilities sysc_omap4_mcasp = { 2906 .type = TI_SYSC_OMAP4_MCASP, 2907 .regbits = &sysc_regbits_omap4_mcasp, 2908 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2909 }; 2910 2911 /* 2912 * McASP found on dra7 and later 2913 */ 2914 static const struct sysc_capabilities sysc_dra7_mcasp = { 2915 .type = TI_SYSC_OMAP4_SIMPLE, 2916 .regbits = &sysc_regbits_omap4_simple, 2917 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2918 }; 2919 2920 /* 2921 * FS USB host found on omap4 and later 2922 */ 2923 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2924 .dmadisable_shift = -ENODEV, 2925 .midle_shift = -ENODEV, 2926 .sidle_shift = 24, 2927 .clkact_shift = -ENODEV, 2928 .enwkup_shift = 26, 2929 .srst_shift = -ENODEV, 2930 .emufree_shift = -ENODEV, 2931 .autoidle_shift = -ENODEV, 2932 }; 2933 2934 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2935 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2936 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2937 .regbits = &sysc_regbits_omap4_usb_host_fs, 2938 }; 2939 2940 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2941 .dmadisable_shift = -ENODEV, 2942 .midle_shift = -ENODEV, 2943 .sidle_shift = -ENODEV, 2944 .clkact_shift = -ENODEV, 2945 .enwkup_shift = 4, 2946 .srst_shift = 0, 2947 .emufree_shift = -ENODEV, 2948 .autoidle_shift = -ENODEV, 2949 }; 2950 2951 static const struct sysc_capabilities sysc_dra7_mcan = { 2952 .type = TI_SYSC_DRA7_MCAN, 2953 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2954 .regbits = &sysc_regbits_dra7_mcan, 2955 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2956 }; 2957 2958 /* 2959 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2960 */ 2961 static const struct sysc_capabilities sysc_pruss = { 2962 .type = TI_SYSC_PRUSS, 2963 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2964 .regbits = &sysc_regbits_omap4_simple, 2965 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2966 }; 2967 2968 static int sysc_init_pdata(struct sysc *ddata) 2969 { 2970 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2971 struct ti_sysc_module_data *mdata; 2972 2973 if (!pdata) 2974 return 0; 2975 2976 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2977 if (!mdata) 2978 return -ENOMEM; 2979 2980 if (ddata->legacy_mode) { 2981 mdata->name = ddata->legacy_mode; 2982 mdata->module_pa = ddata->module_pa; 2983 mdata->module_size = ddata->module_size; 2984 mdata->offsets = ddata->offsets; 2985 mdata->nr_offsets = SYSC_MAX_REGS; 2986 mdata->cap = ddata->cap; 2987 mdata->cfg = &ddata->cfg; 2988 } 2989 2990 ddata->mdata = mdata; 2991 2992 return 0; 2993 } 2994 2995 static int sysc_init_match(struct sysc *ddata) 2996 { 2997 const struct sysc_capabilities *cap; 2998 2999 cap = of_device_get_match_data(ddata->dev); 3000 if (!cap) 3001 return -EINVAL; 3002 3003 ddata->cap = cap; 3004 if (ddata->cap) 3005 ddata->cfg.quirks |= ddata->cap->mod_quirks; 3006 3007 return 0; 3008 } 3009 3010 static void ti_sysc_idle(struct work_struct *work) 3011 { 3012 struct sysc *ddata; 3013 3014 ddata = container_of(work, struct sysc, idle_work.work); 3015 3016 /* 3017 * One time decrement of clock usage counts if left on from init. 3018 * Note that we disable opt clocks unconditionally in this case 3019 * as they are enabled unconditionally during init without 3020 * considering sysc_opt_clks_needed() at that point. 3021 */ 3022 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3023 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 3024 sysc_disable_main_clocks(ddata); 3025 sysc_disable_opt_clocks(ddata); 3026 sysc_clkdm_allow_idle(ddata); 3027 } 3028 3029 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 3030 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 3031 return; 3032 3033 /* 3034 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 3035 * and SYSC_QUIRK_NO_RESET_ON_INIT 3036 */ 3037 if (pm_runtime_active(ddata->dev)) 3038 pm_runtime_put_sync(ddata->dev); 3039 } 3040 3041 /* 3042 * SoC model and features detection. Only needed for SoCs that need 3043 * special handling for quirks, no need to list others. 3044 */ 3045 static const struct soc_device_attribute sysc_soc_match[] = { 3046 SOC_FLAG("OMAP242*", SOC_2420), 3047 SOC_FLAG("OMAP243*", SOC_2430), 3048 SOC_FLAG("OMAP3[45]*", SOC_3430), 3049 SOC_FLAG("OMAP3[67]*", SOC_3630), 3050 SOC_FLAG("OMAP443*", SOC_4430), 3051 SOC_FLAG("OMAP446*", SOC_4460), 3052 SOC_FLAG("OMAP447*", SOC_4470), 3053 SOC_FLAG("OMAP54*", SOC_5430), 3054 SOC_FLAG("AM433", SOC_AM3), 3055 SOC_FLAG("AM43*", SOC_AM4), 3056 SOC_FLAG("DRA7*", SOC_DRA7), 3057 3058 { /* sentinel */ } 3059 }; 3060 3061 /* 3062 * List of SoCs variants with disabled features. By default we assume all 3063 * devices in the device tree are available so no need to list those SoCs. 3064 */ 3065 static const struct soc_device_attribute sysc_soc_feat_match[] = { 3066 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 3067 SOC_FLAG("AM3505", DIS_SGX), 3068 SOC_FLAG("OMAP3525", DIS_SGX), 3069 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 3070 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 3071 3072 /* OMAP3630/DM3730 variants with some accelerators disabled */ 3073 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 3074 SOC_FLAG("DM3725", DIS_SGX), 3075 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 3076 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 3077 SOC_FLAG("OMAP3621", DIS_ISP), 3078 3079 { /* sentinel */ } 3080 }; 3081 3082 static int sysc_add_disabled(unsigned long base) 3083 { 3084 struct sysc_address *disabled_module; 3085 3086 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 3087 if (!disabled_module) 3088 return -ENOMEM; 3089 3090 disabled_module->base = base; 3091 3092 mutex_lock(&sysc_soc->list_lock); 3093 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 3094 mutex_unlock(&sysc_soc->list_lock); 3095 3096 return 0; 3097 } 3098 3099 /* 3100 * One time init to detect the booted SoC, disable unavailable features 3101 * and initialize list for optional cpu_pm notifier. 3102 * 3103 * Note that we initialize static data shared across all ti-sysc instances 3104 * so ddata is only used for SoC type. This can be called from module_init 3105 * once we no longer need to rely on platform data. 3106 */ 3107 static int sysc_init_static_data(struct sysc *ddata) 3108 { 3109 const struct soc_device_attribute *match; 3110 struct ti_sysc_platform_data *pdata; 3111 unsigned long features = 0; 3112 struct device_node *np; 3113 3114 if (sysc_soc) 3115 return 0; 3116 3117 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 3118 if (!sysc_soc) 3119 return -ENOMEM; 3120 3121 mutex_init(&sysc_soc->list_lock); 3122 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 3123 INIT_LIST_HEAD(&sysc_soc->restored_modules); 3124 sysc_soc->general_purpose = true; 3125 3126 pdata = dev_get_platdata(ddata->dev); 3127 if (pdata && pdata->soc_type_gp) 3128 sysc_soc->general_purpose = pdata->soc_type_gp(); 3129 3130 match = soc_device_match(sysc_soc_match); 3131 if (match && match->data) 3132 sysc_soc->soc = (int)match->data; 3133 3134 /* 3135 * Check and warn about possible old incomplete dtb. We now want to see 3136 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 3137 */ 3138 switch (sysc_soc->soc) { 3139 case SOC_AM3: 3140 case SOC_AM4: 3141 case SOC_4430 ... SOC_4470: 3142 case SOC_5430: 3143 case SOC_DRA7: 3144 np = of_find_node_by_path("/ocp"); 3145 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 3146 "ti-sysc: Incomplete old dtb, please update\n"); 3147 break; 3148 default: 3149 break; 3150 } 3151 3152 /* Ignore devices that are not available on HS and EMU SoCs */ 3153 if (!sysc_soc->general_purpose) { 3154 switch (sysc_soc->soc) { 3155 case SOC_3430 ... SOC_3630: 3156 sysc_add_disabled(0x48304000); /* timer12 */ 3157 break; 3158 case SOC_AM3: 3159 sysc_add_disabled(0x48310000); /* rng */ 3160 break; 3161 default: 3162 break; 3163 } 3164 } 3165 3166 match = soc_device_match(sysc_soc_feat_match); 3167 if (!match) 3168 return 0; 3169 3170 if (match->data) 3171 features = (unsigned long)match->data; 3172 3173 /* 3174 * Add disabled devices to the list based on the module base. 3175 * Note that this must be done before we attempt to access the 3176 * device and have module revision checks working. 3177 */ 3178 if (features & DIS_ISP) 3179 sysc_add_disabled(0x480bd400); 3180 if (features & DIS_IVA) 3181 sysc_add_disabled(0x5d000000); 3182 if (features & DIS_SGX) 3183 sysc_add_disabled(0x50000000); 3184 3185 return 0; 3186 } 3187 3188 static void sysc_cleanup_static_data(void) 3189 { 3190 struct sysc_module *restored_module; 3191 struct sysc_address *disabled_module; 3192 struct list_head *pos, *tmp; 3193 3194 if (!sysc_soc) 3195 return; 3196 3197 if (sysc_soc->nb.notifier_call) 3198 cpu_pm_unregister_notifier(&sysc_soc->nb); 3199 3200 mutex_lock(&sysc_soc->list_lock); 3201 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { 3202 restored_module = list_entry(pos, struct sysc_module, node); 3203 list_del(pos); 3204 kfree(restored_module); 3205 } 3206 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 3207 disabled_module = list_entry(pos, struct sysc_address, node); 3208 list_del(pos); 3209 kfree(disabled_module); 3210 } 3211 mutex_unlock(&sysc_soc->list_lock); 3212 } 3213 3214 static int sysc_check_disabled_devices(struct sysc *ddata) 3215 { 3216 struct sysc_address *disabled_module; 3217 struct list_head *pos; 3218 int error = 0; 3219 3220 mutex_lock(&sysc_soc->list_lock); 3221 list_for_each(pos, &sysc_soc->disabled_modules) { 3222 disabled_module = list_entry(pos, struct sysc_address, node); 3223 if (ddata->module_pa == disabled_module->base) { 3224 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3225 error = -ENODEV; 3226 break; 3227 } 3228 } 3229 mutex_unlock(&sysc_soc->list_lock); 3230 3231 return error; 3232 } 3233 3234 /* 3235 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3236 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3237 * are needed, we could also look at the timer register configuration. 3238 */ 3239 static int sysc_check_active_timer(struct sysc *ddata) 3240 { 3241 int error; 3242 3243 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3244 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3245 return 0; 3246 3247 /* 3248 * Quirk for omap3 beagleboard revision A to B4 to use gpt12. 3249 * Revision C and later are fixed with commit 23885389dbbb ("ARM: 3250 * dts: Fix timer regression for beagleboard revision c"). This all 3251 * can be dropped if we stop supporting old beagleboard revisions 3252 * A to B4 at some point. 3253 */ 3254 if (sysc_soc->soc == SOC_3430) 3255 error = -ENXIO; 3256 else 3257 error = -EBUSY; 3258 3259 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3260 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3261 return error; 3262 3263 return 0; 3264 } 3265 3266 static const struct of_device_id sysc_match_table[] = { 3267 { .compatible = "simple-bus", }, 3268 { /* sentinel */ }, 3269 }; 3270 3271 static int sysc_probe(struct platform_device *pdev) 3272 { 3273 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3274 struct sysc *ddata; 3275 int error; 3276 3277 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3278 if (!ddata) 3279 return -ENOMEM; 3280 3281 ddata->offsets[SYSC_REVISION] = -ENODEV; 3282 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3283 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3284 ddata->dev = &pdev->dev; 3285 platform_set_drvdata(pdev, ddata); 3286 3287 error = sysc_init_static_data(ddata); 3288 if (error) 3289 return error; 3290 3291 error = sysc_init_match(ddata); 3292 if (error) 3293 return error; 3294 3295 error = sysc_init_dts_quirks(ddata); 3296 if (error) 3297 return error; 3298 3299 error = sysc_map_and_check_registers(ddata); 3300 if (error) 3301 return error; 3302 3303 error = sysc_init_sysc_mask(ddata); 3304 if (error) 3305 return error; 3306 3307 error = sysc_init_idlemodes(ddata); 3308 if (error) 3309 return error; 3310 3311 error = sysc_init_syss_mask(ddata); 3312 if (error) 3313 return error; 3314 3315 error = sysc_init_pdata(ddata); 3316 if (error) 3317 return error; 3318 3319 sysc_init_early_quirks(ddata); 3320 3321 error = sysc_check_disabled_devices(ddata); 3322 if (error) 3323 return error; 3324 3325 error = sysc_check_active_timer(ddata); 3326 if (error == -ENXIO) 3327 ddata->reserved = true; 3328 else if (error) 3329 return error; 3330 3331 error = sysc_get_clocks(ddata); 3332 if (error) 3333 return error; 3334 3335 error = sysc_init_resets(ddata); 3336 if (error) 3337 goto unprepare; 3338 3339 error = sysc_init_module(ddata); 3340 if (error) 3341 goto unprepare; 3342 3343 pm_runtime_enable(ddata->dev); 3344 error = pm_runtime_resume_and_get(ddata->dev); 3345 if (error < 0) { 3346 pm_runtime_disable(ddata->dev); 3347 goto unprepare; 3348 } 3349 3350 /* Balance use counts as PM runtime should have enabled these all */ 3351 if (!(ddata->cfg.quirks & 3352 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3353 sysc_disable_main_clocks(ddata); 3354 sysc_disable_opt_clocks(ddata); 3355 sysc_clkdm_allow_idle(ddata); 3356 } 3357 3358 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3359 reset_control_assert(ddata->rsts); 3360 3361 sysc_show_registers(ddata); 3362 3363 ddata->dev->type = &sysc_device_type; 3364 3365 if (!ddata->reserved) { 3366 error = of_platform_populate(ddata->dev->of_node, 3367 sysc_match_table, 3368 pdata ? pdata->auxdata : NULL, 3369 ddata->dev); 3370 if (error) 3371 goto err; 3372 } 3373 3374 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3375 3376 /* At least earlycon won't survive without deferred idle */ 3377 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3378 SYSC_QUIRK_NO_IDLE_ON_INIT | 3379 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3380 schedule_delayed_work(&ddata->idle_work, 3000); 3381 } else { 3382 pm_runtime_put(&pdev->dev); 3383 } 3384 3385 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) 3386 sysc_add_restored(ddata); 3387 3388 return 0; 3389 3390 err: 3391 pm_runtime_put_sync(&pdev->dev); 3392 pm_runtime_disable(&pdev->dev); 3393 unprepare: 3394 sysc_unprepare(ddata); 3395 3396 return error; 3397 } 3398 3399 static int sysc_remove(struct platform_device *pdev) 3400 { 3401 struct sysc *ddata = platform_get_drvdata(pdev); 3402 int error; 3403 3404 /* Device can still be enabled, see deferred idle quirk in probe */ 3405 if (cancel_delayed_work_sync(&ddata->idle_work)) 3406 ti_sysc_idle(&ddata->idle_work.work); 3407 3408 error = pm_runtime_resume_and_get(ddata->dev); 3409 if (error < 0) { 3410 pm_runtime_disable(ddata->dev); 3411 goto unprepare; 3412 } 3413 3414 of_platform_depopulate(&pdev->dev); 3415 3416 pm_runtime_put_sync(&pdev->dev); 3417 pm_runtime_disable(&pdev->dev); 3418 3419 if (!reset_control_status(ddata->rsts)) 3420 reset_control_assert(ddata->rsts); 3421 3422 unprepare: 3423 sysc_unprepare(ddata); 3424 3425 return 0; 3426 } 3427 3428 static const struct of_device_id sysc_match[] = { 3429 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3430 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3431 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3432 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3433 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3434 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3435 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3436 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3437 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3438 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3439 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3440 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3441 { .compatible = "ti,sysc-usb-host-fs", 3442 .data = &sysc_omap4_usb_host_fs, }, 3443 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3444 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3445 { }, 3446 }; 3447 MODULE_DEVICE_TABLE(of, sysc_match); 3448 3449 static struct platform_driver sysc_driver = { 3450 .probe = sysc_probe, 3451 .remove = sysc_remove, 3452 .driver = { 3453 .name = "ti-sysc", 3454 .of_match_table = sysc_match, 3455 .pm = &sysc_pm_ops, 3456 }, 3457 }; 3458 3459 static int __init sysc_init(void) 3460 { 3461 bus_register_notifier(&platform_bus_type, &sysc_nb); 3462 3463 return platform_driver_register(&sysc_driver); 3464 } 3465 module_init(sysc_init); 3466 3467 static void __exit sysc_exit(void) 3468 { 3469 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3470 platform_driver_unregister(&sysc_driver); 3471 sysc_cleanup_static_data(); 3472 } 3473 module_exit(sysc_exit); 3474 3475 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3476 MODULE_LICENSE("GPL v2"); 3477