1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/delay.h> 10 #include <linux/list.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_domain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/slab.h> 19 #include <linux/sys_soc.h> 20 #include <linux/iopoll.h> 21 22 #include <linux/platform_data/ti-sysc.h> 23 24 #include <dt-bindings/bus/ti-sysc.h> 25 26 #define DIS_ISP BIT(2) 27 #define DIS_IVA BIT(1) 28 #define DIS_SGX BIT(0) 29 30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 enum sysc_soc { 35 SOC_UNKNOWN, 36 SOC_2420, 37 SOC_2430, 38 SOC_3430, 39 SOC_3630, 40 SOC_4430, 41 SOC_4460, 42 SOC_4470, 43 SOC_5430, 44 SOC_AM3, 45 SOC_AM4, 46 SOC_DRA7, 47 }; 48 49 struct sysc_address { 50 unsigned long base; 51 struct list_head node; 52 }; 53 54 struct sysc_soc_info { 55 unsigned long general_purpose:1; 56 enum sysc_soc soc; 57 struct mutex list_lock; /* disabled modules list lock */ 58 struct list_head disabled_modules; 59 }; 60 61 enum sysc_clocks { 62 SYSC_FCK, 63 SYSC_ICK, 64 SYSC_OPTFCK0, 65 SYSC_OPTFCK1, 66 SYSC_OPTFCK2, 67 SYSC_OPTFCK3, 68 SYSC_OPTFCK4, 69 SYSC_OPTFCK5, 70 SYSC_OPTFCK6, 71 SYSC_OPTFCK7, 72 SYSC_MAX_CLOCKS, 73 }; 74 75 static struct sysc_soc_info *sysc_soc; 76 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 77 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 79 "opt5", "opt6", "opt7", 80 }; 81 82 #define SYSC_IDLEMODE_MASK 3 83 #define SYSC_CLOCKACTIVITY_MASK 3 84 85 /** 86 * struct sysc - TI sysc interconnect target module registers and capabilities 87 * @dev: struct device pointer 88 * @module_pa: physical address of the interconnect target module 89 * @module_size: size of the interconnect target module 90 * @module_va: virtual address of the interconnect target module 91 * @offsets: register offsets from module base 92 * @mdata: ti-sysc to hwmod translation data for a module 93 * @clocks: clocks used by the interconnect target module 94 * @clock_roles: clock role names for the found clocks 95 * @nr_clocks: number of clocks used by the interconnect target module 96 * @rsts: resets used by the interconnect target module 97 * @legacy_mode: configured for legacy mode if set 98 * @cap: interconnect target module capabilities 99 * @cfg: interconnect target module configuration 100 * @cookie: data used by legacy platform callbacks 101 * @name: name if available 102 * @revision: interconnect target module revision 103 * @enabled: sysc runtime enabled status 104 * @needs_resume: runtime resume needed on resume from suspend 105 * @child_needs_resume: runtime resume needed for child on resume from suspend 106 * @disable_on_idle: status flag used for disabling modules with resets 107 * @idle_work: work structure used to perform delayed idle on a module 108 * @pre_reset_quirk: module specific pre-reset quirk 109 * @post_reset_quirk: module specific post-reset quirk 110 * @reset_done_quirk: module specific reset done quirk 111 * @module_enable_quirk: module specific enable quirk 112 * @module_disable_quirk: module specific disable quirk 113 * @module_unlock_quirk: module specific sysconfig unlock quirk 114 * @module_lock_quirk: module specific sysconfig lock quirk 115 */ 116 struct sysc { 117 struct device *dev; 118 u64 module_pa; 119 u32 module_size; 120 void __iomem *module_va; 121 int offsets[SYSC_MAX_REGS]; 122 struct ti_sysc_module_data *mdata; 123 struct clk **clocks; 124 const char **clock_roles; 125 int nr_clocks; 126 struct reset_control *rsts; 127 const char *legacy_mode; 128 const struct sysc_capabilities *cap; 129 struct sysc_config cfg; 130 struct ti_sysc_cookie cookie; 131 const char *name; 132 u32 revision; 133 unsigned int enabled:1; 134 unsigned int needs_resume:1; 135 unsigned int child_needs_resume:1; 136 struct delayed_work idle_work; 137 void (*pre_reset_quirk)(struct sysc *sysc); 138 void (*post_reset_quirk)(struct sysc *sysc); 139 void (*reset_done_quirk)(struct sysc *sysc); 140 void (*module_enable_quirk)(struct sysc *sysc); 141 void (*module_disable_quirk)(struct sysc *sysc); 142 void (*module_unlock_quirk)(struct sysc *sysc); 143 void (*module_lock_quirk)(struct sysc *sysc); 144 }; 145 146 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 147 bool is_child); 148 149 static void sysc_write(struct sysc *ddata, int offset, u32 value) 150 { 151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 152 writew_relaxed(value & 0xffff, ddata->module_va + offset); 153 154 /* Only i2c revision has LO and HI register with stride of 4 */ 155 if (ddata->offsets[SYSC_REVISION] >= 0 && 156 offset == ddata->offsets[SYSC_REVISION]) { 157 u16 hi = value >> 16; 158 159 writew_relaxed(hi, ddata->module_va + offset + 4); 160 } 161 162 return; 163 } 164 165 writel_relaxed(value, ddata->module_va + offset); 166 } 167 168 static u32 sysc_read(struct sysc *ddata, int offset) 169 { 170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 171 u32 val; 172 173 val = readw_relaxed(ddata->module_va + offset); 174 175 /* Only i2c revision has LO and HI register with stride of 4 */ 176 if (ddata->offsets[SYSC_REVISION] >= 0 && 177 offset == ddata->offsets[SYSC_REVISION]) { 178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 179 180 val |= tmp << 16; 181 } 182 183 return val; 184 } 185 186 return readl_relaxed(ddata->module_va + offset); 187 } 188 189 static bool sysc_opt_clks_needed(struct sysc *ddata) 190 { 191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 192 } 193 194 static u32 sysc_read_revision(struct sysc *ddata) 195 { 196 int offset = ddata->offsets[SYSC_REVISION]; 197 198 if (offset < 0) 199 return 0; 200 201 return sysc_read(ddata, offset); 202 } 203 204 static u32 sysc_read_sysconfig(struct sysc *ddata) 205 { 206 int offset = ddata->offsets[SYSC_SYSCONFIG]; 207 208 if (offset < 0) 209 return 0; 210 211 return sysc_read(ddata, offset); 212 } 213 214 static u32 sysc_read_sysstatus(struct sysc *ddata) 215 { 216 int offset = ddata->offsets[SYSC_SYSSTATUS]; 217 218 if (offset < 0) 219 return 0; 220 221 return sysc_read(ddata, offset); 222 } 223 224 /* Poll on reset status */ 225 static int sysc_wait_softreset(struct sysc *ddata) 226 { 227 u32 sysc_mask, syss_done, rstval; 228 int syss_offset, error = 0; 229 230 if (ddata->cap->regbits->srst_shift < 0) 231 return 0; 232 233 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 234 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 235 236 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 237 syss_done = 0; 238 else 239 syss_done = ddata->cfg.syss_mask; 240 241 if (syss_offset >= 0) { 242 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 243 rstval, (rstval & ddata->cfg.syss_mask) == 244 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 245 246 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 247 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 248 rstval, !(rstval & sysc_mask), 249 100, MAX_MODULE_SOFTRESET_WAIT); 250 } 251 252 return error; 253 } 254 255 static int sysc_add_named_clock_from_child(struct sysc *ddata, 256 const char *name, 257 const char *optfck_name) 258 { 259 struct device_node *np = ddata->dev->of_node; 260 struct device_node *child; 261 struct clk_lookup *cl; 262 struct clk *clock; 263 const char *n; 264 265 if (name) 266 n = name; 267 else 268 n = optfck_name; 269 270 /* Does the clock alias already exist? */ 271 clock = of_clk_get_by_name(np, n); 272 if (!IS_ERR(clock)) { 273 clk_put(clock); 274 275 return 0; 276 } 277 278 child = of_get_next_available_child(np, NULL); 279 if (!child) 280 return -ENODEV; 281 282 clock = devm_get_clk_from_child(ddata->dev, child, name); 283 if (IS_ERR(clock)) 284 return PTR_ERR(clock); 285 286 /* 287 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 288 * limit for clk_get(). If cl ever needs to be freed, it should be done 289 * with clkdev_drop(). 290 */ 291 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 292 if (!cl) 293 return -ENOMEM; 294 295 cl->con_id = n; 296 cl->dev_id = dev_name(ddata->dev); 297 cl->clk = clock; 298 clkdev_add(cl); 299 300 clk_put(clock); 301 302 return 0; 303 } 304 305 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 306 { 307 const char *optfck_name; 308 int error, index; 309 310 if (ddata->nr_clocks < SYSC_OPTFCK0) 311 index = SYSC_OPTFCK0; 312 else 313 index = ddata->nr_clocks; 314 315 if (name) 316 optfck_name = name; 317 else 318 optfck_name = clock_names[index]; 319 320 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 321 if (error) 322 return error; 323 324 ddata->clock_roles[index] = optfck_name; 325 ddata->nr_clocks++; 326 327 return 0; 328 } 329 330 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 331 { 332 int error, i, index = -ENODEV; 333 334 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 335 index = SYSC_FCK; 336 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 337 index = SYSC_ICK; 338 339 if (index < 0) { 340 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 341 if (!ddata->clocks[i]) { 342 index = i; 343 break; 344 } 345 } 346 } 347 348 if (index < 0) { 349 dev_err(ddata->dev, "clock %s not added\n", name); 350 return index; 351 } 352 353 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 354 if (IS_ERR(ddata->clocks[index])) { 355 dev_err(ddata->dev, "clock get error for %s: %li\n", 356 name, PTR_ERR(ddata->clocks[index])); 357 358 return PTR_ERR(ddata->clocks[index]); 359 } 360 361 error = clk_prepare(ddata->clocks[index]); 362 if (error) { 363 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 364 name, error); 365 366 return error; 367 } 368 369 return 0; 370 } 371 372 static int sysc_get_clocks(struct sysc *ddata) 373 { 374 struct device_node *np = ddata->dev->of_node; 375 struct property *prop; 376 const char *name; 377 int nr_fck = 0, nr_ick = 0, i, error = 0; 378 379 ddata->clock_roles = devm_kcalloc(ddata->dev, 380 SYSC_MAX_CLOCKS, 381 sizeof(*ddata->clock_roles), 382 GFP_KERNEL); 383 if (!ddata->clock_roles) 384 return -ENOMEM; 385 386 of_property_for_each_string(np, "clock-names", prop, name) { 387 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 388 nr_fck++; 389 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 390 nr_ick++; 391 ddata->clock_roles[ddata->nr_clocks] = name; 392 ddata->nr_clocks++; 393 } 394 395 if (ddata->nr_clocks < 1) 396 return 0; 397 398 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 399 error = sysc_init_ext_opt_clock(ddata, NULL); 400 if (error) 401 return error; 402 } 403 404 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 405 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 406 407 return -EINVAL; 408 } 409 410 if (nr_fck > 1 || nr_ick > 1) { 411 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 412 413 return -EINVAL; 414 } 415 416 /* Always add a slot for main clocks fck and ick even if unused */ 417 if (!nr_fck) 418 ddata->nr_clocks++; 419 if (!nr_ick) 420 ddata->nr_clocks++; 421 422 ddata->clocks = devm_kcalloc(ddata->dev, 423 ddata->nr_clocks, sizeof(*ddata->clocks), 424 GFP_KERNEL); 425 if (!ddata->clocks) 426 return -ENOMEM; 427 428 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 429 const char *name = ddata->clock_roles[i]; 430 431 if (!name) 432 continue; 433 434 error = sysc_get_one_clock(ddata, name); 435 if (error) 436 return error; 437 } 438 439 return 0; 440 } 441 442 static int sysc_enable_main_clocks(struct sysc *ddata) 443 { 444 struct clk *clock; 445 int i, error; 446 447 if (!ddata->clocks) 448 return 0; 449 450 for (i = 0; i < SYSC_OPTFCK0; i++) { 451 clock = ddata->clocks[i]; 452 453 /* Main clocks may not have ick */ 454 if (IS_ERR_OR_NULL(clock)) 455 continue; 456 457 error = clk_enable(clock); 458 if (error) 459 goto err_disable; 460 } 461 462 return 0; 463 464 err_disable: 465 for (i--; i >= 0; i--) { 466 clock = ddata->clocks[i]; 467 468 /* Main clocks may not have ick */ 469 if (IS_ERR_OR_NULL(clock)) 470 continue; 471 472 clk_disable(clock); 473 } 474 475 return error; 476 } 477 478 static void sysc_disable_main_clocks(struct sysc *ddata) 479 { 480 struct clk *clock; 481 int i; 482 483 if (!ddata->clocks) 484 return; 485 486 for (i = 0; i < SYSC_OPTFCK0; i++) { 487 clock = ddata->clocks[i]; 488 if (IS_ERR_OR_NULL(clock)) 489 continue; 490 491 clk_disable(clock); 492 } 493 } 494 495 static int sysc_enable_opt_clocks(struct sysc *ddata) 496 { 497 struct clk *clock; 498 int i, error; 499 500 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 501 return 0; 502 503 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 504 clock = ddata->clocks[i]; 505 506 /* Assume no holes for opt clocks */ 507 if (IS_ERR_OR_NULL(clock)) 508 return 0; 509 510 error = clk_enable(clock); 511 if (error) 512 goto err_disable; 513 } 514 515 return 0; 516 517 err_disable: 518 for (i--; i >= 0; i--) { 519 clock = ddata->clocks[i]; 520 if (IS_ERR_OR_NULL(clock)) 521 continue; 522 523 clk_disable(clock); 524 } 525 526 return error; 527 } 528 529 static void sysc_disable_opt_clocks(struct sysc *ddata) 530 { 531 struct clk *clock; 532 int i; 533 534 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 535 return; 536 537 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 538 clock = ddata->clocks[i]; 539 540 /* Assume no holes for opt clocks */ 541 if (IS_ERR_OR_NULL(clock)) 542 return; 543 544 clk_disable(clock); 545 } 546 } 547 548 static void sysc_clkdm_deny_idle(struct sysc *ddata) 549 { 550 struct ti_sysc_platform_data *pdata; 551 552 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 553 return; 554 555 pdata = dev_get_platdata(ddata->dev); 556 if (pdata && pdata->clkdm_deny_idle) 557 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 558 } 559 560 static void sysc_clkdm_allow_idle(struct sysc *ddata) 561 { 562 struct ti_sysc_platform_data *pdata; 563 564 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 565 return; 566 567 pdata = dev_get_platdata(ddata->dev); 568 if (pdata && pdata->clkdm_allow_idle) 569 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 570 } 571 572 /** 573 * sysc_init_resets - init rstctrl reset line if configured 574 * @ddata: device driver data 575 * 576 * See sysc_rstctrl_reset_deassert(). 577 */ 578 static int sysc_init_resets(struct sysc *ddata) 579 { 580 ddata->rsts = 581 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 582 583 return PTR_ERR_OR_ZERO(ddata->rsts); 584 } 585 586 /** 587 * sysc_parse_and_check_child_range - parses module IO region from ranges 588 * @ddata: device driver data 589 * 590 * In general we only need rev, syss, and sysc registers and not the whole 591 * module range. But we do want the offsets for these registers from the 592 * module base. This allows us to check them against the legacy hwmod 593 * platform data. Let's also check the ranges are configured properly. 594 */ 595 static int sysc_parse_and_check_child_range(struct sysc *ddata) 596 { 597 struct device_node *np = ddata->dev->of_node; 598 const __be32 *ranges; 599 u32 nr_addr, nr_size; 600 int len, error; 601 602 ranges = of_get_property(np, "ranges", &len); 603 if (!ranges) { 604 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 605 606 return -ENOENT; 607 } 608 609 len /= sizeof(*ranges); 610 611 if (len < 3) { 612 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 613 614 return -EINVAL; 615 } 616 617 error = of_property_read_u32(np, "#address-cells", &nr_addr); 618 if (error) 619 return -ENOENT; 620 621 error = of_property_read_u32(np, "#size-cells", &nr_size); 622 if (error) 623 return -ENOENT; 624 625 if (nr_addr != 1 || nr_size != 1) { 626 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 627 628 return -EINVAL; 629 } 630 631 ranges++; 632 ddata->module_pa = of_translate_address(np, ranges++); 633 ddata->module_size = be32_to_cpup(ranges); 634 635 return 0; 636 } 637 638 /* Interconnect instances to probe before l4_per instances */ 639 static struct resource early_bus_ranges[] = { 640 /* am3/4 l4_wkup */ 641 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, 642 /* omap4/5 and dra7 l4_cfg */ 643 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, 644 /* omap4 l4_wkup */ 645 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, 646 /* omap5 and dra7 l4_wkup without dra7 dcan segment */ 647 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, 648 }; 649 650 static atomic_t sysc_defer = ATOMIC_INIT(10); 651 652 /** 653 * sysc_defer_non_critical - defer non_critical interconnect probing 654 * @ddata: device driver data 655 * 656 * We want to probe l4_cfg and l4_wkup interconnect instances before any 657 * l4_per instances as l4_per instances depend on resources on l4_cfg and 658 * l4_wkup interconnects. 659 */ 660 static int sysc_defer_non_critical(struct sysc *ddata) 661 { 662 struct resource *res; 663 int i; 664 665 if (!atomic_read(&sysc_defer)) 666 return 0; 667 668 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { 669 res = &early_bus_ranges[i]; 670 if (ddata->module_pa >= res->start && 671 ddata->module_pa <= res->end) { 672 atomic_set(&sysc_defer, 0); 673 674 return 0; 675 } 676 } 677 678 atomic_dec_if_positive(&sysc_defer); 679 680 return -EPROBE_DEFER; 681 } 682 683 static struct device_node *stdout_path; 684 685 static void sysc_init_stdout_path(struct sysc *ddata) 686 { 687 struct device_node *np = NULL; 688 const char *uart; 689 690 if (IS_ERR(stdout_path)) 691 return; 692 693 if (stdout_path) 694 return; 695 696 np = of_find_node_by_path("/chosen"); 697 if (!np) 698 goto err; 699 700 uart = of_get_property(np, "stdout-path", NULL); 701 if (!uart) 702 goto err; 703 704 np = of_find_node_by_path(uart); 705 if (!np) 706 goto err; 707 708 stdout_path = np; 709 710 return; 711 712 err: 713 stdout_path = ERR_PTR(-ENODEV); 714 } 715 716 static void sysc_check_quirk_stdout(struct sysc *ddata, 717 struct device_node *np) 718 { 719 sysc_init_stdout_path(ddata); 720 if (np != stdout_path) 721 return; 722 723 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 724 SYSC_QUIRK_NO_RESET_ON_INIT; 725 } 726 727 /** 728 * sysc_check_one_child - check child configuration 729 * @ddata: device driver data 730 * @np: child device node 731 * 732 * Let's avoid messy situations where we have new interconnect target 733 * node but children have "ti,hwmods". These belong to the interconnect 734 * target node and are managed by this driver. 735 */ 736 static void sysc_check_one_child(struct sysc *ddata, 737 struct device_node *np) 738 { 739 const char *name; 740 741 name = of_get_property(np, "ti,hwmods", NULL); 742 if (name && !of_device_is_compatible(np, "ti,sysc")) 743 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 744 745 sysc_check_quirk_stdout(ddata, np); 746 sysc_parse_dts_quirks(ddata, np, true); 747 } 748 749 static void sysc_check_children(struct sysc *ddata) 750 { 751 struct device_node *child; 752 753 for_each_child_of_node(ddata->dev->of_node, child) 754 sysc_check_one_child(ddata, child); 755 } 756 757 /* 758 * So far only I2C uses 16-bit read access with clockactivity with revision 759 * in two registers with stride of 4. We can detect this based on the rev 760 * register size to configure things far enough to be able to properly read 761 * the revision register. 762 */ 763 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 764 { 765 if (resource_size(res) == 8) 766 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 767 } 768 769 /** 770 * sysc_parse_one - parses the interconnect target module registers 771 * @ddata: device driver data 772 * @reg: register to parse 773 */ 774 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 775 { 776 struct resource *res; 777 const char *name; 778 779 switch (reg) { 780 case SYSC_REVISION: 781 case SYSC_SYSCONFIG: 782 case SYSC_SYSSTATUS: 783 name = reg_names[reg]; 784 break; 785 default: 786 return -EINVAL; 787 } 788 789 res = platform_get_resource_byname(to_platform_device(ddata->dev), 790 IORESOURCE_MEM, name); 791 if (!res) { 792 ddata->offsets[reg] = -ENODEV; 793 794 return 0; 795 } 796 797 ddata->offsets[reg] = res->start - ddata->module_pa; 798 if (reg == SYSC_REVISION) 799 sysc_check_quirk_16bit(ddata, res); 800 801 return 0; 802 } 803 804 static int sysc_parse_registers(struct sysc *ddata) 805 { 806 int i, error; 807 808 for (i = 0; i < SYSC_MAX_REGS; i++) { 809 error = sysc_parse_one(ddata, i); 810 if (error) 811 return error; 812 } 813 814 return 0; 815 } 816 817 /** 818 * sysc_check_registers - check for misconfigured register overlaps 819 * @ddata: device driver data 820 */ 821 static int sysc_check_registers(struct sysc *ddata) 822 { 823 int i, j, nr_regs = 0, nr_matches = 0; 824 825 for (i = 0; i < SYSC_MAX_REGS; i++) { 826 if (ddata->offsets[i] < 0) 827 continue; 828 829 if (ddata->offsets[i] > (ddata->module_size - 4)) { 830 dev_err(ddata->dev, "register outside module range"); 831 832 return -EINVAL; 833 } 834 835 for (j = 0; j < SYSC_MAX_REGS; j++) { 836 if (ddata->offsets[j] < 0) 837 continue; 838 839 if (ddata->offsets[i] == ddata->offsets[j]) 840 nr_matches++; 841 } 842 nr_regs++; 843 } 844 845 if (nr_matches > nr_regs) { 846 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 847 nr_regs, nr_matches); 848 849 return -EINVAL; 850 } 851 852 return 0; 853 } 854 855 /** 856 * syc_ioremap - ioremap register space for the interconnect target module 857 * @ddata: device driver data 858 * 859 * Note that the interconnect target module registers can be anywhere 860 * within the interconnect target module range. For example, SGX has 861 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 862 * has them at offset 0x1200 in the CPSW_WR child. Usually the 863 * the interconnect target module registers are at the beginning of 864 * the module range though. 865 */ 866 static int sysc_ioremap(struct sysc *ddata) 867 { 868 int size; 869 870 if (ddata->offsets[SYSC_REVISION] < 0 && 871 ddata->offsets[SYSC_SYSCONFIG] < 0 && 872 ddata->offsets[SYSC_SYSSTATUS] < 0) { 873 size = ddata->module_size; 874 } else { 875 size = max3(ddata->offsets[SYSC_REVISION], 876 ddata->offsets[SYSC_SYSCONFIG], 877 ddata->offsets[SYSC_SYSSTATUS]); 878 879 if (size < SZ_1K) 880 size = SZ_1K; 881 882 if ((size + sizeof(u32)) > ddata->module_size) 883 size = ddata->module_size; 884 } 885 886 ddata->module_va = devm_ioremap(ddata->dev, 887 ddata->module_pa, 888 size + sizeof(u32)); 889 if (!ddata->module_va) 890 return -EIO; 891 892 return 0; 893 } 894 895 /** 896 * sysc_map_and_check_registers - ioremap and check device registers 897 * @ddata: device driver data 898 */ 899 static int sysc_map_and_check_registers(struct sysc *ddata) 900 { 901 struct device_node *np = ddata->dev->of_node; 902 int error; 903 904 error = sysc_parse_and_check_child_range(ddata); 905 if (error) 906 return error; 907 908 error = sysc_defer_non_critical(ddata); 909 if (error) 910 return error; 911 912 sysc_check_children(ddata); 913 914 if (!of_get_property(np, "reg", NULL)) 915 return 0; 916 917 error = sysc_parse_registers(ddata); 918 if (error) 919 return error; 920 921 error = sysc_ioremap(ddata); 922 if (error) 923 return error; 924 925 error = sysc_check_registers(ddata); 926 if (error) 927 return error; 928 929 return 0; 930 } 931 932 /** 933 * sysc_show_rev - read and show interconnect target module revision 934 * @bufp: buffer to print the information to 935 * @ddata: device driver data 936 */ 937 static int sysc_show_rev(char *bufp, struct sysc *ddata) 938 { 939 int len; 940 941 if (ddata->offsets[SYSC_REVISION] < 0) 942 return sprintf(bufp, ":NA"); 943 944 len = sprintf(bufp, ":%08x", ddata->revision); 945 946 return len; 947 } 948 949 static int sysc_show_reg(struct sysc *ddata, 950 char *bufp, enum sysc_registers reg) 951 { 952 if (ddata->offsets[reg] < 0) 953 return sprintf(bufp, ":NA"); 954 955 return sprintf(bufp, ":%x", ddata->offsets[reg]); 956 } 957 958 static int sysc_show_name(char *bufp, struct sysc *ddata) 959 { 960 if (!ddata->name) 961 return 0; 962 963 return sprintf(bufp, ":%s", ddata->name); 964 } 965 966 /** 967 * sysc_show_registers - show information about interconnect target module 968 * @ddata: device driver data 969 */ 970 static void sysc_show_registers(struct sysc *ddata) 971 { 972 char buf[128]; 973 char *bufp = buf; 974 int i; 975 976 for (i = 0; i < SYSC_MAX_REGS; i++) 977 bufp += sysc_show_reg(ddata, bufp, i); 978 979 bufp += sysc_show_rev(bufp, ddata); 980 bufp += sysc_show_name(bufp, ddata); 981 982 dev_dbg(ddata->dev, "%llx:%x%s\n", 983 ddata->module_pa, ddata->module_size, 984 buf); 985 } 986 987 /** 988 * sysc_write_sysconfig - handle sysconfig quirks for register write 989 * @ddata: device driver data 990 * @value: register value 991 */ 992 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 993 { 994 if (ddata->module_unlock_quirk) 995 ddata->module_unlock_quirk(ddata); 996 997 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 998 999 if (ddata->module_lock_quirk) 1000 ddata->module_lock_quirk(ddata); 1001 } 1002 1003 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 1004 #define SYSC_CLOCACT_ICK 2 1005 1006 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1007 static int sysc_enable_module(struct device *dev) 1008 { 1009 struct sysc *ddata; 1010 const struct sysc_regbits *regbits; 1011 u32 reg, idlemodes, best_mode; 1012 int error; 1013 1014 ddata = dev_get_drvdata(dev); 1015 1016 /* 1017 * Some modules like DSS reset automatically on idle. Enable optional 1018 * reset clocks and wait for OCP softreset to complete. 1019 */ 1020 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1021 error = sysc_enable_opt_clocks(ddata); 1022 if (error) { 1023 dev_err(ddata->dev, 1024 "Optional clocks failed for enable: %i\n", 1025 error); 1026 return error; 1027 } 1028 } 1029 /* 1030 * Some modules like i2c and hdq1w have unusable reset status unless 1031 * the module reset quirk is enabled. Skip status check on enable. 1032 */ 1033 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1034 error = sysc_wait_softreset(ddata); 1035 if (error) 1036 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1037 } 1038 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1039 sysc_disable_opt_clocks(ddata); 1040 1041 /* 1042 * Some subsystem private interconnects, like DSS top level module, 1043 * need only the automatic OCP softreset handling with no sysconfig 1044 * register bits to configure. 1045 */ 1046 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1047 return 0; 1048 1049 regbits = ddata->cap->regbits; 1050 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1051 1052 /* 1053 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1054 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1055 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1056 */ 1057 if (regbits->clkact_shift >= 0 && 1058 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1059 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1060 1061 /* Set SIDLE mode */ 1062 idlemodes = ddata->cfg.sidlemodes; 1063 if (!idlemodes || regbits->sidle_shift < 0) 1064 goto set_midle; 1065 1066 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1067 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1068 best_mode = SYSC_IDLE_NO; 1069 } else { 1070 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1071 if (best_mode > SYSC_IDLE_MASK) { 1072 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1073 return -EINVAL; 1074 } 1075 1076 /* Set WAKEUP */ 1077 if (regbits->enwkup_shift >= 0 && 1078 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1079 reg |= BIT(regbits->enwkup_shift); 1080 } 1081 1082 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1083 reg |= best_mode << regbits->sidle_shift; 1084 sysc_write_sysconfig(ddata, reg); 1085 1086 set_midle: 1087 /* Set MIDLE mode */ 1088 idlemodes = ddata->cfg.midlemodes; 1089 if (!idlemodes || regbits->midle_shift < 0) 1090 goto set_autoidle; 1091 1092 best_mode = fls(ddata->cfg.midlemodes) - 1; 1093 if (best_mode > SYSC_IDLE_MASK) { 1094 dev_err(dev, "%s: invalid midlemode\n", __func__); 1095 return -EINVAL; 1096 } 1097 1098 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1099 best_mode = SYSC_IDLE_NO; 1100 1101 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1102 reg |= best_mode << regbits->midle_shift; 1103 sysc_write_sysconfig(ddata, reg); 1104 1105 set_autoidle: 1106 /* Autoidle bit must enabled separately if available */ 1107 if (regbits->autoidle_shift >= 0 && 1108 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1109 reg |= 1 << regbits->autoidle_shift; 1110 sysc_write_sysconfig(ddata, reg); 1111 } 1112 1113 /* Flush posted write */ 1114 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1115 1116 if (ddata->module_enable_quirk) 1117 ddata->module_enable_quirk(ddata); 1118 1119 return 0; 1120 } 1121 1122 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1123 { 1124 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1125 *best_mode = SYSC_IDLE_SMART_WKUP; 1126 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1127 *best_mode = SYSC_IDLE_SMART; 1128 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1129 *best_mode = SYSC_IDLE_FORCE; 1130 else 1131 return -EINVAL; 1132 1133 return 0; 1134 } 1135 1136 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1137 static int sysc_disable_module(struct device *dev) 1138 { 1139 struct sysc *ddata; 1140 const struct sysc_regbits *regbits; 1141 u32 reg, idlemodes, best_mode; 1142 int ret; 1143 1144 ddata = dev_get_drvdata(dev); 1145 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1146 return 0; 1147 1148 if (ddata->module_disable_quirk) 1149 ddata->module_disable_quirk(ddata); 1150 1151 regbits = ddata->cap->regbits; 1152 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1153 1154 /* Set MIDLE mode */ 1155 idlemodes = ddata->cfg.midlemodes; 1156 if (!idlemodes || regbits->midle_shift < 0) 1157 goto set_sidle; 1158 1159 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1160 if (ret) { 1161 dev_err(dev, "%s: invalid midlemode\n", __func__); 1162 return ret; 1163 } 1164 1165 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1166 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1167 best_mode = SYSC_IDLE_FORCE; 1168 1169 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1170 reg |= best_mode << regbits->midle_shift; 1171 sysc_write_sysconfig(ddata, reg); 1172 1173 set_sidle: 1174 /* Set SIDLE mode */ 1175 idlemodes = ddata->cfg.sidlemodes; 1176 if (!idlemodes || regbits->sidle_shift < 0) 1177 return 0; 1178 1179 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1180 best_mode = SYSC_IDLE_FORCE; 1181 } else { 1182 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1183 if (ret) { 1184 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1185 return ret; 1186 } 1187 } 1188 1189 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1190 reg |= best_mode << regbits->sidle_shift; 1191 if (regbits->autoidle_shift >= 0 && 1192 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1193 reg |= 1 << regbits->autoidle_shift; 1194 sysc_write_sysconfig(ddata, reg); 1195 1196 /* Flush posted write */ 1197 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1198 1199 return 0; 1200 } 1201 1202 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1203 struct sysc *ddata) 1204 { 1205 struct ti_sysc_platform_data *pdata; 1206 int error; 1207 1208 pdata = dev_get_platdata(ddata->dev); 1209 if (!pdata) 1210 return 0; 1211 1212 if (!pdata->idle_module) 1213 return -ENODEV; 1214 1215 error = pdata->idle_module(dev, &ddata->cookie); 1216 if (error) 1217 dev_err(dev, "%s: could not idle: %i\n", 1218 __func__, error); 1219 1220 reset_control_assert(ddata->rsts); 1221 1222 return 0; 1223 } 1224 1225 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1226 struct sysc *ddata) 1227 { 1228 struct ti_sysc_platform_data *pdata; 1229 int error; 1230 1231 pdata = dev_get_platdata(ddata->dev); 1232 if (!pdata) 1233 return 0; 1234 1235 if (!pdata->enable_module) 1236 return -ENODEV; 1237 1238 error = pdata->enable_module(dev, &ddata->cookie); 1239 if (error) 1240 dev_err(dev, "%s: could not enable: %i\n", 1241 __func__, error); 1242 1243 reset_control_deassert(ddata->rsts); 1244 1245 return 0; 1246 } 1247 1248 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1249 { 1250 struct sysc *ddata; 1251 int error = 0; 1252 1253 ddata = dev_get_drvdata(dev); 1254 1255 if (!ddata->enabled) 1256 return 0; 1257 1258 sysc_clkdm_deny_idle(ddata); 1259 1260 if (ddata->legacy_mode) { 1261 error = sysc_runtime_suspend_legacy(dev, ddata); 1262 if (error) 1263 goto err_allow_idle; 1264 } else { 1265 error = sysc_disable_module(dev); 1266 if (error) 1267 goto err_allow_idle; 1268 } 1269 1270 sysc_disable_main_clocks(ddata); 1271 1272 if (sysc_opt_clks_needed(ddata)) 1273 sysc_disable_opt_clocks(ddata); 1274 1275 ddata->enabled = false; 1276 1277 err_allow_idle: 1278 sysc_clkdm_allow_idle(ddata); 1279 1280 reset_control_assert(ddata->rsts); 1281 1282 return error; 1283 } 1284 1285 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1286 { 1287 struct sysc *ddata; 1288 int error = 0; 1289 1290 ddata = dev_get_drvdata(dev); 1291 1292 if (ddata->enabled) 1293 return 0; 1294 1295 1296 sysc_clkdm_deny_idle(ddata); 1297 1298 if (sysc_opt_clks_needed(ddata)) { 1299 error = sysc_enable_opt_clocks(ddata); 1300 if (error) 1301 goto err_allow_idle; 1302 } 1303 1304 error = sysc_enable_main_clocks(ddata); 1305 if (error) 1306 goto err_opt_clocks; 1307 1308 reset_control_deassert(ddata->rsts); 1309 1310 if (ddata->legacy_mode) { 1311 error = sysc_runtime_resume_legacy(dev, ddata); 1312 if (error) 1313 goto err_main_clocks; 1314 } else { 1315 error = sysc_enable_module(dev); 1316 if (error) 1317 goto err_main_clocks; 1318 } 1319 1320 ddata->enabled = true; 1321 1322 sysc_clkdm_allow_idle(ddata); 1323 1324 return 0; 1325 1326 err_main_clocks: 1327 sysc_disable_main_clocks(ddata); 1328 err_opt_clocks: 1329 if (sysc_opt_clks_needed(ddata)) 1330 sysc_disable_opt_clocks(ddata); 1331 err_allow_idle: 1332 sysc_clkdm_allow_idle(ddata); 1333 1334 return error; 1335 } 1336 1337 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1338 { 1339 struct device *dev = ddata->dev; 1340 int error; 1341 1342 /* Disable target module if it is enabled */ 1343 if (ddata->enabled) { 1344 error = sysc_runtime_suspend(dev); 1345 if (error) 1346 dev_warn(dev, "reinit suspend failed: %i\n", error); 1347 } 1348 1349 /* Enable target module */ 1350 error = sysc_runtime_resume(dev); 1351 if (error) 1352 dev_warn(dev, "reinit resume failed: %i\n", error); 1353 1354 if (leave_enabled) 1355 return error; 1356 1357 /* Disable target module if no leave_enabled was set */ 1358 error = sysc_runtime_suspend(dev); 1359 if (error) 1360 dev_warn(dev, "reinit suspend failed: %i\n", error); 1361 1362 return error; 1363 } 1364 1365 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1366 { 1367 struct sysc *ddata; 1368 1369 ddata = dev_get_drvdata(dev); 1370 1371 if (ddata->cfg.quirks & 1372 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1373 return 0; 1374 1375 if (!ddata->enabled) 1376 return 0; 1377 1378 ddata->needs_resume = 1; 1379 1380 return sysc_runtime_suspend(dev); 1381 } 1382 1383 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1384 { 1385 struct sysc *ddata; 1386 int error = 0; 1387 1388 ddata = dev_get_drvdata(dev); 1389 1390 if (ddata->cfg.quirks & 1391 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1392 return 0; 1393 1394 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1395 error = sysc_reinit_module(ddata, ddata->needs_resume); 1396 if (error) 1397 dev_warn(dev, "noirq_resume failed: %i\n", error); 1398 } else if (ddata->needs_resume) { 1399 error = sysc_runtime_resume(dev); 1400 if (error) 1401 dev_warn(dev, "noirq_resume failed: %i\n", error); 1402 } 1403 1404 ddata->needs_resume = 0; 1405 1406 return error; 1407 } 1408 1409 static const struct dev_pm_ops sysc_pm_ops = { 1410 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1411 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1412 sysc_runtime_resume, 1413 NULL) 1414 }; 1415 1416 /* Module revision register based quirks */ 1417 struct sysc_revision_quirk { 1418 const char *name; 1419 u32 base; 1420 int rev_offset; 1421 int sysc_offset; 1422 int syss_offset; 1423 u32 revision; 1424 u32 revision_mask; 1425 u32 quirks; 1426 }; 1427 1428 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1429 optrev_val, optrevmask, optquirkmask) \ 1430 { \ 1431 .name = (optname), \ 1432 .base = (optbase), \ 1433 .rev_offset = (optrev), \ 1434 .sysc_offset = (optsysc), \ 1435 .syss_offset = (optsyss), \ 1436 .revision = (optrev_val), \ 1437 .revision_mask = (optrevmask), \ 1438 .quirks = (optquirkmask), \ 1439 } 1440 1441 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1442 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1443 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1444 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1445 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1446 SYSC_QUIRK_LEGACY_IDLE), 1447 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 1448 SYSC_QUIRK_LEGACY_IDLE), 1449 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 1450 SYSC_QUIRK_LEGACY_IDLE), 1451 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1452 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1453 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1454 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1455 /* Uarts on omap4 and later */ 1456 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1457 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1458 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1459 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1460 1461 /* Quirks that need to be set based on the module address */ 1462 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1463 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1464 SYSC_QUIRK_SWSUP_SIDLE), 1465 1466 /* Quirks that need to be set based on detected module */ 1467 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1468 SYSC_MODULE_QUIRK_AESS), 1469 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1470 SYSC_QUIRK_CLKDM_NOAUTO), 1471 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1472 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1473 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1474 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1475 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1476 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1477 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1478 SYSC_QUIRK_CLKDM_NOAUTO), 1479 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1480 SYSC_QUIRK_CLKDM_NOAUTO), 1481 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1482 SYSC_QUIRK_GPMC_DEBUG), 1483 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1484 SYSC_QUIRK_OPT_CLKS_NEEDED), 1485 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1486 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1487 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1488 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1489 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1490 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1491 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1492 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1493 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1494 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1495 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1496 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1497 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1498 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1499 SYSC_MODULE_QUIRK_SGX), 1500 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1501 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1502 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1503 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1504 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1505 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1506 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1507 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1508 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1509 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1510 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1511 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1512 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1513 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1514 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1515 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1516 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1517 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1518 SYSC_QUIRK_REINIT_ON_RESUME), 1519 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1520 SYSC_MODULE_QUIRK_WDT), 1521 /* PRUSS on am3, am4 and am5 */ 1522 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1523 SYSC_MODULE_QUIRK_PRUSS), 1524 /* Watchdog on am3 and am4 */ 1525 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1526 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1527 1528 #ifdef DEBUG 1529 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1530 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1531 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1532 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1533 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1534 0xffff00f0, 0), 1535 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1536 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1537 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1538 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1539 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1540 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1541 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1542 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1543 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1544 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1545 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1546 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1547 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1548 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1549 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1550 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1551 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1552 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1553 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1554 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1555 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1556 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1557 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1558 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0), 1559 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1560 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1561 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1562 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1563 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1564 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1565 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1566 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1567 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1568 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1569 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1570 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1571 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1572 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1573 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1574 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1575 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1576 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1577 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1578 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1579 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1580 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1581 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1582 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1583 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1584 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1585 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1586 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1587 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1588 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1589 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1590 /* Some timers on omap4 and later */ 1591 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1592 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1593 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1594 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1595 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1596 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1597 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1598 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1599 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1600 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1601 #endif 1602 }; 1603 1604 /* 1605 * Early quirks based on module base and register offsets only that are 1606 * needed before the module revision can be read 1607 */ 1608 static void sysc_init_early_quirks(struct sysc *ddata) 1609 { 1610 const struct sysc_revision_quirk *q; 1611 int i; 1612 1613 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1614 q = &sysc_revision_quirks[i]; 1615 1616 if (!q->base) 1617 continue; 1618 1619 if (q->base != ddata->module_pa) 1620 continue; 1621 1622 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1623 continue; 1624 1625 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1626 continue; 1627 1628 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1629 continue; 1630 1631 ddata->name = q->name; 1632 ddata->cfg.quirks |= q->quirks; 1633 } 1634 } 1635 1636 /* Quirks that also consider the revision register value */ 1637 static void sysc_init_revision_quirks(struct sysc *ddata) 1638 { 1639 const struct sysc_revision_quirk *q; 1640 int i; 1641 1642 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1643 q = &sysc_revision_quirks[i]; 1644 1645 if (q->base && q->base != ddata->module_pa) 1646 continue; 1647 1648 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1649 continue; 1650 1651 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1652 continue; 1653 1654 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1655 continue; 1656 1657 if (q->revision == ddata->revision || 1658 (q->revision & q->revision_mask) == 1659 (ddata->revision & q->revision_mask)) { 1660 ddata->name = q->name; 1661 ddata->cfg.quirks |= q->quirks; 1662 } 1663 } 1664 } 1665 1666 /* 1667 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1668 * enabled DSS interrupts. Eventually we may be able to do this on 1669 * dispc init rather than top-level DSS init. 1670 */ 1671 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1672 bool disable) 1673 { 1674 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1675 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1676 int manager_count; 1677 bool framedonetv_irq = true; 1678 u32 val, irq_mask = 0; 1679 1680 switch (sysc_soc->soc) { 1681 case SOC_2420 ... SOC_3630: 1682 manager_count = 2; 1683 framedonetv_irq = false; 1684 break; 1685 case SOC_4430 ... SOC_4470: 1686 manager_count = 3; 1687 break; 1688 case SOC_5430: 1689 case SOC_DRA7: 1690 manager_count = 4; 1691 break; 1692 case SOC_AM4: 1693 manager_count = 1; 1694 framedonetv_irq = false; 1695 break; 1696 case SOC_UNKNOWN: 1697 default: 1698 return 0; 1699 } 1700 1701 /* Remap the whole module range to be able to reset dispc outputs */ 1702 devm_iounmap(ddata->dev, ddata->module_va); 1703 ddata->module_va = devm_ioremap(ddata->dev, 1704 ddata->module_pa, 1705 ddata->module_size); 1706 if (!ddata->module_va) 1707 return -EIO; 1708 1709 /* DISP_CONTROL */ 1710 val = sysc_read(ddata, dispc_offset + 0x40); 1711 lcd_en = val & lcd_en_mask; 1712 digit_en = val & digit_en_mask; 1713 if (lcd_en) 1714 irq_mask |= BIT(0); /* FRAMEDONE */ 1715 if (digit_en) { 1716 if (framedonetv_irq) 1717 irq_mask |= BIT(24); /* FRAMEDONETV */ 1718 else 1719 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1720 } 1721 if (disable & (lcd_en | digit_en)) 1722 sysc_write(ddata, dispc_offset + 0x40, 1723 val & ~(lcd_en_mask | digit_en_mask)); 1724 1725 if (manager_count <= 2) 1726 return irq_mask; 1727 1728 /* DISPC_CONTROL2 */ 1729 val = sysc_read(ddata, dispc_offset + 0x238); 1730 lcd2_en = val & lcd_en_mask; 1731 if (lcd2_en) 1732 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1733 if (disable && lcd2_en) 1734 sysc_write(ddata, dispc_offset + 0x238, 1735 val & ~lcd_en_mask); 1736 1737 if (manager_count <= 3) 1738 return irq_mask; 1739 1740 /* DISPC_CONTROL3 */ 1741 val = sysc_read(ddata, dispc_offset + 0x848); 1742 lcd3_en = val & lcd_en_mask; 1743 if (lcd3_en) 1744 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1745 if (disable && lcd3_en) 1746 sysc_write(ddata, dispc_offset + 0x848, 1747 val & ~lcd_en_mask); 1748 1749 return irq_mask; 1750 } 1751 1752 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1753 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1754 { 1755 const int dispc_offset = 0x1000; 1756 int error; 1757 u32 irq_mask, val; 1758 1759 /* Get enabled outputs */ 1760 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1761 if (!irq_mask) 1762 return; 1763 1764 /* Clear IRQSTATUS */ 1765 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1766 1767 /* Disable outputs */ 1768 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1769 1770 /* Poll IRQSTATUS */ 1771 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1772 val, val != irq_mask, 100, 50); 1773 if (error) 1774 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1775 __func__, val, irq_mask); 1776 1777 if (sysc_soc->soc == SOC_3430) { 1778 /* Clear DSS_SDI_CONTROL */ 1779 sysc_write(ddata, 0x44, 0); 1780 1781 /* Clear DSS_PLL_CONTROL */ 1782 sysc_write(ddata, 0x48, 0); 1783 } 1784 1785 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1786 sysc_write(ddata, 0x40, 0); 1787 } 1788 1789 /* 1-wire needs module's internal clocks enabled for reset */ 1790 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1791 { 1792 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1793 u16 val; 1794 1795 val = sysc_read(ddata, offset); 1796 val |= BIT(5); 1797 sysc_write(ddata, offset, val); 1798 } 1799 1800 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1801 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1802 { 1803 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1804 1805 sysc_write(ddata, offset, 1); 1806 } 1807 1808 /* I2C needs to be disabled for reset */ 1809 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1810 { 1811 int offset; 1812 u16 val; 1813 1814 /* I2C_CON, omap2/3 is different from omap4 and later */ 1815 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1816 offset = 0x24; 1817 else 1818 offset = 0xa4; 1819 1820 /* I2C_EN */ 1821 val = sysc_read(ddata, offset); 1822 if (enable) 1823 val |= BIT(15); 1824 else 1825 val &= ~BIT(15); 1826 sysc_write(ddata, offset, val); 1827 } 1828 1829 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1830 { 1831 sysc_clk_quirk_i2c(ddata, false); 1832 } 1833 1834 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1835 { 1836 sysc_clk_quirk_i2c(ddata, true); 1837 } 1838 1839 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1840 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1841 { 1842 u32 val, kick0_val = 0, kick1_val = 0; 1843 unsigned long flags; 1844 int error; 1845 1846 if (!lock) { 1847 kick0_val = 0x83e70b13; 1848 kick1_val = 0x95a4f1e0; 1849 } 1850 1851 local_irq_save(flags); 1852 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1853 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1854 !(val & BIT(0)), 100, 50); 1855 if (error) 1856 dev_warn(ddata->dev, "rtc busy timeout\n"); 1857 /* Now we have ~15 microseconds to read/write various registers */ 1858 sysc_write(ddata, 0x6c, kick0_val); 1859 sysc_write(ddata, 0x70, kick1_val); 1860 local_irq_restore(flags); 1861 } 1862 1863 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1864 { 1865 sysc_quirk_rtc(ddata, false); 1866 } 1867 1868 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1869 { 1870 sysc_quirk_rtc(ddata, true); 1871 } 1872 1873 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1874 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1875 { 1876 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1877 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1878 1879 sysc_write(ddata, offset, val); 1880 } 1881 1882 /* Watchdog timer needs a disable sequence after reset */ 1883 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1884 { 1885 int wps, spr, error; 1886 u32 val; 1887 1888 wps = 0x34; 1889 spr = 0x48; 1890 1891 sysc_write(ddata, spr, 0xaaaa); 1892 error = readl_poll_timeout(ddata->module_va + wps, val, 1893 !(val & 0x10), 100, 1894 MAX_MODULE_SOFTRESET_WAIT); 1895 if (error) 1896 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1897 1898 sysc_write(ddata, spr, 0x5555); 1899 error = readl_poll_timeout(ddata->module_va + wps, val, 1900 !(val & 0x10), 100, 1901 MAX_MODULE_SOFTRESET_WAIT); 1902 if (error) 1903 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1904 } 1905 1906 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1907 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1908 { 1909 u32 reg; 1910 1911 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1912 reg |= SYSC_PRUSS_STANDBY_INIT; 1913 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1914 } 1915 1916 static void sysc_init_module_quirks(struct sysc *ddata) 1917 { 1918 if (ddata->legacy_mode || !ddata->name) 1919 return; 1920 1921 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1922 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 1923 1924 return; 1925 } 1926 1927 #ifdef CONFIG_OMAP_GPMC_DEBUG 1928 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 1929 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 1930 1931 return; 1932 } 1933 #endif 1934 1935 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1936 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 1937 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 1938 1939 return; 1940 } 1941 1942 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 1943 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 1944 1945 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 1946 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 1947 1948 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 1949 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 1950 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 1951 1952 return; 1953 } 1954 1955 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 1956 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 1957 1958 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 1959 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1960 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 1961 } 1962 1963 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 1964 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 1965 } 1966 1967 static int sysc_clockdomain_init(struct sysc *ddata) 1968 { 1969 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1970 struct clk *fck = NULL, *ick = NULL; 1971 int error; 1972 1973 if (!pdata || !pdata->init_clockdomain) 1974 return 0; 1975 1976 switch (ddata->nr_clocks) { 1977 case 2: 1978 ick = ddata->clocks[SYSC_ICK]; 1979 fallthrough; 1980 case 1: 1981 fck = ddata->clocks[SYSC_FCK]; 1982 break; 1983 case 0: 1984 return 0; 1985 } 1986 1987 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1988 if (!error || error == -ENODEV) 1989 return 0; 1990 1991 return error; 1992 } 1993 1994 /* 1995 * Note that pdata->init_module() typically does a reset first. After 1996 * pdata->init_module() is done, PM runtime can be used for the interconnect 1997 * target module. 1998 */ 1999 static int sysc_legacy_init(struct sysc *ddata) 2000 { 2001 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2002 int error; 2003 2004 if (!pdata || !pdata->init_module) 2005 return 0; 2006 2007 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2008 if (error == -EEXIST) 2009 error = 0; 2010 2011 return error; 2012 } 2013 2014 /* 2015 * Note that the caller must ensure the interconnect target module is enabled 2016 * before calling reset. Otherwise reset will not complete. 2017 */ 2018 static int sysc_reset(struct sysc *ddata) 2019 { 2020 int sysc_offset, sysc_val, error; 2021 u32 sysc_mask; 2022 2023 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2024 2025 if (ddata->legacy_mode || 2026 ddata->cap->regbits->srst_shift < 0 || 2027 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 2028 return 0; 2029 2030 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2031 2032 if (ddata->pre_reset_quirk) 2033 ddata->pre_reset_quirk(ddata); 2034 2035 if (sysc_offset >= 0) { 2036 sysc_val = sysc_read_sysconfig(ddata); 2037 sysc_val |= sysc_mask; 2038 sysc_write(ddata, sysc_offset, sysc_val); 2039 } 2040 2041 if (ddata->cfg.srst_udelay) 2042 usleep_range(ddata->cfg.srst_udelay, 2043 ddata->cfg.srst_udelay * 2); 2044 2045 if (ddata->post_reset_quirk) 2046 ddata->post_reset_quirk(ddata); 2047 2048 error = sysc_wait_softreset(ddata); 2049 if (error) 2050 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2051 2052 if (ddata->reset_done_quirk) 2053 ddata->reset_done_quirk(ddata); 2054 2055 return error; 2056 } 2057 2058 /* 2059 * At this point the module is configured enough to read the revision but 2060 * module may not be completely configured yet to use PM runtime. Enable 2061 * all clocks directly during init to configure the quirks needed for PM 2062 * runtime based on the revision register. 2063 */ 2064 static int sysc_init_module(struct sysc *ddata) 2065 { 2066 bool rstctrl_deasserted = false; 2067 int error = 0; 2068 2069 error = sysc_clockdomain_init(ddata); 2070 if (error) 2071 return error; 2072 2073 sysc_clkdm_deny_idle(ddata); 2074 2075 /* 2076 * Always enable clocks. The bootloader may or may not have enabled 2077 * the related clocks. 2078 */ 2079 error = sysc_enable_opt_clocks(ddata); 2080 if (error) 2081 return error; 2082 2083 error = sysc_enable_main_clocks(ddata); 2084 if (error) 2085 goto err_opt_clocks; 2086 2087 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2088 error = reset_control_deassert(ddata->rsts); 2089 if (error) 2090 goto err_main_clocks; 2091 rstctrl_deasserted = true; 2092 } 2093 2094 ddata->revision = sysc_read_revision(ddata); 2095 sysc_init_revision_quirks(ddata); 2096 sysc_init_module_quirks(ddata); 2097 2098 if (ddata->legacy_mode) { 2099 error = sysc_legacy_init(ddata); 2100 if (error) 2101 goto err_main_clocks; 2102 } 2103 2104 if (!ddata->legacy_mode) { 2105 error = sysc_enable_module(ddata->dev); 2106 if (error) 2107 goto err_main_clocks; 2108 } 2109 2110 error = sysc_reset(ddata); 2111 if (error) 2112 dev_err(ddata->dev, "Reset failed with %d\n", error); 2113 2114 if (error && !ddata->legacy_mode) 2115 sysc_disable_module(ddata->dev); 2116 2117 err_main_clocks: 2118 if (error) 2119 sysc_disable_main_clocks(ddata); 2120 err_opt_clocks: 2121 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2122 if (error) { 2123 sysc_disable_opt_clocks(ddata); 2124 sysc_clkdm_allow_idle(ddata); 2125 } 2126 2127 if (error && rstctrl_deasserted && 2128 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2129 reset_control_assert(ddata->rsts); 2130 2131 return error; 2132 } 2133 2134 static int sysc_init_sysc_mask(struct sysc *ddata) 2135 { 2136 struct device_node *np = ddata->dev->of_node; 2137 int error; 2138 u32 val; 2139 2140 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2141 if (error) 2142 return 0; 2143 2144 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2145 2146 return 0; 2147 } 2148 2149 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2150 const char *name) 2151 { 2152 struct device_node *np = ddata->dev->of_node; 2153 struct property *prop; 2154 const __be32 *p; 2155 u32 val; 2156 2157 of_property_for_each_u32(np, name, prop, p, val) { 2158 if (val >= SYSC_NR_IDLEMODES) { 2159 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2160 return -EINVAL; 2161 } 2162 *idlemodes |= (1 << val); 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int sysc_init_idlemodes(struct sysc *ddata) 2169 { 2170 int error; 2171 2172 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2173 "ti,sysc-midle"); 2174 if (error) 2175 return error; 2176 2177 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2178 "ti,sysc-sidle"); 2179 if (error) 2180 return error; 2181 2182 return 0; 2183 } 2184 2185 /* 2186 * Only some devices on omap4 and later have SYSCONFIG reset done 2187 * bit. We can detect this if there is no SYSSTATUS at all, or the 2188 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2189 * have multiple bits for the child devices like OHCI and EHCI. 2190 * Depends on SYSC being parsed first. 2191 */ 2192 static int sysc_init_syss_mask(struct sysc *ddata) 2193 { 2194 struct device_node *np = ddata->dev->of_node; 2195 int error; 2196 u32 val; 2197 2198 error = of_property_read_u32(np, "ti,syss-mask", &val); 2199 if (error) { 2200 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2201 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2202 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2203 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2204 2205 return 0; 2206 } 2207 2208 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2209 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2210 2211 ddata->cfg.syss_mask = val; 2212 2213 return 0; 2214 } 2215 2216 /* 2217 * Many child device drivers need to have fck and opt clocks available 2218 * to get the clock rate for device internal configuration etc. 2219 */ 2220 static int sysc_child_add_named_clock(struct sysc *ddata, 2221 struct device *child, 2222 const char *name) 2223 { 2224 struct clk *clk; 2225 struct clk_lookup *l; 2226 int error = 0; 2227 2228 if (!name) 2229 return 0; 2230 2231 clk = clk_get(child, name); 2232 if (!IS_ERR(clk)) { 2233 error = -EEXIST; 2234 goto put_clk; 2235 } 2236 2237 clk = clk_get(ddata->dev, name); 2238 if (IS_ERR(clk)) 2239 return -ENODEV; 2240 2241 l = clkdev_create(clk, name, dev_name(child)); 2242 if (!l) 2243 error = -ENOMEM; 2244 put_clk: 2245 clk_put(clk); 2246 2247 return error; 2248 } 2249 2250 static int sysc_child_add_clocks(struct sysc *ddata, 2251 struct device *child) 2252 { 2253 int i, error; 2254 2255 for (i = 0; i < ddata->nr_clocks; i++) { 2256 error = sysc_child_add_named_clock(ddata, 2257 child, 2258 ddata->clock_roles[i]); 2259 if (error && error != -EEXIST) { 2260 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2261 ddata->clock_roles[i], error); 2262 2263 return error; 2264 } 2265 } 2266 2267 return 0; 2268 } 2269 2270 static struct device_type sysc_device_type = { 2271 }; 2272 2273 static struct sysc *sysc_child_to_parent(struct device *dev) 2274 { 2275 struct device *parent = dev->parent; 2276 2277 if (!parent || parent->type != &sysc_device_type) 2278 return NULL; 2279 2280 return dev_get_drvdata(parent); 2281 } 2282 2283 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2284 { 2285 struct sysc *ddata; 2286 int error; 2287 2288 ddata = sysc_child_to_parent(dev); 2289 2290 error = pm_generic_runtime_suspend(dev); 2291 if (error) 2292 return error; 2293 2294 if (!ddata->enabled) 2295 return 0; 2296 2297 return sysc_runtime_suspend(ddata->dev); 2298 } 2299 2300 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2301 { 2302 struct sysc *ddata; 2303 int error; 2304 2305 ddata = sysc_child_to_parent(dev); 2306 2307 if (!ddata->enabled) { 2308 error = sysc_runtime_resume(ddata->dev); 2309 if (error < 0) 2310 dev_err(ddata->dev, 2311 "%s error: %i\n", __func__, error); 2312 } 2313 2314 return pm_generic_runtime_resume(dev); 2315 } 2316 2317 #ifdef CONFIG_PM_SLEEP 2318 static int sysc_child_suspend_noirq(struct device *dev) 2319 { 2320 struct sysc *ddata; 2321 int error; 2322 2323 ddata = sysc_child_to_parent(dev); 2324 2325 dev_dbg(ddata->dev, "%s %s\n", __func__, 2326 ddata->name ? ddata->name : ""); 2327 2328 error = pm_generic_suspend_noirq(dev); 2329 if (error) { 2330 dev_err(dev, "%s error at %i: %i\n", 2331 __func__, __LINE__, error); 2332 2333 return error; 2334 } 2335 2336 if (!pm_runtime_status_suspended(dev)) { 2337 error = pm_generic_runtime_suspend(dev); 2338 if (error) { 2339 dev_dbg(dev, "%s busy at %i: %i\n", 2340 __func__, __LINE__, error); 2341 2342 return 0; 2343 } 2344 2345 error = sysc_runtime_suspend(ddata->dev); 2346 if (error) { 2347 dev_err(dev, "%s error at %i: %i\n", 2348 __func__, __LINE__, error); 2349 2350 return error; 2351 } 2352 2353 ddata->child_needs_resume = true; 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int sysc_child_resume_noirq(struct device *dev) 2360 { 2361 struct sysc *ddata; 2362 int error; 2363 2364 ddata = sysc_child_to_parent(dev); 2365 2366 dev_dbg(ddata->dev, "%s %s\n", __func__, 2367 ddata->name ? ddata->name : ""); 2368 2369 if (ddata->child_needs_resume) { 2370 ddata->child_needs_resume = false; 2371 2372 error = sysc_runtime_resume(ddata->dev); 2373 if (error) 2374 dev_err(ddata->dev, 2375 "%s runtime resume error: %i\n", 2376 __func__, error); 2377 2378 error = pm_generic_runtime_resume(dev); 2379 if (error) 2380 dev_err(ddata->dev, 2381 "%s generic runtime resume: %i\n", 2382 __func__, error); 2383 } 2384 2385 return pm_generic_resume_noirq(dev); 2386 } 2387 #endif 2388 2389 static struct dev_pm_domain sysc_child_pm_domain = { 2390 .ops = { 2391 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2392 sysc_child_runtime_resume, 2393 NULL) 2394 USE_PLATFORM_PM_SLEEP_OPS 2395 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2396 sysc_child_resume_noirq) 2397 } 2398 }; 2399 2400 /** 2401 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2402 * @ddata: device driver data 2403 * @child: child device driver 2404 * 2405 * Allow idle for child devices as done with _od_runtime_suspend(). 2406 * Otherwise many child devices will not idle because of the permanent 2407 * parent usecount set in pm_runtime_irq_safe(). 2408 * 2409 * Note that the long term solution is to just modify the child device 2410 * drivers to not set pm_runtime_irq_safe() and then this can be just 2411 * dropped. 2412 */ 2413 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2414 { 2415 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2416 dev_pm_domain_set(child, &sysc_child_pm_domain); 2417 } 2418 2419 static int sysc_notifier_call(struct notifier_block *nb, 2420 unsigned long event, void *device) 2421 { 2422 struct device *dev = device; 2423 struct sysc *ddata; 2424 int error; 2425 2426 ddata = sysc_child_to_parent(dev); 2427 if (!ddata) 2428 return NOTIFY_DONE; 2429 2430 switch (event) { 2431 case BUS_NOTIFY_ADD_DEVICE: 2432 error = sysc_child_add_clocks(ddata, dev); 2433 if (error) 2434 return error; 2435 sysc_legacy_idle_quirk(ddata, dev); 2436 break; 2437 default: 2438 break; 2439 } 2440 2441 return NOTIFY_DONE; 2442 } 2443 2444 static struct notifier_block sysc_nb = { 2445 .notifier_call = sysc_notifier_call, 2446 }; 2447 2448 /* Device tree configured quirks */ 2449 struct sysc_dts_quirk { 2450 const char *name; 2451 u32 mask; 2452 }; 2453 2454 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2455 { .name = "ti,no-idle-on-init", 2456 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2457 { .name = "ti,no-reset-on-init", 2458 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2459 { .name = "ti,no-idle", 2460 .mask = SYSC_QUIRK_NO_IDLE, }, 2461 }; 2462 2463 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2464 bool is_child) 2465 { 2466 const struct property *prop; 2467 int i, len; 2468 2469 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2470 const char *name = sysc_dts_quirks[i].name; 2471 2472 prop = of_get_property(np, name, &len); 2473 if (!prop) 2474 continue; 2475 2476 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2477 if (is_child) { 2478 dev_warn(ddata->dev, 2479 "dts flag should be at module level for %s\n", 2480 name); 2481 } 2482 } 2483 } 2484 2485 static int sysc_init_dts_quirks(struct sysc *ddata) 2486 { 2487 struct device_node *np = ddata->dev->of_node; 2488 int error; 2489 u32 val; 2490 2491 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2492 2493 sysc_parse_dts_quirks(ddata, np, false); 2494 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2495 if (!error) { 2496 if (val > 255) { 2497 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2498 val); 2499 } 2500 2501 ddata->cfg.srst_udelay = (u8)val; 2502 } 2503 2504 return 0; 2505 } 2506 2507 static void sysc_unprepare(struct sysc *ddata) 2508 { 2509 int i; 2510 2511 if (!ddata->clocks) 2512 return; 2513 2514 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2515 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2516 clk_unprepare(ddata->clocks[i]); 2517 } 2518 } 2519 2520 /* 2521 * Common sysc register bits found on omap2, also known as type1 2522 */ 2523 static const struct sysc_regbits sysc_regbits_omap2 = { 2524 .dmadisable_shift = -ENODEV, 2525 .midle_shift = 12, 2526 .sidle_shift = 3, 2527 .clkact_shift = 8, 2528 .emufree_shift = 5, 2529 .enwkup_shift = 2, 2530 .srst_shift = 1, 2531 .autoidle_shift = 0, 2532 }; 2533 2534 static const struct sysc_capabilities sysc_omap2 = { 2535 .type = TI_SYSC_OMAP2, 2536 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2537 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2538 SYSC_OMAP2_AUTOIDLE, 2539 .regbits = &sysc_regbits_omap2, 2540 }; 2541 2542 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2543 static const struct sysc_capabilities sysc_omap2_timer = { 2544 .type = TI_SYSC_OMAP2_TIMER, 2545 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2546 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2547 SYSC_OMAP2_AUTOIDLE, 2548 .regbits = &sysc_regbits_omap2, 2549 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2550 }; 2551 2552 /* 2553 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2554 * with different sidle position 2555 */ 2556 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2557 .dmadisable_shift = -ENODEV, 2558 .midle_shift = -ENODEV, 2559 .sidle_shift = 4, 2560 .clkact_shift = -ENODEV, 2561 .enwkup_shift = -ENODEV, 2562 .srst_shift = 1, 2563 .autoidle_shift = 0, 2564 .emufree_shift = -ENODEV, 2565 }; 2566 2567 static const struct sysc_capabilities sysc_omap3_sham = { 2568 .type = TI_SYSC_OMAP3_SHAM, 2569 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2570 .regbits = &sysc_regbits_omap3_sham, 2571 }; 2572 2573 /* 2574 * AES register bits found on omap3 and later, a variant of 2575 * sysc_regbits_omap2 with different sidle position 2576 */ 2577 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2578 .dmadisable_shift = -ENODEV, 2579 .midle_shift = -ENODEV, 2580 .sidle_shift = 6, 2581 .clkact_shift = -ENODEV, 2582 .enwkup_shift = -ENODEV, 2583 .srst_shift = 1, 2584 .autoidle_shift = 0, 2585 .emufree_shift = -ENODEV, 2586 }; 2587 2588 static const struct sysc_capabilities sysc_omap3_aes = { 2589 .type = TI_SYSC_OMAP3_AES, 2590 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2591 .regbits = &sysc_regbits_omap3_aes, 2592 }; 2593 2594 /* 2595 * Common sysc register bits found on omap4, also known as type2 2596 */ 2597 static const struct sysc_regbits sysc_regbits_omap4 = { 2598 .dmadisable_shift = 16, 2599 .midle_shift = 4, 2600 .sidle_shift = 2, 2601 .clkact_shift = -ENODEV, 2602 .enwkup_shift = -ENODEV, 2603 .emufree_shift = 1, 2604 .srst_shift = 0, 2605 .autoidle_shift = -ENODEV, 2606 }; 2607 2608 static const struct sysc_capabilities sysc_omap4 = { 2609 .type = TI_SYSC_OMAP4, 2610 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2611 SYSC_OMAP4_SOFTRESET, 2612 .regbits = &sysc_regbits_omap4, 2613 }; 2614 2615 static const struct sysc_capabilities sysc_omap4_timer = { 2616 .type = TI_SYSC_OMAP4_TIMER, 2617 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2618 SYSC_OMAP4_SOFTRESET, 2619 .regbits = &sysc_regbits_omap4, 2620 }; 2621 2622 /* 2623 * Common sysc register bits found on omap4, also known as type3 2624 */ 2625 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2626 .dmadisable_shift = -ENODEV, 2627 .midle_shift = 2, 2628 .sidle_shift = 0, 2629 .clkact_shift = -ENODEV, 2630 .enwkup_shift = -ENODEV, 2631 .srst_shift = -ENODEV, 2632 .emufree_shift = -ENODEV, 2633 .autoidle_shift = -ENODEV, 2634 }; 2635 2636 static const struct sysc_capabilities sysc_omap4_simple = { 2637 .type = TI_SYSC_OMAP4_SIMPLE, 2638 .regbits = &sysc_regbits_omap4_simple, 2639 }; 2640 2641 /* 2642 * SmartReflex sysc found on omap34xx 2643 */ 2644 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2645 .dmadisable_shift = -ENODEV, 2646 .midle_shift = -ENODEV, 2647 .sidle_shift = -ENODEV, 2648 .clkact_shift = 20, 2649 .enwkup_shift = -ENODEV, 2650 .srst_shift = -ENODEV, 2651 .emufree_shift = -ENODEV, 2652 .autoidle_shift = -ENODEV, 2653 }; 2654 2655 static const struct sysc_capabilities sysc_34xx_sr = { 2656 .type = TI_SYSC_OMAP34XX_SR, 2657 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2658 .regbits = &sysc_regbits_omap34xx_sr, 2659 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2660 SYSC_QUIRK_LEGACY_IDLE, 2661 }; 2662 2663 /* 2664 * SmartReflex sysc found on omap36xx and later 2665 */ 2666 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2667 .dmadisable_shift = -ENODEV, 2668 .midle_shift = -ENODEV, 2669 .sidle_shift = 24, 2670 .clkact_shift = -ENODEV, 2671 .enwkup_shift = 26, 2672 .srst_shift = -ENODEV, 2673 .emufree_shift = -ENODEV, 2674 .autoidle_shift = -ENODEV, 2675 }; 2676 2677 static const struct sysc_capabilities sysc_36xx_sr = { 2678 .type = TI_SYSC_OMAP36XX_SR, 2679 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2680 .regbits = &sysc_regbits_omap36xx_sr, 2681 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2682 }; 2683 2684 static const struct sysc_capabilities sysc_omap4_sr = { 2685 .type = TI_SYSC_OMAP4_SR, 2686 .regbits = &sysc_regbits_omap36xx_sr, 2687 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2688 }; 2689 2690 /* 2691 * McASP register bits found on omap4 and later 2692 */ 2693 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2694 .dmadisable_shift = -ENODEV, 2695 .midle_shift = -ENODEV, 2696 .sidle_shift = 0, 2697 .clkact_shift = -ENODEV, 2698 .enwkup_shift = -ENODEV, 2699 .srst_shift = -ENODEV, 2700 .emufree_shift = -ENODEV, 2701 .autoidle_shift = -ENODEV, 2702 }; 2703 2704 static const struct sysc_capabilities sysc_omap4_mcasp = { 2705 .type = TI_SYSC_OMAP4_MCASP, 2706 .regbits = &sysc_regbits_omap4_mcasp, 2707 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2708 }; 2709 2710 /* 2711 * McASP found on dra7 and later 2712 */ 2713 static const struct sysc_capabilities sysc_dra7_mcasp = { 2714 .type = TI_SYSC_OMAP4_SIMPLE, 2715 .regbits = &sysc_regbits_omap4_simple, 2716 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2717 }; 2718 2719 /* 2720 * FS USB host found on omap4 and later 2721 */ 2722 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2723 .dmadisable_shift = -ENODEV, 2724 .midle_shift = -ENODEV, 2725 .sidle_shift = 24, 2726 .clkact_shift = -ENODEV, 2727 .enwkup_shift = 26, 2728 .srst_shift = -ENODEV, 2729 .emufree_shift = -ENODEV, 2730 .autoidle_shift = -ENODEV, 2731 }; 2732 2733 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2734 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2735 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2736 .regbits = &sysc_regbits_omap4_usb_host_fs, 2737 }; 2738 2739 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2740 .dmadisable_shift = -ENODEV, 2741 .midle_shift = -ENODEV, 2742 .sidle_shift = -ENODEV, 2743 .clkact_shift = -ENODEV, 2744 .enwkup_shift = 4, 2745 .srst_shift = 0, 2746 .emufree_shift = -ENODEV, 2747 .autoidle_shift = -ENODEV, 2748 }; 2749 2750 static const struct sysc_capabilities sysc_dra7_mcan = { 2751 .type = TI_SYSC_DRA7_MCAN, 2752 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2753 .regbits = &sysc_regbits_dra7_mcan, 2754 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2755 }; 2756 2757 /* 2758 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2759 */ 2760 static const struct sysc_capabilities sysc_pruss = { 2761 .type = TI_SYSC_PRUSS, 2762 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2763 .regbits = &sysc_regbits_omap4_simple, 2764 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2765 }; 2766 2767 static int sysc_init_pdata(struct sysc *ddata) 2768 { 2769 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2770 struct ti_sysc_module_data *mdata; 2771 2772 if (!pdata) 2773 return 0; 2774 2775 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2776 if (!mdata) 2777 return -ENOMEM; 2778 2779 if (ddata->legacy_mode) { 2780 mdata->name = ddata->legacy_mode; 2781 mdata->module_pa = ddata->module_pa; 2782 mdata->module_size = ddata->module_size; 2783 mdata->offsets = ddata->offsets; 2784 mdata->nr_offsets = SYSC_MAX_REGS; 2785 mdata->cap = ddata->cap; 2786 mdata->cfg = &ddata->cfg; 2787 } 2788 2789 ddata->mdata = mdata; 2790 2791 return 0; 2792 } 2793 2794 static int sysc_init_match(struct sysc *ddata) 2795 { 2796 const struct sysc_capabilities *cap; 2797 2798 cap = of_device_get_match_data(ddata->dev); 2799 if (!cap) 2800 return -EINVAL; 2801 2802 ddata->cap = cap; 2803 if (ddata->cap) 2804 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2805 2806 return 0; 2807 } 2808 2809 static void ti_sysc_idle(struct work_struct *work) 2810 { 2811 struct sysc *ddata; 2812 2813 ddata = container_of(work, struct sysc, idle_work.work); 2814 2815 /* 2816 * One time decrement of clock usage counts if left on from init. 2817 * Note that we disable opt clocks unconditionally in this case 2818 * as they are enabled unconditionally during init without 2819 * considering sysc_opt_clks_needed() at that point. 2820 */ 2821 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2822 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2823 sysc_disable_main_clocks(ddata); 2824 sysc_disable_opt_clocks(ddata); 2825 sysc_clkdm_allow_idle(ddata); 2826 } 2827 2828 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2829 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2830 return; 2831 2832 /* 2833 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2834 * and SYSC_QUIRK_NO_RESET_ON_INIT 2835 */ 2836 if (pm_runtime_active(ddata->dev)) 2837 pm_runtime_put_sync(ddata->dev); 2838 } 2839 2840 /* 2841 * SoC model and features detection. Only needed for SoCs that need 2842 * special handling for quirks, no need to list others. 2843 */ 2844 static const struct soc_device_attribute sysc_soc_match[] = { 2845 SOC_FLAG("OMAP242*", SOC_2420), 2846 SOC_FLAG("OMAP243*", SOC_2430), 2847 SOC_FLAG("OMAP3[45]*", SOC_3430), 2848 SOC_FLAG("OMAP3[67]*", SOC_3630), 2849 SOC_FLAG("OMAP443*", SOC_4430), 2850 SOC_FLAG("OMAP446*", SOC_4460), 2851 SOC_FLAG("OMAP447*", SOC_4470), 2852 SOC_FLAG("OMAP54*", SOC_5430), 2853 SOC_FLAG("AM433", SOC_AM3), 2854 SOC_FLAG("AM43*", SOC_AM4), 2855 SOC_FLAG("DRA7*", SOC_DRA7), 2856 2857 { /* sentinel */ }, 2858 }; 2859 2860 /* 2861 * List of SoCs variants with disabled features. By default we assume all 2862 * devices in the device tree are available so no need to list those SoCs. 2863 */ 2864 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2865 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2866 SOC_FLAG("AM3505", DIS_SGX), 2867 SOC_FLAG("OMAP3525", DIS_SGX), 2868 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2869 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2870 2871 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2872 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2873 SOC_FLAG("DM3725", DIS_SGX), 2874 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2875 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2876 SOC_FLAG("OMAP3621", DIS_ISP), 2877 2878 { /* sentinel */ }, 2879 }; 2880 2881 static int sysc_add_disabled(unsigned long base) 2882 { 2883 struct sysc_address *disabled_module; 2884 2885 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2886 if (!disabled_module) 2887 return -ENOMEM; 2888 2889 disabled_module->base = base; 2890 2891 mutex_lock(&sysc_soc->list_lock); 2892 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2893 mutex_unlock(&sysc_soc->list_lock); 2894 2895 return 0; 2896 } 2897 2898 /* 2899 * One time init to detect the booted SoC and disable unavailable features. 2900 * Note that we initialize static data shared across all ti-sysc instances 2901 * so ddata is only used for SoC type. This can be called from module_init 2902 * once we no longer need to rely on platform data. 2903 */ 2904 static int sysc_init_soc(struct sysc *ddata) 2905 { 2906 const struct soc_device_attribute *match; 2907 struct ti_sysc_platform_data *pdata; 2908 unsigned long features = 0; 2909 struct device_node *np; 2910 2911 if (sysc_soc) 2912 return 0; 2913 2914 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2915 if (!sysc_soc) 2916 return -ENOMEM; 2917 2918 mutex_init(&sysc_soc->list_lock); 2919 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2920 sysc_soc->general_purpose = true; 2921 2922 pdata = dev_get_platdata(ddata->dev); 2923 if (pdata && pdata->soc_type_gp) 2924 sysc_soc->general_purpose = pdata->soc_type_gp(); 2925 2926 match = soc_device_match(sysc_soc_match); 2927 if (match && match->data) 2928 sysc_soc->soc = (int)match->data; 2929 2930 /* 2931 * Check and warn about possible old incomplete dtb. We now want to see 2932 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 2933 */ 2934 switch (sysc_soc->soc) { 2935 case SOC_AM3: 2936 case SOC_AM4: 2937 case SOC_4430 ... SOC_4470: 2938 case SOC_5430: 2939 case SOC_DRA7: 2940 np = of_find_node_by_path("/ocp"); 2941 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 2942 "ti-sysc: Incomplete old dtb, please update\n"); 2943 break; 2944 default: 2945 break; 2946 } 2947 2948 /* Ignore devices that are not available on HS and EMU SoCs */ 2949 if (!sysc_soc->general_purpose) { 2950 switch (sysc_soc->soc) { 2951 case SOC_3430 ... SOC_3630: 2952 sysc_add_disabled(0x48304000); /* timer12 */ 2953 break; 2954 default: 2955 break; 2956 } 2957 } 2958 2959 match = soc_device_match(sysc_soc_feat_match); 2960 if (!match) 2961 return 0; 2962 2963 if (match->data) 2964 features = (unsigned long)match->data; 2965 2966 /* 2967 * Add disabled devices to the list based on the module base. 2968 * Note that this must be done before we attempt to access the 2969 * device and have module revision checks working. 2970 */ 2971 if (features & DIS_ISP) 2972 sysc_add_disabled(0x480bd400); 2973 if (features & DIS_IVA) 2974 sysc_add_disabled(0x5d000000); 2975 if (features & DIS_SGX) 2976 sysc_add_disabled(0x50000000); 2977 2978 return 0; 2979 } 2980 2981 static void sysc_cleanup_soc(void) 2982 { 2983 struct sysc_address *disabled_module; 2984 struct list_head *pos, *tmp; 2985 2986 if (!sysc_soc) 2987 return; 2988 2989 mutex_lock(&sysc_soc->list_lock); 2990 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 2991 disabled_module = list_entry(pos, struct sysc_address, node); 2992 list_del(pos); 2993 kfree(disabled_module); 2994 } 2995 mutex_unlock(&sysc_soc->list_lock); 2996 } 2997 2998 static int sysc_check_disabled_devices(struct sysc *ddata) 2999 { 3000 struct sysc_address *disabled_module; 3001 struct list_head *pos; 3002 int error = 0; 3003 3004 mutex_lock(&sysc_soc->list_lock); 3005 list_for_each(pos, &sysc_soc->disabled_modules) { 3006 disabled_module = list_entry(pos, struct sysc_address, node); 3007 if (ddata->module_pa == disabled_module->base) { 3008 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3009 error = -ENODEV; 3010 break; 3011 } 3012 } 3013 mutex_unlock(&sysc_soc->list_lock); 3014 3015 return error; 3016 } 3017 3018 /* 3019 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3020 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3021 * are needed, we could also look at the timer register configuration. 3022 */ 3023 static int sysc_check_active_timer(struct sysc *ddata) 3024 { 3025 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3026 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3027 return 0; 3028 3029 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3030 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3031 return -ENXIO; 3032 3033 return 0; 3034 } 3035 3036 static const struct of_device_id sysc_match_table[] = { 3037 { .compatible = "simple-bus", }, 3038 { /* sentinel */ }, 3039 }; 3040 3041 static int sysc_probe(struct platform_device *pdev) 3042 { 3043 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3044 struct sysc *ddata; 3045 int error; 3046 3047 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3048 if (!ddata) 3049 return -ENOMEM; 3050 3051 ddata->offsets[SYSC_REVISION] = -ENODEV; 3052 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3053 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3054 ddata->dev = &pdev->dev; 3055 platform_set_drvdata(pdev, ddata); 3056 3057 error = sysc_init_soc(ddata); 3058 if (error) 3059 return error; 3060 3061 error = sysc_init_match(ddata); 3062 if (error) 3063 return error; 3064 3065 error = sysc_init_dts_quirks(ddata); 3066 if (error) 3067 return error; 3068 3069 error = sysc_map_and_check_registers(ddata); 3070 if (error) 3071 return error; 3072 3073 error = sysc_init_sysc_mask(ddata); 3074 if (error) 3075 return error; 3076 3077 error = sysc_init_idlemodes(ddata); 3078 if (error) 3079 return error; 3080 3081 error = sysc_init_syss_mask(ddata); 3082 if (error) 3083 return error; 3084 3085 error = sysc_init_pdata(ddata); 3086 if (error) 3087 return error; 3088 3089 sysc_init_early_quirks(ddata); 3090 3091 error = sysc_check_disabled_devices(ddata); 3092 if (error) 3093 return error; 3094 3095 error = sysc_check_active_timer(ddata); 3096 if (error) 3097 return error; 3098 3099 error = sysc_get_clocks(ddata); 3100 if (error) 3101 return error; 3102 3103 error = sysc_init_resets(ddata); 3104 if (error) 3105 goto unprepare; 3106 3107 error = sysc_init_module(ddata); 3108 if (error) 3109 goto unprepare; 3110 3111 pm_runtime_enable(ddata->dev); 3112 error = pm_runtime_get_sync(ddata->dev); 3113 if (error < 0) { 3114 pm_runtime_put_noidle(ddata->dev); 3115 pm_runtime_disable(ddata->dev); 3116 goto unprepare; 3117 } 3118 3119 /* Balance use counts as PM runtime should have enabled these all */ 3120 if (!(ddata->cfg.quirks & 3121 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3122 sysc_disable_main_clocks(ddata); 3123 sysc_disable_opt_clocks(ddata); 3124 sysc_clkdm_allow_idle(ddata); 3125 } 3126 3127 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3128 reset_control_assert(ddata->rsts); 3129 3130 sysc_show_registers(ddata); 3131 3132 ddata->dev->type = &sysc_device_type; 3133 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 3134 pdata ? pdata->auxdata : NULL, 3135 ddata->dev); 3136 if (error) 3137 goto err; 3138 3139 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3140 3141 /* At least earlycon won't survive without deferred idle */ 3142 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3143 SYSC_QUIRK_NO_IDLE_ON_INIT | 3144 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3145 schedule_delayed_work(&ddata->idle_work, 3000); 3146 } else { 3147 pm_runtime_put(&pdev->dev); 3148 } 3149 3150 return 0; 3151 3152 err: 3153 pm_runtime_put_sync(&pdev->dev); 3154 pm_runtime_disable(&pdev->dev); 3155 unprepare: 3156 sysc_unprepare(ddata); 3157 3158 return error; 3159 } 3160 3161 static int sysc_remove(struct platform_device *pdev) 3162 { 3163 struct sysc *ddata = platform_get_drvdata(pdev); 3164 int error; 3165 3166 cancel_delayed_work_sync(&ddata->idle_work); 3167 3168 error = pm_runtime_get_sync(ddata->dev); 3169 if (error < 0) { 3170 pm_runtime_put_noidle(ddata->dev); 3171 pm_runtime_disable(ddata->dev); 3172 goto unprepare; 3173 } 3174 3175 of_platform_depopulate(&pdev->dev); 3176 3177 pm_runtime_put_sync(&pdev->dev); 3178 pm_runtime_disable(&pdev->dev); 3179 3180 if (!reset_control_status(ddata->rsts)) 3181 reset_control_assert(ddata->rsts); 3182 3183 unprepare: 3184 sysc_unprepare(ddata); 3185 3186 return 0; 3187 } 3188 3189 static const struct of_device_id sysc_match[] = { 3190 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3191 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3192 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3193 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3194 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3195 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3196 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3197 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3198 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3199 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3200 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3201 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3202 { .compatible = "ti,sysc-usb-host-fs", 3203 .data = &sysc_omap4_usb_host_fs, }, 3204 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3205 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3206 { }, 3207 }; 3208 MODULE_DEVICE_TABLE(of, sysc_match); 3209 3210 static struct platform_driver sysc_driver = { 3211 .probe = sysc_probe, 3212 .remove = sysc_remove, 3213 .driver = { 3214 .name = "ti-sysc", 3215 .of_match_table = sysc_match, 3216 .pm = &sysc_pm_ops, 3217 }, 3218 }; 3219 3220 static int __init sysc_init(void) 3221 { 3222 bus_register_notifier(&platform_bus_type, &sysc_nb); 3223 3224 return platform_driver_register(&sysc_driver); 3225 } 3226 module_init(sysc_init); 3227 3228 static void __exit sysc_exit(void) 3229 { 3230 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3231 platform_driver_unregister(&sysc_driver); 3232 sysc_cleanup_soc(); 3233 } 3234 module_exit(sysc_exit); 3235 3236 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3237 MODULE_LICENSE("GPL v2"); 3238