1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/delay.h> 10 #include <linux/list.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_domain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/slab.h> 19 #include <linux/sys_soc.h> 20 #include <linux/iopoll.h> 21 22 #include <linux/platform_data/ti-sysc.h> 23 24 #include <dt-bindings/bus/ti-sysc.h> 25 26 #define DIS_ISP BIT(2) 27 #define DIS_IVA BIT(1) 28 #define DIS_SGX BIT(0) 29 30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 enum sysc_soc { 35 SOC_UNKNOWN, 36 SOC_2420, 37 SOC_2430, 38 SOC_3430, 39 SOC_3630, 40 SOC_4430, 41 SOC_4460, 42 SOC_4470, 43 SOC_5430, 44 SOC_AM3, 45 SOC_AM4, 46 SOC_DRA7, 47 }; 48 49 struct sysc_address { 50 unsigned long base; 51 struct list_head node; 52 }; 53 54 struct sysc_soc_info { 55 unsigned long general_purpose:1; 56 enum sysc_soc soc; 57 struct mutex list_lock; /* disabled modules list lock */ 58 struct list_head disabled_modules; 59 }; 60 61 enum sysc_clocks { 62 SYSC_FCK, 63 SYSC_ICK, 64 SYSC_OPTFCK0, 65 SYSC_OPTFCK1, 66 SYSC_OPTFCK2, 67 SYSC_OPTFCK3, 68 SYSC_OPTFCK4, 69 SYSC_OPTFCK5, 70 SYSC_OPTFCK6, 71 SYSC_OPTFCK7, 72 SYSC_MAX_CLOCKS, 73 }; 74 75 static struct sysc_soc_info *sysc_soc; 76 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 77 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 79 "opt5", "opt6", "opt7", 80 }; 81 82 #define SYSC_IDLEMODE_MASK 3 83 #define SYSC_CLOCKACTIVITY_MASK 3 84 85 /** 86 * struct sysc - TI sysc interconnect target module registers and capabilities 87 * @dev: struct device pointer 88 * @module_pa: physical address of the interconnect target module 89 * @module_size: size of the interconnect target module 90 * @module_va: virtual address of the interconnect target module 91 * @offsets: register offsets from module base 92 * @mdata: ti-sysc to hwmod translation data for a module 93 * @clocks: clocks used by the interconnect target module 94 * @clock_roles: clock role names for the found clocks 95 * @nr_clocks: number of clocks used by the interconnect target module 96 * @rsts: resets used by the interconnect target module 97 * @legacy_mode: configured for legacy mode if set 98 * @cap: interconnect target module capabilities 99 * @cfg: interconnect target module configuration 100 * @cookie: data used by legacy platform callbacks 101 * @name: name if available 102 * @revision: interconnect target module revision 103 * @enabled: sysc runtime enabled status 104 * @needs_resume: runtime resume needed on resume from suspend 105 * @child_needs_resume: runtime resume needed for child on resume from suspend 106 * @disable_on_idle: status flag used for disabling modules with resets 107 * @idle_work: work structure used to perform delayed idle on a module 108 * @pre_reset_quirk: module specific pre-reset quirk 109 * @post_reset_quirk: module specific post-reset quirk 110 * @reset_done_quirk: module specific reset done quirk 111 * @module_enable_quirk: module specific enable quirk 112 * @module_disable_quirk: module specific disable quirk 113 * @module_unlock_quirk: module specific sysconfig unlock quirk 114 * @module_lock_quirk: module specific sysconfig lock quirk 115 */ 116 struct sysc { 117 struct device *dev; 118 u64 module_pa; 119 u32 module_size; 120 void __iomem *module_va; 121 int offsets[SYSC_MAX_REGS]; 122 struct ti_sysc_module_data *mdata; 123 struct clk **clocks; 124 const char **clock_roles; 125 int nr_clocks; 126 struct reset_control *rsts; 127 const char *legacy_mode; 128 const struct sysc_capabilities *cap; 129 struct sysc_config cfg; 130 struct ti_sysc_cookie cookie; 131 const char *name; 132 u32 revision; 133 unsigned int enabled:1; 134 unsigned int needs_resume:1; 135 unsigned int child_needs_resume:1; 136 struct delayed_work idle_work; 137 void (*pre_reset_quirk)(struct sysc *sysc); 138 void (*post_reset_quirk)(struct sysc *sysc); 139 void (*reset_done_quirk)(struct sysc *sysc); 140 void (*module_enable_quirk)(struct sysc *sysc); 141 void (*module_disable_quirk)(struct sysc *sysc); 142 void (*module_unlock_quirk)(struct sysc *sysc); 143 void (*module_lock_quirk)(struct sysc *sysc); 144 }; 145 146 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 147 bool is_child); 148 149 static void sysc_write(struct sysc *ddata, int offset, u32 value) 150 { 151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 152 writew_relaxed(value & 0xffff, ddata->module_va + offset); 153 154 /* Only i2c revision has LO and HI register with stride of 4 */ 155 if (ddata->offsets[SYSC_REVISION] >= 0 && 156 offset == ddata->offsets[SYSC_REVISION]) { 157 u16 hi = value >> 16; 158 159 writew_relaxed(hi, ddata->module_va + offset + 4); 160 } 161 162 return; 163 } 164 165 writel_relaxed(value, ddata->module_va + offset); 166 } 167 168 static u32 sysc_read(struct sysc *ddata, int offset) 169 { 170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 171 u32 val; 172 173 val = readw_relaxed(ddata->module_va + offset); 174 175 /* Only i2c revision has LO and HI register with stride of 4 */ 176 if (ddata->offsets[SYSC_REVISION] >= 0 && 177 offset == ddata->offsets[SYSC_REVISION]) { 178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 179 180 val |= tmp << 16; 181 } 182 183 return val; 184 } 185 186 return readl_relaxed(ddata->module_va + offset); 187 } 188 189 static bool sysc_opt_clks_needed(struct sysc *ddata) 190 { 191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 192 } 193 194 static u32 sysc_read_revision(struct sysc *ddata) 195 { 196 int offset = ddata->offsets[SYSC_REVISION]; 197 198 if (offset < 0) 199 return 0; 200 201 return sysc_read(ddata, offset); 202 } 203 204 static u32 sysc_read_sysconfig(struct sysc *ddata) 205 { 206 int offset = ddata->offsets[SYSC_SYSCONFIG]; 207 208 if (offset < 0) 209 return 0; 210 211 return sysc_read(ddata, offset); 212 } 213 214 static u32 sysc_read_sysstatus(struct sysc *ddata) 215 { 216 int offset = ddata->offsets[SYSC_SYSSTATUS]; 217 218 if (offset < 0) 219 return 0; 220 221 return sysc_read(ddata, offset); 222 } 223 224 /* Poll on reset status */ 225 static int sysc_wait_softreset(struct sysc *ddata) 226 { 227 u32 sysc_mask, syss_done, rstval; 228 int syss_offset, error = 0; 229 230 if (ddata->cap->regbits->srst_shift < 0) 231 return 0; 232 233 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 234 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 235 236 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 237 syss_done = 0; 238 else 239 syss_done = ddata->cfg.syss_mask; 240 241 if (syss_offset >= 0) { 242 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 243 rstval, (rstval & ddata->cfg.syss_mask) == 244 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 245 246 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 247 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 248 rstval, !(rstval & sysc_mask), 249 100, MAX_MODULE_SOFTRESET_WAIT); 250 } 251 252 return error; 253 } 254 255 static int sysc_add_named_clock_from_child(struct sysc *ddata, 256 const char *name, 257 const char *optfck_name) 258 { 259 struct device_node *np = ddata->dev->of_node; 260 struct device_node *child; 261 struct clk_lookup *cl; 262 struct clk *clock; 263 const char *n; 264 265 if (name) 266 n = name; 267 else 268 n = optfck_name; 269 270 /* Does the clock alias already exist? */ 271 clock = of_clk_get_by_name(np, n); 272 if (!IS_ERR(clock)) { 273 clk_put(clock); 274 275 return 0; 276 } 277 278 child = of_get_next_available_child(np, NULL); 279 if (!child) 280 return -ENODEV; 281 282 clock = devm_get_clk_from_child(ddata->dev, child, name); 283 if (IS_ERR(clock)) 284 return PTR_ERR(clock); 285 286 /* 287 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 288 * limit for clk_get(). If cl ever needs to be freed, it should be done 289 * with clkdev_drop(). 290 */ 291 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); 292 if (!cl) 293 return -ENOMEM; 294 295 cl->con_id = n; 296 cl->dev_id = dev_name(ddata->dev); 297 cl->clk = clock; 298 clkdev_add(cl); 299 300 clk_put(clock); 301 302 return 0; 303 } 304 305 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 306 { 307 const char *optfck_name; 308 int error, index; 309 310 if (ddata->nr_clocks < SYSC_OPTFCK0) 311 index = SYSC_OPTFCK0; 312 else 313 index = ddata->nr_clocks; 314 315 if (name) 316 optfck_name = name; 317 else 318 optfck_name = clock_names[index]; 319 320 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 321 if (error) 322 return error; 323 324 ddata->clock_roles[index] = optfck_name; 325 ddata->nr_clocks++; 326 327 return 0; 328 } 329 330 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 331 { 332 int error, i, index = -ENODEV; 333 334 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 335 index = SYSC_FCK; 336 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 337 index = SYSC_ICK; 338 339 if (index < 0) { 340 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 341 if (!ddata->clocks[i]) { 342 index = i; 343 break; 344 } 345 } 346 } 347 348 if (index < 0) { 349 dev_err(ddata->dev, "clock %s not added\n", name); 350 return index; 351 } 352 353 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 354 if (IS_ERR(ddata->clocks[index])) { 355 dev_err(ddata->dev, "clock get error for %s: %li\n", 356 name, PTR_ERR(ddata->clocks[index])); 357 358 return PTR_ERR(ddata->clocks[index]); 359 } 360 361 error = clk_prepare(ddata->clocks[index]); 362 if (error) { 363 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 364 name, error); 365 366 return error; 367 } 368 369 return 0; 370 } 371 372 static int sysc_get_clocks(struct sysc *ddata) 373 { 374 struct device_node *np = ddata->dev->of_node; 375 struct property *prop; 376 const char *name; 377 int nr_fck = 0, nr_ick = 0, i, error = 0; 378 379 ddata->clock_roles = devm_kcalloc(ddata->dev, 380 SYSC_MAX_CLOCKS, 381 sizeof(*ddata->clock_roles), 382 GFP_KERNEL); 383 if (!ddata->clock_roles) 384 return -ENOMEM; 385 386 of_property_for_each_string(np, "clock-names", prop, name) { 387 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 388 nr_fck++; 389 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 390 nr_ick++; 391 ddata->clock_roles[ddata->nr_clocks] = name; 392 ddata->nr_clocks++; 393 } 394 395 if (ddata->nr_clocks < 1) 396 return 0; 397 398 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 399 error = sysc_init_ext_opt_clock(ddata, NULL); 400 if (error) 401 return error; 402 } 403 404 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 405 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 406 407 return -EINVAL; 408 } 409 410 if (nr_fck > 1 || nr_ick > 1) { 411 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 412 413 return -EINVAL; 414 } 415 416 /* Always add a slot for main clocks fck and ick even if unused */ 417 if (!nr_fck) 418 ddata->nr_clocks++; 419 if (!nr_ick) 420 ddata->nr_clocks++; 421 422 ddata->clocks = devm_kcalloc(ddata->dev, 423 ddata->nr_clocks, sizeof(*ddata->clocks), 424 GFP_KERNEL); 425 if (!ddata->clocks) 426 return -ENOMEM; 427 428 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 429 const char *name = ddata->clock_roles[i]; 430 431 if (!name) 432 continue; 433 434 error = sysc_get_one_clock(ddata, name); 435 if (error) 436 return error; 437 } 438 439 return 0; 440 } 441 442 static int sysc_enable_main_clocks(struct sysc *ddata) 443 { 444 struct clk *clock; 445 int i, error; 446 447 if (!ddata->clocks) 448 return 0; 449 450 for (i = 0; i < SYSC_OPTFCK0; i++) { 451 clock = ddata->clocks[i]; 452 453 /* Main clocks may not have ick */ 454 if (IS_ERR_OR_NULL(clock)) 455 continue; 456 457 error = clk_enable(clock); 458 if (error) 459 goto err_disable; 460 } 461 462 return 0; 463 464 err_disable: 465 for (i--; i >= 0; i--) { 466 clock = ddata->clocks[i]; 467 468 /* Main clocks may not have ick */ 469 if (IS_ERR_OR_NULL(clock)) 470 continue; 471 472 clk_disable(clock); 473 } 474 475 return error; 476 } 477 478 static void sysc_disable_main_clocks(struct sysc *ddata) 479 { 480 struct clk *clock; 481 int i; 482 483 if (!ddata->clocks) 484 return; 485 486 for (i = 0; i < SYSC_OPTFCK0; i++) { 487 clock = ddata->clocks[i]; 488 if (IS_ERR_OR_NULL(clock)) 489 continue; 490 491 clk_disable(clock); 492 } 493 } 494 495 static int sysc_enable_opt_clocks(struct sysc *ddata) 496 { 497 struct clk *clock; 498 int i, error; 499 500 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 501 return 0; 502 503 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 504 clock = ddata->clocks[i]; 505 506 /* Assume no holes for opt clocks */ 507 if (IS_ERR_OR_NULL(clock)) 508 return 0; 509 510 error = clk_enable(clock); 511 if (error) 512 goto err_disable; 513 } 514 515 return 0; 516 517 err_disable: 518 for (i--; i >= 0; i--) { 519 clock = ddata->clocks[i]; 520 if (IS_ERR_OR_NULL(clock)) 521 continue; 522 523 clk_disable(clock); 524 } 525 526 return error; 527 } 528 529 static void sysc_disable_opt_clocks(struct sysc *ddata) 530 { 531 struct clk *clock; 532 int i; 533 534 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 535 return; 536 537 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 538 clock = ddata->clocks[i]; 539 540 /* Assume no holes for opt clocks */ 541 if (IS_ERR_OR_NULL(clock)) 542 return; 543 544 clk_disable(clock); 545 } 546 } 547 548 static void sysc_clkdm_deny_idle(struct sysc *ddata) 549 { 550 struct ti_sysc_platform_data *pdata; 551 552 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 553 return; 554 555 pdata = dev_get_platdata(ddata->dev); 556 if (pdata && pdata->clkdm_deny_idle) 557 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 558 } 559 560 static void sysc_clkdm_allow_idle(struct sysc *ddata) 561 { 562 struct ti_sysc_platform_data *pdata; 563 564 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 565 return; 566 567 pdata = dev_get_platdata(ddata->dev); 568 if (pdata && pdata->clkdm_allow_idle) 569 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 570 } 571 572 /** 573 * sysc_init_resets - init rstctrl reset line if configured 574 * @ddata: device driver data 575 * 576 * See sysc_rstctrl_reset_deassert(). 577 */ 578 static int sysc_init_resets(struct sysc *ddata) 579 { 580 ddata->rsts = 581 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 582 583 return PTR_ERR_OR_ZERO(ddata->rsts); 584 } 585 586 /** 587 * sysc_parse_and_check_child_range - parses module IO region from ranges 588 * @ddata: device driver data 589 * 590 * In general we only need rev, syss, and sysc registers and not the whole 591 * module range. But we do want the offsets for these registers from the 592 * module base. This allows us to check them against the legacy hwmod 593 * platform data. Let's also check the ranges are configured properly. 594 */ 595 static int sysc_parse_and_check_child_range(struct sysc *ddata) 596 { 597 struct device_node *np = ddata->dev->of_node; 598 const __be32 *ranges; 599 u32 nr_addr, nr_size; 600 int len, error; 601 602 ranges = of_get_property(np, "ranges", &len); 603 if (!ranges) { 604 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 605 606 return -ENOENT; 607 } 608 609 len /= sizeof(*ranges); 610 611 if (len < 3) { 612 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 613 614 return -EINVAL; 615 } 616 617 error = of_property_read_u32(np, "#address-cells", &nr_addr); 618 if (error) 619 return -ENOENT; 620 621 error = of_property_read_u32(np, "#size-cells", &nr_size); 622 if (error) 623 return -ENOENT; 624 625 if (nr_addr != 1 || nr_size != 1) { 626 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 627 628 return -EINVAL; 629 } 630 631 ranges++; 632 ddata->module_pa = of_translate_address(np, ranges++); 633 ddata->module_size = be32_to_cpup(ranges); 634 635 return 0; 636 } 637 638 static struct device_node *stdout_path; 639 640 static void sysc_init_stdout_path(struct sysc *ddata) 641 { 642 struct device_node *np = NULL; 643 const char *uart; 644 645 if (IS_ERR(stdout_path)) 646 return; 647 648 if (stdout_path) 649 return; 650 651 np = of_find_node_by_path("/chosen"); 652 if (!np) 653 goto err; 654 655 uart = of_get_property(np, "stdout-path", NULL); 656 if (!uart) 657 goto err; 658 659 np = of_find_node_by_path(uart); 660 if (!np) 661 goto err; 662 663 stdout_path = np; 664 665 return; 666 667 err: 668 stdout_path = ERR_PTR(-ENODEV); 669 } 670 671 static void sysc_check_quirk_stdout(struct sysc *ddata, 672 struct device_node *np) 673 { 674 sysc_init_stdout_path(ddata); 675 if (np != stdout_path) 676 return; 677 678 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 679 SYSC_QUIRK_NO_RESET_ON_INIT; 680 } 681 682 /** 683 * sysc_check_one_child - check child configuration 684 * @ddata: device driver data 685 * @np: child device node 686 * 687 * Let's avoid messy situations where we have new interconnect target 688 * node but children have "ti,hwmods". These belong to the interconnect 689 * target node and are managed by this driver. 690 */ 691 static void sysc_check_one_child(struct sysc *ddata, 692 struct device_node *np) 693 { 694 const char *name; 695 696 name = of_get_property(np, "ti,hwmods", NULL); 697 if (name && !of_device_is_compatible(np, "ti,sysc")) 698 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 699 700 sysc_check_quirk_stdout(ddata, np); 701 sysc_parse_dts_quirks(ddata, np, true); 702 } 703 704 static void sysc_check_children(struct sysc *ddata) 705 { 706 struct device_node *child; 707 708 for_each_child_of_node(ddata->dev->of_node, child) 709 sysc_check_one_child(ddata, child); 710 } 711 712 /* 713 * So far only I2C uses 16-bit read access with clockactivity with revision 714 * in two registers with stride of 4. We can detect this based on the rev 715 * register size to configure things far enough to be able to properly read 716 * the revision register. 717 */ 718 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 719 { 720 if (resource_size(res) == 8) 721 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 722 } 723 724 /** 725 * sysc_parse_one - parses the interconnect target module registers 726 * @ddata: device driver data 727 * @reg: register to parse 728 */ 729 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 730 { 731 struct resource *res; 732 const char *name; 733 734 switch (reg) { 735 case SYSC_REVISION: 736 case SYSC_SYSCONFIG: 737 case SYSC_SYSSTATUS: 738 name = reg_names[reg]; 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 res = platform_get_resource_byname(to_platform_device(ddata->dev), 745 IORESOURCE_MEM, name); 746 if (!res) { 747 ddata->offsets[reg] = -ENODEV; 748 749 return 0; 750 } 751 752 ddata->offsets[reg] = res->start - ddata->module_pa; 753 if (reg == SYSC_REVISION) 754 sysc_check_quirk_16bit(ddata, res); 755 756 return 0; 757 } 758 759 static int sysc_parse_registers(struct sysc *ddata) 760 { 761 int i, error; 762 763 for (i = 0; i < SYSC_MAX_REGS; i++) { 764 error = sysc_parse_one(ddata, i); 765 if (error) 766 return error; 767 } 768 769 return 0; 770 } 771 772 /** 773 * sysc_check_registers - check for misconfigured register overlaps 774 * @ddata: device driver data 775 */ 776 static int sysc_check_registers(struct sysc *ddata) 777 { 778 int i, j, nr_regs = 0, nr_matches = 0; 779 780 for (i = 0; i < SYSC_MAX_REGS; i++) { 781 if (ddata->offsets[i] < 0) 782 continue; 783 784 if (ddata->offsets[i] > (ddata->module_size - 4)) { 785 dev_err(ddata->dev, "register outside module range"); 786 787 return -EINVAL; 788 } 789 790 for (j = 0; j < SYSC_MAX_REGS; j++) { 791 if (ddata->offsets[j] < 0) 792 continue; 793 794 if (ddata->offsets[i] == ddata->offsets[j]) 795 nr_matches++; 796 } 797 nr_regs++; 798 } 799 800 if (nr_matches > nr_regs) { 801 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 802 nr_regs, nr_matches); 803 804 return -EINVAL; 805 } 806 807 return 0; 808 } 809 810 /** 811 * syc_ioremap - ioremap register space for the interconnect target module 812 * @ddata: device driver data 813 * 814 * Note that the interconnect target module registers can be anywhere 815 * within the interconnect target module range. For example, SGX has 816 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 817 * has them at offset 0x1200 in the CPSW_WR child. Usually the 818 * the interconnect target module registers are at the beginning of 819 * the module range though. 820 */ 821 static int sysc_ioremap(struct sysc *ddata) 822 { 823 int size; 824 825 if (ddata->offsets[SYSC_REVISION] < 0 && 826 ddata->offsets[SYSC_SYSCONFIG] < 0 && 827 ddata->offsets[SYSC_SYSSTATUS] < 0) { 828 size = ddata->module_size; 829 } else { 830 size = max3(ddata->offsets[SYSC_REVISION], 831 ddata->offsets[SYSC_SYSCONFIG], 832 ddata->offsets[SYSC_SYSSTATUS]); 833 834 if (size < SZ_1K) 835 size = SZ_1K; 836 837 if ((size + sizeof(u32)) > ddata->module_size) 838 size = ddata->module_size; 839 } 840 841 ddata->module_va = devm_ioremap(ddata->dev, 842 ddata->module_pa, 843 size + sizeof(u32)); 844 if (!ddata->module_va) 845 return -EIO; 846 847 return 0; 848 } 849 850 /** 851 * sysc_map_and_check_registers - ioremap and check device registers 852 * @ddata: device driver data 853 */ 854 static int sysc_map_and_check_registers(struct sysc *ddata) 855 { 856 struct device_node *np = ddata->dev->of_node; 857 int error; 858 859 if (!of_get_property(np, "reg", NULL)) 860 return 0; 861 862 error = sysc_parse_and_check_child_range(ddata); 863 if (error) 864 return error; 865 866 sysc_check_children(ddata); 867 868 error = sysc_parse_registers(ddata); 869 if (error) 870 return error; 871 872 error = sysc_ioremap(ddata); 873 if (error) 874 return error; 875 876 error = sysc_check_registers(ddata); 877 if (error) 878 return error; 879 880 return 0; 881 } 882 883 /** 884 * sysc_show_rev - read and show interconnect target module revision 885 * @bufp: buffer to print the information to 886 * @ddata: device driver data 887 */ 888 static int sysc_show_rev(char *bufp, struct sysc *ddata) 889 { 890 int len; 891 892 if (ddata->offsets[SYSC_REVISION] < 0) 893 return sprintf(bufp, ":NA"); 894 895 len = sprintf(bufp, ":%08x", ddata->revision); 896 897 return len; 898 } 899 900 static int sysc_show_reg(struct sysc *ddata, 901 char *bufp, enum sysc_registers reg) 902 { 903 if (ddata->offsets[reg] < 0) 904 return sprintf(bufp, ":NA"); 905 906 return sprintf(bufp, ":%x", ddata->offsets[reg]); 907 } 908 909 static int sysc_show_name(char *bufp, struct sysc *ddata) 910 { 911 if (!ddata->name) 912 return 0; 913 914 return sprintf(bufp, ":%s", ddata->name); 915 } 916 917 /** 918 * sysc_show_registers - show information about interconnect target module 919 * @ddata: device driver data 920 */ 921 static void sysc_show_registers(struct sysc *ddata) 922 { 923 char buf[128]; 924 char *bufp = buf; 925 int i; 926 927 for (i = 0; i < SYSC_MAX_REGS; i++) 928 bufp += sysc_show_reg(ddata, bufp, i); 929 930 bufp += sysc_show_rev(bufp, ddata); 931 bufp += sysc_show_name(bufp, ddata); 932 933 dev_dbg(ddata->dev, "%llx:%x%s\n", 934 ddata->module_pa, ddata->module_size, 935 buf); 936 } 937 938 /** 939 * sysc_write_sysconfig - handle sysconfig quirks for register write 940 * @ddata: device driver data 941 * @value: register value 942 */ 943 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 944 { 945 if (ddata->module_unlock_quirk) 946 ddata->module_unlock_quirk(ddata); 947 948 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 949 950 if (ddata->module_lock_quirk) 951 ddata->module_lock_quirk(ddata); 952 } 953 954 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 955 #define SYSC_CLOCACT_ICK 2 956 957 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 958 static int sysc_enable_module(struct device *dev) 959 { 960 struct sysc *ddata; 961 const struct sysc_regbits *regbits; 962 u32 reg, idlemodes, best_mode; 963 int error; 964 965 ddata = dev_get_drvdata(dev); 966 967 /* 968 * Some modules like DSS reset automatically on idle. Enable optional 969 * reset clocks and wait for OCP softreset to complete. 970 */ 971 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 972 error = sysc_enable_opt_clocks(ddata); 973 if (error) { 974 dev_err(ddata->dev, 975 "Optional clocks failed for enable: %i\n", 976 error); 977 return error; 978 } 979 } 980 /* 981 * Some modules like i2c and hdq1w have unusable reset status unless 982 * the module reset quirk is enabled. Skip status check on enable. 983 */ 984 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 985 error = sysc_wait_softreset(ddata); 986 if (error) 987 dev_warn(ddata->dev, "OCP softreset timed out\n"); 988 } 989 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 990 sysc_disable_opt_clocks(ddata); 991 992 /* 993 * Some subsystem private interconnects, like DSS top level module, 994 * need only the automatic OCP softreset handling with no sysconfig 995 * register bits to configure. 996 */ 997 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 998 return 0; 999 1000 regbits = ddata->cap->regbits; 1001 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1002 1003 /* 1004 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1005 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1006 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1007 */ 1008 if (regbits->clkact_shift >= 0 && 1009 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1010 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1011 1012 /* Set SIDLE mode */ 1013 idlemodes = ddata->cfg.sidlemodes; 1014 if (!idlemodes || regbits->sidle_shift < 0) 1015 goto set_midle; 1016 1017 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1018 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1019 best_mode = SYSC_IDLE_NO; 1020 } else { 1021 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1022 if (best_mode > SYSC_IDLE_MASK) { 1023 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1024 return -EINVAL; 1025 } 1026 1027 /* Set WAKEUP */ 1028 if (regbits->enwkup_shift >= 0 && 1029 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1030 reg |= BIT(regbits->enwkup_shift); 1031 } 1032 1033 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1034 reg |= best_mode << regbits->sidle_shift; 1035 sysc_write_sysconfig(ddata, reg); 1036 1037 set_midle: 1038 /* Set MIDLE mode */ 1039 idlemodes = ddata->cfg.midlemodes; 1040 if (!idlemodes || regbits->midle_shift < 0) 1041 goto set_autoidle; 1042 1043 best_mode = fls(ddata->cfg.midlemodes) - 1; 1044 if (best_mode > SYSC_IDLE_MASK) { 1045 dev_err(dev, "%s: invalid midlemode\n", __func__); 1046 return -EINVAL; 1047 } 1048 1049 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1050 best_mode = SYSC_IDLE_NO; 1051 1052 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1053 reg |= best_mode << regbits->midle_shift; 1054 sysc_write_sysconfig(ddata, reg); 1055 1056 set_autoidle: 1057 /* Autoidle bit must enabled separately if available */ 1058 if (regbits->autoidle_shift >= 0 && 1059 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1060 reg |= 1 << regbits->autoidle_shift; 1061 sysc_write_sysconfig(ddata, reg); 1062 } 1063 1064 /* Flush posted write */ 1065 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1066 1067 if (ddata->module_enable_quirk) 1068 ddata->module_enable_quirk(ddata); 1069 1070 return 0; 1071 } 1072 1073 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1074 { 1075 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1076 *best_mode = SYSC_IDLE_SMART_WKUP; 1077 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1078 *best_mode = SYSC_IDLE_SMART; 1079 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1080 *best_mode = SYSC_IDLE_FORCE; 1081 else 1082 return -EINVAL; 1083 1084 return 0; 1085 } 1086 1087 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1088 static int sysc_disable_module(struct device *dev) 1089 { 1090 struct sysc *ddata; 1091 const struct sysc_regbits *regbits; 1092 u32 reg, idlemodes, best_mode; 1093 int ret; 1094 1095 ddata = dev_get_drvdata(dev); 1096 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1097 return 0; 1098 1099 if (ddata->module_disable_quirk) 1100 ddata->module_disable_quirk(ddata); 1101 1102 regbits = ddata->cap->regbits; 1103 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1104 1105 /* Set MIDLE mode */ 1106 idlemodes = ddata->cfg.midlemodes; 1107 if (!idlemodes || regbits->midle_shift < 0) 1108 goto set_sidle; 1109 1110 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1111 if (ret) { 1112 dev_err(dev, "%s: invalid midlemode\n", __func__); 1113 return ret; 1114 } 1115 1116 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1117 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1118 best_mode = SYSC_IDLE_FORCE; 1119 1120 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1121 reg |= best_mode << regbits->midle_shift; 1122 sysc_write_sysconfig(ddata, reg); 1123 1124 set_sidle: 1125 /* Set SIDLE mode */ 1126 idlemodes = ddata->cfg.sidlemodes; 1127 if (!idlemodes || regbits->sidle_shift < 0) 1128 return 0; 1129 1130 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1131 best_mode = SYSC_IDLE_FORCE; 1132 } else { 1133 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1134 if (ret) { 1135 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1136 return ret; 1137 } 1138 } 1139 1140 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1141 reg |= best_mode << regbits->sidle_shift; 1142 if (regbits->autoidle_shift >= 0 && 1143 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1144 reg |= 1 << regbits->autoidle_shift; 1145 sysc_write_sysconfig(ddata, reg); 1146 1147 /* Flush posted write */ 1148 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1149 1150 return 0; 1151 } 1152 1153 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1154 struct sysc *ddata) 1155 { 1156 struct ti_sysc_platform_data *pdata; 1157 int error; 1158 1159 pdata = dev_get_platdata(ddata->dev); 1160 if (!pdata) 1161 return 0; 1162 1163 if (!pdata->idle_module) 1164 return -ENODEV; 1165 1166 error = pdata->idle_module(dev, &ddata->cookie); 1167 if (error) 1168 dev_err(dev, "%s: could not idle: %i\n", 1169 __func__, error); 1170 1171 reset_control_assert(ddata->rsts); 1172 1173 return 0; 1174 } 1175 1176 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1177 struct sysc *ddata) 1178 { 1179 struct ti_sysc_platform_data *pdata; 1180 int error; 1181 1182 pdata = dev_get_platdata(ddata->dev); 1183 if (!pdata) 1184 return 0; 1185 1186 if (!pdata->enable_module) 1187 return -ENODEV; 1188 1189 error = pdata->enable_module(dev, &ddata->cookie); 1190 if (error) 1191 dev_err(dev, "%s: could not enable: %i\n", 1192 __func__, error); 1193 1194 reset_control_deassert(ddata->rsts); 1195 1196 return 0; 1197 } 1198 1199 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1200 { 1201 struct sysc *ddata; 1202 int error = 0; 1203 1204 ddata = dev_get_drvdata(dev); 1205 1206 if (!ddata->enabled) 1207 return 0; 1208 1209 sysc_clkdm_deny_idle(ddata); 1210 1211 if (ddata->legacy_mode) { 1212 error = sysc_runtime_suspend_legacy(dev, ddata); 1213 if (error) 1214 goto err_allow_idle; 1215 } else { 1216 error = sysc_disable_module(dev); 1217 if (error) 1218 goto err_allow_idle; 1219 } 1220 1221 sysc_disable_main_clocks(ddata); 1222 1223 if (sysc_opt_clks_needed(ddata)) 1224 sysc_disable_opt_clocks(ddata); 1225 1226 ddata->enabled = false; 1227 1228 err_allow_idle: 1229 sysc_clkdm_allow_idle(ddata); 1230 1231 reset_control_assert(ddata->rsts); 1232 1233 return error; 1234 } 1235 1236 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1237 { 1238 struct sysc *ddata; 1239 int error = 0; 1240 1241 ddata = dev_get_drvdata(dev); 1242 1243 if (ddata->enabled) 1244 return 0; 1245 1246 1247 sysc_clkdm_deny_idle(ddata); 1248 1249 if (sysc_opt_clks_needed(ddata)) { 1250 error = sysc_enable_opt_clocks(ddata); 1251 if (error) 1252 goto err_allow_idle; 1253 } 1254 1255 error = sysc_enable_main_clocks(ddata); 1256 if (error) 1257 goto err_opt_clocks; 1258 1259 reset_control_deassert(ddata->rsts); 1260 1261 if (ddata->legacy_mode) { 1262 error = sysc_runtime_resume_legacy(dev, ddata); 1263 if (error) 1264 goto err_main_clocks; 1265 } else { 1266 error = sysc_enable_module(dev); 1267 if (error) 1268 goto err_main_clocks; 1269 } 1270 1271 ddata->enabled = true; 1272 1273 sysc_clkdm_allow_idle(ddata); 1274 1275 return 0; 1276 1277 err_main_clocks: 1278 sysc_disable_main_clocks(ddata); 1279 err_opt_clocks: 1280 if (sysc_opt_clks_needed(ddata)) 1281 sysc_disable_opt_clocks(ddata); 1282 err_allow_idle: 1283 sysc_clkdm_allow_idle(ddata); 1284 1285 return error; 1286 } 1287 1288 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1289 { 1290 struct sysc *ddata; 1291 1292 ddata = dev_get_drvdata(dev); 1293 1294 if (ddata->cfg.quirks & 1295 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1296 return 0; 1297 1298 return pm_runtime_force_suspend(dev); 1299 } 1300 1301 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1302 { 1303 struct sysc *ddata; 1304 1305 ddata = dev_get_drvdata(dev); 1306 1307 if (ddata->cfg.quirks & 1308 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1309 return 0; 1310 1311 return pm_runtime_force_resume(dev); 1312 } 1313 1314 static const struct dev_pm_ops sysc_pm_ops = { 1315 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1316 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1317 sysc_runtime_resume, 1318 NULL) 1319 }; 1320 1321 /* Module revision register based quirks */ 1322 struct sysc_revision_quirk { 1323 const char *name; 1324 u32 base; 1325 int rev_offset; 1326 int sysc_offset; 1327 int syss_offset; 1328 u32 revision; 1329 u32 revision_mask; 1330 u32 quirks; 1331 }; 1332 1333 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1334 optrev_val, optrevmask, optquirkmask) \ 1335 { \ 1336 .name = (optname), \ 1337 .base = (optbase), \ 1338 .rev_offset = (optrev), \ 1339 .sysc_offset = (optsysc), \ 1340 .syss_offset = (optsyss), \ 1341 .revision = (optrev_val), \ 1342 .revision_mask = (optrevmask), \ 1343 .quirks = (optquirkmask), \ 1344 } 1345 1346 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1347 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1348 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1349 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1350 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1351 SYSC_QUIRK_LEGACY_IDLE), 1352 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 1353 SYSC_QUIRK_LEGACY_IDLE), 1354 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 1355 SYSC_QUIRK_LEGACY_IDLE), 1356 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1357 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1358 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1359 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1360 /* Uarts on omap4 and later */ 1361 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1362 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1363 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1364 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1365 1366 /* Quirks that need to be set based on the module address */ 1367 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1368 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1369 SYSC_QUIRK_SWSUP_SIDLE), 1370 1371 /* Quirks that need to be set based on detected module */ 1372 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1373 SYSC_MODULE_QUIRK_AESS), 1374 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1375 SYSC_QUIRK_CLKDM_NOAUTO), 1376 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1377 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1378 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1379 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1380 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1381 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1382 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1383 SYSC_QUIRK_CLKDM_NOAUTO), 1384 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1385 SYSC_QUIRK_CLKDM_NOAUTO), 1386 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1387 SYSC_QUIRK_GPMC_DEBUG), 1388 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1389 SYSC_QUIRK_OPT_CLKS_NEEDED), 1390 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1391 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1392 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1393 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1394 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1395 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1396 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1397 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1398 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1399 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1400 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1401 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1402 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1403 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1404 SYSC_MODULE_QUIRK_SGX), 1405 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1406 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1407 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1408 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1409 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1410 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1411 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1412 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1413 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1414 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1415 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1416 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1417 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1418 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1419 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1420 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1421 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1422 SYSC_MODULE_QUIRK_WDT), 1423 /* PRUSS on am3, am4 and am5 */ 1424 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1425 SYSC_MODULE_QUIRK_PRUSS), 1426 /* Watchdog on am3 and am4 */ 1427 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1428 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1429 1430 #ifdef DEBUG 1431 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1432 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1433 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1434 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1435 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1436 0xffff00f0, 0), 1437 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1438 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1439 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1440 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1441 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1442 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1443 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1444 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1445 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1446 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1447 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1448 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1449 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1450 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1451 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1452 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1453 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1454 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1455 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1456 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0), 1457 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1458 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1459 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1460 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1461 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1462 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1463 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1464 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1465 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1466 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1467 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1468 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1469 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1470 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1471 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1472 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1473 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1474 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1475 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1476 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1477 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1478 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1479 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1480 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1481 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1482 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1483 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1484 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1485 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1486 /* Some timers on omap4 and later */ 1487 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1488 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1489 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1490 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1491 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1492 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1493 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1494 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1495 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1496 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1497 #endif 1498 }; 1499 1500 /* 1501 * Early quirks based on module base and register offsets only that are 1502 * needed before the module revision can be read 1503 */ 1504 static void sysc_init_early_quirks(struct sysc *ddata) 1505 { 1506 const struct sysc_revision_quirk *q; 1507 int i; 1508 1509 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1510 q = &sysc_revision_quirks[i]; 1511 1512 if (!q->base) 1513 continue; 1514 1515 if (q->base != ddata->module_pa) 1516 continue; 1517 1518 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1519 continue; 1520 1521 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1522 continue; 1523 1524 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1525 continue; 1526 1527 ddata->name = q->name; 1528 ddata->cfg.quirks |= q->quirks; 1529 } 1530 } 1531 1532 /* Quirks that also consider the revision register value */ 1533 static void sysc_init_revision_quirks(struct sysc *ddata) 1534 { 1535 const struct sysc_revision_quirk *q; 1536 int i; 1537 1538 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1539 q = &sysc_revision_quirks[i]; 1540 1541 if (q->base && q->base != ddata->module_pa) 1542 continue; 1543 1544 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1545 continue; 1546 1547 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1548 continue; 1549 1550 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1551 continue; 1552 1553 if (q->revision == ddata->revision || 1554 (q->revision & q->revision_mask) == 1555 (ddata->revision & q->revision_mask)) { 1556 ddata->name = q->name; 1557 ddata->cfg.quirks |= q->quirks; 1558 } 1559 } 1560 } 1561 1562 /* 1563 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1564 * enabled DSS interrupts. Eventually we may be able to do this on 1565 * dispc init rather than top-level DSS init. 1566 */ 1567 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1568 bool disable) 1569 { 1570 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1571 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1572 int manager_count; 1573 bool framedonetv_irq = true; 1574 u32 val, irq_mask = 0; 1575 1576 switch (sysc_soc->soc) { 1577 case SOC_2420 ... SOC_3630: 1578 manager_count = 2; 1579 framedonetv_irq = false; 1580 break; 1581 case SOC_4430 ... SOC_4470: 1582 manager_count = 3; 1583 break; 1584 case SOC_5430: 1585 case SOC_DRA7: 1586 manager_count = 4; 1587 break; 1588 case SOC_AM4: 1589 manager_count = 1; 1590 framedonetv_irq = false; 1591 break; 1592 case SOC_UNKNOWN: 1593 default: 1594 return 0; 1595 }; 1596 1597 /* Remap the whole module range to be able to reset dispc outputs */ 1598 devm_iounmap(ddata->dev, ddata->module_va); 1599 ddata->module_va = devm_ioremap(ddata->dev, 1600 ddata->module_pa, 1601 ddata->module_size); 1602 if (!ddata->module_va) 1603 return -EIO; 1604 1605 /* DISP_CONTROL */ 1606 val = sysc_read(ddata, dispc_offset + 0x40); 1607 lcd_en = val & lcd_en_mask; 1608 digit_en = val & digit_en_mask; 1609 if (lcd_en) 1610 irq_mask |= BIT(0); /* FRAMEDONE */ 1611 if (digit_en) { 1612 if (framedonetv_irq) 1613 irq_mask |= BIT(24); /* FRAMEDONETV */ 1614 else 1615 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1616 } 1617 if (disable & (lcd_en | digit_en)) 1618 sysc_write(ddata, dispc_offset + 0x40, 1619 val & ~(lcd_en_mask | digit_en_mask)); 1620 1621 if (manager_count <= 2) 1622 return irq_mask; 1623 1624 /* DISPC_CONTROL2 */ 1625 val = sysc_read(ddata, dispc_offset + 0x238); 1626 lcd2_en = val & lcd_en_mask; 1627 if (lcd2_en) 1628 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1629 if (disable && lcd2_en) 1630 sysc_write(ddata, dispc_offset + 0x238, 1631 val & ~lcd_en_mask); 1632 1633 if (manager_count <= 3) 1634 return irq_mask; 1635 1636 /* DISPC_CONTROL3 */ 1637 val = sysc_read(ddata, dispc_offset + 0x848); 1638 lcd3_en = val & lcd_en_mask; 1639 if (lcd3_en) 1640 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1641 if (disable && lcd3_en) 1642 sysc_write(ddata, dispc_offset + 0x848, 1643 val & ~lcd_en_mask); 1644 1645 return irq_mask; 1646 } 1647 1648 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1649 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1650 { 1651 const int dispc_offset = 0x1000; 1652 int error; 1653 u32 irq_mask, val; 1654 1655 /* Get enabled outputs */ 1656 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1657 if (!irq_mask) 1658 return; 1659 1660 /* Clear IRQSTATUS */ 1661 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1662 1663 /* Disable outputs */ 1664 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1665 1666 /* Poll IRQSTATUS */ 1667 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1668 val, val != irq_mask, 100, 50); 1669 if (error) 1670 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1671 __func__, val, irq_mask); 1672 1673 if (sysc_soc->soc == SOC_3430) { 1674 /* Clear DSS_SDI_CONTROL */ 1675 sysc_write(ddata, 0x44, 0); 1676 1677 /* Clear DSS_PLL_CONTROL */ 1678 sysc_write(ddata, 0x48, 0); 1679 } 1680 1681 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1682 sysc_write(ddata, 0x40, 0); 1683 } 1684 1685 /* 1-wire needs module's internal clocks enabled for reset */ 1686 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1687 { 1688 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1689 u16 val; 1690 1691 val = sysc_read(ddata, offset); 1692 val |= BIT(5); 1693 sysc_write(ddata, offset, val); 1694 } 1695 1696 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1697 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1698 { 1699 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1700 1701 sysc_write(ddata, offset, 1); 1702 } 1703 1704 /* I2C needs to be disabled for reset */ 1705 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1706 { 1707 int offset; 1708 u16 val; 1709 1710 /* I2C_CON, omap2/3 is different from omap4 and later */ 1711 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1712 offset = 0x24; 1713 else 1714 offset = 0xa4; 1715 1716 /* I2C_EN */ 1717 val = sysc_read(ddata, offset); 1718 if (enable) 1719 val |= BIT(15); 1720 else 1721 val &= ~BIT(15); 1722 sysc_write(ddata, offset, val); 1723 } 1724 1725 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1726 { 1727 sysc_clk_quirk_i2c(ddata, false); 1728 } 1729 1730 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1731 { 1732 sysc_clk_quirk_i2c(ddata, true); 1733 } 1734 1735 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1736 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1737 { 1738 u32 val, kick0_val = 0, kick1_val = 0; 1739 unsigned long flags; 1740 int error; 1741 1742 if (!lock) { 1743 kick0_val = 0x83e70b13; 1744 kick1_val = 0x95a4f1e0; 1745 } 1746 1747 local_irq_save(flags); 1748 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1749 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1750 !(val & BIT(0)), 100, 50); 1751 if (error) 1752 dev_warn(ddata->dev, "rtc busy timeout\n"); 1753 /* Now we have ~15 microseconds to read/write various registers */ 1754 sysc_write(ddata, 0x6c, kick0_val); 1755 sysc_write(ddata, 0x70, kick1_val); 1756 local_irq_restore(flags); 1757 } 1758 1759 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1760 { 1761 sysc_quirk_rtc(ddata, false); 1762 } 1763 1764 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1765 { 1766 sysc_quirk_rtc(ddata, true); 1767 } 1768 1769 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1770 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1771 { 1772 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1773 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1774 1775 sysc_write(ddata, offset, val); 1776 } 1777 1778 /* Watchdog timer needs a disable sequence after reset */ 1779 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1780 { 1781 int wps, spr, error; 1782 u32 val; 1783 1784 wps = 0x34; 1785 spr = 0x48; 1786 1787 sysc_write(ddata, spr, 0xaaaa); 1788 error = readl_poll_timeout(ddata->module_va + wps, val, 1789 !(val & 0x10), 100, 1790 MAX_MODULE_SOFTRESET_WAIT); 1791 if (error) 1792 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1793 1794 sysc_write(ddata, spr, 0x5555); 1795 error = readl_poll_timeout(ddata->module_va + wps, val, 1796 !(val & 0x10), 100, 1797 MAX_MODULE_SOFTRESET_WAIT); 1798 if (error) 1799 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1800 } 1801 1802 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1803 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1804 { 1805 u32 reg; 1806 1807 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1808 reg |= SYSC_PRUSS_STANDBY_INIT; 1809 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1810 } 1811 1812 static void sysc_init_module_quirks(struct sysc *ddata) 1813 { 1814 if (ddata->legacy_mode || !ddata->name) 1815 return; 1816 1817 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1818 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 1819 1820 return; 1821 } 1822 1823 #ifdef CONFIG_OMAP_GPMC_DEBUG 1824 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 1825 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 1826 1827 return; 1828 } 1829 #endif 1830 1831 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1832 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 1833 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 1834 1835 return; 1836 } 1837 1838 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 1839 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 1840 1841 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 1842 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 1843 1844 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 1845 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 1846 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 1847 1848 return; 1849 } 1850 1851 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 1852 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 1853 1854 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 1855 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1856 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 1857 } 1858 1859 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 1860 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 1861 } 1862 1863 static int sysc_clockdomain_init(struct sysc *ddata) 1864 { 1865 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1866 struct clk *fck = NULL, *ick = NULL; 1867 int error; 1868 1869 if (!pdata || !pdata->init_clockdomain) 1870 return 0; 1871 1872 switch (ddata->nr_clocks) { 1873 case 2: 1874 ick = ddata->clocks[SYSC_ICK]; 1875 fallthrough; 1876 case 1: 1877 fck = ddata->clocks[SYSC_FCK]; 1878 break; 1879 case 0: 1880 return 0; 1881 } 1882 1883 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1884 if (!error || error == -ENODEV) 1885 return 0; 1886 1887 return error; 1888 } 1889 1890 /* 1891 * Note that pdata->init_module() typically does a reset first. After 1892 * pdata->init_module() is done, PM runtime can be used for the interconnect 1893 * target module. 1894 */ 1895 static int sysc_legacy_init(struct sysc *ddata) 1896 { 1897 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1898 int error; 1899 1900 if (!pdata || !pdata->init_module) 1901 return 0; 1902 1903 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 1904 if (error == -EEXIST) 1905 error = 0; 1906 1907 return error; 1908 } 1909 1910 /* 1911 * Note that the caller must ensure the interconnect target module is enabled 1912 * before calling reset. Otherwise reset will not complete. 1913 */ 1914 static int sysc_reset(struct sysc *ddata) 1915 { 1916 int sysc_offset, sysc_val, error; 1917 u32 sysc_mask; 1918 1919 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 1920 1921 if (ddata->legacy_mode || 1922 ddata->cap->regbits->srst_shift < 0 || 1923 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 1924 return 0; 1925 1926 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 1927 1928 if (ddata->pre_reset_quirk) 1929 ddata->pre_reset_quirk(ddata); 1930 1931 if (sysc_offset >= 0) { 1932 sysc_val = sysc_read_sysconfig(ddata); 1933 sysc_val |= sysc_mask; 1934 sysc_write(ddata, sysc_offset, sysc_val); 1935 } 1936 1937 if (ddata->cfg.srst_udelay) 1938 usleep_range(ddata->cfg.srst_udelay, 1939 ddata->cfg.srst_udelay * 2); 1940 1941 if (ddata->post_reset_quirk) 1942 ddata->post_reset_quirk(ddata); 1943 1944 error = sysc_wait_softreset(ddata); 1945 if (error) 1946 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1947 1948 if (ddata->reset_done_quirk) 1949 ddata->reset_done_quirk(ddata); 1950 1951 return error; 1952 } 1953 1954 /* 1955 * At this point the module is configured enough to read the revision but 1956 * module may not be completely configured yet to use PM runtime. Enable 1957 * all clocks directly during init to configure the quirks needed for PM 1958 * runtime based on the revision register. 1959 */ 1960 static int sysc_init_module(struct sysc *ddata) 1961 { 1962 bool rstctrl_deasserted = false; 1963 int error = 0; 1964 1965 error = sysc_clockdomain_init(ddata); 1966 if (error) 1967 return error; 1968 1969 sysc_clkdm_deny_idle(ddata); 1970 1971 /* 1972 * Always enable clocks. The bootloader may or may not have enabled 1973 * the related clocks. 1974 */ 1975 error = sysc_enable_opt_clocks(ddata); 1976 if (error) 1977 return error; 1978 1979 error = sysc_enable_main_clocks(ddata); 1980 if (error) 1981 goto err_opt_clocks; 1982 1983 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1984 error = reset_control_deassert(ddata->rsts); 1985 if (error) 1986 goto err_main_clocks; 1987 rstctrl_deasserted = true; 1988 } 1989 1990 ddata->revision = sysc_read_revision(ddata); 1991 sysc_init_revision_quirks(ddata); 1992 sysc_init_module_quirks(ddata); 1993 1994 if (ddata->legacy_mode) { 1995 error = sysc_legacy_init(ddata); 1996 if (error) 1997 goto err_main_clocks; 1998 } 1999 2000 if (!ddata->legacy_mode) { 2001 error = sysc_enable_module(ddata->dev); 2002 if (error) 2003 goto err_main_clocks; 2004 } 2005 2006 error = sysc_reset(ddata); 2007 if (error) 2008 dev_err(ddata->dev, "Reset failed with %d\n", error); 2009 2010 if (error && !ddata->legacy_mode) 2011 sysc_disable_module(ddata->dev); 2012 2013 err_main_clocks: 2014 if (error) 2015 sysc_disable_main_clocks(ddata); 2016 err_opt_clocks: 2017 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2018 if (error) { 2019 sysc_disable_opt_clocks(ddata); 2020 sysc_clkdm_allow_idle(ddata); 2021 } 2022 2023 if (error && rstctrl_deasserted && 2024 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2025 reset_control_assert(ddata->rsts); 2026 2027 return error; 2028 } 2029 2030 static int sysc_init_sysc_mask(struct sysc *ddata) 2031 { 2032 struct device_node *np = ddata->dev->of_node; 2033 int error; 2034 u32 val; 2035 2036 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2037 if (error) 2038 return 0; 2039 2040 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2041 2042 return 0; 2043 } 2044 2045 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2046 const char *name) 2047 { 2048 struct device_node *np = ddata->dev->of_node; 2049 struct property *prop; 2050 const __be32 *p; 2051 u32 val; 2052 2053 of_property_for_each_u32(np, name, prop, p, val) { 2054 if (val >= SYSC_NR_IDLEMODES) { 2055 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2056 return -EINVAL; 2057 } 2058 *idlemodes |= (1 << val); 2059 } 2060 2061 return 0; 2062 } 2063 2064 static int sysc_init_idlemodes(struct sysc *ddata) 2065 { 2066 int error; 2067 2068 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2069 "ti,sysc-midle"); 2070 if (error) 2071 return error; 2072 2073 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2074 "ti,sysc-sidle"); 2075 if (error) 2076 return error; 2077 2078 return 0; 2079 } 2080 2081 /* 2082 * Only some devices on omap4 and later have SYSCONFIG reset done 2083 * bit. We can detect this if there is no SYSSTATUS at all, or the 2084 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2085 * have multiple bits for the child devices like OHCI and EHCI. 2086 * Depends on SYSC being parsed first. 2087 */ 2088 static int sysc_init_syss_mask(struct sysc *ddata) 2089 { 2090 struct device_node *np = ddata->dev->of_node; 2091 int error; 2092 u32 val; 2093 2094 error = of_property_read_u32(np, "ti,syss-mask", &val); 2095 if (error) { 2096 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2097 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2098 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2099 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2100 2101 return 0; 2102 } 2103 2104 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2105 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2106 2107 ddata->cfg.syss_mask = val; 2108 2109 return 0; 2110 } 2111 2112 /* 2113 * Many child device drivers need to have fck and opt clocks available 2114 * to get the clock rate for device internal configuration etc. 2115 */ 2116 static int sysc_child_add_named_clock(struct sysc *ddata, 2117 struct device *child, 2118 const char *name) 2119 { 2120 struct clk *clk; 2121 struct clk_lookup *l; 2122 int error = 0; 2123 2124 if (!name) 2125 return 0; 2126 2127 clk = clk_get(child, name); 2128 if (!IS_ERR(clk)) { 2129 error = -EEXIST; 2130 goto put_clk; 2131 } 2132 2133 clk = clk_get(ddata->dev, name); 2134 if (IS_ERR(clk)) 2135 return -ENODEV; 2136 2137 l = clkdev_create(clk, name, dev_name(child)); 2138 if (!l) 2139 error = -ENOMEM; 2140 put_clk: 2141 clk_put(clk); 2142 2143 return error; 2144 } 2145 2146 static int sysc_child_add_clocks(struct sysc *ddata, 2147 struct device *child) 2148 { 2149 int i, error; 2150 2151 for (i = 0; i < ddata->nr_clocks; i++) { 2152 error = sysc_child_add_named_clock(ddata, 2153 child, 2154 ddata->clock_roles[i]); 2155 if (error && error != -EEXIST) { 2156 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2157 ddata->clock_roles[i], error); 2158 2159 return error; 2160 } 2161 } 2162 2163 return 0; 2164 } 2165 2166 static struct device_type sysc_device_type = { 2167 }; 2168 2169 static struct sysc *sysc_child_to_parent(struct device *dev) 2170 { 2171 struct device *parent = dev->parent; 2172 2173 if (!parent || parent->type != &sysc_device_type) 2174 return NULL; 2175 2176 return dev_get_drvdata(parent); 2177 } 2178 2179 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2180 { 2181 struct sysc *ddata; 2182 int error; 2183 2184 ddata = sysc_child_to_parent(dev); 2185 2186 error = pm_generic_runtime_suspend(dev); 2187 if (error) 2188 return error; 2189 2190 if (!ddata->enabled) 2191 return 0; 2192 2193 return sysc_runtime_suspend(ddata->dev); 2194 } 2195 2196 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2197 { 2198 struct sysc *ddata; 2199 int error; 2200 2201 ddata = sysc_child_to_parent(dev); 2202 2203 if (!ddata->enabled) { 2204 error = sysc_runtime_resume(ddata->dev); 2205 if (error < 0) 2206 dev_err(ddata->dev, 2207 "%s error: %i\n", __func__, error); 2208 } 2209 2210 return pm_generic_runtime_resume(dev); 2211 } 2212 2213 #ifdef CONFIG_PM_SLEEP 2214 static int sysc_child_suspend_noirq(struct device *dev) 2215 { 2216 struct sysc *ddata; 2217 int error; 2218 2219 ddata = sysc_child_to_parent(dev); 2220 2221 dev_dbg(ddata->dev, "%s %s\n", __func__, 2222 ddata->name ? ddata->name : ""); 2223 2224 error = pm_generic_suspend_noirq(dev); 2225 if (error) { 2226 dev_err(dev, "%s error at %i: %i\n", 2227 __func__, __LINE__, error); 2228 2229 return error; 2230 } 2231 2232 if (!pm_runtime_status_suspended(dev)) { 2233 error = pm_generic_runtime_suspend(dev); 2234 if (error) { 2235 dev_dbg(dev, "%s busy at %i: %i\n", 2236 __func__, __LINE__, error); 2237 2238 return 0; 2239 } 2240 2241 error = sysc_runtime_suspend(ddata->dev); 2242 if (error) { 2243 dev_err(dev, "%s error at %i: %i\n", 2244 __func__, __LINE__, error); 2245 2246 return error; 2247 } 2248 2249 ddata->child_needs_resume = true; 2250 } 2251 2252 return 0; 2253 } 2254 2255 static int sysc_child_resume_noirq(struct device *dev) 2256 { 2257 struct sysc *ddata; 2258 int error; 2259 2260 ddata = sysc_child_to_parent(dev); 2261 2262 dev_dbg(ddata->dev, "%s %s\n", __func__, 2263 ddata->name ? ddata->name : ""); 2264 2265 if (ddata->child_needs_resume) { 2266 ddata->child_needs_resume = false; 2267 2268 error = sysc_runtime_resume(ddata->dev); 2269 if (error) 2270 dev_err(ddata->dev, 2271 "%s runtime resume error: %i\n", 2272 __func__, error); 2273 2274 error = pm_generic_runtime_resume(dev); 2275 if (error) 2276 dev_err(ddata->dev, 2277 "%s generic runtime resume: %i\n", 2278 __func__, error); 2279 } 2280 2281 return pm_generic_resume_noirq(dev); 2282 } 2283 #endif 2284 2285 static struct dev_pm_domain sysc_child_pm_domain = { 2286 .ops = { 2287 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2288 sysc_child_runtime_resume, 2289 NULL) 2290 USE_PLATFORM_PM_SLEEP_OPS 2291 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2292 sysc_child_resume_noirq) 2293 } 2294 }; 2295 2296 /** 2297 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2298 * @ddata: device driver data 2299 * @child: child device driver 2300 * 2301 * Allow idle for child devices as done with _od_runtime_suspend(). 2302 * Otherwise many child devices will not idle because of the permanent 2303 * parent usecount set in pm_runtime_irq_safe(). 2304 * 2305 * Note that the long term solution is to just modify the child device 2306 * drivers to not set pm_runtime_irq_safe() and then this can be just 2307 * dropped. 2308 */ 2309 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2310 { 2311 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2312 dev_pm_domain_set(child, &sysc_child_pm_domain); 2313 } 2314 2315 static int sysc_notifier_call(struct notifier_block *nb, 2316 unsigned long event, void *device) 2317 { 2318 struct device *dev = device; 2319 struct sysc *ddata; 2320 int error; 2321 2322 ddata = sysc_child_to_parent(dev); 2323 if (!ddata) 2324 return NOTIFY_DONE; 2325 2326 switch (event) { 2327 case BUS_NOTIFY_ADD_DEVICE: 2328 error = sysc_child_add_clocks(ddata, dev); 2329 if (error) 2330 return error; 2331 sysc_legacy_idle_quirk(ddata, dev); 2332 break; 2333 default: 2334 break; 2335 } 2336 2337 return NOTIFY_DONE; 2338 } 2339 2340 static struct notifier_block sysc_nb = { 2341 .notifier_call = sysc_notifier_call, 2342 }; 2343 2344 /* Device tree configured quirks */ 2345 struct sysc_dts_quirk { 2346 const char *name; 2347 u32 mask; 2348 }; 2349 2350 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2351 { .name = "ti,no-idle-on-init", 2352 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2353 { .name = "ti,no-reset-on-init", 2354 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2355 { .name = "ti,no-idle", 2356 .mask = SYSC_QUIRK_NO_IDLE, }, 2357 }; 2358 2359 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2360 bool is_child) 2361 { 2362 const struct property *prop; 2363 int i, len; 2364 2365 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2366 const char *name = sysc_dts_quirks[i].name; 2367 2368 prop = of_get_property(np, name, &len); 2369 if (!prop) 2370 continue; 2371 2372 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2373 if (is_child) { 2374 dev_warn(ddata->dev, 2375 "dts flag should be at module level for %s\n", 2376 name); 2377 } 2378 } 2379 } 2380 2381 static int sysc_init_dts_quirks(struct sysc *ddata) 2382 { 2383 struct device_node *np = ddata->dev->of_node; 2384 int error; 2385 u32 val; 2386 2387 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2388 2389 sysc_parse_dts_quirks(ddata, np, false); 2390 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2391 if (!error) { 2392 if (val > 255) { 2393 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2394 val); 2395 } 2396 2397 ddata->cfg.srst_udelay = (u8)val; 2398 } 2399 2400 return 0; 2401 } 2402 2403 static void sysc_unprepare(struct sysc *ddata) 2404 { 2405 int i; 2406 2407 if (!ddata->clocks) 2408 return; 2409 2410 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2411 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2412 clk_unprepare(ddata->clocks[i]); 2413 } 2414 } 2415 2416 /* 2417 * Common sysc register bits found on omap2, also known as type1 2418 */ 2419 static const struct sysc_regbits sysc_regbits_omap2 = { 2420 .dmadisable_shift = -ENODEV, 2421 .midle_shift = 12, 2422 .sidle_shift = 3, 2423 .clkact_shift = 8, 2424 .emufree_shift = 5, 2425 .enwkup_shift = 2, 2426 .srst_shift = 1, 2427 .autoidle_shift = 0, 2428 }; 2429 2430 static const struct sysc_capabilities sysc_omap2 = { 2431 .type = TI_SYSC_OMAP2, 2432 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2433 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2434 SYSC_OMAP2_AUTOIDLE, 2435 .regbits = &sysc_regbits_omap2, 2436 }; 2437 2438 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2439 static const struct sysc_capabilities sysc_omap2_timer = { 2440 .type = TI_SYSC_OMAP2_TIMER, 2441 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2442 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2443 SYSC_OMAP2_AUTOIDLE, 2444 .regbits = &sysc_regbits_omap2, 2445 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2446 }; 2447 2448 /* 2449 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2450 * with different sidle position 2451 */ 2452 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2453 .dmadisable_shift = -ENODEV, 2454 .midle_shift = -ENODEV, 2455 .sidle_shift = 4, 2456 .clkact_shift = -ENODEV, 2457 .enwkup_shift = -ENODEV, 2458 .srst_shift = 1, 2459 .autoidle_shift = 0, 2460 .emufree_shift = -ENODEV, 2461 }; 2462 2463 static const struct sysc_capabilities sysc_omap3_sham = { 2464 .type = TI_SYSC_OMAP3_SHAM, 2465 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2466 .regbits = &sysc_regbits_omap3_sham, 2467 }; 2468 2469 /* 2470 * AES register bits found on omap3 and later, a variant of 2471 * sysc_regbits_omap2 with different sidle position 2472 */ 2473 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2474 .dmadisable_shift = -ENODEV, 2475 .midle_shift = -ENODEV, 2476 .sidle_shift = 6, 2477 .clkact_shift = -ENODEV, 2478 .enwkup_shift = -ENODEV, 2479 .srst_shift = 1, 2480 .autoidle_shift = 0, 2481 .emufree_shift = -ENODEV, 2482 }; 2483 2484 static const struct sysc_capabilities sysc_omap3_aes = { 2485 .type = TI_SYSC_OMAP3_AES, 2486 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2487 .regbits = &sysc_regbits_omap3_aes, 2488 }; 2489 2490 /* 2491 * Common sysc register bits found on omap4, also known as type2 2492 */ 2493 static const struct sysc_regbits sysc_regbits_omap4 = { 2494 .dmadisable_shift = 16, 2495 .midle_shift = 4, 2496 .sidle_shift = 2, 2497 .clkact_shift = -ENODEV, 2498 .enwkup_shift = -ENODEV, 2499 .emufree_shift = 1, 2500 .srst_shift = 0, 2501 .autoidle_shift = -ENODEV, 2502 }; 2503 2504 static const struct sysc_capabilities sysc_omap4 = { 2505 .type = TI_SYSC_OMAP4, 2506 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2507 SYSC_OMAP4_SOFTRESET, 2508 .regbits = &sysc_regbits_omap4, 2509 }; 2510 2511 static const struct sysc_capabilities sysc_omap4_timer = { 2512 .type = TI_SYSC_OMAP4_TIMER, 2513 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2514 SYSC_OMAP4_SOFTRESET, 2515 .regbits = &sysc_regbits_omap4, 2516 }; 2517 2518 /* 2519 * Common sysc register bits found on omap4, also known as type3 2520 */ 2521 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2522 .dmadisable_shift = -ENODEV, 2523 .midle_shift = 2, 2524 .sidle_shift = 0, 2525 .clkact_shift = -ENODEV, 2526 .enwkup_shift = -ENODEV, 2527 .srst_shift = -ENODEV, 2528 .emufree_shift = -ENODEV, 2529 .autoidle_shift = -ENODEV, 2530 }; 2531 2532 static const struct sysc_capabilities sysc_omap4_simple = { 2533 .type = TI_SYSC_OMAP4_SIMPLE, 2534 .regbits = &sysc_regbits_omap4_simple, 2535 }; 2536 2537 /* 2538 * SmartReflex sysc found on omap34xx 2539 */ 2540 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2541 .dmadisable_shift = -ENODEV, 2542 .midle_shift = -ENODEV, 2543 .sidle_shift = -ENODEV, 2544 .clkact_shift = 20, 2545 .enwkup_shift = -ENODEV, 2546 .srst_shift = -ENODEV, 2547 .emufree_shift = -ENODEV, 2548 .autoidle_shift = -ENODEV, 2549 }; 2550 2551 static const struct sysc_capabilities sysc_34xx_sr = { 2552 .type = TI_SYSC_OMAP34XX_SR, 2553 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2554 .regbits = &sysc_regbits_omap34xx_sr, 2555 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2556 SYSC_QUIRK_LEGACY_IDLE, 2557 }; 2558 2559 /* 2560 * SmartReflex sysc found on omap36xx and later 2561 */ 2562 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2563 .dmadisable_shift = -ENODEV, 2564 .midle_shift = -ENODEV, 2565 .sidle_shift = 24, 2566 .clkact_shift = -ENODEV, 2567 .enwkup_shift = 26, 2568 .srst_shift = -ENODEV, 2569 .emufree_shift = -ENODEV, 2570 .autoidle_shift = -ENODEV, 2571 }; 2572 2573 static const struct sysc_capabilities sysc_36xx_sr = { 2574 .type = TI_SYSC_OMAP36XX_SR, 2575 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2576 .regbits = &sysc_regbits_omap36xx_sr, 2577 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2578 }; 2579 2580 static const struct sysc_capabilities sysc_omap4_sr = { 2581 .type = TI_SYSC_OMAP4_SR, 2582 .regbits = &sysc_regbits_omap36xx_sr, 2583 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2584 }; 2585 2586 /* 2587 * McASP register bits found on omap4 and later 2588 */ 2589 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2590 .dmadisable_shift = -ENODEV, 2591 .midle_shift = -ENODEV, 2592 .sidle_shift = 0, 2593 .clkact_shift = -ENODEV, 2594 .enwkup_shift = -ENODEV, 2595 .srst_shift = -ENODEV, 2596 .emufree_shift = -ENODEV, 2597 .autoidle_shift = -ENODEV, 2598 }; 2599 2600 static const struct sysc_capabilities sysc_omap4_mcasp = { 2601 .type = TI_SYSC_OMAP4_MCASP, 2602 .regbits = &sysc_regbits_omap4_mcasp, 2603 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2604 }; 2605 2606 /* 2607 * McASP found on dra7 and later 2608 */ 2609 static const struct sysc_capabilities sysc_dra7_mcasp = { 2610 .type = TI_SYSC_OMAP4_SIMPLE, 2611 .regbits = &sysc_regbits_omap4_simple, 2612 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2613 }; 2614 2615 /* 2616 * FS USB host found on omap4 and later 2617 */ 2618 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2619 .dmadisable_shift = -ENODEV, 2620 .midle_shift = -ENODEV, 2621 .sidle_shift = 24, 2622 .clkact_shift = -ENODEV, 2623 .enwkup_shift = 26, 2624 .srst_shift = -ENODEV, 2625 .emufree_shift = -ENODEV, 2626 .autoidle_shift = -ENODEV, 2627 }; 2628 2629 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2630 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2631 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2632 .regbits = &sysc_regbits_omap4_usb_host_fs, 2633 }; 2634 2635 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2636 .dmadisable_shift = -ENODEV, 2637 .midle_shift = -ENODEV, 2638 .sidle_shift = -ENODEV, 2639 .clkact_shift = -ENODEV, 2640 .enwkup_shift = 4, 2641 .srst_shift = 0, 2642 .emufree_shift = -ENODEV, 2643 .autoidle_shift = -ENODEV, 2644 }; 2645 2646 static const struct sysc_capabilities sysc_dra7_mcan = { 2647 .type = TI_SYSC_DRA7_MCAN, 2648 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2649 .regbits = &sysc_regbits_dra7_mcan, 2650 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2651 }; 2652 2653 /* 2654 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2655 */ 2656 static const struct sysc_capabilities sysc_pruss = { 2657 .type = TI_SYSC_PRUSS, 2658 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2659 .regbits = &sysc_regbits_omap4_simple, 2660 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2661 }; 2662 2663 static int sysc_init_pdata(struct sysc *ddata) 2664 { 2665 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2666 struct ti_sysc_module_data *mdata; 2667 2668 if (!pdata) 2669 return 0; 2670 2671 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2672 if (!mdata) 2673 return -ENOMEM; 2674 2675 if (ddata->legacy_mode) { 2676 mdata->name = ddata->legacy_mode; 2677 mdata->module_pa = ddata->module_pa; 2678 mdata->module_size = ddata->module_size; 2679 mdata->offsets = ddata->offsets; 2680 mdata->nr_offsets = SYSC_MAX_REGS; 2681 mdata->cap = ddata->cap; 2682 mdata->cfg = &ddata->cfg; 2683 } 2684 2685 ddata->mdata = mdata; 2686 2687 return 0; 2688 } 2689 2690 static int sysc_init_match(struct sysc *ddata) 2691 { 2692 const struct sysc_capabilities *cap; 2693 2694 cap = of_device_get_match_data(ddata->dev); 2695 if (!cap) 2696 return -EINVAL; 2697 2698 ddata->cap = cap; 2699 if (ddata->cap) 2700 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2701 2702 return 0; 2703 } 2704 2705 static void ti_sysc_idle(struct work_struct *work) 2706 { 2707 struct sysc *ddata; 2708 2709 ddata = container_of(work, struct sysc, idle_work.work); 2710 2711 /* 2712 * One time decrement of clock usage counts if left on from init. 2713 * Note that we disable opt clocks unconditionally in this case 2714 * as they are enabled unconditionally during init without 2715 * considering sysc_opt_clks_needed() at that point. 2716 */ 2717 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2718 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2719 sysc_disable_main_clocks(ddata); 2720 sysc_disable_opt_clocks(ddata); 2721 sysc_clkdm_allow_idle(ddata); 2722 } 2723 2724 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2725 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2726 return; 2727 2728 /* 2729 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2730 * and SYSC_QUIRK_NO_RESET_ON_INIT 2731 */ 2732 if (pm_runtime_active(ddata->dev)) 2733 pm_runtime_put_sync(ddata->dev); 2734 } 2735 2736 /* 2737 * SoC model and features detection. Only needed for SoCs that need 2738 * special handling for quirks, no need to list others. 2739 */ 2740 static const struct soc_device_attribute sysc_soc_match[] = { 2741 SOC_FLAG("OMAP242*", SOC_2420), 2742 SOC_FLAG("OMAP243*", SOC_2430), 2743 SOC_FLAG("OMAP3[45]*", SOC_3430), 2744 SOC_FLAG("OMAP3[67]*", SOC_3630), 2745 SOC_FLAG("OMAP443*", SOC_4430), 2746 SOC_FLAG("OMAP446*", SOC_4460), 2747 SOC_FLAG("OMAP447*", SOC_4470), 2748 SOC_FLAG("OMAP54*", SOC_5430), 2749 SOC_FLAG("AM433", SOC_AM3), 2750 SOC_FLAG("AM43*", SOC_AM4), 2751 SOC_FLAG("DRA7*", SOC_DRA7), 2752 2753 { /* sentinel */ }, 2754 }; 2755 2756 /* 2757 * List of SoCs variants with disabled features. By default we assume all 2758 * devices in the device tree are available so no need to list those SoCs. 2759 */ 2760 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2761 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2762 SOC_FLAG("AM3505", DIS_SGX), 2763 SOC_FLAG("OMAP3525", DIS_SGX), 2764 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2765 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2766 2767 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2768 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2769 SOC_FLAG("DM3725", DIS_SGX), 2770 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2771 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2772 SOC_FLAG("OMAP3621", DIS_ISP), 2773 2774 { /* sentinel */ }, 2775 }; 2776 2777 static int sysc_add_disabled(unsigned long base) 2778 { 2779 struct sysc_address *disabled_module; 2780 2781 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2782 if (!disabled_module) 2783 return -ENOMEM; 2784 2785 disabled_module->base = base; 2786 2787 mutex_lock(&sysc_soc->list_lock); 2788 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2789 mutex_unlock(&sysc_soc->list_lock); 2790 2791 return 0; 2792 } 2793 2794 /* 2795 * One time init to detect the booted SoC and disable unavailable features. 2796 * Note that we initialize static data shared across all ti-sysc instances 2797 * so ddata is only used for SoC type. This can be called from module_init 2798 * once we no longer need to rely on platform data. 2799 */ 2800 static int sysc_init_soc(struct sysc *ddata) 2801 { 2802 const struct soc_device_attribute *match; 2803 struct ti_sysc_platform_data *pdata; 2804 unsigned long features = 0; 2805 2806 if (sysc_soc) 2807 return 0; 2808 2809 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2810 if (!sysc_soc) 2811 return -ENOMEM; 2812 2813 mutex_init(&sysc_soc->list_lock); 2814 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2815 sysc_soc->general_purpose = true; 2816 2817 pdata = dev_get_platdata(ddata->dev); 2818 if (pdata && pdata->soc_type_gp) 2819 sysc_soc->general_purpose = pdata->soc_type_gp(); 2820 2821 match = soc_device_match(sysc_soc_match); 2822 if (match && match->data) 2823 sysc_soc->soc = (int)match->data; 2824 2825 /* Ignore devices that are not available on HS and EMU SoCs */ 2826 if (!sysc_soc->general_purpose) { 2827 switch (sysc_soc->soc) { 2828 case SOC_3430 ... SOC_3630: 2829 sysc_add_disabled(0x48304000); /* timer12 */ 2830 break; 2831 default: 2832 break; 2833 }; 2834 } 2835 2836 match = soc_device_match(sysc_soc_feat_match); 2837 if (!match) 2838 return 0; 2839 2840 if (match->data) 2841 features = (unsigned long)match->data; 2842 2843 /* 2844 * Add disabled devices to the list based on the module base. 2845 * Note that this must be done before we attempt to access the 2846 * device and have module revision checks working. 2847 */ 2848 if (features & DIS_ISP) 2849 sysc_add_disabled(0x480bd400); 2850 if (features & DIS_IVA) 2851 sysc_add_disabled(0x5d000000); 2852 if (features & DIS_SGX) 2853 sysc_add_disabled(0x50000000); 2854 2855 return 0; 2856 } 2857 2858 static void sysc_cleanup_soc(void) 2859 { 2860 struct sysc_address *disabled_module; 2861 struct list_head *pos, *tmp; 2862 2863 if (!sysc_soc) 2864 return; 2865 2866 mutex_lock(&sysc_soc->list_lock); 2867 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 2868 disabled_module = list_entry(pos, struct sysc_address, node); 2869 list_del(pos); 2870 kfree(disabled_module); 2871 } 2872 mutex_unlock(&sysc_soc->list_lock); 2873 } 2874 2875 static int sysc_check_disabled_devices(struct sysc *ddata) 2876 { 2877 struct sysc_address *disabled_module; 2878 struct list_head *pos; 2879 int error = 0; 2880 2881 mutex_lock(&sysc_soc->list_lock); 2882 list_for_each(pos, &sysc_soc->disabled_modules) { 2883 disabled_module = list_entry(pos, struct sysc_address, node); 2884 if (ddata->module_pa == disabled_module->base) { 2885 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 2886 error = -ENODEV; 2887 break; 2888 } 2889 } 2890 mutex_unlock(&sysc_soc->list_lock); 2891 2892 return error; 2893 } 2894 2895 /* 2896 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 2897 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 2898 * are needed, we could also look at the timer register configuration. 2899 */ 2900 static int sysc_check_active_timer(struct sysc *ddata) 2901 { 2902 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 2903 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 2904 return 0; 2905 2906 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 2907 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 2908 return -ENXIO; 2909 2910 return 0; 2911 } 2912 2913 static const struct of_device_id sysc_match_table[] = { 2914 { .compatible = "simple-bus", }, 2915 { /* sentinel */ }, 2916 }; 2917 2918 static int sysc_probe(struct platform_device *pdev) 2919 { 2920 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 2921 struct sysc *ddata; 2922 int error; 2923 2924 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 2925 if (!ddata) 2926 return -ENOMEM; 2927 2928 ddata->offsets[SYSC_REVISION] = -ENODEV; 2929 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 2930 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 2931 ddata->dev = &pdev->dev; 2932 platform_set_drvdata(pdev, ddata); 2933 2934 error = sysc_init_soc(ddata); 2935 if (error) 2936 return error; 2937 2938 error = sysc_init_match(ddata); 2939 if (error) 2940 return error; 2941 2942 error = sysc_init_dts_quirks(ddata); 2943 if (error) 2944 return error; 2945 2946 error = sysc_map_and_check_registers(ddata); 2947 if (error) 2948 return error; 2949 2950 error = sysc_init_sysc_mask(ddata); 2951 if (error) 2952 return error; 2953 2954 error = sysc_init_idlemodes(ddata); 2955 if (error) 2956 return error; 2957 2958 error = sysc_init_syss_mask(ddata); 2959 if (error) 2960 return error; 2961 2962 error = sysc_init_pdata(ddata); 2963 if (error) 2964 return error; 2965 2966 sysc_init_early_quirks(ddata); 2967 2968 error = sysc_check_disabled_devices(ddata); 2969 if (error) 2970 return error; 2971 2972 error = sysc_check_active_timer(ddata); 2973 if (error) 2974 return error; 2975 2976 error = sysc_get_clocks(ddata); 2977 if (error) 2978 return error; 2979 2980 error = sysc_init_resets(ddata); 2981 if (error) 2982 goto unprepare; 2983 2984 error = sysc_init_module(ddata); 2985 if (error) 2986 goto unprepare; 2987 2988 pm_runtime_enable(ddata->dev); 2989 error = pm_runtime_get_sync(ddata->dev); 2990 if (error < 0) { 2991 pm_runtime_put_noidle(ddata->dev); 2992 pm_runtime_disable(ddata->dev); 2993 goto unprepare; 2994 } 2995 2996 /* Balance use counts as PM runtime should have enabled these all */ 2997 if (!(ddata->cfg.quirks & 2998 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 2999 sysc_disable_main_clocks(ddata); 3000 sysc_disable_opt_clocks(ddata); 3001 sysc_clkdm_allow_idle(ddata); 3002 } 3003 3004 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3005 reset_control_assert(ddata->rsts); 3006 3007 sysc_show_registers(ddata); 3008 3009 ddata->dev->type = &sysc_device_type; 3010 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 3011 pdata ? pdata->auxdata : NULL, 3012 ddata->dev); 3013 if (error) 3014 goto err; 3015 3016 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3017 3018 /* At least earlycon won't survive without deferred idle */ 3019 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3020 SYSC_QUIRK_NO_IDLE_ON_INIT | 3021 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3022 schedule_delayed_work(&ddata->idle_work, 3000); 3023 } else { 3024 pm_runtime_put(&pdev->dev); 3025 } 3026 3027 return 0; 3028 3029 err: 3030 pm_runtime_put_sync(&pdev->dev); 3031 pm_runtime_disable(&pdev->dev); 3032 unprepare: 3033 sysc_unprepare(ddata); 3034 3035 return error; 3036 } 3037 3038 static int sysc_remove(struct platform_device *pdev) 3039 { 3040 struct sysc *ddata = platform_get_drvdata(pdev); 3041 int error; 3042 3043 cancel_delayed_work_sync(&ddata->idle_work); 3044 3045 error = pm_runtime_get_sync(ddata->dev); 3046 if (error < 0) { 3047 pm_runtime_put_noidle(ddata->dev); 3048 pm_runtime_disable(ddata->dev); 3049 goto unprepare; 3050 } 3051 3052 of_platform_depopulate(&pdev->dev); 3053 3054 pm_runtime_put_sync(&pdev->dev); 3055 pm_runtime_disable(&pdev->dev); 3056 reset_control_assert(ddata->rsts); 3057 3058 unprepare: 3059 sysc_unprepare(ddata); 3060 3061 return 0; 3062 } 3063 3064 static const struct of_device_id sysc_match[] = { 3065 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3066 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3067 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3068 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3069 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3070 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3071 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3072 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3073 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3074 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3075 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3076 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3077 { .compatible = "ti,sysc-usb-host-fs", 3078 .data = &sysc_omap4_usb_host_fs, }, 3079 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3080 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3081 { }, 3082 }; 3083 MODULE_DEVICE_TABLE(of, sysc_match); 3084 3085 static struct platform_driver sysc_driver = { 3086 .probe = sysc_probe, 3087 .remove = sysc_remove, 3088 .driver = { 3089 .name = "ti-sysc", 3090 .of_match_table = sysc_match, 3091 .pm = &sysc_pm_ops, 3092 }, 3093 }; 3094 3095 static int __init sysc_init(void) 3096 { 3097 bus_register_notifier(&platform_bus_type, &sysc_nb); 3098 3099 return platform_driver_register(&sysc_driver); 3100 } 3101 module_init(sysc_init); 3102 3103 static void __exit sysc_exit(void) 3104 { 3105 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3106 platform_driver_unregister(&sysc_driver); 3107 sysc_cleanup_soc(); 3108 } 3109 module_exit(sysc_exit); 3110 3111 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3112 MODULE_LICENSE("GPL v2"); 3113