1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for NVIDIA Generic Memory Interface 4 * 5 * Copyright (C) 2016 Host Mobility AB. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 16 #include <soc/tegra/common.h> 17 18 #define TEGRA_GMI_CONFIG 0x00 19 #define TEGRA_GMI_CONFIG_GO BIT(31) 20 #define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30) 21 #define TEGRA_GMI_MUX_MODE BIT(28) 22 #define TEGRA_GMI_RDY_BEFORE_DATA BIT(24) 23 #define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23) 24 #define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22) 25 #define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21) 26 #define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20) 27 #define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4) 28 29 #define TEGRA_GMI_TIMING0 0x10 30 #define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12) 31 #define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8) 32 #define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4) 33 #define TEGRA_GMI_CE_WIDTH(x) (x & 0xf) 34 35 #define TEGRA_GMI_TIMING1 0x14 36 #define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16) 37 #define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8) 38 #define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff) 39 40 #define TEGRA_GMI_MAX_CHIP_SELECT 8 41 42 struct tegra_gmi { 43 struct device *dev; 44 void __iomem *base; 45 struct clk *clk; 46 struct reset_control *rst; 47 48 u32 snor_config; 49 u32 snor_timing0; 50 u32 snor_timing1; 51 }; 52 53 static int tegra_gmi_enable(struct tegra_gmi *gmi) 54 { 55 int err; 56 57 pm_runtime_enable(gmi->dev); 58 err = pm_runtime_resume_and_get(gmi->dev); 59 if (err) { 60 pm_runtime_disable(gmi->dev); 61 return err; 62 } 63 64 reset_control_assert(gmi->rst); 65 usleep_range(2000, 4000); 66 reset_control_deassert(gmi->rst); 67 68 writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0); 69 writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1); 70 71 gmi->snor_config |= TEGRA_GMI_CONFIG_GO; 72 writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG); 73 74 return 0; 75 } 76 77 static void tegra_gmi_disable(struct tegra_gmi *gmi) 78 { 79 u32 config; 80 81 /* stop GMI operation */ 82 config = readl(gmi->base + TEGRA_GMI_CONFIG); 83 config &= ~TEGRA_GMI_CONFIG_GO; 84 writel(config, gmi->base + TEGRA_GMI_CONFIG); 85 86 reset_control_assert(gmi->rst); 87 88 pm_runtime_put_sync_suspend(gmi->dev); 89 pm_runtime_force_suspend(gmi->dev); 90 } 91 92 static int tegra_gmi_parse_dt(struct tegra_gmi *gmi) 93 { 94 struct device_node *child; 95 u32 property, ranges[4]; 96 int err; 97 98 child = of_get_next_available_child(gmi->dev->of_node, NULL); 99 if (!child) { 100 dev_err(gmi->dev, "no child nodes found\n"); 101 return -ENODEV; 102 } 103 104 /* 105 * We currently only support one child device due to lack of 106 * chip-select address decoding. Which means that we only have one 107 * chip-select line from the GMI controller. 108 */ 109 if (of_get_child_count(gmi->dev->of_node) > 1) 110 dev_warn(gmi->dev, "only one child device is supported."); 111 112 if (of_property_read_bool(child, "nvidia,snor-data-width-32bit")) 113 gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT; 114 115 if (of_property_read_bool(child, "nvidia,snor-mux-mode")) 116 gmi->snor_config |= TEGRA_GMI_MUX_MODE; 117 118 if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data")) 119 gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA; 120 121 if (of_property_read_bool(child, "nvidia,snor-rdy-active-high")) 122 gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH; 123 124 if (of_property_read_bool(child, "nvidia,snor-adv-active-high")) 125 gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH; 126 127 if (of_property_read_bool(child, "nvidia,snor-oe-active-high")) 128 gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH; 129 130 if (of_property_read_bool(child, "nvidia,snor-cs-active-high")) 131 gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH; 132 133 /* Decode the CS# */ 134 err = of_property_read_u32_array(child, "ranges", ranges, 4); 135 if (err < 0) { 136 /* Invalid binding */ 137 if (err == -EOVERFLOW) { 138 dev_err(gmi->dev, 139 "failed to decode CS: invalid ranges length\n"); 140 goto error_cs; 141 } 142 143 /* 144 * If we reach here it means that the child node has an empty 145 * ranges or it does not exist at all. Attempt to decode the 146 * CS# from the reg property instead. 147 */ 148 err = of_property_read_u32(child, "reg", &property); 149 if (err < 0) { 150 dev_err(gmi->dev, 151 "failed to decode CS: no reg property found\n"); 152 goto error_cs; 153 } 154 } else { 155 property = ranges[1]; 156 } 157 158 /* Valid chip selects are CS0-CS7 */ 159 if (property >= TEGRA_GMI_MAX_CHIP_SELECT) { 160 dev_err(gmi->dev, "invalid chip select: %d", property); 161 err = -EINVAL; 162 goto error_cs; 163 } 164 165 gmi->snor_config |= TEGRA_GMI_CS_SELECT(property); 166 167 /* The default values that are provided below are reset values */ 168 if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property)) 169 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property); 170 else 171 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1); 172 173 if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property)) 174 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property); 175 else 176 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1); 177 178 if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property)) 179 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property); 180 else 181 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1); 182 183 if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property)) 184 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property); 185 else 186 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4); 187 188 if (!of_property_read_u32(child, "nvidia,snor-we-width", &property)) 189 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property); 190 else 191 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1); 192 193 if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property)) 194 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property); 195 else 196 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1); 197 198 if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property)) 199 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property); 200 else 201 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3); 202 203 error_cs: 204 of_node_put(child); 205 return err; 206 } 207 208 static int tegra_gmi_probe(struct platform_device *pdev) 209 { 210 struct device *dev = &pdev->dev; 211 struct tegra_gmi *gmi; 212 struct resource *res; 213 int err; 214 215 gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL); 216 if (!gmi) 217 return -ENOMEM; 218 219 platform_set_drvdata(pdev, gmi); 220 gmi->dev = dev; 221 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 223 gmi->base = devm_ioremap_resource(dev, res); 224 if (IS_ERR(gmi->base)) 225 return PTR_ERR(gmi->base); 226 227 gmi->clk = devm_clk_get(dev, "gmi"); 228 if (IS_ERR(gmi->clk)) { 229 dev_err(dev, "can not get clock\n"); 230 return PTR_ERR(gmi->clk); 231 } 232 233 gmi->rst = devm_reset_control_get(dev, "gmi"); 234 if (IS_ERR(gmi->rst)) { 235 dev_err(dev, "can not get reset\n"); 236 return PTR_ERR(gmi->rst); 237 } 238 239 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 240 if (err) 241 return err; 242 243 err = tegra_gmi_parse_dt(gmi); 244 if (err) 245 return err; 246 247 err = tegra_gmi_enable(gmi); 248 if (err < 0) 249 return err; 250 251 err = of_platform_default_populate(dev->of_node, NULL, dev); 252 if (err < 0) { 253 dev_err(dev, "fail to create devices.\n"); 254 tegra_gmi_disable(gmi); 255 return err; 256 } 257 258 return 0; 259 } 260 261 static int tegra_gmi_remove(struct platform_device *pdev) 262 { 263 struct tegra_gmi *gmi = platform_get_drvdata(pdev); 264 265 of_platform_depopulate(gmi->dev); 266 tegra_gmi_disable(gmi); 267 268 return 0; 269 } 270 271 static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev) 272 { 273 struct tegra_gmi *gmi = dev_get_drvdata(dev); 274 int err; 275 276 err = clk_prepare_enable(gmi->clk); 277 if (err < 0) { 278 dev_err(gmi->dev, "failed to enable clock: %d\n", err); 279 return err; 280 } 281 282 return 0; 283 } 284 285 static int __maybe_unused tegra_gmi_runtime_suspend(struct device *dev) 286 { 287 struct tegra_gmi *gmi = dev_get_drvdata(dev); 288 289 clk_disable_unprepare(gmi->clk); 290 291 return 0; 292 } 293 294 static const struct dev_pm_ops tegra_gmi_pm = { 295 SET_RUNTIME_PM_OPS(tegra_gmi_runtime_suspend, tegra_gmi_runtime_resume, 296 NULL) 297 }; 298 299 static const struct of_device_id tegra_gmi_id_table[] = { 300 { .compatible = "nvidia,tegra20-gmi", }, 301 { .compatible = "nvidia,tegra30-gmi", }, 302 { } 303 }; 304 MODULE_DEVICE_TABLE(of, tegra_gmi_id_table); 305 306 static struct platform_driver tegra_gmi_driver = { 307 .probe = tegra_gmi_probe, 308 .remove = tegra_gmi_remove, 309 .driver = { 310 .name = "tegra-gmi", 311 .of_match_table = tegra_gmi_id_table, 312 .pm = &tegra_gmi_pm, 313 }, 314 }; 315 module_platform_driver(tegra_gmi_driver); 316 317 MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com"); 318 MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver"); 319 MODULE_LICENSE("GPL v2"); 320