1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada 4 * 370/XP, Dove, Orion5x and MV78xx0) 5 * 6 * The Marvell EBU SoCs have a configurable physical address space: 7 * the physical address at which certain devices (PCIe, NOR, NAND, 8 * etc.) sit can be configured. The configuration takes place through 9 * two sets of registers: 10 * 11 * - One to configure the access of the CPU to the devices. Depending 12 * on the families, there are between 8 and 20 configurable windows, 13 * each can be use to create a physical memory window that maps to a 14 * specific device. Devices are identified by a tuple (target, 15 * attribute). 16 * 17 * - One to configure the access to the CPU to the SDRAM. There are 18 * either 2 (for Dove) or 4 (for other families) windows to map the 19 * SDRAM into the physical address space. 20 * 21 * This driver: 22 * 23 * - Reads out the SDRAM address decoding windows at initialization 24 * time, and fills the mvebu_mbus_dram_info structure with these 25 * information. The exported function mv_mbus_dram_info() allow 26 * device drivers to get those information related to the SDRAM 27 * address decoding windows. This is because devices also have their 28 * own windows (configured through registers that are part of each 29 * device register space), and therefore the drivers for Marvell 30 * devices have to configure those device -> SDRAM windows to ensure 31 * that DMA works properly. 32 * 33 * - Provides an API for platform code or device drivers to 34 * dynamically add or remove address decoding windows for the CPU -> 35 * device accesses. This API is mvebu_mbus_add_window_by_id(), 36 * mvebu_mbus_add_window_remap_by_id() and 37 * mvebu_mbus_del_window(). 38 * 39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to 40 * see the list of CPU -> SDRAM windows and their configuration 41 * (file 'sdram') and the list of CPU -> devices windows and their 42 * configuration (file 'devices'). 43 */ 44 45 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 46 47 #include <linux/kernel.h> 48 #include <linux/module.h> 49 #include <linux/init.h> 50 #include <linux/mbus.h> 51 #include <linux/io.h> 52 #include <linux/ioport.h> 53 #include <linux/of.h> 54 #include <linux/of_address.h> 55 #include <linux/debugfs.h> 56 #include <linux/log2.h> 57 #include <linux/memblock.h> 58 #include <linux/syscore_ops.h> 59 60 /* 61 * DDR target is the same on all platforms. 62 */ 63 #define TARGET_DDR 0 64 65 /* 66 * CPU Address Decode Windows registers 67 */ 68 #define WIN_CTRL_OFF 0x0000 69 #define WIN_CTRL_ENABLE BIT(0) 70 /* Only on HW I/O coherency capable platforms */ 71 #define WIN_CTRL_SYNCBARRIER BIT(1) 72 #define WIN_CTRL_TGT_MASK 0xf0 73 #define WIN_CTRL_TGT_SHIFT 4 74 #define WIN_CTRL_ATTR_MASK 0xff00 75 #define WIN_CTRL_ATTR_SHIFT 8 76 #define WIN_CTRL_SIZE_MASK 0xffff0000 77 #define WIN_CTRL_SIZE_SHIFT 16 78 #define WIN_BASE_OFF 0x0004 79 #define WIN_BASE_LOW 0xffff0000 80 #define WIN_BASE_HIGH 0xf 81 #define WIN_REMAP_LO_OFF 0x0008 82 #define WIN_REMAP_LOW 0xffff0000 83 #define WIN_REMAP_HI_OFF 0x000c 84 85 #define UNIT_SYNC_BARRIER_OFF 0x84 86 #define UNIT_SYNC_BARRIER_ALL 0xFFFF 87 88 #define ATTR_HW_COHERENCY (0x1 << 4) 89 90 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 91 #define DDR_BASE_CS_HIGH_MASK 0xf 92 #define DDR_BASE_CS_LOW_MASK 0xff000000 93 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 94 #define DDR_SIZE_ENABLED BIT(0) 95 #define DDR_SIZE_CS_MASK 0x1c 96 #define DDR_SIZE_CS_SHIFT 2 97 #define DDR_SIZE_MASK 0xff000000 98 99 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) 100 101 /* Relative to mbusbridge_base */ 102 #define MBUS_BRIDGE_CTRL_OFF 0x0 103 #define MBUS_BRIDGE_BASE_OFF 0x4 104 105 /* Maximum number of windows, for all known platforms */ 106 #define MBUS_WINS_MAX 20 107 108 struct mvebu_mbus_state; 109 110 struct mvebu_mbus_soc_data { 111 unsigned int num_wins; 112 bool has_mbus_bridge; 113 unsigned int (*win_cfg_offset)(const int win); 114 unsigned int (*win_remap_offset)(const int win); 115 void (*setup_cpu_target)(struct mvebu_mbus_state *s); 116 int (*save_cpu_target)(struct mvebu_mbus_state *s, 117 u32 __iomem *store_addr); 118 int (*show_cpu_target)(struct mvebu_mbus_state *s, 119 struct seq_file *seq, void *v); 120 }; 121 122 /* 123 * Used to store the state of one MBus window across suspend/resume. 124 */ 125 struct mvebu_mbus_win_data { 126 u32 ctrl; 127 u32 base; 128 u32 remap_lo; 129 u32 remap_hi; 130 }; 131 132 struct mvebu_mbus_state { 133 void __iomem *mbuswins_base; 134 void __iomem *sdramwins_base; 135 void __iomem *mbusbridge_base; 136 phys_addr_t sdramwins_phys_base; 137 struct dentry *debugfs_root; 138 struct dentry *debugfs_sdram; 139 struct dentry *debugfs_devs; 140 struct resource pcie_mem_aperture; 141 struct resource pcie_io_aperture; 142 const struct mvebu_mbus_soc_data *soc; 143 int hw_io_coherency; 144 145 /* Used during suspend/resume */ 146 u32 mbus_bridge_ctrl; 147 u32 mbus_bridge_base; 148 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX]; 149 }; 150 151 static struct mvebu_mbus_state mbus_state; 152 153 /* 154 * We provide two variants of the mv_mbus_dram_info() function: 155 * 156 * - The normal one, where the described DRAM ranges may overlap with 157 * the I/O windows, but for which the DRAM ranges are guaranteed to 158 * have a power of two size. Such ranges are suitable for the DMA 159 * masters that only DMA between the RAM and the device, which is 160 * actually all devices except the crypto engines. 161 * 162 * - The 'nooverlap' one, where the described DRAM ranges are 163 * guaranteed to not overlap with the I/O windows, but for which the 164 * DRAM ranges will not have power of two sizes. They will only be 165 * aligned on a 64 KB boundary, and have a size multiple of 64 166 * KB. Such ranges are suitable for the DMA masters that DMA between 167 * the crypto SRAM (which is mapped through an I/O window) and a 168 * device. This is the case for the crypto engines. 169 */ 170 171 static struct mbus_dram_target_info mvebu_mbus_dram_info; 172 static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap; 173 174 const struct mbus_dram_target_info *mv_mbus_dram_info(void) 175 { 176 return &mvebu_mbus_dram_info; 177 } 178 EXPORT_SYMBOL_GPL(mv_mbus_dram_info); 179 180 const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void) 181 { 182 return &mvebu_mbus_dram_info_nooverlap; 183 } 184 EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap); 185 186 /* Checks whether the given window has remap capability */ 187 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus, 188 const int win) 189 { 190 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP; 191 } 192 193 /* 194 * Functions to manipulate the address decoding windows 195 */ 196 197 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, 198 int win, int *enabled, u64 *base, 199 u32 *size, u8 *target, u8 *attr, 200 u64 *remap) 201 { 202 void __iomem *addr = mbus->mbuswins_base + 203 mbus->soc->win_cfg_offset(win); 204 u32 basereg = readl(addr + WIN_BASE_OFF); 205 u32 ctrlreg = readl(addr + WIN_CTRL_OFF); 206 207 if (!(ctrlreg & WIN_CTRL_ENABLE)) { 208 *enabled = 0; 209 return; 210 } 211 212 *enabled = 1; 213 *base = ((u64)basereg & WIN_BASE_HIGH) << 32; 214 *base |= (basereg & WIN_BASE_LOW); 215 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; 216 217 if (target) 218 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; 219 220 if (attr) 221 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; 222 223 if (remap) { 224 if (mvebu_mbus_window_is_remappable(mbus, win)) { 225 u32 remap_low, remap_hi; 226 void __iomem *addr_rmp = mbus->mbuswins_base + 227 mbus->soc->win_remap_offset(win); 228 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF); 229 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); 230 *remap = ((u64)remap_hi << 32) | remap_low; 231 } else 232 *remap = 0; 233 } 234 } 235 236 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, 237 int win) 238 { 239 void __iomem *addr; 240 241 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); 242 writel(0, addr + WIN_BASE_OFF); 243 writel(0, addr + WIN_CTRL_OFF); 244 245 if (mvebu_mbus_window_is_remappable(mbus, win)) { 246 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); 247 writel(0, addr + WIN_REMAP_LO_OFF); 248 writel(0, addr + WIN_REMAP_HI_OFF); 249 } 250 } 251 252 /* Checks whether the given window number is available */ 253 254 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, 255 const int win) 256 { 257 void __iomem *addr = mbus->mbuswins_base + 258 mbus->soc->win_cfg_offset(win); 259 u32 ctrl = readl(addr + WIN_CTRL_OFF); 260 261 return !(ctrl & WIN_CTRL_ENABLE); 262 } 263 264 /* 265 * Checks whether the given (base, base+size) area doesn't overlap an 266 * existing region 267 */ 268 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, 269 phys_addr_t base, size_t size, 270 u8 target, u8 attr) 271 { 272 u64 end = (u64)base + size; 273 int win; 274 275 for (win = 0; win < mbus->soc->num_wins; win++) { 276 u64 wbase, wend; 277 u32 wsize; 278 u8 wtarget, wattr; 279 int enabled; 280 281 mvebu_mbus_read_window(mbus, win, 282 &enabled, &wbase, &wsize, 283 &wtarget, &wattr, NULL); 284 285 if (!enabled) 286 continue; 287 288 wend = wbase + wsize; 289 290 /* 291 * Check if the current window overlaps with the 292 * proposed physical range 293 */ 294 if ((u64)base < wend && end > wbase) 295 return 0; 296 } 297 298 return 1; 299 } 300 301 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, 302 phys_addr_t base, size_t size) 303 { 304 int win; 305 306 for (win = 0; win < mbus->soc->num_wins; win++) { 307 u64 wbase; 308 u32 wsize; 309 int enabled; 310 311 mvebu_mbus_read_window(mbus, win, 312 &enabled, &wbase, &wsize, 313 NULL, NULL, NULL); 314 315 if (!enabled) 316 continue; 317 318 if (base == wbase && size == wsize) 319 return win; 320 } 321 322 return -ENODEV; 323 } 324 325 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, 326 int win, phys_addr_t base, size_t size, 327 phys_addr_t remap, u8 target, 328 u8 attr) 329 { 330 void __iomem *addr = mbus->mbuswins_base + 331 mbus->soc->win_cfg_offset(win); 332 u32 ctrl, remap_addr; 333 334 if (!is_power_of_2(size)) { 335 WARN(true, "Invalid MBus window size: 0x%zx\n", size); 336 return -EINVAL; 337 } 338 339 if ((base & (phys_addr_t)(size - 1)) != 0) { 340 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base, 341 size); 342 return -EINVAL; 343 } 344 345 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | 346 (attr << WIN_CTRL_ATTR_SHIFT) | 347 (target << WIN_CTRL_TGT_SHIFT) | 348 WIN_CTRL_ENABLE; 349 if (mbus->hw_io_coherency) 350 ctrl |= WIN_CTRL_SYNCBARRIER; 351 352 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); 353 writel(ctrl, addr + WIN_CTRL_OFF); 354 355 if (mvebu_mbus_window_is_remappable(mbus, win)) { 356 void __iomem *addr_rmp = mbus->mbuswins_base + 357 mbus->soc->win_remap_offset(win); 358 359 if (remap == MVEBU_MBUS_NO_REMAP) 360 remap_addr = base; 361 else 362 remap_addr = remap; 363 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF); 364 writel(0, addr_rmp + WIN_REMAP_HI_OFF); 365 } 366 367 return 0; 368 } 369 370 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, 371 phys_addr_t base, size_t size, 372 phys_addr_t remap, u8 target, 373 u8 attr) 374 { 375 int win; 376 377 if (remap == MVEBU_MBUS_NO_REMAP) { 378 for (win = 0; win < mbus->soc->num_wins; win++) { 379 if (mvebu_mbus_window_is_remappable(mbus, win)) 380 continue; 381 382 if (mvebu_mbus_window_is_free(mbus, win)) 383 return mvebu_mbus_setup_window(mbus, win, base, 384 size, remap, 385 target, attr); 386 } 387 } 388 389 for (win = 0; win < mbus->soc->num_wins; win++) { 390 /* Skip window if need remap but is not supported */ 391 if ((remap != MVEBU_MBUS_NO_REMAP) && 392 !mvebu_mbus_window_is_remappable(mbus, win)) 393 continue; 394 395 if (mvebu_mbus_window_is_free(mbus, win)) 396 return mvebu_mbus_setup_window(mbus, win, base, size, 397 remap, target, attr); 398 } 399 400 return -ENOMEM; 401 } 402 403 /* 404 * Debugfs debugging 405 */ 406 407 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */ 408 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus, 409 struct seq_file *seq, void *v) 410 { 411 int i; 412 413 for (i = 0; i < 4; i++) { 414 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); 415 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); 416 u64 base; 417 u32 size; 418 419 if (!(sizereg & DDR_SIZE_ENABLED)) { 420 seq_printf(seq, "[%d] disabled\n", i); 421 continue; 422 } 423 424 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; 425 base |= basereg & DDR_BASE_CS_LOW_MASK; 426 size = (sizereg | ~DDR_SIZE_MASK); 427 428 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", 429 i, (unsigned long long)base, 430 (unsigned long long)base + size + 1, 431 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT); 432 } 433 434 return 0; 435 } 436 437 /* Special function for Dove */ 438 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus, 439 struct seq_file *seq, void *v) 440 { 441 int i; 442 443 for (i = 0; i < 2; i++) { 444 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); 445 u64 base; 446 u32 size; 447 448 if (!(map & 1)) { 449 seq_printf(seq, "[%d] disabled\n", i); 450 continue; 451 } 452 453 base = map & 0xff800000; 454 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 455 456 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", 457 i, (unsigned long long)base, 458 (unsigned long long)base + size, i); 459 } 460 461 return 0; 462 } 463 464 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v) 465 { 466 struct mvebu_mbus_state *mbus = &mbus_state; 467 return mbus->soc->show_cpu_target(mbus, seq, v); 468 } 469 470 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file) 471 { 472 return single_open(file, mvebu_sdram_debug_show, inode->i_private); 473 } 474 475 static const struct file_operations mvebu_sdram_debug_fops = { 476 .open = mvebu_sdram_debug_open, 477 .read = seq_read, 478 .llseek = seq_lseek, 479 .release = single_release, 480 }; 481 482 static int mvebu_devs_debug_show(struct seq_file *seq, void *v) 483 { 484 struct mvebu_mbus_state *mbus = &mbus_state; 485 int win; 486 487 for (win = 0; win < mbus->soc->num_wins; win++) { 488 u64 wbase, wremap; 489 u32 wsize; 490 u8 wtarget, wattr; 491 int enabled; 492 493 mvebu_mbus_read_window(mbus, win, 494 &enabled, &wbase, &wsize, 495 &wtarget, &wattr, &wremap); 496 497 if (!enabled) { 498 seq_printf(seq, "[%02d] disabled\n", win); 499 continue; 500 } 501 502 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x", 503 win, (unsigned long long)wbase, 504 (unsigned long long)(wbase + wsize), wtarget, wattr); 505 506 if (!is_power_of_2(wsize) || 507 ((wbase & (u64)(wsize - 1)) != 0)) 508 seq_puts(seq, " (Invalid base/size!!)"); 509 510 if (mvebu_mbus_window_is_remappable(mbus, win)) { 511 seq_printf(seq, " (remap %016llx)\n", 512 (unsigned long long)wremap); 513 } else 514 seq_printf(seq, "\n"); 515 } 516 517 return 0; 518 } 519 520 static int mvebu_devs_debug_open(struct inode *inode, struct file *file) 521 { 522 return single_open(file, mvebu_devs_debug_show, inode->i_private); 523 } 524 525 static const struct file_operations mvebu_devs_debug_fops = { 526 .open = mvebu_devs_debug_open, 527 .read = seq_read, 528 .llseek = seq_lseek, 529 .release = single_release, 530 }; 531 532 /* 533 * SoC-specific functions and definitions 534 */ 535 536 static unsigned int generic_mbus_win_cfg_offset(int win) 537 { 538 return win << 4; 539 } 540 541 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win) 542 { 543 /* The register layout is a bit annoying and the below code 544 * tries to cope with it. 545 * - At offset 0x0, there are the registers for the first 8 546 * windows, with 4 registers of 32 bits per window (ctrl, 547 * base, remap low, remap high) 548 * - Then at offset 0x80, there is a hole of 0x10 bytes for 549 * the internal registers base address and internal units 550 * sync barrier register. 551 * - Then at offset 0x90, there the registers for 12 552 * windows, with only 2 registers of 32 bits per window 553 * (ctrl, base). 554 */ 555 if (win < 8) 556 return win << 4; 557 else 558 return 0x90 + ((win - 8) << 3); 559 } 560 561 static unsigned int mv78xx0_mbus_win_cfg_offset(int win) 562 { 563 if (win < 8) 564 return win << 4; 565 else 566 return 0x900 + ((win - 8) << 4); 567 } 568 569 static unsigned int generic_mbus_win_remap_2_offset(int win) 570 { 571 if (win < 2) 572 return generic_mbus_win_cfg_offset(win); 573 else 574 return MVEBU_MBUS_NO_REMAP; 575 } 576 577 static unsigned int generic_mbus_win_remap_4_offset(int win) 578 { 579 if (win < 4) 580 return generic_mbus_win_cfg_offset(win); 581 else 582 return MVEBU_MBUS_NO_REMAP; 583 } 584 585 static unsigned int generic_mbus_win_remap_8_offset(int win) 586 { 587 if (win < 8) 588 return generic_mbus_win_cfg_offset(win); 589 else 590 return MVEBU_MBUS_NO_REMAP; 591 } 592 593 static unsigned int armada_xp_mbus_win_remap_offset(int win) 594 { 595 if (win < 8) 596 return generic_mbus_win_cfg_offset(win); 597 else if (win == 13) 598 return 0xF0 - WIN_REMAP_LO_OFF; 599 else 600 return MVEBU_MBUS_NO_REMAP; 601 } 602 603 /* 604 * Use the memblock information to find the MBus bridge hole in the 605 * physical address space. 606 */ 607 static void __init 608 mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end) 609 { 610 phys_addr_t reg_start, reg_end; 611 uint64_t i, s = 0; 612 613 for_each_mem_range(i, ®_start, ®_end) { 614 /* 615 * This part of the memory is above 4 GB, so we don't 616 * care for the MBus bridge hole. 617 */ 618 if ((u64)reg_start >= 0x100000000ULL) 619 continue; 620 621 /* 622 * The MBus bridge hole is at the end of the RAM under 623 * the 4 GB limit. 624 */ 625 if (reg_end > s) 626 s = reg_end; 627 } 628 629 *start = s; 630 *end = 0x100000000ULL; 631 } 632 633 /* 634 * This function fills in the mvebu_mbus_dram_info_nooverlap data 635 * structure, by looking at the mvebu_mbus_dram_info data, and 636 * removing the parts of it that overlap with I/O windows. 637 */ 638 static void __init 639 mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus) 640 { 641 uint64_t mbus_bridge_base, mbus_bridge_end; 642 int cs_nooverlap = 0; 643 int i; 644 645 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end); 646 647 for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) { 648 struct mbus_dram_window *w; 649 u64 base, size, end; 650 651 w = &mvebu_mbus_dram_info.cs[i]; 652 base = w->base; 653 size = w->size; 654 end = base + size; 655 656 /* 657 * The CS is fully enclosed inside the MBus bridge 658 * area, so ignore it. 659 */ 660 if (base >= mbus_bridge_base && end <= mbus_bridge_end) 661 continue; 662 663 /* 664 * Beginning of CS overlaps with end of MBus, raise CS 665 * base address, and shrink its size. 666 */ 667 if (base >= mbus_bridge_base && end > mbus_bridge_end) { 668 size -= mbus_bridge_end - base; 669 base = mbus_bridge_end; 670 } 671 672 /* 673 * End of CS overlaps with beginning of MBus, shrink 674 * CS size. 675 */ 676 if (base < mbus_bridge_base && end > mbus_bridge_base) 677 size -= end - mbus_bridge_base; 678 679 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++]; 680 w->cs_index = i; 681 w->mbus_attr = 0xf & ~(1 << i); 682 if (mbus->hw_io_coherency) 683 w->mbus_attr |= ATTR_HW_COHERENCY; 684 w->base = base; 685 w->size = size; 686 } 687 688 mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR; 689 mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap; 690 } 691 692 static void __init 693 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) 694 { 695 int i; 696 int cs; 697 698 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 699 700 for (i = 0, cs = 0; i < 4; i++) { 701 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); 702 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); 703 704 /* 705 * We only take care of entries for which the chip 706 * select is enabled, and that don't have high base 707 * address bits set (devices can only access the first 708 * 32 bits of the memory). 709 */ 710 if ((size & DDR_SIZE_ENABLED) && 711 !(base & DDR_BASE_CS_HIGH_MASK)) { 712 struct mbus_dram_window *w; 713 714 w = &mvebu_mbus_dram_info.cs[cs++]; 715 w->cs_index = i; 716 w->mbus_attr = 0xf & ~(1 << i); 717 if (mbus->hw_io_coherency) 718 w->mbus_attr |= ATTR_HW_COHERENCY; 719 w->base = base & DDR_BASE_CS_LOW_MASK; 720 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1; 721 } 722 } 723 mvebu_mbus_dram_info.num_cs = cs; 724 } 725 726 static int 727 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus, 728 u32 __iomem *store_addr) 729 { 730 int i; 731 732 for (i = 0; i < 4; i++) { 733 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); 734 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); 735 736 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i), 737 store_addr++); 738 writel(base, store_addr++); 739 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i), 740 store_addr++); 741 writel(size, store_addr++); 742 } 743 744 /* We've written 16 words to the store address */ 745 return 16; 746 } 747 748 static void __init 749 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus) 750 { 751 int i; 752 int cs; 753 754 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 755 756 for (i = 0, cs = 0; i < 2; i++) { 757 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); 758 759 /* 760 * Chip select enabled? 761 */ 762 if (map & 1) { 763 struct mbus_dram_window *w; 764 765 w = &mvebu_mbus_dram_info.cs[cs++]; 766 w->cs_index = i; 767 w->mbus_attr = 0; /* CS address decoding done inside */ 768 /* the DDR controller, no need to */ 769 /* provide attributes */ 770 w->base = map & 0xff800000; 771 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 772 } 773 } 774 775 mvebu_mbus_dram_info.num_cs = cs; 776 } 777 778 static int 779 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus, 780 u32 __iomem *store_addr) 781 { 782 int i; 783 784 for (i = 0; i < 2; i++) { 785 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); 786 787 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i), 788 store_addr++); 789 writel(map, store_addr++); 790 } 791 792 /* We've written 4 words to the store address */ 793 return 4; 794 } 795 796 int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr) 797 { 798 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr); 799 } 800 801 static const struct mvebu_mbus_soc_data armada_370_mbus_data = { 802 .num_wins = 20, 803 .has_mbus_bridge = true, 804 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset, 805 .win_remap_offset = generic_mbus_win_remap_8_offset, 806 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 807 .show_cpu_target = mvebu_sdram_debug_show_orion, 808 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 809 }; 810 811 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = { 812 .num_wins = 20, 813 .has_mbus_bridge = true, 814 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset, 815 .win_remap_offset = armada_xp_mbus_win_remap_offset, 816 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 817 .show_cpu_target = mvebu_sdram_debug_show_orion, 818 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 819 }; 820 821 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = { 822 .num_wins = 8, 823 .win_cfg_offset = generic_mbus_win_cfg_offset, 824 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 825 .win_remap_offset = generic_mbus_win_remap_4_offset, 826 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 827 .show_cpu_target = mvebu_sdram_debug_show_orion, 828 }; 829 830 static const struct mvebu_mbus_soc_data dove_mbus_data = { 831 .num_wins = 8, 832 .win_cfg_offset = generic_mbus_win_cfg_offset, 833 .save_cpu_target = mvebu_mbus_dove_save_cpu_target, 834 .win_remap_offset = generic_mbus_win_remap_4_offset, 835 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target, 836 .show_cpu_target = mvebu_sdram_debug_show_dove, 837 }; 838 839 /* 840 * Some variants of Orion5x have 4 remappable windows, some other have 841 * only two of them. 842 */ 843 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = { 844 .num_wins = 8, 845 .win_cfg_offset = generic_mbus_win_cfg_offset, 846 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 847 .win_remap_offset = generic_mbus_win_remap_4_offset, 848 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 849 .show_cpu_target = mvebu_sdram_debug_show_orion, 850 }; 851 852 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = { 853 .num_wins = 8, 854 .win_cfg_offset = generic_mbus_win_cfg_offset, 855 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 856 .win_remap_offset = generic_mbus_win_remap_2_offset, 857 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 858 .show_cpu_target = mvebu_sdram_debug_show_orion, 859 }; 860 861 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = { 862 .num_wins = 14, 863 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset, 864 .save_cpu_target = mvebu_mbus_default_save_cpu_target, 865 .win_remap_offset = generic_mbus_win_remap_8_offset, 866 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, 867 .show_cpu_target = mvebu_sdram_debug_show_orion, 868 }; 869 870 static const struct of_device_id of_mvebu_mbus_ids[] = { 871 { .compatible = "marvell,armada370-mbus", 872 .data = &armada_370_mbus_data, }, 873 { .compatible = "marvell,armada375-mbus", 874 .data = &armada_xp_mbus_data, }, 875 { .compatible = "marvell,armada380-mbus", 876 .data = &armada_xp_mbus_data, }, 877 { .compatible = "marvell,armadaxp-mbus", 878 .data = &armada_xp_mbus_data, }, 879 { .compatible = "marvell,kirkwood-mbus", 880 .data = &kirkwood_mbus_data, }, 881 { .compatible = "marvell,dove-mbus", 882 .data = &dove_mbus_data, }, 883 { .compatible = "marvell,orion5x-88f5281-mbus", 884 .data = &orion5x_4win_mbus_data, }, 885 { .compatible = "marvell,orion5x-88f5182-mbus", 886 .data = &orion5x_2win_mbus_data, }, 887 { .compatible = "marvell,orion5x-88f5181-mbus", 888 .data = &orion5x_2win_mbus_data, }, 889 { .compatible = "marvell,orion5x-88f6183-mbus", 890 .data = &orion5x_4win_mbus_data, }, 891 { .compatible = "marvell,mv78xx0-mbus", 892 .data = &mv78xx0_mbus_data, }, 893 { }, 894 }; 895 896 /* 897 * Public API of the driver 898 */ 899 int mvebu_mbus_add_window_remap_by_id(unsigned int target, 900 unsigned int attribute, 901 phys_addr_t base, size_t size, 902 phys_addr_t remap) 903 { 904 struct mvebu_mbus_state *s = &mbus_state; 905 906 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { 907 pr_err("cannot add window '%x:%x', conflicts with another window\n", 908 target, attribute); 909 return -EINVAL; 910 } 911 912 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); 913 } 914 EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id); 915 916 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, 917 phys_addr_t base, size_t size) 918 { 919 return mvebu_mbus_add_window_remap_by_id(target, attribute, base, 920 size, MVEBU_MBUS_NO_REMAP); 921 } 922 EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id); 923 924 int mvebu_mbus_del_window(phys_addr_t base, size_t size) 925 { 926 int win; 927 928 win = mvebu_mbus_find_window(&mbus_state, base, size); 929 if (win < 0) 930 return win; 931 932 mvebu_mbus_disable_window(&mbus_state, win); 933 return 0; 934 } 935 EXPORT_SYMBOL_GPL(mvebu_mbus_del_window); 936 937 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res) 938 { 939 if (!res) 940 return; 941 *res = mbus_state.pcie_mem_aperture; 942 } 943 EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture); 944 945 void mvebu_mbus_get_pcie_io_aperture(struct resource *res) 946 { 947 if (!res) 948 return; 949 *res = mbus_state.pcie_io_aperture; 950 } 951 EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture); 952 953 int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) 954 { 955 const struct mbus_dram_target_info *dram; 956 int i; 957 958 /* Get dram info */ 959 dram = mv_mbus_dram_info(); 960 if (!dram) { 961 pr_err("missing DRAM information\n"); 962 return -ENODEV; 963 } 964 965 /* Try to find matching DRAM window for phyaddr */ 966 for (i = 0; i < dram->num_cs; i++) { 967 const struct mbus_dram_window *cs = dram->cs + i; 968 969 if (cs->base <= phyaddr && 970 phyaddr <= (cs->base + cs->size - 1)) { 971 *target = dram->mbus_dram_target_id; 972 *attr = cs->mbus_attr; 973 return 0; 974 } 975 } 976 977 pr_err("invalid dram address %pa\n", &phyaddr); 978 return -EINVAL; 979 } 980 EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info); 981 982 int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target, 983 u8 *attr) 984 { 985 int win; 986 987 for (win = 0; win < mbus_state.soc->num_wins; win++) { 988 u64 wbase; 989 int enabled; 990 991 mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase, 992 size, target, attr, NULL); 993 994 if (!enabled) 995 continue; 996 997 if (wbase <= phyaddr && phyaddr <= wbase + *size) 998 return win; 999 } 1000 1001 return -EINVAL; 1002 } 1003 EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info); 1004 1005 static __init int mvebu_mbus_debugfs_init(void) 1006 { 1007 struct mvebu_mbus_state *s = &mbus_state; 1008 1009 /* 1010 * If no base has been initialized, doesn't make sense to 1011 * register the debugfs entries. We may be on a multiplatform 1012 * kernel that isn't running a Marvell EBU SoC. 1013 */ 1014 if (!s->mbuswins_base) 1015 return 0; 1016 1017 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL); 1018 if (s->debugfs_root) { 1019 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO, 1020 s->debugfs_root, NULL, 1021 &mvebu_sdram_debug_fops); 1022 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO, 1023 s->debugfs_root, NULL, 1024 &mvebu_devs_debug_fops); 1025 } 1026 1027 return 0; 1028 } 1029 fs_initcall(mvebu_mbus_debugfs_init); 1030 1031 static int mvebu_mbus_suspend(void) 1032 { 1033 struct mvebu_mbus_state *s = &mbus_state; 1034 int win; 1035 1036 if (!s->mbusbridge_base) 1037 return -ENODEV; 1038 1039 for (win = 0; win < s->soc->num_wins; win++) { 1040 void __iomem *addr = s->mbuswins_base + 1041 s->soc->win_cfg_offset(win); 1042 void __iomem *addr_rmp; 1043 1044 s->wins[win].base = readl(addr + WIN_BASE_OFF); 1045 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF); 1046 1047 if (!mvebu_mbus_window_is_remappable(s, win)) 1048 continue; 1049 1050 addr_rmp = s->mbuswins_base + 1051 s->soc->win_remap_offset(win); 1052 1053 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF); 1054 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); 1055 } 1056 1057 s->mbus_bridge_ctrl = readl(s->mbusbridge_base + 1058 MBUS_BRIDGE_CTRL_OFF); 1059 s->mbus_bridge_base = readl(s->mbusbridge_base + 1060 MBUS_BRIDGE_BASE_OFF); 1061 1062 return 0; 1063 } 1064 1065 static void mvebu_mbus_resume(void) 1066 { 1067 struct mvebu_mbus_state *s = &mbus_state; 1068 int win; 1069 1070 writel(s->mbus_bridge_ctrl, 1071 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF); 1072 writel(s->mbus_bridge_base, 1073 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF); 1074 1075 for (win = 0; win < s->soc->num_wins; win++) { 1076 void __iomem *addr = s->mbuswins_base + 1077 s->soc->win_cfg_offset(win); 1078 void __iomem *addr_rmp; 1079 1080 writel(s->wins[win].base, addr + WIN_BASE_OFF); 1081 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF); 1082 1083 if (!mvebu_mbus_window_is_remappable(s, win)) 1084 continue; 1085 1086 addr_rmp = s->mbuswins_base + 1087 s->soc->win_remap_offset(win); 1088 1089 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF); 1090 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF); 1091 } 1092 } 1093 1094 static struct syscore_ops mvebu_mbus_syscore_ops = { 1095 .suspend = mvebu_mbus_suspend, 1096 .resume = mvebu_mbus_resume, 1097 }; 1098 1099 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, 1100 phys_addr_t mbuswins_phys_base, 1101 size_t mbuswins_size, 1102 phys_addr_t sdramwins_phys_base, 1103 size_t sdramwins_size, 1104 phys_addr_t mbusbridge_phys_base, 1105 size_t mbusbridge_size, 1106 bool is_coherent) 1107 { 1108 int win; 1109 1110 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size); 1111 if (!mbus->mbuswins_base) 1112 return -ENOMEM; 1113 1114 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size); 1115 if (!mbus->sdramwins_base) { 1116 iounmap(mbus->mbuswins_base); 1117 return -ENOMEM; 1118 } 1119 1120 mbus->sdramwins_phys_base = sdramwins_phys_base; 1121 1122 if (mbusbridge_phys_base) { 1123 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base, 1124 mbusbridge_size); 1125 if (!mbus->mbusbridge_base) { 1126 iounmap(mbus->sdramwins_base); 1127 iounmap(mbus->mbuswins_base); 1128 return -ENOMEM; 1129 } 1130 } else 1131 mbus->mbusbridge_base = NULL; 1132 1133 for (win = 0; win < mbus->soc->num_wins; win++) 1134 mvebu_mbus_disable_window(mbus, win); 1135 1136 mbus->soc->setup_cpu_target(mbus); 1137 mvebu_mbus_setup_cpu_target_nooverlap(mbus); 1138 1139 if (is_coherent) 1140 writel(UNIT_SYNC_BARRIER_ALL, 1141 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); 1142 1143 register_syscore_ops(&mvebu_mbus_syscore_ops); 1144 1145 return 0; 1146 } 1147 1148 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base, 1149 size_t mbuswins_size, 1150 phys_addr_t sdramwins_phys_base, 1151 size_t sdramwins_size) 1152 { 1153 const struct of_device_id *of_id; 1154 1155 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++) 1156 if (!strcmp(of_id->compatible, soc)) 1157 break; 1158 1159 if (!of_id->compatible[0]) { 1160 pr_err("could not find a matching SoC family\n"); 1161 return -ENODEV; 1162 } 1163 1164 mbus_state.soc = of_id->data; 1165 1166 return mvebu_mbus_common_init(&mbus_state, 1167 mbuswins_phys_base, 1168 mbuswins_size, 1169 sdramwins_phys_base, 1170 sdramwins_size, 0, 0, false); 1171 } 1172 1173 #ifdef CONFIG_OF 1174 /* 1175 * The window IDs in the ranges DT property have the following format: 1176 * - bits 28 to 31: MBus custom field 1177 * - bits 24 to 27: window target ID 1178 * - bits 16 to 23: window attribute ID 1179 * - bits 0 to 15: unused 1180 */ 1181 #define CUSTOM(id) (((id) & 0xF0000000) >> 24) 1182 #define TARGET(id) (((id) & 0x0F000000) >> 24) 1183 #define ATTR(id) (((id) & 0x00FF0000) >> 16) 1184 1185 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus, 1186 u32 base, u32 size, 1187 u8 target, u8 attr) 1188 { 1189 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { 1190 pr_err("cannot add window '%04x:%04x', conflicts with another window\n", 1191 target, attr); 1192 return -EBUSY; 1193 } 1194 1195 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP, 1196 target, attr)) { 1197 pr_err("cannot add window '%04x:%04x', too many windows\n", 1198 target, attr); 1199 return -ENOMEM; 1200 } 1201 return 0; 1202 } 1203 1204 static int __init 1205 mbus_parse_ranges(struct device_node *node, 1206 int *addr_cells, int *c_addr_cells, int *c_size_cells, 1207 int *cell_count, const __be32 **ranges_start, 1208 const __be32 **ranges_end) 1209 { 1210 const __be32 *prop; 1211 int ranges_len, tuple_len; 1212 1213 /* Allow a node with no 'ranges' property */ 1214 *ranges_start = of_get_property(node, "ranges", &ranges_len); 1215 if (*ranges_start == NULL) { 1216 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0; 1217 *ranges_start = *ranges_end = NULL; 1218 return 0; 1219 } 1220 *ranges_end = *ranges_start + ranges_len / sizeof(__be32); 1221 1222 *addr_cells = of_n_addr_cells(node); 1223 1224 prop = of_get_property(node, "#address-cells", NULL); 1225 *c_addr_cells = be32_to_cpup(prop); 1226 1227 prop = of_get_property(node, "#size-cells", NULL); 1228 *c_size_cells = be32_to_cpup(prop); 1229 1230 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells; 1231 tuple_len = (*cell_count) * sizeof(__be32); 1232 1233 if (ranges_len % tuple_len) { 1234 pr_warn("malformed ranges entry '%pOFn'\n", node); 1235 return -EINVAL; 1236 } 1237 return 0; 1238 } 1239 1240 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus, 1241 struct device_node *np) 1242 { 1243 int addr_cells, c_addr_cells, c_size_cells; 1244 int i, ret, cell_count; 1245 const __be32 *r, *ranges_start, *ranges_end; 1246 1247 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells, 1248 &c_size_cells, &cell_count, 1249 &ranges_start, &ranges_end); 1250 if (ret < 0) 1251 return ret; 1252 1253 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) { 1254 u32 windowid, base, size; 1255 u8 target, attr; 1256 1257 /* 1258 * An entry with a non-zero custom field do not 1259 * correspond to a static window, so skip it. 1260 */ 1261 windowid = of_read_number(r, 1); 1262 if (CUSTOM(windowid)) 1263 continue; 1264 1265 target = TARGET(windowid); 1266 attr = ATTR(windowid); 1267 1268 base = of_read_number(r + c_addr_cells, addr_cells); 1269 size = of_read_number(r + c_addr_cells + addr_cells, 1270 c_size_cells); 1271 ret = mbus_dt_setup_win(mbus, base, size, target, attr); 1272 if (ret < 0) 1273 return ret; 1274 } 1275 return 0; 1276 } 1277 1278 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, 1279 struct resource *mem, 1280 struct resource *io) 1281 { 1282 u32 reg[2]; 1283 int ret; 1284 1285 /* 1286 * These are optional, so we make sure that resource_size(x) will 1287 * return 0. 1288 */ 1289 memset(mem, 0, sizeof(struct resource)); 1290 mem->end = -1; 1291 memset(io, 0, sizeof(struct resource)); 1292 io->end = -1; 1293 1294 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); 1295 if (!ret) { 1296 mem->start = reg[0]; 1297 mem->end = mem->start + reg[1] - 1; 1298 mem->flags = IORESOURCE_MEM; 1299 } 1300 1301 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg)); 1302 if (!ret) { 1303 io->start = reg[0]; 1304 io->end = io->start + reg[1] - 1; 1305 io->flags = IORESOURCE_IO; 1306 } 1307 } 1308 1309 int __init mvebu_mbus_dt_init(bool is_coherent) 1310 { 1311 struct resource mbuswins_res, sdramwins_res, mbusbridge_res; 1312 struct device_node *np, *controller; 1313 const struct of_device_id *of_id; 1314 const __be32 *prop; 1315 int ret; 1316 1317 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id); 1318 if (!np) { 1319 pr_err("could not find a matching SoC family\n"); 1320 return -ENODEV; 1321 } 1322 1323 mbus_state.soc = of_id->data; 1324 1325 prop = of_get_property(np, "controller", NULL); 1326 if (!prop) { 1327 pr_err("required 'controller' property missing\n"); 1328 return -EINVAL; 1329 } 1330 1331 controller = of_find_node_by_phandle(be32_to_cpup(prop)); 1332 if (!controller) { 1333 pr_err("could not find an 'mbus-controller' node\n"); 1334 return -ENODEV; 1335 } 1336 1337 if (of_address_to_resource(controller, 0, &mbuswins_res)) { 1338 pr_err("cannot get MBUS register address\n"); 1339 return -EINVAL; 1340 } 1341 1342 if (of_address_to_resource(controller, 1, &sdramwins_res)) { 1343 pr_err("cannot get SDRAM register address\n"); 1344 return -EINVAL; 1345 } 1346 1347 /* 1348 * Set the resource to 0 so that it can be left unmapped by 1349 * mvebu_mbus_common_init() if the DT doesn't carry the 1350 * necessary information. This is needed to preserve backward 1351 * compatibility. 1352 */ 1353 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res)); 1354 1355 if (mbus_state.soc->has_mbus_bridge) { 1356 if (of_address_to_resource(controller, 2, &mbusbridge_res)) 1357 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n"); 1358 } 1359 1360 mbus_state.hw_io_coherency = is_coherent; 1361 1362 /* Get optional pcie-{mem,io}-aperture properties */ 1363 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, 1364 &mbus_state.pcie_io_aperture); 1365 1366 ret = mvebu_mbus_common_init(&mbus_state, 1367 mbuswins_res.start, 1368 resource_size(&mbuswins_res), 1369 sdramwins_res.start, 1370 resource_size(&sdramwins_res), 1371 mbusbridge_res.start, 1372 resource_size(&mbusbridge_res), 1373 is_coherent); 1374 if (ret) 1375 return ret; 1376 1377 /* Setup statically declared windows in the DT */ 1378 return mbus_dt_setup(&mbus_state, np); 1379 } 1380 #endif 1381