1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/dma-direction.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/list.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/wait.h> 17 #include "internal.h" 18 19 /* 20 * Not all MHI state transitions are synchronous. Transitions like Linkdown, 21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will 22 * transition to a new state only if we're allowed to. 23 * 24 * Priority increases as we go down. For instance, from any state in L0, the 25 * transition can be made to states in L1, L2 and L3. A notable exception to 26 * this rule is state DISABLE. From DISABLE state we can only transition to 27 * POR state. Also, while in L2 state, user cannot jump back to previous 28 * L1 or L0 states. 29 * 30 * Valid transitions: 31 * L0: DISABLE <--> POR 32 * POR <--> POR 33 * POR -> M0 -> M2 --> M0 34 * POR -> FW_DL_ERR 35 * FW_DL_ERR <--> FW_DL_ERR 36 * M0 <--> M0 37 * M0 -> FW_DL_ERR 38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0 39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR 40 * L2: SHUTDOWN_PROCESS -> LD_ERR_FATAL_DETECT 41 * SHUTDOWN_PROCESS -> DISABLE 42 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT 43 * LD_ERR_FATAL_DETECT -> DISABLE 44 */ 45 static const struct mhi_pm_transitions dev_state_transitions[] = { 46 /* L0 States */ 47 { 48 MHI_PM_DISABLE, 49 MHI_PM_POR 50 }, 51 { 52 MHI_PM_POR, 53 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 | 54 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS | 55 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR 56 }, 57 { 58 MHI_PM_M0, 59 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER | 60 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS | 61 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR 62 }, 63 { 64 MHI_PM_M2, 65 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS | 66 MHI_PM_LD_ERR_FATAL_DETECT 67 }, 68 { 69 MHI_PM_M3_ENTER, 70 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS | 71 MHI_PM_LD_ERR_FATAL_DETECT 72 }, 73 { 74 MHI_PM_M3, 75 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT | 76 MHI_PM_LD_ERR_FATAL_DETECT 77 }, 78 { 79 MHI_PM_M3_EXIT, 80 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS | 81 MHI_PM_LD_ERR_FATAL_DETECT 82 }, 83 { 84 MHI_PM_FW_DL_ERR, 85 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT | 86 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT 87 }, 88 /* L1 States */ 89 { 90 MHI_PM_SYS_ERR_DETECT, 91 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS | 92 MHI_PM_LD_ERR_FATAL_DETECT 93 }, 94 { 95 MHI_PM_SYS_ERR_PROCESS, 96 MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS | 97 MHI_PM_LD_ERR_FATAL_DETECT 98 }, 99 /* L2 States */ 100 { 101 MHI_PM_SHUTDOWN_PROCESS, 102 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT 103 }, 104 /* L3 States */ 105 { 106 MHI_PM_LD_ERR_FATAL_DETECT, 107 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_DISABLE 108 }, 109 }; 110 111 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl, 112 enum mhi_pm_state state) 113 { 114 unsigned long cur_state = mhi_cntrl->pm_state; 115 int index = find_last_bit(&cur_state, 32); 116 117 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions))) 118 return cur_state; 119 120 if (unlikely(dev_state_transitions[index].from_state != cur_state)) 121 return cur_state; 122 123 if (unlikely(!(dev_state_transitions[index].to_states & state))) 124 return cur_state; 125 126 mhi_cntrl->pm_state = state; 127 return mhi_cntrl->pm_state; 128 } 129 130 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state) 131 { 132 if (state == MHI_STATE_RESET) { 133 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, 134 MHICTRL_RESET_MASK, 1); 135 } else { 136 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, 137 MHICTRL_MHISTATE_MASK, state); 138 } 139 } 140 141 /* NOP for backward compatibility, host allowed to ring DB in M2 state */ 142 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl) 143 { 144 } 145 146 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl) 147 { 148 mhi_cntrl->wake_get(mhi_cntrl, false); 149 mhi_cntrl->wake_put(mhi_cntrl, true); 150 } 151 152 /* Handle device ready state transition */ 153 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl) 154 { 155 struct mhi_event *mhi_event; 156 enum mhi_pm_state cur_state; 157 struct device *dev = &mhi_cntrl->mhi_dev->dev; 158 u32 interval_us = 25000; /* poll register field every 25 milliseconds */ 159 int ret, i; 160 161 /* Check if device entered error state */ 162 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) { 163 dev_err(dev, "Device link is not accessible\n"); 164 return -EIO; 165 } 166 167 /* Wait for RESET to be cleared and READY bit to be set by the device */ 168 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, 169 MHICTRL_RESET_MASK, 0, interval_us); 170 if (ret) { 171 dev_err(dev, "Device failed to clear MHI Reset\n"); 172 return ret; 173 } 174 175 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS, 176 MHISTATUS_READY_MASK, 1, interval_us); 177 if (ret) { 178 dev_err(dev, "Device failed to enter MHI Ready\n"); 179 return ret; 180 } 181 182 dev_dbg(dev, "Device in READY State\n"); 183 write_lock_irq(&mhi_cntrl->pm_lock); 184 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR); 185 mhi_cntrl->dev_state = MHI_STATE_READY; 186 write_unlock_irq(&mhi_cntrl->pm_lock); 187 188 if (cur_state != MHI_PM_POR) { 189 dev_err(dev, "Error moving to state %s from %s\n", 190 to_mhi_pm_state_str(MHI_PM_POR), 191 to_mhi_pm_state_str(cur_state)); 192 return -EIO; 193 } 194 195 read_lock_bh(&mhi_cntrl->pm_lock); 196 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { 197 dev_err(dev, "Device registers not accessible\n"); 198 goto error_mmio; 199 } 200 201 /* Configure MMIO registers */ 202 ret = mhi_init_mmio(mhi_cntrl); 203 if (ret) { 204 dev_err(dev, "Error configuring MMIO registers\n"); 205 goto error_mmio; 206 } 207 208 /* Add elements to all SW event rings */ 209 mhi_event = mhi_cntrl->mhi_event; 210 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 211 struct mhi_ring *ring = &mhi_event->ring; 212 213 /* Skip if this is an offload or HW event */ 214 if (mhi_event->offload_ev || mhi_event->hw_ring) 215 continue; 216 217 ring->wp = ring->base + ring->len - ring->el_size; 218 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size); 219 /* Update all cores */ 220 smp_wmb(); 221 222 /* Ring the event ring db */ 223 spin_lock_irq(&mhi_event->lock); 224 mhi_ring_er_db(mhi_event); 225 spin_unlock_irq(&mhi_event->lock); 226 } 227 228 /* Set MHI to M0 state */ 229 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0); 230 read_unlock_bh(&mhi_cntrl->pm_lock); 231 232 return 0; 233 234 error_mmio: 235 read_unlock_bh(&mhi_cntrl->pm_lock); 236 237 return -EIO; 238 } 239 240 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) 241 { 242 enum mhi_pm_state cur_state; 243 struct mhi_chan *mhi_chan; 244 struct device *dev = &mhi_cntrl->mhi_dev->dev; 245 int i; 246 247 write_lock_irq(&mhi_cntrl->pm_lock); 248 mhi_cntrl->dev_state = MHI_STATE_M0; 249 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0); 250 write_unlock_irq(&mhi_cntrl->pm_lock); 251 if (unlikely(cur_state != MHI_PM_M0)) { 252 dev_err(dev, "Unable to transition to M0 state\n"); 253 return -EIO; 254 } 255 mhi_cntrl->M0++; 256 257 /* Wake up the device */ 258 read_lock_bh(&mhi_cntrl->pm_lock); 259 mhi_cntrl->wake_get(mhi_cntrl, true); 260 261 /* Ring all event rings and CMD ring only if we're in mission mode */ 262 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) { 263 struct mhi_event *mhi_event = mhi_cntrl->mhi_event; 264 struct mhi_cmd *mhi_cmd = 265 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; 266 267 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 268 if (mhi_event->offload_ev) 269 continue; 270 271 spin_lock_irq(&mhi_event->lock); 272 mhi_ring_er_db(mhi_event); 273 spin_unlock_irq(&mhi_event->lock); 274 } 275 276 /* Only ring primary cmd ring if ring is not empty */ 277 spin_lock_irq(&mhi_cmd->lock); 278 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp) 279 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); 280 spin_unlock_irq(&mhi_cmd->lock); 281 } 282 283 /* Ring channel DB registers */ 284 mhi_chan = mhi_cntrl->mhi_chan; 285 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 286 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 287 288 if (mhi_chan->db_cfg.reset_req) { 289 write_lock_irq(&mhi_chan->lock); 290 mhi_chan->db_cfg.db_mode = true; 291 write_unlock_irq(&mhi_chan->lock); 292 } 293 294 read_lock_irq(&mhi_chan->lock); 295 296 /* Only ring DB if ring is not empty */ 297 if (tre_ring->base && tre_ring->wp != tre_ring->rp) 298 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 299 read_unlock_irq(&mhi_chan->lock); 300 } 301 302 mhi_cntrl->wake_put(mhi_cntrl, false); 303 read_unlock_bh(&mhi_cntrl->pm_lock); 304 wake_up_all(&mhi_cntrl->state_event); 305 306 return 0; 307 } 308 309 /* 310 * After receiving the MHI state change event from the device indicating the 311 * transition to M1 state, the host can transition the device to M2 state 312 * for keeping it in low power state. 313 */ 314 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl) 315 { 316 enum mhi_pm_state state; 317 struct device *dev = &mhi_cntrl->mhi_dev->dev; 318 319 write_lock_irq(&mhi_cntrl->pm_lock); 320 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2); 321 if (state == MHI_PM_M2) { 322 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2); 323 mhi_cntrl->dev_state = MHI_STATE_M2; 324 325 write_unlock_irq(&mhi_cntrl->pm_lock); 326 327 mhi_cntrl->M2++; 328 wake_up_all(&mhi_cntrl->state_event); 329 330 /* If there are any pending resources, exit M2 immediately */ 331 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) || 332 atomic_read(&mhi_cntrl->dev_wake))) { 333 dev_dbg(dev, 334 "Exiting M2, pending_pkts: %d dev_wake: %d\n", 335 atomic_read(&mhi_cntrl->pending_pkts), 336 atomic_read(&mhi_cntrl->dev_wake)); 337 read_lock_bh(&mhi_cntrl->pm_lock); 338 mhi_cntrl->wake_get(mhi_cntrl, true); 339 mhi_cntrl->wake_put(mhi_cntrl, true); 340 read_unlock_bh(&mhi_cntrl->pm_lock); 341 } else { 342 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE); 343 } 344 } else { 345 write_unlock_irq(&mhi_cntrl->pm_lock); 346 } 347 } 348 349 /* MHI M3 completion handler */ 350 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl) 351 { 352 enum mhi_pm_state state; 353 struct device *dev = &mhi_cntrl->mhi_dev->dev; 354 355 write_lock_irq(&mhi_cntrl->pm_lock); 356 mhi_cntrl->dev_state = MHI_STATE_M3; 357 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3); 358 write_unlock_irq(&mhi_cntrl->pm_lock); 359 if (state != MHI_PM_M3) { 360 dev_err(dev, "Unable to transition to M3 state\n"); 361 return -EIO; 362 } 363 364 mhi_cntrl->M3++; 365 wake_up_all(&mhi_cntrl->state_event); 366 367 return 0; 368 } 369 370 /* Handle device Mission Mode transition */ 371 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) 372 { 373 struct mhi_event *mhi_event; 374 struct device *dev = &mhi_cntrl->mhi_dev->dev; 375 enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee; 376 int i, ret; 377 378 dev_dbg(dev, "Processing Mission Mode transition\n"); 379 380 write_lock_irq(&mhi_cntrl->pm_lock); 381 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) 382 ee = mhi_get_exec_env(mhi_cntrl); 383 384 if (!MHI_IN_MISSION_MODE(ee)) { 385 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT; 386 write_unlock_irq(&mhi_cntrl->pm_lock); 387 wake_up_all(&mhi_cntrl->state_event); 388 return -EIO; 389 } 390 mhi_cntrl->ee = ee; 391 write_unlock_irq(&mhi_cntrl->pm_lock); 392 393 wake_up_all(&mhi_cntrl->state_event); 394 395 device_for_each_child(&mhi_cntrl->mhi_dev->dev, ¤t_ee, 396 mhi_destroy_device); 397 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE); 398 399 /* Force MHI to be in M0 state before continuing */ 400 ret = __mhi_device_get_sync(mhi_cntrl); 401 if (ret) 402 return ret; 403 404 read_lock_bh(&mhi_cntrl->pm_lock); 405 406 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 407 ret = -EIO; 408 goto error_mission_mode; 409 } 410 411 /* Add elements to all HW event rings */ 412 mhi_event = mhi_cntrl->mhi_event; 413 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 414 struct mhi_ring *ring = &mhi_event->ring; 415 416 if (mhi_event->offload_ev || !mhi_event->hw_ring) 417 continue; 418 419 ring->wp = ring->base + ring->len - ring->el_size; 420 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size); 421 /* Update to all cores */ 422 smp_wmb(); 423 424 spin_lock_irq(&mhi_event->lock); 425 if (MHI_DB_ACCESS_VALID(mhi_cntrl)) 426 mhi_ring_er_db(mhi_event); 427 spin_unlock_irq(&mhi_event->lock); 428 } 429 430 read_unlock_bh(&mhi_cntrl->pm_lock); 431 432 /* 433 * The MHI devices are only created when the client device switches its 434 * Execution Environment (EE) to either SBL or AMSS states 435 */ 436 mhi_create_devices(mhi_cntrl); 437 438 read_lock_bh(&mhi_cntrl->pm_lock); 439 440 error_mission_mode: 441 mhi_cntrl->wake_put(mhi_cntrl, false); 442 read_unlock_bh(&mhi_cntrl->pm_lock); 443 444 return ret; 445 } 446 447 /* Handle shutdown transitions */ 448 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl) 449 { 450 enum mhi_pm_state cur_state; 451 struct mhi_event *mhi_event; 452 struct mhi_cmd_ctxt *cmd_ctxt; 453 struct mhi_cmd *mhi_cmd; 454 struct mhi_event_ctxt *er_ctxt; 455 struct device *dev = &mhi_cntrl->mhi_dev->dev; 456 int ret, i; 457 458 dev_dbg(dev, "Processing disable transition with PM state: %s\n", 459 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 460 461 mutex_lock(&mhi_cntrl->pm_mutex); 462 463 /* Trigger MHI RESET so that the device will not access host memory */ 464 if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) { 465 dev_dbg(dev, "Triggering MHI Reset in device\n"); 466 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); 467 468 /* Wait for the reset bit to be cleared by the device */ 469 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, 470 MHICTRL_RESET_MASK, 0, 25000); 471 if (ret) 472 dev_err(dev, "Device failed to clear MHI Reset\n"); 473 474 /* 475 * Device will clear BHI_INTVEC as a part of RESET processing, 476 * hence re-program it 477 */ 478 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); 479 } 480 481 dev_dbg(dev, 482 "Waiting for all pending event ring processing to complete\n"); 483 mhi_event = mhi_cntrl->mhi_event; 484 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 485 if (mhi_event->offload_ev) 486 continue; 487 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); 488 tasklet_kill(&mhi_event->task); 489 } 490 491 /* Release lock and wait for all pending threads to complete */ 492 mutex_unlock(&mhi_cntrl->pm_mutex); 493 dev_dbg(dev, "Waiting for all pending threads to complete\n"); 494 wake_up_all(&mhi_cntrl->state_event); 495 496 dev_dbg(dev, "Reset all active channels and remove MHI devices\n"); 497 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device); 498 499 mutex_lock(&mhi_cntrl->pm_mutex); 500 501 WARN_ON(atomic_read(&mhi_cntrl->dev_wake)); 502 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts)); 503 504 /* Reset the ev rings and cmd rings */ 505 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n"); 506 mhi_cmd = mhi_cntrl->mhi_cmd; 507 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt; 508 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) { 509 struct mhi_ring *ring = &mhi_cmd->ring; 510 511 ring->rp = ring->base; 512 ring->wp = ring->base; 513 cmd_ctxt->rp = cmd_ctxt->rbase; 514 cmd_ctxt->wp = cmd_ctxt->rbase; 515 } 516 517 mhi_event = mhi_cntrl->mhi_event; 518 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt; 519 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, 520 mhi_event++) { 521 struct mhi_ring *ring = &mhi_event->ring; 522 523 /* Skip offload events */ 524 if (mhi_event->offload_ev) 525 continue; 526 527 ring->rp = ring->base; 528 ring->wp = ring->base; 529 er_ctxt->rp = er_ctxt->rbase; 530 er_ctxt->wp = er_ctxt->rbase; 531 } 532 533 /* Move to disable state */ 534 write_lock_irq(&mhi_cntrl->pm_lock); 535 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE); 536 write_unlock_irq(&mhi_cntrl->pm_lock); 537 if (unlikely(cur_state != MHI_PM_DISABLE)) 538 dev_err(dev, "Error moving from PM state: %s to: %s\n", 539 to_mhi_pm_state_str(cur_state), 540 to_mhi_pm_state_str(MHI_PM_DISABLE)); 541 542 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n", 543 to_mhi_pm_state_str(mhi_cntrl->pm_state), 544 mhi_state_str(mhi_cntrl->dev_state)); 545 546 mutex_unlock(&mhi_cntrl->pm_mutex); 547 } 548 549 /* Handle system error transitions */ 550 static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl) 551 { 552 enum mhi_pm_state cur_state, prev_state; 553 enum dev_st_transition next_state; 554 struct mhi_event *mhi_event; 555 struct mhi_cmd_ctxt *cmd_ctxt; 556 struct mhi_cmd *mhi_cmd; 557 struct mhi_event_ctxt *er_ctxt; 558 struct device *dev = &mhi_cntrl->mhi_dev->dev; 559 int ret, i; 560 561 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n", 562 to_mhi_pm_state_str(mhi_cntrl->pm_state), 563 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS)); 564 565 /* We must notify MHI control driver so it can clean up first */ 566 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR); 567 568 mutex_lock(&mhi_cntrl->pm_mutex); 569 write_lock_irq(&mhi_cntrl->pm_lock); 570 prev_state = mhi_cntrl->pm_state; 571 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS); 572 write_unlock_irq(&mhi_cntrl->pm_lock); 573 574 if (cur_state != MHI_PM_SYS_ERR_PROCESS) { 575 dev_err(dev, "Failed to transition from PM state: %s to: %s\n", 576 to_mhi_pm_state_str(cur_state), 577 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS)); 578 goto exit_sys_error_transition; 579 } 580 581 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION; 582 mhi_cntrl->dev_state = MHI_STATE_RESET; 583 584 /* Wake up threads waiting for state transition */ 585 wake_up_all(&mhi_cntrl->state_event); 586 587 /* Trigger MHI RESET so that the device will not access host memory */ 588 if (MHI_REG_ACCESS_VALID(prev_state)) { 589 u32 in_reset = -1; 590 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms); 591 592 dev_dbg(dev, "Triggering MHI Reset in device\n"); 593 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); 594 595 /* Wait for the reset bit to be cleared by the device */ 596 ret = wait_event_timeout(mhi_cntrl->state_event, 597 mhi_read_reg_field(mhi_cntrl, 598 mhi_cntrl->regs, 599 MHICTRL, 600 MHICTRL_RESET_MASK, 601 &in_reset) || 602 !in_reset, timeout); 603 if (!ret || in_reset) { 604 dev_err(dev, "Device failed to exit MHI Reset state\n"); 605 goto exit_sys_error_transition; 606 } 607 608 /* 609 * Device will clear BHI_INTVEC as a part of RESET processing, 610 * hence re-program it 611 */ 612 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); 613 } 614 615 dev_dbg(dev, 616 "Waiting for all pending event ring processing to complete\n"); 617 mhi_event = mhi_cntrl->mhi_event; 618 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 619 if (mhi_event->offload_ev) 620 continue; 621 tasklet_kill(&mhi_event->task); 622 } 623 624 /* Release lock and wait for all pending threads to complete */ 625 mutex_unlock(&mhi_cntrl->pm_mutex); 626 dev_dbg(dev, "Waiting for all pending threads to complete\n"); 627 wake_up_all(&mhi_cntrl->state_event); 628 629 dev_dbg(dev, "Reset all active channels and remove MHI devices\n"); 630 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device); 631 632 mutex_lock(&mhi_cntrl->pm_mutex); 633 634 WARN_ON(atomic_read(&mhi_cntrl->dev_wake)); 635 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts)); 636 637 /* Reset the ev rings and cmd rings */ 638 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n"); 639 mhi_cmd = mhi_cntrl->mhi_cmd; 640 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt; 641 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) { 642 struct mhi_ring *ring = &mhi_cmd->ring; 643 644 ring->rp = ring->base; 645 ring->wp = ring->base; 646 cmd_ctxt->rp = cmd_ctxt->rbase; 647 cmd_ctxt->wp = cmd_ctxt->rbase; 648 } 649 650 mhi_event = mhi_cntrl->mhi_event; 651 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt; 652 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, 653 mhi_event++) { 654 struct mhi_ring *ring = &mhi_event->ring; 655 656 /* Skip offload events */ 657 if (mhi_event->offload_ev) 658 continue; 659 660 ring->rp = ring->base; 661 ring->wp = ring->base; 662 er_ctxt->rp = er_ctxt->rbase; 663 er_ctxt->wp = er_ctxt->rbase; 664 } 665 666 /* Transition to next state */ 667 if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) { 668 write_lock_irq(&mhi_cntrl->pm_lock); 669 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR); 670 write_unlock_irq(&mhi_cntrl->pm_lock); 671 if (cur_state != MHI_PM_POR) { 672 dev_err(dev, "Error moving to state %s from %s\n", 673 to_mhi_pm_state_str(MHI_PM_POR), 674 to_mhi_pm_state_str(cur_state)); 675 goto exit_sys_error_transition; 676 } 677 next_state = DEV_ST_TRANSITION_PBL; 678 } else { 679 next_state = DEV_ST_TRANSITION_READY; 680 } 681 682 mhi_queue_state_transition(mhi_cntrl, next_state); 683 684 exit_sys_error_transition: 685 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n", 686 to_mhi_pm_state_str(mhi_cntrl->pm_state), 687 mhi_state_str(mhi_cntrl->dev_state)); 688 689 mutex_unlock(&mhi_cntrl->pm_mutex); 690 } 691 692 /* Queue a new work item and schedule work */ 693 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, 694 enum dev_st_transition state) 695 { 696 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC); 697 unsigned long flags; 698 699 if (!item) 700 return -ENOMEM; 701 702 item->state = state; 703 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags); 704 list_add_tail(&item->node, &mhi_cntrl->transition_list); 705 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags); 706 707 queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker); 708 709 return 0; 710 } 711 712 /* SYS_ERR worker */ 713 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl) 714 { 715 struct device *dev = &mhi_cntrl->mhi_dev->dev; 716 717 /* skip if controller supports RDDM */ 718 if (mhi_cntrl->rddm_image) { 719 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n"); 720 return; 721 } 722 723 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR); 724 } 725 726 /* Device State Transition worker */ 727 void mhi_pm_st_worker(struct work_struct *work) 728 { 729 struct state_transition *itr, *tmp; 730 LIST_HEAD(head); 731 struct mhi_controller *mhi_cntrl = container_of(work, 732 struct mhi_controller, 733 st_worker); 734 struct device *dev = &mhi_cntrl->mhi_dev->dev; 735 736 spin_lock_irq(&mhi_cntrl->transition_lock); 737 list_splice_tail_init(&mhi_cntrl->transition_list, &head); 738 spin_unlock_irq(&mhi_cntrl->transition_lock); 739 740 list_for_each_entry_safe(itr, tmp, &head, node) { 741 list_del(&itr->node); 742 dev_dbg(dev, "Handling state transition: %s\n", 743 TO_DEV_STATE_TRANS_STR(itr->state)); 744 745 switch (itr->state) { 746 case DEV_ST_TRANSITION_PBL: 747 write_lock_irq(&mhi_cntrl->pm_lock); 748 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) 749 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); 750 write_unlock_irq(&mhi_cntrl->pm_lock); 751 mhi_fw_load_handler(mhi_cntrl); 752 break; 753 case DEV_ST_TRANSITION_SBL: 754 write_lock_irq(&mhi_cntrl->pm_lock); 755 mhi_cntrl->ee = MHI_EE_SBL; 756 write_unlock_irq(&mhi_cntrl->pm_lock); 757 /* 758 * The MHI devices are only created when the client 759 * device switches its Execution Environment (EE) to 760 * either SBL or AMSS states 761 */ 762 mhi_create_devices(mhi_cntrl); 763 if (mhi_cntrl->fbc_download) 764 mhi_download_amss_image(mhi_cntrl); 765 break; 766 case DEV_ST_TRANSITION_MISSION_MODE: 767 mhi_pm_mission_mode_transition(mhi_cntrl); 768 break; 769 case DEV_ST_TRANSITION_FP: 770 write_lock_irq(&mhi_cntrl->pm_lock); 771 mhi_cntrl->ee = MHI_EE_FP; 772 write_unlock_irq(&mhi_cntrl->pm_lock); 773 mhi_create_devices(mhi_cntrl); 774 break; 775 case DEV_ST_TRANSITION_READY: 776 mhi_ready_state_transition(mhi_cntrl); 777 break; 778 case DEV_ST_TRANSITION_SYS_ERR: 779 mhi_pm_sys_error_transition(mhi_cntrl); 780 break; 781 case DEV_ST_TRANSITION_DISABLE: 782 mhi_pm_disable_transition(mhi_cntrl); 783 break; 784 default: 785 break; 786 } 787 kfree(itr); 788 } 789 } 790 791 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) 792 { 793 struct mhi_chan *itr, *tmp; 794 struct device *dev = &mhi_cntrl->mhi_dev->dev; 795 enum mhi_pm_state new_state; 796 int ret; 797 798 if (mhi_cntrl->pm_state == MHI_PM_DISABLE) 799 return -EINVAL; 800 801 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) 802 return -EIO; 803 804 /* Return busy if there are any pending resources */ 805 if (atomic_read(&mhi_cntrl->dev_wake) || 806 atomic_read(&mhi_cntrl->pending_pkts)) 807 return -EBUSY; 808 809 /* Take MHI out of M2 state */ 810 read_lock_bh(&mhi_cntrl->pm_lock); 811 mhi_cntrl->wake_get(mhi_cntrl, false); 812 read_unlock_bh(&mhi_cntrl->pm_lock); 813 814 ret = wait_event_timeout(mhi_cntrl->state_event, 815 mhi_cntrl->dev_state == MHI_STATE_M0 || 816 mhi_cntrl->dev_state == MHI_STATE_M1 || 817 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), 818 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 819 820 read_lock_bh(&mhi_cntrl->pm_lock); 821 mhi_cntrl->wake_put(mhi_cntrl, false); 822 read_unlock_bh(&mhi_cntrl->pm_lock); 823 824 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 825 dev_err(dev, 826 "Could not enter M0/M1 state"); 827 return -EIO; 828 } 829 830 write_lock_irq(&mhi_cntrl->pm_lock); 831 832 if (atomic_read(&mhi_cntrl->dev_wake) || 833 atomic_read(&mhi_cntrl->pending_pkts)) { 834 write_unlock_irq(&mhi_cntrl->pm_lock); 835 return -EBUSY; 836 } 837 838 dev_dbg(dev, "Allowing M3 transition\n"); 839 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER); 840 if (new_state != MHI_PM_M3_ENTER) { 841 write_unlock_irq(&mhi_cntrl->pm_lock); 842 dev_err(dev, 843 "Error setting to PM state: %s from: %s\n", 844 to_mhi_pm_state_str(MHI_PM_M3_ENTER), 845 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 846 return -EIO; 847 } 848 849 /* Set MHI to M3 and wait for completion */ 850 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3); 851 write_unlock_irq(&mhi_cntrl->pm_lock); 852 dev_dbg(dev, "Waiting for M3 completion\n"); 853 854 ret = wait_event_timeout(mhi_cntrl->state_event, 855 mhi_cntrl->dev_state == MHI_STATE_M3 || 856 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), 857 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 858 859 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 860 dev_err(dev, 861 "Did not enter M3 state, MHI state: %s, PM state: %s\n", 862 mhi_state_str(mhi_cntrl->dev_state), 863 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 864 return -EIO; 865 } 866 867 /* Notify clients about entering LPM */ 868 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { 869 mutex_lock(&itr->mutex); 870 if (itr->mhi_dev) 871 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER); 872 mutex_unlock(&itr->mutex); 873 } 874 875 return 0; 876 } 877 EXPORT_SYMBOL_GPL(mhi_pm_suspend); 878 879 static int __mhi_pm_resume(struct mhi_controller *mhi_cntrl, bool force) 880 { 881 struct mhi_chan *itr, *tmp; 882 struct device *dev = &mhi_cntrl->mhi_dev->dev; 883 enum mhi_pm_state cur_state; 884 int ret; 885 886 dev_dbg(dev, "Entered with PM state: %s, MHI state: %s\n", 887 to_mhi_pm_state_str(mhi_cntrl->pm_state), 888 mhi_state_str(mhi_cntrl->dev_state)); 889 890 if (mhi_cntrl->pm_state == MHI_PM_DISABLE) 891 return 0; 892 893 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) 894 return -EIO; 895 896 if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3) { 897 dev_warn(dev, "Resuming from non M3 state (%s)\n", 898 mhi_state_str(mhi_get_mhi_state(mhi_cntrl))); 899 if (!force) 900 return -EINVAL; 901 } 902 903 /* Notify clients about exiting LPM */ 904 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { 905 mutex_lock(&itr->mutex); 906 if (itr->mhi_dev) 907 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT); 908 mutex_unlock(&itr->mutex); 909 } 910 911 write_lock_irq(&mhi_cntrl->pm_lock); 912 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT); 913 if (cur_state != MHI_PM_M3_EXIT) { 914 write_unlock_irq(&mhi_cntrl->pm_lock); 915 dev_info(dev, 916 "Error setting to PM state: %s from: %s\n", 917 to_mhi_pm_state_str(MHI_PM_M3_EXIT), 918 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 919 return -EIO; 920 } 921 922 /* Set MHI to M0 and wait for completion */ 923 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0); 924 write_unlock_irq(&mhi_cntrl->pm_lock); 925 926 ret = wait_event_timeout(mhi_cntrl->state_event, 927 mhi_cntrl->dev_state == MHI_STATE_M0 || 928 mhi_cntrl->dev_state == MHI_STATE_M2 || 929 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), 930 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 931 932 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 933 dev_err(dev, 934 "Did not enter M0 state, MHI state: %s, PM state: %s\n", 935 mhi_state_str(mhi_cntrl->dev_state), 936 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 937 return -EIO; 938 } 939 940 return 0; 941 } 942 943 int mhi_pm_resume(struct mhi_controller *mhi_cntrl) 944 { 945 return __mhi_pm_resume(mhi_cntrl, false); 946 } 947 EXPORT_SYMBOL_GPL(mhi_pm_resume); 948 949 int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl) 950 { 951 return __mhi_pm_resume(mhi_cntrl, true); 952 } 953 EXPORT_SYMBOL_GPL(mhi_pm_resume_force); 954 955 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) 956 { 957 int ret; 958 959 /* Wake up the device */ 960 read_lock_bh(&mhi_cntrl->pm_lock); 961 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 962 read_unlock_bh(&mhi_cntrl->pm_lock); 963 return -EIO; 964 } 965 mhi_cntrl->wake_get(mhi_cntrl, true); 966 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) 967 mhi_trigger_resume(mhi_cntrl); 968 read_unlock_bh(&mhi_cntrl->pm_lock); 969 970 ret = wait_event_timeout(mhi_cntrl->state_event, 971 mhi_cntrl->pm_state == MHI_PM_M0 || 972 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), 973 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 974 975 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { 976 read_lock_bh(&mhi_cntrl->pm_lock); 977 mhi_cntrl->wake_put(mhi_cntrl, false); 978 read_unlock_bh(&mhi_cntrl->pm_lock); 979 return -EIO; 980 } 981 982 return 0; 983 } 984 985 /* Assert device wake db */ 986 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force) 987 { 988 unsigned long flags; 989 990 /* 991 * If force flag is set, then increment the wake count value and 992 * ring wake db 993 */ 994 if (unlikely(force)) { 995 spin_lock_irqsave(&mhi_cntrl->wlock, flags); 996 atomic_inc(&mhi_cntrl->dev_wake); 997 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) && 998 !mhi_cntrl->wake_set) { 999 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1); 1000 mhi_cntrl->wake_set = true; 1001 } 1002 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); 1003 } else { 1004 /* 1005 * If resources are already requested, then just increment 1006 * the wake count value and return 1007 */ 1008 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0))) 1009 return; 1010 1011 spin_lock_irqsave(&mhi_cntrl->wlock, flags); 1012 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) && 1013 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) && 1014 !mhi_cntrl->wake_set) { 1015 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1); 1016 mhi_cntrl->wake_set = true; 1017 } 1018 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); 1019 } 1020 } 1021 1022 /* De-assert device wake db */ 1023 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl, 1024 bool override) 1025 { 1026 unsigned long flags; 1027 1028 /* 1029 * Only continue if there is a single resource, else just decrement 1030 * and return 1031 */ 1032 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1))) 1033 return; 1034 1035 spin_lock_irqsave(&mhi_cntrl->wlock, flags); 1036 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) && 1037 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override && 1038 mhi_cntrl->wake_set) { 1039 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0); 1040 mhi_cntrl->wake_set = false; 1041 } 1042 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); 1043 } 1044 1045 int mhi_async_power_up(struct mhi_controller *mhi_cntrl) 1046 { 1047 enum mhi_state state; 1048 enum mhi_ee_type current_ee; 1049 enum dev_st_transition next_state; 1050 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1051 u32 interval_us = 25000; /* poll register field every 25 milliseconds */ 1052 int ret; 1053 1054 dev_info(dev, "Requested to power ON\n"); 1055 1056 /* Supply default wake routines if not provided by controller driver */ 1057 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put || 1058 !mhi_cntrl->wake_toggle) { 1059 mhi_cntrl->wake_get = mhi_assert_dev_wake; 1060 mhi_cntrl->wake_put = mhi_deassert_dev_wake; 1061 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ? 1062 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake; 1063 } 1064 1065 mutex_lock(&mhi_cntrl->pm_mutex); 1066 mhi_cntrl->pm_state = MHI_PM_DISABLE; 1067 1068 /* Setup BHI INTVEC */ 1069 write_lock_irq(&mhi_cntrl->pm_lock); 1070 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); 1071 mhi_cntrl->pm_state = MHI_PM_POR; 1072 mhi_cntrl->ee = MHI_EE_MAX; 1073 current_ee = mhi_get_exec_env(mhi_cntrl); 1074 write_unlock_irq(&mhi_cntrl->pm_lock); 1075 1076 /* Confirm that the device is in valid exec env */ 1077 if (!MHI_POWER_UP_CAPABLE(current_ee)) { 1078 dev_err(dev, "%s is not a valid EE for power on\n", 1079 TO_MHI_EXEC_STR(current_ee)); 1080 ret = -EIO; 1081 goto error_exit; 1082 } 1083 1084 state = mhi_get_mhi_state(mhi_cntrl); 1085 dev_dbg(dev, "Attempting power on with EE: %s, state: %s\n", 1086 TO_MHI_EXEC_STR(current_ee), mhi_state_str(state)); 1087 1088 if (state == MHI_STATE_SYS_ERR) { 1089 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); 1090 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL, 1091 MHICTRL_RESET_MASK, 0, interval_us); 1092 if (ret) { 1093 dev_info(dev, "Failed to reset MHI due to syserr state\n"); 1094 goto error_exit; 1095 } 1096 1097 /* 1098 * device cleares INTVEC as part of RESET processing, 1099 * re-program it 1100 */ 1101 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); 1102 } 1103 1104 ret = mhi_init_irq_setup(mhi_cntrl); 1105 if (ret) 1106 goto error_exit; 1107 1108 /* Transition to next state */ 1109 next_state = MHI_IN_PBL(current_ee) ? 1110 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY; 1111 1112 mhi_queue_state_transition(mhi_cntrl, next_state); 1113 1114 mutex_unlock(&mhi_cntrl->pm_mutex); 1115 1116 dev_info(dev, "Power on setup success\n"); 1117 1118 return 0; 1119 1120 error_exit: 1121 mhi_cntrl->pm_state = MHI_PM_DISABLE; 1122 mutex_unlock(&mhi_cntrl->pm_mutex); 1123 1124 return ret; 1125 } 1126 EXPORT_SYMBOL_GPL(mhi_async_power_up); 1127 1128 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful) 1129 { 1130 enum mhi_pm_state cur_state, transition_state; 1131 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1132 1133 mutex_lock(&mhi_cntrl->pm_mutex); 1134 write_lock_irq(&mhi_cntrl->pm_lock); 1135 cur_state = mhi_cntrl->pm_state; 1136 if (cur_state == MHI_PM_DISABLE) { 1137 write_unlock_irq(&mhi_cntrl->pm_lock); 1138 mutex_unlock(&mhi_cntrl->pm_mutex); 1139 return; /* Already powered down */ 1140 } 1141 1142 /* If it's not a graceful shutdown, force MHI to linkdown state */ 1143 transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS : 1144 MHI_PM_LD_ERR_FATAL_DETECT; 1145 1146 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state); 1147 if (cur_state != transition_state) { 1148 dev_err(dev, "Failed to move to state: %s from: %s\n", 1149 to_mhi_pm_state_str(transition_state), 1150 to_mhi_pm_state_str(mhi_cntrl->pm_state)); 1151 /* Force link down or error fatal detected state */ 1152 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT; 1153 } 1154 1155 /* mark device inactive to avoid any further host processing */ 1156 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION; 1157 mhi_cntrl->dev_state = MHI_STATE_RESET; 1158 1159 wake_up_all(&mhi_cntrl->state_event); 1160 1161 write_unlock_irq(&mhi_cntrl->pm_lock); 1162 mutex_unlock(&mhi_cntrl->pm_mutex); 1163 1164 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE); 1165 1166 /* Wait for shutdown to complete */ 1167 flush_work(&mhi_cntrl->st_worker); 1168 1169 free_irq(mhi_cntrl->irq[0], mhi_cntrl); 1170 } 1171 EXPORT_SYMBOL_GPL(mhi_power_down); 1172 1173 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl) 1174 { 1175 int ret = mhi_async_power_up(mhi_cntrl); 1176 1177 if (ret) 1178 return ret; 1179 1180 wait_event_timeout(mhi_cntrl->state_event, 1181 MHI_IN_MISSION_MODE(mhi_cntrl->ee) || 1182 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), 1183 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 1184 1185 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT; 1186 if (ret) 1187 mhi_power_down(mhi_cntrl, false); 1188 1189 return ret; 1190 } 1191 EXPORT_SYMBOL(mhi_sync_power_up); 1192 1193 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl) 1194 { 1195 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1196 int ret; 1197 1198 /* Check if device is already in RDDM */ 1199 if (mhi_cntrl->ee == MHI_EE_RDDM) 1200 return 0; 1201 1202 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n"); 1203 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR); 1204 1205 /* Wait for RDDM event */ 1206 ret = wait_event_timeout(mhi_cntrl->state_event, 1207 mhi_cntrl->ee == MHI_EE_RDDM, 1208 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 1209 ret = ret ? 0 : -EIO; 1210 1211 return ret; 1212 } 1213 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode); 1214 1215 void mhi_device_get(struct mhi_device *mhi_dev) 1216 { 1217 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1218 1219 mhi_dev->dev_wake++; 1220 read_lock_bh(&mhi_cntrl->pm_lock); 1221 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) 1222 mhi_trigger_resume(mhi_cntrl); 1223 1224 mhi_cntrl->wake_get(mhi_cntrl, true); 1225 read_unlock_bh(&mhi_cntrl->pm_lock); 1226 } 1227 EXPORT_SYMBOL_GPL(mhi_device_get); 1228 1229 int mhi_device_get_sync(struct mhi_device *mhi_dev) 1230 { 1231 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1232 int ret; 1233 1234 ret = __mhi_device_get_sync(mhi_cntrl); 1235 if (!ret) 1236 mhi_dev->dev_wake++; 1237 1238 return ret; 1239 } 1240 EXPORT_SYMBOL_GPL(mhi_device_get_sync); 1241 1242 void mhi_device_put(struct mhi_device *mhi_dev) 1243 { 1244 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1245 1246 mhi_dev->dev_wake--; 1247 read_lock_bh(&mhi_cntrl->pm_lock); 1248 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) 1249 mhi_trigger_resume(mhi_cntrl); 1250 1251 mhi_cntrl->wake_put(mhi_cntrl, false); 1252 read_unlock_bh(&mhi_cntrl->pm_lock); 1253 } 1254 EXPORT_SYMBOL_GPL(mhi_device_put); 1255