1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/aer.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/mhi.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/timer.h> 19 #include <linux/workqueue.h> 20 21 #define MHI_PCI_DEFAULT_BAR_NUM 0 22 23 #define MHI_POST_RESET_DELAY_MS 2000 24 25 #define HEALTH_CHECK_PERIOD (HZ * 2) 26 27 /** 28 * struct mhi_pci_dev_info - MHI PCI device specific information 29 * @config: MHI controller configuration 30 * @name: name of the PCI module 31 * @fw: firmware path (if any) 32 * @edl: emergency download mode firmware path (if any) 33 * @bar_num: PCI base address register to use for MHI MMIO register space 34 * @dma_data_width: DMA transfer word size (32 or 64 bits) 35 * @mru_default: default MRU size for MBIM network packets 36 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 37 * of inband wake support (such as sdx24) 38 */ 39 struct mhi_pci_dev_info { 40 const struct mhi_controller_config *config; 41 const char *name; 42 const char *fw; 43 const char *edl; 44 unsigned int bar_num; 45 unsigned int dma_data_width; 46 unsigned int mru_default; 47 bool sideband_wake; 48 }; 49 50 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 51 { \ 52 .num = ch_num, \ 53 .name = ch_name, \ 54 .num_elements = el_count, \ 55 .event_ring = ev_ring, \ 56 .dir = DMA_TO_DEVICE, \ 57 .ee_mask = BIT(MHI_EE_AMSS), \ 58 .pollcfg = 0, \ 59 .doorbell = MHI_DB_BRST_DISABLE, \ 60 .lpm_notify = false, \ 61 .offload_channel = false, \ 62 .doorbell_mode_switch = false, \ 63 } \ 64 65 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 66 { \ 67 .num = ch_num, \ 68 .name = ch_name, \ 69 .num_elements = el_count, \ 70 .event_ring = ev_ring, \ 71 .dir = DMA_FROM_DEVICE, \ 72 .ee_mask = BIT(MHI_EE_AMSS), \ 73 .pollcfg = 0, \ 74 .doorbell = MHI_DB_BRST_DISABLE, \ 75 .lpm_notify = false, \ 76 .offload_channel = false, \ 77 .doorbell_mode_switch = false, \ 78 } 79 80 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 81 { \ 82 .num = ch_num, \ 83 .name = ch_name, \ 84 .num_elements = el_count, \ 85 .event_ring = ev_ring, \ 86 .dir = DMA_FROM_DEVICE, \ 87 .ee_mask = BIT(MHI_EE_AMSS), \ 88 .pollcfg = 0, \ 89 .doorbell = MHI_DB_BRST_DISABLE, \ 90 .lpm_notify = false, \ 91 .offload_channel = false, \ 92 .doorbell_mode_switch = false, \ 93 .auto_queue = true, \ 94 } 95 96 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 97 { \ 98 .num_elements = el_count, \ 99 .irq_moderation_ms = 0, \ 100 .irq = (ev_ring) + 1, \ 101 .priority = 1, \ 102 .mode = MHI_DB_BRST_DISABLE, \ 103 .data_type = MHI_ER_CTRL, \ 104 .hardware_event = false, \ 105 .client_managed = false, \ 106 .offload_channel = false, \ 107 } 108 109 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 110 { \ 111 .num = ch_num, \ 112 .name = ch_name, \ 113 .num_elements = el_count, \ 114 .event_ring = ev_ring, \ 115 .dir = DMA_TO_DEVICE, \ 116 .ee_mask = BIT(MHI_EE_AMSS), \ 117 .pollcfg = 0, \ 118 .doorbell = MHI_DB_BRST_ENABLE, \ 119 .lpm_notify = false, \ 120 .offload_channel = false, \ 121 .doorbell_mode_switch = true, \ 122 } \ 123 124 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 125 { \ 126 .num = ch_num, \ 127 .name = ch_name, \ 128 .num_elements = el_count, \ 129 .event_ring = ev_ring, \ 130 .dir = DMA_FROM_DEVICE, \ 131 .ee_mask = BIT(MHI_EE_AMSS), \ 132 .pollcfg = 0, \ 133 .doorbell = MHI_DB_BRST_ENABLE, \ 134 .lpm_notify = false, \ 135 .offload_channel = false, \ 136 .doorbell_mode_switch = true, \ 137 } 138 139 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 140 { \ 141 .num = ch_num, \ 142 .name = ch_name, \ 143 .num_elements = el_count, \ 144 .event_ring = ev_ring, \ 145 .dir = DMA_TO_DEVICE, \ 146 .ee_mask = BIT(MHI_EE_SBL), \ 147 .pollcfg = 0, \ 148 .doorbell = MHI_DB_BRST_DISABLE, \ 149 .lpm_notify = false, \ 150 .offload_channel = false, \ 151 .doorbell_mode_switch = false, \ 152 } \ 153 154 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 155 { \ 156 .num = ch_num, \ 157 .name = ch_name, \ 158 .num_elements = el_count, \ 159 .event_ring = ev_ring, \ 160 .dir = DMA_FROM_DEVICE, \ 161 .ee_mask = BIT(MHI_EE_SBL), \ 162 .pollcfg = 0, \ 163 .doorbell = MHI_DB_BRST_DISABLE, \ 164 .lpm_notify = false, \ 165 .offload_channel = false, \ 166 .doorbell_mode_switch = false, \ 167 } 168 169 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 170 { \ 171 .num = ch_num, \ 172 .name = ch_name, \ 173 .num_elements = el_count, \ 174 .event_ring = ev_ring, \ 175 .dir = DMA_TO_DEVICE, \ 176 .ee_mask = BIT(MHI_EE_FP), \ 177 .pollcfg = 0, \ 178 .doorbell = MHI_DB_BRST_DISABLE, \ 179 .lpm_notify = false, \ 180 .offload_channel = false, \ 181 .doorbell_mode_switch = false, \ 182 } \ 183 184 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 185 { \ 186 .num = ch_num, \ 187 .name = ch_name, \ 188 .num_elements = el_count, \ 189 .event_ring = ev_ring, \ 190 .dir = DMA_FROM_DEVICE, \ 191 .ee_mask = BIT(MHI_EE_FP), \ 192 .pollcfg = 0, \ 193 .doorbell = MHI_DB_BRST_DISABLE, \ 194 .lpm_notify = false, \ 195 .offload_channel = false, \ 196 .doorbell_mode_switch = false, \ 197 } 198 199 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 200 { \ 201 .num_elements = el_count, \ 202 .irq_moderation_ms = 5, \ 203 .irq = (ev_ring) + 1, \ 204 .priority = 1, \ 205 .mode = MHI_DB_BRST_DISABLE, \ 206 .data_type = MHI_ER_DATA, \ 207 .hardware_event = false, \ 208 .client_managed = false, \ 209 .offload_channel = false, \ 210 } 211 212 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 213 { \ 214 .num_elements = el_count, \ 215 .irq_moderation_ms = 1, \ 216 .irq = (ev_ring) + 1, \ 217 .priority = 1, \ 218 .mode = MHI_DB_BRST_DISABLE, \ 219 .data_type = MHI_ER_DATA, \ 220 .hardware_event = true, \ 221 .client_managed = false, \ 222 .offload_channel = false, \ 223 .channel = ch_num, \ 224 } 225 226 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 227 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 228 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 229 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 230 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 231 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 232 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 233 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 234 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 235 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 236 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 237 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 238 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 239 }; 240 241 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 242 /* first ring is control+data ring */ 243 MHI_EVENT_CONFIG_CTRL(0, 64), 244 /* DIAG dedicated event ring */ 245 MHI_EVENT_CONFIG_DATA(1, 128), 246 /* Hardware channels request dedicated hardware event rings */ 247 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 248 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 249 }; 250 251 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 252 .max_channels = 128, 253 .timeout_ms = 8000, 254 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 255 .ch_cfg = modem_qcom_v1_mhi_channels, 256 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 257 .event_cfg = modem_qcom_v1_mhi_events, 258 }; 259 260 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 261 .name = "qcom-sdx65m", 262 .fw = "qcom/sdx65m/xbl.elf", 263 .edl = "qcom/sdx65m/edl.mbn", 264 .config = &modem_qcom_v1_mhiv_config, 265 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 266 .dma_data_width = 32, 267 .sideband_wake = false, 268 }; 269 270 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 271 .name = "qcom-sdx55m", 272 .fw = "qcom/sdx55m/sbl1.mbn", 273 .edl = "qcom/sdx55m/edl.mbn", 274 .config = &modem_qcom_v1_mhiv_config, 275 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 276 .dma_data_width = 32, 277 .mru_default = 32768, 278 .sideband_wake = false, 279 }; 280 281 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 282 .name = "qcom-sdx24", 283 .edl = "qcom/prog_firehose_sdx24.mbn", 284 .config = &modem_qcom_v1_mhiv_config, 285 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 286 .dma_data_width = 32, 287 .sideband_wake = true, 288 }; 289 290 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 291 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 292 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 293 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 294 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 295 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 296 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 297 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 298 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 299 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 300 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 301 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 302 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 303 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 304 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 305 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 306 }; 307 308 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 309 MHI_EVENT_CONFIG_CTRL(0, 128), 310 MHI_EVENT_CONFIG_DATA(1, 128), 311 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 312 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 313 }; 314 315 static const struct mhi_controller_config modem_quectel_em1xx_config = { 316 .max_channels = 128, 317 .timeout_ms = 20000, 318 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 319 .ch_cfg = mhi_quectel_em1xx_channels, 320 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 321 .event_cfg = mhi_quectel_em1xx_events, 322 }; 323 324 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 325 .name = "quectel-em1xx", 326 .edl = "qcom/prog_firehose_sdx24.mbn", 327 .config = &modem_quectel_em1xx_config, 328 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 329 .dma_data_width = 32, 330 .mru_default = 32768, 331 .sideband_wake = true, 332 }; 333 334 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 335 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 336 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 337 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 338 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 339 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 340 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 341 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 342 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 343 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 344 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 345 }; 346 347 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 348 MHI_EVENT_CONFIG_CTRL(0, 128), 349 MHI_EVENT_CONFIG_DATA(1, 128), 350 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 351 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 352 }; 353 354 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 355 .max_channels = 128, 356 .timeout_ms = 20000, 357 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 358 .ch_cfg = mhi_foxconn_sdx55_channels, 359 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 360 .event_cfg = mhi_foxconn_sdx55_events, 361 }; 362 363 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 364 .name = "foxconn-sdx55", 365 .fw = "qcom/sdx55m/sbl1.mbn", 366 .edl = "qcom/sdx55m/edl.mbn", 367 .config = &modem_foxconn_sdx55_config, 368 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 369 .dma_data_width = 32, 370 .mru_default = 32768, 371 .sideband_wake = false, 372 }; 373 374 static const struct mhi_pci_dev_info mhi_foxconn_sdx65_info = { 375 .name = "foxconn-sdx65", 376 .config = &modem_foxconn_sdx55_config, 377 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 378 .dma_data_width = 32, 379 .mru_default = 32768, 380 .sideband_wake = false, 381 }; 382 383 static const struct mhi_channel_config mhi_mv3x_channels[] = { 384 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 385 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 386 /* MBIM Control Channel */ 387 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 388 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 389 /* MBIM Data Channel */ 390 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 391 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 392 }; 393 394 static struct mhi_event_config mhi_mv3x_events[] = { 395 MHI_EVENT_CONFIG_CTRL(0, 256), 396 MHI_EVENT_CONFIG_DATA(1, 256), 397 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 398 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 399 }; 400 401 static const struct mhi_controller_config modem_mv3x_config = { 402 .max_channels = 128, 403 .timeout_ms = 20000, 404 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 405 .ch_cfg = mhi_mv3x_channels, 406 .num_events = ARRAY_SIZE(mhi_mv3x_events), 407 .event_cfg = mhi_mv3x_events, 408 }; 409 410 static const struct mhi_pci_dev_info mhi_mv31_info = { 411 .name = "cinterion-mv31", 412 .config = &modem_mv3x_config, 413 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 414 .dma_data_width = 32, 415 .mru_default = 32768, 416 }; 417 418 static const struct mhi_pci_dev_info mhi_mv32_info = { 419 .name = "cinterion-mv32", 420 .config = &modem_mv3x_config, 421 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 422 .dma_data_width = 32, 423 .mru_default = 32768, 424 }; 425 426 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 427 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 428 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 429 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 430 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 431 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 432 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 433 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 434 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 435 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 436 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 437 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 438 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 439 }; 440 441 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 442 /* first ring is control+data and DIAG ring */ 443 MHI_EVENT_CONFIG_CTRL(0, 2048), 444 /* Hardware channels request dedicated hardware event rings */ 445 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 446 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 447 }; 448 449 static const struct mhi_controller_config modem_sierra_em919x_config = { 450 .max_channels = 128, 451 .timeout_ms = 24000, 452 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 453 .ch_cfg = mhi_sierra_em919x_channels, 454 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 455 .event_cfg = modem_sierra_em919x_mhi_events, 456 }; 457 458 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 459 .name = "sierra-em919x", 460 .config = &modem_sierra_em919x_config, 461 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 462 .dma_data_width = 32, 463 .sideband_wake = false, 464 }; 465 466 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 467 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 468 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 469 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 470 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), 471 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 472 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 473 }; 474 475 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 476 MHI_EVENT_CONFIG_CTRL(0, 128), 477 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 478 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 479 }; 480 481 static struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 482 .max_channels = 128, 483 .timeout_ms = 20000, 484 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 485 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 486 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 487 .event_cfg = mhi_telit_fn980_hw_v1_events, 488 }; 489 490 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 491 .name = "telit-fn980-hwv1", 492 .fw = "qcom/sdx55m/sbl1.mbn", 493 .edl = "qcom/sdx55m/edl.mbn", 494 .config = &modem_telit_fn980_hw_v1_config, 495 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 496 .dma_data_width = 32, 497 .mru_default = 32768, 498 .sideband_wake = false, 499 }; 500 501 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 502 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 503 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 504 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 505 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 506 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 507 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 508 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 509 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 510 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 511 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 512 }; 513 514 static struct mhi_event_config mhi_telit_fn990_events[] = { 515 MHI_EVENT_CONFIG_CTRL(0, 128), 516 MHI_EVENT_CONFIG_DATA(1, 128), 517 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 518 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 519 }; 520 521 static const struct mhi_controller_config modem_telit_fn990_config = { 522 .max_channels = 128, 523 .timeout_ms = 20000, 524 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 525 .ch_cfg = mhi_telit_fn990_channels, 526 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 527 .event_cfg = mhi_telit_fn990_events, 528 }; 529 530 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 531 .name = "telit-fn990", 532 .config = &modem_telit_fn990_config, 533 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 534 .dma_data_width = 32, 535 .sideband_wake = false, 536 .mru_default = 32768, 537 }; 538 539 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 540 static const struct pci_device_id mhi_pci_id_table[] = { 541 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 542 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 543 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 544 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 545 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 546 /* Telit FN980 hardware revision v1 */ 547 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 548 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 549 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 550 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 551 /* Telit FN990 */ 552 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 553 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 554 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 555 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 556 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ 557 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 558 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ 559 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 560 { PCI_DEVICE(0x1eac, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 561 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 562 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 563 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 564 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 565 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 566 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 567 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 568 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 569 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 570 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 571 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 572 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 573 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 574 /* T99W175 (sdx55) */ 575 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 576 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 577 /* T99W368 (sdx65) */ 578 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 579 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, 580 /* T99W373 (sdx62) */ 581 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 582 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, 583 /* MV31-W (Cinterion) */ 584 { PCI_DEVICE(0x1269, 0x00b3), 585 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 586 /* MV31-W (Cinterion), based on new baseline */ 587 { PCI_DEVICE(0x1269, 0x00b4), 588 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 589 /* MV32-WA (Cinterion) */ 590 { PCI_DEVICE(0x1269, 0x00ba), 591 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 592 /* MV32-WB (Cinterion) */ 593 { PCI_DEVICE(0x1269, 0x00bb), 594 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 595 { } 596 }; 597 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 598 599 enum mhi_pci_device_status { 600 MHI_PCI_DEV_STARTED, 601 MHI_PCI_DEV_SUSPENDED, 602 }; 603 604 struct mhi_pci_device { 605 struct mhi_controller mhi_cntrl; 606 struct pci_saved_state *pci_state; 607 struct work_struct recovery_work; 608 struct timer_list health_check_timer; 609 unsigned long status; 610 }; 611 612 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 613 void __iomem *addr, u32 *out) 614 { 615 *out = readl(addr); 616 return 0; 617 } 618 619 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 620 void __iomem *addr, u32 val) 621 { 622 writel(val, addr); 623 } 624 625 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 626 enum mhi_callback cb) 627 { 628 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 629 630 /* Nothing to do for now */ 631 switch (cb) { 632 case MHI_CB_FATAL_ERROR: 633 case MHI_CB_SYS_ERROR: 634 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 635 pm_runtime_forbid(&pdev->dev); 636 break; 637 case MHI_CB_EE_MISSION_MODE: 638 pm_runtime_allow(&pdev->dev); 639 break; 640 default: 641 break; 642 } 643 } 644 645 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 646 { 647 /* no-op */ 648 } 649 650 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 651 { 652 /* no-op */ 653 } 654 655 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 656 { 657 /* no-op */ 658 } 659 660 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 661 { 662 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 663 u16 vendor = 0; 664 665 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) 666 return false; 667 668 if (vendor == (u16) ~0 || vendor == 0) 669 return false; 670 671 return true; 672 } 673 674 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 675 unsigned int bar_num, u64 dma_mask) 676 { 677 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 678 int err; 679 680 err = pci_assign_resource(pdev, bar_num); 681 if (err) 682 return err; 683 684 err = pcim_enable_device(pdev); 685 if (err) { 686 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 687 return err; 688 } 689 690 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev)); 691 if (err) { 692 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 693 return err; 694 } 695 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num]; 696 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 697 698 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 699 if (err) { 700 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 701 return err; 702 } 703 704 pci_set_master(pdev); 705 706 return 0; 707 } 708 709 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 710 const struct mhi_controller_config *mhi_cntrl_config) 711 { 712 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 713 int nr_vectors, i; 714 int *irq; 715 716 /* 717 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 718 * No explicit pci_free_irq_vectors required, done by pcim_release. 719 */ 720 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 721 722 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI); 723 if (nr_vectors < 0) { 724 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 725 nr_vectors); 726 return nr_vectors; 727 } 728 729 if (nr_vectors < mhi_cntrl->nr_irqs) { 730 dev_warn(&pdev->dev, "using shared MSI\n"); 731 732 /* Patch msi vectors, use only one (shared) */ 733 for (i = 0; i < mhi_cntrl_config->num_events; i++) 734 mhi_cntrl_config->event_cfg[i].irq = 0; 735 mhi_cntrl->nr_irqs = 1; 736 } 737 738 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 739 if (!irq) 740 return -ENOMEM; 741 742 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 743 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 744 745 irq[i] = pci_irq_vector(pdev, vector); 746 } 747 748 mhi_cntrl->irq = irq; 749 750 return 0; 751 } 752 753 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 754 { 755 /* The runtime_get() MHI callback means: 756 * Do whatever is requested to leave M3. 757 */ 758 return pm_runtime_get(mhi_cntrl->cntrl_dev); 759 } 760 761 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 762 { 763 /* The runtime_put() MHI callback means: 764 * Device can be moved in M3 state. 765 */ 766 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 767 pm_runtime_put(mhi_cntrl->cntrl_dev); 768 } 769 770 static void mhi_pci_recovery_work(struct work_struct *work) 771 { 772 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 773 recovery_work); 774 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 775 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 776 int err; 777 778 dev_warn(&pdev->dev, "device recovery started\n"); 779 780 del_timer(&mhi_pdev->health_check_timer); 781 pm_runtime_forbid(&pdev->dev); 782 783 /* Clean up MHI state */ 784 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 785 mhi_power_down(mhi_cntrl, false); 786 mhi_unprepare_after_power_down(mhi_cntrl); 787 } 788 789 pci_set_power_state(pdev, PCI_D0); 790 pci_load_saved_state(pdev, mhi_pdev->pci_state); 791 pci_restore_state(pdev); 792 793 if (!mhi_pci_is_alive(mhi_cntrl)) 794 goto err_try_reset; 795 796 err = mhi_prepare_for_power_up(mhi_cntrl); 797 if (err) 798 goto err_try_reset; 799 800 err = mhi_sync_power_up(mhi_cntrl); 801 if (err) 802 goto err_unprepare; 803 804 dev_dbg(&pdev->dev, "Recovery completed\n"); 805 806 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 807 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 808 return; 809 810 err_unprepare: 811 mhi_unprepare_after_power_down(mhi_cntrl); 812 err_try_reset: 813 if (pci_reset_function(pdev)) 814 dev_err(&pdev->dev, "Recovery failed\n"); 815 } 816 817 static void health_check(struct timer_list *t) 818 { 819 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); 820 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 821 822 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 823 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 824 return; 825 826 if (!mhi_pci_is_alive(mhi_cntrl)) { 827 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 828 queue_work(system_long_wq, &mhi_pdev->recovery_work); 829 return; 830 } 831 832 /* reschedule in two seconds */ 833 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 834 } 835 836 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 837 { 838 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 839 const struct mhi_controller_config *mhi_cntrl_config; 840 struct mhi_pci_device *mhi_pdev; 841 struct mhi_controller *mhi_cntrl; 842 int err; 843 844 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); 845 846 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 847 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 848 if (!mhi_pdev) 849 return -ENOMEM; 850 851 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 852 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 853 854 mhi_cntrl_config = info->config; 855 mhi_cntrl = &mhi_pdev->mhi_cntrl; 856 857 mhi_cntrl->cntrl_dev = &pdev->dev; 858 mhi_cntrl->iova_start = 0; 859 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); 860 mhi_cntrl->fw_image = info->fw; 861 mhi_cntrl->edl_image = info->edl; 862 863 mhi_cntrl->read_reg = mhi_pci_read_reg; 864 mhi_cntrl->write_reg = mhi_pci_write_reg; 865 mhi_cntrl->status_cb = mhi_pci_status_cb; 866 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 867 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 868 mhi_cntrl->mru = info->mru_default; 869 870 if (info->sideband_wake) { 871 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 872 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 873 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 874 } 875 876 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); 877 if (err) 878 return err; 879 880 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 881 if (err) 882 return err; 883 884 pci_set_drvdata(pdev, mhi_pdev); 885 886 /* Have stored pci confspace at hand for restore in sudden PCI error. 887 * cache the state locally and discard the PCI core one. 888 */ 889 pci_save_state(pdev); 890 mhi_pdev->pci_state = pci_store_saved_state(pdev); 891 pci_load_saved_state(pdev, NULL); 892 893 pci_enable_pcie_error_reporting(pdev); 894 895 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 896 if (err) 897 goto err_disable_reporting; 898 899 /* MHI bus does not power up the controller by default */ 900 err = mhi_prepare_for_power_up(mhi_cntrl); 901 if (err) { 902 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 903 goto err_unregister; 904 } 905 906 err = mhi_sync_power_up(mhi_cntrl); 907 if (err) { 908 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 909 goto err_unprepare; 910 } 911 912 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 913 914 /* start health check */ 915 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 916 917 /* Only allow runtime-suspend if PME capable (for wakeup) */ 918 if (pci_pme_capable(pdev, PCI_D3hot)) { 919 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 920 pm_runtime_use_autosuspend(&pdev->dev); 921 pm_runtime_mark_last_busy(&pdev->dev); 922 pm_runtime_put_noidle(&pdev->dev); 923 } 924 925 return 0; 926 927 err_unprepare: 928 mhi_unprepare_after_power_down(mhi_cntrl); 929 err_unregister: 930 mhi_unregister_controller(mhi_cntrl); 931 err_disable_reporting: 932 pci_disable_pcie_error_reporting(pdev); 933 934 return err; 935 } 936 937 static void mhi_pci_remove(struct pci_dev *pdev) 938 { 939 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 940 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 941 942 del_timer_sync(&mhi_pdev->health_check_timer); 943 cancel_work_sync(&mhi_pdev->recovery_work); 944 945 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 946 mhi_power_down(mhi_cntrl, true); 947 mhi_unprepare_after_power_down(mhi_cntrl); 948 } 949 950 /* balancing probe put_noidle */ 951 if (pci_pme_capable(pdev, PCI_D3hot)) 952 pm_runtime_get_noresume(&pdev->dev); 953 954 mhi_unregister_controller(mhi_cntrl); 955 pci_disable_pcie_error_reporting(pdev); 956 } 957 958 static void mhi_pci_shutdown(struct pci_dev *pdev) 959 { 960 mhi_pci_remove(pdev); 961 pci_set_power_state(pdev, PCI_D3hot); 962 } 963 964 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 965 { 966 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 967 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 968 969 dev_info(&pdev->dev, "reset\n"); 970 971 del_timer(&mhi_pdev->health_check_timer); 972 973 /* Clean up MHI state */ 974 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 975 mhi_power_down(mhi_cntrl, false); 976 mhi_unprepare_after_power_down(mhi_cntrl); 977 } 978 979 /* cause internal device reset */ 980 mhi_soc_reset(mhi_cntrl); 981 982 /* Be sure device reset has been executed */ 983 msleep(MHI_POST_RESET_DELAY_MS); 984 } 985 986 static void mhi_pci_reset_done(struct pci_dev *pdev) 987 { 988 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 989 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 990 int err; 991 992 /* Restore initial known working PCI state */ 993 pci_load_saved_state(pdev, mhi_pdev->pci_state); 994 pci_restore_state(pdev); 995 996 /* Is device status available ? */ 997 if (!mhi_pci_is_alive(mhi_cntrl)) { 998 dev_err(&pdev->dev, "reset failed\n"); 999 return; 1000 } 1001 1002 err = mhi_prepare_for_power_up(mhi_cntrl); 1003 if (err) { 1004 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1005 return; 1006 } 1007 1008 err = mhi_sync_power_up(mhi_cntrl); 1009 if (err) { 1010 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1011 mhi_unprepare_after_power_down(mhi_cntrl); 1012 return; 1013 } 1014 1015 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1016 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1017 } 1018 1019 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1020 pci_channel_state_t state) 1021 { 1022 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1023 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1024 1025 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1026 1027 if (state == pci_channel_io_perm_failure) 1028 return PCI_ERS_RESULT_DISCONNECT; 1029 1030 /* Clean up MHI state */ 1031 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1032 mhi_power_down(mhi_cntrl, false); 1033 mhi_unprepare_after_power_down(mhi_cntrl); 1034 } else { 1035 /* Nothing to do */ 1036 return PCI_ERS_RESULT_RECOVERED; 1037 } 1038 1039 pci_disable_device(pdev); 1040 1041 return PCI_ERS_RESULT_NEED_RESET; 1042 } 1043 1044 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1045 { 1046 if (pci_enable_device(pdev)) { 1047 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1048 return PCI_ERS_RESULT_DISCONNECT; 1049 } 1050 1051 return PCI_ERS_RESULT_RECOVERED; 1052 } 1053 1054 static void mhi_pci_io_resume(struct pci_dev *pdev) 1055 { 1056 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1057 1058 dev_err(&pdev->dev, "PCI slot reset done\n"); 1059 1060 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1061 } 1062 1063 static const struct pci_error_handlers mhi_pci_err_handler = { 1064 .error_detected = mhi_pci_error_detected, 1065 .slot_reset = mhi_pci_slot_reset, 1066 .resume = mhi_pci_io_resume, 1067 .reset_prepare = mhi_pci_reset_prepare, 1068 .reset_done = mhi_pci_reset_done, 1069 }; 1070 1071 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1072 { 1073 struct pci_dev *pdev = to_pci_dev(dev); 1074 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1075 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1076 int err; 1077 1078 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1079 return 0; 1080 1081 del_timer(&mhi_pdev->health_check_timer); 1082 cancel_work_sync(&mhi_pdev->recovery_work); 1083 1084 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1085 mhi_cntrl->ee != MHI_EE_AMSS) 1086 goto pci_suspend; /* Nothing to do at MHI level */ 1087 1088 /* Transition to M3 state */ 1089 err = mhi_pm_suspend(mhi_cntrl); 1090 if (err) { 1091 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1092 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1093 return -EBUSY; 1094 } 1095 1096 pci_suspend: 1097 pci_disable_device(pdev); 1098 pci_wake_from_d3(pdev, true); 1099 1100 return 0; 1101 } 1102 1103 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1104 { 1105 struct pci_dev *pdev = to_pci_dev(dev); 1106 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1107 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1108 int err; 1109 1110 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1111 return 0; 1112 1113 err = pci_enable_device(pdev); 1114 if (err) 1115 goto err_recovery; 1116 1117 pci_set_master(pdev); 1118 pci_wake_from_d3(pdev, false); 1119 1120 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1121 mhi_cntrl->ee != MHI_EE_AMSS) 1122 return 0; /* Nothing to do at MHI level */ 1123 1124 /* Exit M3, transition to M0 state */ 1125 err = mhi_pm_resume(mhi_cntrl); 1126 if (err) { 1127 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1128 goto err_recovery; 1129 } 1130 1131 /* Resume health check */ 1132 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1133 1134 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1135 pm_runtime_mark_last_busy(dev); 1136 1137 return 0; 1138 1139 err_recovery: 1140 /* Do not fail to not mess up our PCI device state, the device likely 1141 * lost power (d3cold) and we simply need to reset it from the recovery 1142 * procedure, trigger the recovery asynchronously to prevent system 1143 * suspend exit delaying. 1144 */ 1145 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1146 pm_runtime_mark_last_busy(dev); 1147 1148 return 0; 1149 } 1150 1151 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1152 { 1153 pm_runtime_disable(dev); 1154 return mhi_pci_runtime_suspend(dev); 1155 } 1156 1157 static int __maybe_unused mhi_pci_resume(struct device *dev) 1158 { 1159 int ret; 1160 1161 /* Depending the platform, device may have lost power (d3cold), we need 1162 * to resume it now to check its state and recover when necessary. 1163 */ 1164 ret = mhi_pci_runtime_resume(dev); 1165 pm_runtime_enable(dev); 1166 1167 return ret; 1168 } 1169 1170 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1171 { 1172 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1173 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1174 1175 /* We want to stop all operations, hibernation does not guarantee that 1176 * device will be in the same state as before freezing, especially if 1177 * the intermediate restore kernel reinitializes MHI device with new 1178 * context. 1179 */ 1180 flush_work(&mhi_pdev->recovery_work); 1181 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1182 mhi_power_down(mhi_cntrl, true); 1183 mhi_unprepare_after_power_down(mhi_cntrl); 1184 } 1185 1186 return 0; 1187 } 1188 1189 static int __maybe_unused mhi_pci_restore(struct device *dev) 1190 { 1191 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1192 1193 /* Reinitialize the device */ 1194 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1195 1196 return 0; 1197 } 1198 1199 static const struct dev_pm_ops mhi_pci_pm_ops = { 1200 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1201 #ifdef CONFIG_PM_SLEEP 1202 .suspend = mhi_pci_suspend, 1203 .resume = mhi_pci_resume, 1204 .freeze = mhi_pci_freeze, 1205 .thaw = mhi_pci_restore, 1206 .poweroff = mhi_pci_freeze, 1207 .restore = mhi_pci_restore, 1208 #endif 1209 }; 1210 1211 static struct pci_driver mhi_pci_driver = { 1212 .name = "mhi-pci-generic", 1213 .id_table = mhi_pci_id_table, 1214 .probe = mhi_pci_probe, 1215 .remove = mhi_pci_remove, 1216 .shutdown = mhi_pci_shutdown, 1217 .err_handler = &mhi_pci_err_handler, 1218 .driver.pm = &mhi_pci_pm_ops 1219 }; 1220 module_pci_driver(mhi_pci_driver); 1221 1222 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1223 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1224 MODULE_LICENSE("GPL"); 1225