1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/aer.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/mhi.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/timer.h> 19 #include <linux/workqueue.h> 20 21 #define MHI_PCI_DEFAULT_BAR_NUM 0 22 23 #define MHI_POST_RESET_DELAY_MS 2000 24 25 #define HEALTH_CHECK_PERIOD (HZ * 2) 26 27 /** 28 * struct mhi_pci_dev_info - MHI PCI device specific information 29 * @config: MHI controller configuration 30 * @name: name of the PCI module 31 * @fw: firmware path (if any) 32 * @edl: emergency download mode firmware path (if any) 33 * @bar_num: PCI base address register to use for MHI MMIO register space 34 * @dma_data_width: DMA transfer word size (32 or 64 bits) 35 * @mru_default: default MRU size for MBIM network packets 36 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 37 * of inband wake support (such as sdx24) 38 */ 39 struct mhi_pci_dev_info { 40 const struct mhi_controller_config *config; 41 const char *name; 42 const char *fw; 43 const char *edl; 44 unsigned int bar_num; 45 unsigned int dma_data_width; 46 unsigned int mru_default; 47 bool sideband_wake; 48 }; 49 50 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 51 { \ 52 .num = ch_num, \ 53 .name = ch_name, \ 54 .num_elements = el_count, \ 55 .event_ring = ev_ring, \ 56 .dir = DMA_TO_DEVICE, \ 57 .ee_mask = BIT(MHI_EE_AMSS), \ 58 .pollcfg = 0, \ 59 .doorbell = MHI_DB_BRST_DISABLE, \ 60 .lpm_notify = false, \ 61 .offload_channel = false, \ 62 .doorbell_mode_switch = false, \ 63 } \ 64 65 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 66 { \ 67 .num = ch_num, \ 68 .name = ch_name, \ 69 .num_elements = el_count, \ 70 .event_ring = ev_ring, \ 71 .dir = DMA_FROM_DEVICE, \ 72 .ee_mask = BIT(MHI_EE_AMSS), \ 73 .pollcfg = 0, \ 74 .doorbell = MHI_DB_BRST_DISABLE, \ 75 .lpm_notify = false, \ 76 .offload_channel = false, \ 77 .doorbell_mode_switch = false, \ 78 } 79 80 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 81 { \ 82 .num = ch_num, \ 83 .name = ch_name, \ 84 .num_elements = el_count, \ 85 .event_ring = ev_ring, \ 86 .dir = DMA_FROM_DEVICE, \ 87 .ee_mask = BIT(MHI_EE_AMSS), \ 88 .pollcfg = 0, \ 89 .doorbell = MHI_DB_BRST_DISABLE, \ 90 .lpm_notify = false, \ 91 .offload_channel = false, \ 92 .doorbell_mode_switch = false, \ 93 .auto_queue = true, \ 94 } 95 96 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 97 { \ 98 .num_elements = el_count, \ 99 .irq_moderation_ms = 0, \ 100 .irq = (ev_ring) + 1, \ 101 .priority = 1, \ 102 .mode = MHI_DB_BRST_DISABLE, \ 103 .data_type = MHI_ER_CTRL, \ 104 .hardware_event = false, \ 105 .client_managed = false, \ 106 .offload_channel = false, \ 107 } 108 109 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 110 { \ 111 .num = ch_num, \ 112 .name = ch_name, \ 113 .num_elements = el_count, \ 114 .event_ring = ev_ring, \ 115 .dir = DMA_TO_DEVICE, \ 116 .ee_mask = BIT(MHI_EE_AMSS), \ 117 .pollcfg = 0, \ 118 .doorbell = MHI_DB_BRST_ENABLE, \ 119 .lpm_notify = false, \ 120 .offload_channel = false, \ 121 .doorbell_mode_switch = true, \ 122 } \ 123 124 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 125 { \ 126 .num = ch_num, \ 127 .name = ch_name, \ 128 .num_elements = el_count, \ 129 .event_ring = ev_ring, \ 130 .dir = DMA_FROM_DEVICE, \ 131 .ee_mask = BIT(MHI_EE_AMSS), \ 132 .pollcfg = 0, \ 133 .doorbell = MHI_DB_BRST_ENABLE, \ 134 .lpm_notify = false, \ 135 .offload_channel = false, \ 136 .doorbell_mode_switch = true, \ 137 } 138 139 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 140 { \ 141 .num = ch_num, \ 142 .name = ch_name, \ 143 .num_elements = el_count, \ 144 .event_ring = ev_ring, \ 145 .dir = DMA_TO_DEVICE, \ 146 .ee_mask = BIT(MHI_EE_SBL), \ 147 .pollcfg = 0, \ 148 .doorbell = MHI_DB_BRST_DISABLE, \ 149 .lpm_notify = false, \ 150 .offload_channel = false, \ 151 .doorbell_mode_switch = false, \ 152 } \ 153 154 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 155 { \ 156 .num = ch_num, \ 157 .name = ch_name, \ 158 .num_elements = el_count, \ 159 .event_ring = ev_ring, \ 160 .dir = DMA_FROM_DEVICE, \ 161 .ee_mask = BIT(MHI_EE_SBL), \ 162 .pollcfg = 0, \ 163 .doorbell = MHI_DB_BRST_DISABLE, \ 164 .lpm_notify = false, \ 165 .offload_channel = false, \ 166 .doorbell_mode_switch = false, \ 167 } 168 169 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 170 { \ 171 .num = ch_num, \ 172 .name = ch_name, \ 173 .num_elements = el_count, \ 174 .event_ring = ev_ring, \ 175 .dir = DMA_TO_DEVICE, \ 176 .ee_mask = BIT(MHI_EE_FP), \ 177 .pollcfg = 0, \ 178 .doorbell = MHI_DB_BRST_DISABLE, \ 179 .lpm_notify = false, \ 180 .offload_channel = false, \ 181 .doorbell_mode_switch = false, \ 182 } \ 183 184 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 185 { \ 186 .num = ch_num, \ 187 .name = ch_name, \ 188 .num_elements = el_count, \ 189 .event_ring = ev_ring, \ 190 .dir = DMA_FROM_DEVICE, \ 191 .ee_mask = BIT(MHI_EE_FP), \ 192 .pollcfg = 0, \ 193 .doorbell = MHI_DB_BRST_DISABLE, \ 194 .lpm_notify = false, \ 195 .offload_channel = false, \ 196 .doorbell_mode_switch = false, \ 197 } 198 199 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 200 { \ 201 .num_elements = el_count, \ 202 .irq_moderation_ms = 5, \ 203 .irq = (ev_ring) + 1, \ 204 .priority = 1, \ 205 .mode = MHI_DB_BRST_DISABLE, \ 206 .data_type = MHI_ER_DATA, \ 207 .hardware_event = false, \ 208 .client_managed = false, \ 209 .offload_channel = false, \ 210 } 211 212 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 213 { \ 214 .num_elements = el_count, \ 215 .irq_moderation_ms = 1, \ 216 .irq = (ev_ring) + 1, \ 217 .priority = 1, \ 218 .mode = MHI_DB_BRST_DISABLE, \ 219 .data_type = MHI_ER_DATA, \ 220 .hardware_event = true, \ 221 .client_managed = false, \ 222 .offload_channel = false, \ 223 .channel = ch_num, \ 224 } 225 226 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 227 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 228 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 229 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 230 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 231 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 232 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 233 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 234 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 235 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 236 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 237 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 238 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 239 }; 240 241 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 242 /* first ring is control+data ring */ 243 MHI_EVENT_CONFIG_CTRL(0, 64), 244 /* DIAG dedicated event ring */ 245 MHI_EVENT_CONFIG_DATA(1, 128), 246 /* Hardware channels request dedicated hardware event rings */ 247 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 248 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 249 }; 250 251 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 252 .max_channels = 128, 253 .timeout_ms = 8000, 254 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 255 .ch_cfg = modem_qcom_v1_mhi_channels, 256 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 257 .event_cfg = modem_qcom_v1_mhi_events, 258 }; 259 260 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 261 .name = "qcom-sdx65m", 262 .fw = "qcom/sdx65m/xbl.elf", 263 .edl = "qcom/sdx65m/edl.mbn", 264 .config = &modem_qcom_v1_mhiv_config, 265 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 266 .dma_data_width = 32, 267 .sideband_wake = false, 268 }; 269 270 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 271 .name = "qcom-sdx55m", 272 .fw = "qcom/sdx55m/sbl1.mbn", 273 .edl = "qcom/sdx55m/edl.mbn", 274 .config = &modem_qcom_v1_mhiv_config, 275 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 276 .dma_data_width = 32, 277 .mru_default = 32768, 278 .sideband_wake = false, 279 }; 280 281 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 282 .name = "qcom-sdx24", 283 .edl = "qcom/prog_firehose_sdx24.mbn", 284 .config = &modem_qcom_v1_mhiv_config, 285 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 286 .dma_data_width = 32, 287 .sideband_wake = true, 288 }; 289 290 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 291 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 292 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 293 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 294 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 295 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 296 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 297 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 298 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 299 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 300 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 301 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 302 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 303 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 304 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 305 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 306 }; 307 308 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 309 MHI_EVENT_CONFIG_CTRL(0, 128), 310 MHI_EVENT_CONFIG_DATA(1, 128), 311 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 312 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 313 }; 314 315 static const struct mhi_controller_config modem_quectel_em1xx_config = { 316 .max_channels = 128, 317 .timeout_ms = 20000, 318 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 319 .ch_cfg = mhi_quectel_em1xx_channels, 320 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 321 .event_cfg = mhi_quectel_em1xx_events, 322 }; 323 324 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 325 .name = "quectel-em1xx", 326 .edl = "qcom/prog_firehose_sdx24.mbn", 327 .config = &modem_quectel_em1xx_config, 328 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 329 .dma_data_width = 32, 330 .mru_default = 32768, 331 .sideband_wake = true, 332 }; 333 334 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 335 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 336 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 337 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 338 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 339 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 340 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 341 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 342 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 343 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 344 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 345 }; 346 347 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 348 MHI_EVENT_CONFIG_CTRL(0, 128), 349 MHI_EVENT_CONFIG_DATA(1, 128), 350 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 351 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 352 }; 353 354 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 355 .max_channels = 128, 356 .timeout_ms = 20000, 357 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 358 .ch_cfg = mhi_foxconn_sdx55_channels, 359 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 360 .event_cfg = mhi_foxconn_sdx55_events, 361 }; 362 363 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 364 .name = "foxconn-sdx55", 365 .fw = "qcom/sdx55m/sbl1.mbn", 366 .edl = "qcom/sdx55m/edl.mbn", 367 .config = &modem_foxconn_sdx55_config, 368 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 369 .dma_data_width = 32, 370 .mru_default = 32768, 371 .sideband_wake = false, 372 }; 373 374 static const struct mhi_channel_config mhi_mv31_channels[] = { 375 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 376 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 377 /* MBIM Control Channel */ 378 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 379 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 380 /* MBIM Data Channel */ 381 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 382 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 383 }; 384 385 static struct mhi_event_config mhi_mv31_events[] = { 386 MHI_EVENT_CONFIG_CTRL(0, 256), 387 MHI_EVENT_CONFIG_DATA(1, 256), 388 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 389 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 390 }; 391 392 static const struct mhi_controller_config modem_mv31_config = { 393 .max_channels = 128, 394 .timeout_ms = 20000, 395 .num_channels = ARRAY_SIZE(mhi_mv31_channels), 396 .ch_cfg = mhi_mv31_channels, 397 .num_events = ARRAY_SIZE(mhi_mv31_events), 398 .event_cfg = mhi_mv31_events, 399 }; 400 401 static const struct mhi_pci_dev_info mhi_mv31_info = { 402 .name = "cinterion-mv31", 403 .config = &modem_mv31_config, 404 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 405 .dma_data_width = 32, 406 .mru_default = 32768, 407 }; 408 409 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 410 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 411 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 412 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 413 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 414 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 415 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 416 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 417 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 418 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 419 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 420 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 421 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 422 }; 423 424 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 425 /* first ring is control+data and DIAG ring */ 426 MHI_EVENT_CONFIG_CTRL(0, 2048), 427 /* Hardware channels request dedicated hardware event rings */ 428 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 429 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 430 }; 431 432 static const struct mhi_controller_config modem_sierra_em919x_config = { 433 .max_channels = 128, 434 .timeout_ms = 24000, 435 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 436 .ch_cfg = mhi_sierra_em919x_channels, 437 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 438 .event_cfg = modem_sierra_em919x_mhi_events, 439 }; 440 441 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 442 .name = "sierra-em919x", 443 .config = &modem_sierra_em919x_config, 444 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 445 .dma_data_width = 32, 446 .sideband_wake = false, 447 }; 448 449 static const struct pci_device_id mhi_pci_id_table[] = { 450 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 451 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 452 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 453 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 454 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 455 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 456 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 457 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ 458 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 459 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ 460 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 461 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 462 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 463 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 464 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 465 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 466 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 467 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 468 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 469 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 470 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 471 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 472 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 473 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 474 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 475 /* MV31-W (Cinterion) */ 476 { PCI_DEVICE(0x1269, 0x00b3), 477 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 478 { } 479 }; 480 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 481 482 enum mhi_pci_device_status { 483 MHI_PCI_DEV_STARTED, 484 MHI_PCI_DEV_SUSPENDED, 485 }; 486 487 struct mhi_pci_device { 488 struct mhi_controller mhi_cntrl; 489 struct pci_saved_state *pci_state; 490 struct work_struct recovery_work; 491 struct timer_list health_check_timer; 492 unsigned long status; 493 }; 494 495 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 496 void __iomem *addr, u32 *out) 497 { 498 *out = readl(addr); 499 return 0; 500 } 501 502 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 503 void __iomem *addr, u32 val) 504 { 505 writel(val, addr); 506 } 507 508 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 509 enum mhi_callback cb) 510 { 511 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 512 513 /* Nothing to do for now */ 514 switch (cb) { 515 case MHI_CB_FATAL_ERROR: 516 case MHI_CB_SYS_ERROR: 517 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 518 pm_runtime_forbid(&pdev->dev); 519 break; 520 case MHI_CB_EE_MISSION_MODE: 521 pm_runtime_allow(&pdev->dev); 522 break; 523 default: 524 break; 525 } 526 } 527 528 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 529 { 530 /* no-op */ 531 } 532 533 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 534 { 535 /* no-op */ 536 } 537 538 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 539 { 540 /* no-op */ 541 } 542 543 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 544 { 545 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 546 u16 vendor = 0; 547 548 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) 549 return false; 550 551 if (vendor == (u16) ~0 || vendor == 0) 552 return false; 553 554 return true; 555 } 556 557 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 558 unsigned int bar_num, u64 dma_mask) 559 { 560 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 561 int err; 562 563 err = pci_assign_resource(pdev, bar_num); 564 if (err) 565 return err; 566 567 err = pcim_enable_device(pdev); 568 if (err) { 569 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 570 return err; 571 } 572 573 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev)); 574 if (err) { 575 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 576 return err; 577 } 578 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num]; 579 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 580 581 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 582 if (err) { 583 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 584 return err; 585 } 586 587 pci_set_master(pdev); 588 589 return 0; 590 } 591 592 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 593 const struct mhi_controller_config *mhi_cntrl_config) 594 { 595 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 596 int nr_vectors, i; 597 int *irq; 598 599 /* 600 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 601 * No explicit pci_free_irq_vectors required, done by pcim_release. 602 */ 603 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 604 605 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI); 606 if (nr_vectors < 0) { 607 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 608 nr_vectors); 609 return nr_vectors; 610 } 611 612 if (nr_vectors < mhi_cntrl->nr_irqs) { 613 dev_warn(&pdev->dev, "using shared MSI\n"); 614 615 /* Patch msi vectors, use only one (shared) */ 616 for (i = 0; i < mhi_cntrl_config->num_events; i++) 617 mhi_cntrl_config->event_cfg[i].irq = 0; 618 mhi_cntrl->nr_irqs = 1; 619 } 620 621 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 622 if (!irq) 623 return -ENOMEM; 624 625 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 626 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 627 628 irq[i] = pci_irq_vector(pdev, vector); 629 } 630 631 mhi_cntrl->irq = irq; 632 633 return 0; 634 } 635 636 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 637 { 638 /* The runtime_get() MHI callback means: 639 * Do whatever is requested to leave M3. 640 */ 641 return pm_runtime_get(mhi_cntrl->cntrl_dev); 642 } 643 644 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 645 { 646 /* The runtime_put() MHI callback means: 647 * Device can be moved in M3 state. 648 */ 649 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 650 pm_runtime_put(mhi_cntrl->cntrl_dev); 651 } 652 653 static void mhi_pci_recovery_work(struct work_struct *work) 654 { 655 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 656 recovery_work); 657 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 658 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 659 int err; 660 661 dev_warn(&pdev->dev, "device recovery started\n"); 662 663 del_timer(&mhi_pdev->health_check_timer); 664 pm_runtime_forbid(&pdev->dev); 665 666 /* Clean up MHI state */ 667 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 668 mhi_power_down(mhi_cntrl, false); 669 mhi_unprepare_after_power_down(mhi_cntrl); 670 } 671 672 pci_set_power_state(pdev, PCI_D0); 673 pci_load_saved_state(pdev, mhi_pdev->pci_state); 674 pci_restore_state(pdev); 675 676 if (!mhi_pci_is_alive(mhi_cntrl)) 677 goto err_try_reset; 678 679 err = mhi_prepare_for_power_up(mhi_cntrl); 680 if (err) 681 goto err_try_reset; 682 683 err = mhi_sync_power_up(mhi_cntrl); 684 if (err) 685 goto err_unprepare; 686 687 dev_dbg(&pdev->dev, "Recovery completed\n"); 688 689 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 690 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 691 return; 692 693 err_unprepare: 694 mhi_unprepare_after_power_down(mhi_cntrl); 695 err_try_reset: 696 if (pci_reset_function(pdev)) 697 dev_err(&pdev->dev, "Recovery failed\n"); 698 } 699 700 static void health_check(struct timer_list *t) 701 { 702 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); 703 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 704 705 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 706 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 707 return; 708 709 if (!mhi_pci_is_alive(mhi_cntrl)) { 710 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 711 queue_work(system_long_wq, &mhi_pdev->recovery_work); 712 return; 713 } 714 715 /* reschedule in two seconds */ 716 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 717 } 718 719 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 720 { 721 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 722 const struct mhi_controller_config *mhi_cntrl_config; 723 struct mhi_pci_device *mhi_pdev; 724 struct mhi_controller *mhi_cntrl; 725 int err; 726 727 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); 728 729 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 730 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 731 if (!mhi_pdev) 732 return -ENOMEM; 733 734 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 735 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 736 737 mhi_cntrl_config = info->config; 738 mhi_cntrl = &mhi_pdev->mhi_cntrl; 739 740 mhi_cntrl->cntrl_dev = &pdev->dev; 741 mhi_cntrl->iova_start = 0; 742 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); 743 mhi_cntrl->fw_image = info->fw; 744 mhi_cntrl->edl_image = info->edl; 745 746 mhi_cntrl->read_reg = mhi_pci_read_reg; 747 mhi_cntrl->write_reg = mhi_pci_write_reg; 748 mhi_cntrl->status_cb = mhi_pci_status_cb; 749 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 750 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 751 mhi_cntrl->mru = info->mru_default; 752 753 if (info->sideband_wake) { 754 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 755 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 756 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 757 } 758 759 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); 760 if (err) 761 return err; 762 763 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 764 if (err) 765 return err; 766 767 pci_set_drvdata(pdev, mhi_pdev); 768 769 /* Have stored pci confspace at hand for restore in sudden PCI error. 770 * cache the state locally and discard the PCI core one. 771 */ 772 pci_save_state(pdev); 773 mhi_pdev->pci_state = pci_store_saved_state(pdev); 774 pci_load_saved_state(pdev, NULL); 775 776 pci_enable_pcie_error_reporting(pdev); 777 778 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 779 if (err) 780 goto err_disable_reporting; 781 782 /* MHI bus does not power up the controller by default */ 783 err = mhi_prepare_for_power_up(mhi_cntrl); 784 if (err) { 785 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 786 goto err_unregister; 787 } 788 789 err = mhi_sync_power_up(mhi_cntrl); 790 if (err) { 791 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 792 goto err_unprepare; 793 } 794 795 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 796 797 /* start health check */ 798 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 799 800 /* Only allow runtime-suspend if PME capable (for wakeup) */ 801 if (pci_pme_capable(pdev, PCI_D3hot)) { 802 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 803 pm_runtime_use_autosuspend(&pdev->dev); 804 pm_runtime_mark_last_busy(&pdev->dev); 805 pm_runtime_put_noidle(&pdev->dev); 806 } 807 808 return 0; 809 810 err_unprepare: 811 mhi_unprepare_after_power_down(mhi_cntrl); 812 err_unregister: 813 mhi_unregister_controller(mhi_cntrl); 814 err_disable_reporting: 815 pci_disable_pcie_error_reporting(pdev); 816 817 return err; 818 } 819 820 static void mhi_pci_remove(struct pci_dev *pdev) 821 { 822 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 823 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 824 825 del_timer_sync(&mhi_pdev->health_check_timer); 826 cancel_work_sync(&mhi_pdev->recovery_work); 827 828 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 829 mhi_power_down(mhi_cntrl, true); 830 mhi_unprepare_after_power_down(mhi_cntrl); 831 } 832 833 /* balancing probe put_noidle */ 834 if (pci_pme_capable(pdev, PCI_D3hot)) 835 pm_runtime_get_noresume(&pdev->dev); 836 837 mhi_unregister_controller(mhi_cntrl); 838 pci_disable_pcie_error_reporting(pdev); 839 } 840 841 static void mhi_pci_shutdown(struct pci_dev *pdev) 842 { 843 mhi_pci_remove(pdev); 844 pci_set_power_state(pdev, PCI_D3hot); 845 } 846 847 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 848 { 849 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 850 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 851 852 dev_info(&pdev->dev, "reset\n"); 853 854 del_timer(&mhi_pdev->health_check_timer); 855 856 /* Clean up MHI state */ 857 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 858 mhi_power_down(mhi_cntrl, false); 859 mhi_unprepare_after_power_down(mhi_cntrl); 860 } 861 862 /* cause internal device reset */ 863 mhi_soc_reset(mhi_cntrl); 864 865 /* Be sure device reset has been executed */ 866 msleep(MHI_POST_RESET_DELAY_MS); 867 } 868 869 static void mhi_pci_reset_done(struct pci_dev *pdev) 870 { 871 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 872 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 873 int err; 874 875 /* Restore initial known working PCI state */ 876 pci_load_saved_state(pdev, mhi_pdev->pci_state); 877 pci_restore_state(pdev); 878 879 /* Is device status available ? */ 880 if (!mhi_pci_is_alive(mhi_cntrl)) { 881 dev_err(&pdev->dev, "reset failed\n"); 882 return; 883 } 884 885 err = mhi_prepare_for_power_up(mhi_cntrl); 886 if (err) { 887 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 888 return; 889 } 890 891 err = mhi_sync_power_up(mhi_cntrl); 892 if (err) { 893 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 894 mhi_unprepare_after_power_down(mhi_cntrl); 895 return; 896 } 897 898 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 899 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 900 } 901 902 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 903 pci_channel_state_t state) 904 { 905 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 906 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 907 908 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 909 910 if (state == pci_channel_io_perm_failure) 911 return PCI_ERS_RESULT_DISCONNECT; 912 913 /* Clean up MHI state */ 914 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 915 mhi_power_down(mhi_cntrl, false); 916 mhi_unprepare_after_power_down(mhi_cntrl); 917 } else { 918 /* Nothing to do */ 919 return PCI_ERS_RESULT_RECOVERED; 920 } 921 922 pci_disable_device(pdev); 923 924 return PCI_ERS_RESULT_NEED_RESET; 925 } 926 927 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 928 { 929 if (pci_enable_device(pdev)) { 930 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 931 return PCI_ERS_RESULT_DISCONNECT; 932 } 933 934 return PCI_ERS_RESULT_RECOVERED; 935 } 936 937 static void mhi_pci_io_resume(struct pci_dev *pdev) 938 { 939 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 940 941 dev_err(&pdev->dev, "PCI slot reset done\n"); 942 943 queue_work(system_long_wq, &mhi_pdev->recovery_work); 944 } 945 946 static const struct pci_error_handlers mhi_pci_err_handler = { 947 .error_detected = mhi_pci_error_detected, 948 .slot_reset = mhi_pci_slot_reset, 949 .resume = mhi_pci_io_resume, 950 .reset_prepare = mhi_pci_reset_prepare, 951 .reset_done = mhi_pci_reset_done, 952 }; 953 954 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 955 { 956 struct pci_dev *pdev = to_pci_dev(dev); 957 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 958 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 959 int err; 960 961 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 962 return 0; 963 964 del_timer(&mhi_pdev->health_check_timer); 965 cancel_work_sync(&mhi_pdev->recovery_work); 966 967 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 968 mhi_cntrl->ee != MHI_EE_AMSS) 969 goto pci_suspend; /* Nothing to do at MHI level */ 970 971 /* Transition to M3 state */ 972 err = mhi_pm_suspend(mhi_cntrl); 973 if (err) { 974 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 975 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 976 return -EBUSY; 977 } 978 979 pci_suspend: 980 pci_disable_device(pdev); 981 pci_wake_from_d3(pdev, true); 982 983 return 0; 984 } 985 986 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 987 { 988 struct pci_dev *pdev = to_pci_dev(dev); 989 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 990 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 991 int err; 992 993 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 994 return 0; 995 996 err = pci_enable_device(pdev); 997 if (err) 998 goto err_recovery; 999 1000 pci_set_master(pdev); 1001 pci_wake_from_d3(pdev, false); 1002 1003 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1004 mhi_cntrl->ee != MHI_EE_AMSS) 1005 return 0; /* Nothing to do at MHI level */ 1006 1007 /* Exit M3, transition to M0 state */ 1008 err = mhi_pm_resume(mhi_cntrl); 1009 if (err) { 1010 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1011 goto err_recovery; 1012 } 1013 1014 /* Resume health check */ 1015 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1016 1017 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1018 pm_runtime_mark_last_busy(dev); 1019 1020 return 0; 1021 1022 err_recovery: 1023 /* Do not fail to not mess up our PCI device state, the device likely 1024 * lost power (d3cold) and we simply need to reset it from the recovery 1025 * procedure, trigger the recovery asynchronously to prevent system 1026 * suspend exit delaying. 1027 */ 1028 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1029 pm_runtime_mark_last_busy(dev); 1030 1031 return 0; 1032 } 1033 1034 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1035 { 1036 pm_runtime_disable(dev); 1037 return mhi_pci_runtime_suspend(dev); 1038 } 1039 1040 static int __maybe_unused mhi_pci_resume(struct device *dev) 1041 { 1042 int ret; 1043 1044 /* Depending the platform, device may have lost power (d3cold), we need 1045 * to resume it now to check its state and recover when necessary. 1046 */ 1047 ret = mhi_pci_runtime_resume(dev); 1048 pm_runtime_enable(dev); 1049 1050 return ret; 1051 } 1052 1053 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1054 { 1055 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1056 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1057 1058 /* We want to stop all operations, hibernation does not guarantee that 1059 * device will be in the same state as before freezing, especially if 1060 * the intermediate restore kernel reinitializes MHI device with new 1061 * context. 1062 */ 1063 flush_work(&mhi_pdev->recovery_work); 1064 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1065 mhi_power_down(mhi_cntrl, true); 1066 mhi_unprepare_after_power_down(mhi_cntrl); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int __maybe_unused mhi_pci_restore(struct device *dev) 1073 { 1074 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1075 1076 /* Reinitialize the device */ 1077 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1078 1079 return 0; 1080 } 1081 1082 static const struct dev_pm_ops mhi_pci_pm_ops = { 1083 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1084 #ifdef CONFIG_PM_SLEEP 1085 .suspend = mhi_pci_suspend, 1086 .resume = mhi_pci_resume, 1087 .freeze = mhi_pci_freeze, 1088 .thaw = mhi_pci_restore, 1089 .poweroff = mhi_pci_freeze, 1090 .restore = mhi_pci_restore, 1091 #endif 1092 }; 1093 1094 static struct pci_driver mhi_pci_driver = { 1095 .name = "mhi-pci-generic", 1096 .id_table = mhi_pci_id_table, 1097 .probe = mhi_pci_probe, 1098 .remove = mhi_pci_remove, 1099 .shutdown = mhi_pci_shutdown, 1100 .err_handler = &mhi_pci_err_handler, 1101 .driver.pm = &mhi_pci_pm_ops 1102 }; 1103 module_pci_driver(mhi_pci_driver); 1104 1105 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1106 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1107 MODULE_LICENSE("GPL"); 1108