1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2021 MediaTek Inc. */ 3 4 #define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin" 5 #define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin" 6 #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin" 7 8 #define HCI_WMT_MAX_EVENT_SIZE 64 9 10 #define BTMTK_WMT_REG_WRITE 0x1 11 #define BTMTK_WMT_REG_READ 0x2 12 13 #define MT7921_BTSYS_RST 0x70002610 14 #define MT7921_BTSYS_RST_WITH_GPIO BIT(7) 15 16 #define MT7921_PINMUX_0 0x70005050 17 #define MT7921_PINMUX_1 0x70005054 18 19 #define MT7921_DLSTATUS 0x7c053c10 20 #define BT_DL_STATE BIT(1) 21 22 enum { 23 BTMTK_WMT_PATCH_DWNLD = 0x1, 24 BTMTK_WMT_TEST = 0x2, 25 BTMTK_WMT_WAKEUP = 0x3, 26 BTMTK_WMT_HIF = 0x4, 27 BTMTK_WMT_FUNC_CTRL = 0x6, 28 BTMTK_WMT_RST = 0x7, 29 BTMTK_WMT_REGISTER = 0x8, 30 BTMTK_WMT_SEMAPHORE = 0x17, 31 }; 32 33 enum { 34 BTMTK_WMT_INVALID, 35 BTMTK_WMT_PATCH_UNDONE, 36 BTMTK_WMT_PATCH_PROGRESS, 37 BTMTK_WMT_PATCH_DONE, 38 BTMTK_WMT_ON_UNDONE, 39 BTMTK_WMT_ON_DONE, 40 BTMTK_WMT_ON_PROGRESS, 41 }; 42 43 struct btmtk_wmt_hdr { 44 u8 dir; 45 u8 op; 46 __le16 dlen; 47 u8 flag; 48 } __packed; 49 50 struct btmtk_hci_wmt_cmd { 51 struct btmtk_wmt_hdr hdr; 52 u8 data[]; 53 } __packed; 54 55 struct btmtk_hci_wmt_evt { 56 struct hci_event_hdr hhdr; 57 struct btmtk_wmt_hdr whdr; 58 } __packed; 59 60 struct btmtk_hci_wmt_evt_funcc { 61 struct btmtk_hci_wmt_evt hwhdr; 62 __be16 status; 63 } __packed; 64 65 struct btmtk_hci_wmt_evt_reg { 66 struct btmtk_hci_wmt_evt hwhdr; 67 u8 rsv[2]; 68 u8 num; 69 __le32 addr; 70 __le32 val; 71 } __packed; 72 73 struct btmtk_tci_sleep { 74 u8 mode; 75 __le16 duration; 76 __le16 host_duration; 77 u8 host_wakeup_pin; 78 u8 time_compensation; 79 } __packed; 80 81 struct btmtk_wakeon { 82 u8 mode; 83 u8 gpo; 84 u8 active_high; 85 __le16 enable_delay; 86 __le16 wakeup_delay; 87 } __packed; 88 89 struct btmtk_sco { 90 u8 clock_config; 91 u8 transmit_format_config; 92 u8 channel_format_config; 93 u8 channel_select_config; 94 } __packed; 95 96 struct reg_read_cmd { 97 u8 type; 98 u8 rsv; 99 u8 num; 100 __le32 addr; 101 } __packed; 102 103 struct reg_write_cmd { 104 u8 type; 105 u8 rsv; 106 u8 num; 107 __le32 addr; 108 __le32 data; 109 __le32 mask; 110 } __packed; 111 112 struct btmtk_hci_wmt_params { 113 u8 op; 114 u8 flag; 115 u16 dlen; 116 const void *data; 117 u32 *status; 118 }; 119 120 typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *, 121 struct btmtk_hci_wmt_params *); 122 123 #if IS_ENABLED(CONFIG_BT_MTK) 124 125 int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); 126 127 int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 128 wmt_cmd_sync_func_t wmt_cmd_sync); 129 130 int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 131 wmt_cmd_sync_func_t wmt_cmd_sync); 132 #else 133 134 static inline int btmtk_set_bdaddr(struct hci_dev *hdev, 135 const bdaddr_t *bdaddr) 136 { 137 return -EOPNOTSUPP; 138 } 139 140 static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 141 wmt_cmd_sync_func_t wmt_cmd_sync) 142 { 143 return -EOPNOTSUPP; 144 } 145 146 static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 147 wmt_cmd_sync_func_t wmt_cmd_sync) 148 { 149 return -EOPNOTSUPP; 150 } 151 152 #endif 153