1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2021 MediaTek Inc. */ 3 4 #define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin" 5 #define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin" 6 #define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin" 7 #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin" 8 #define FIRMWARE_MT7925 "mediatek/mt7925/BT_RAM_CODE_MT7925_1_1_hdr.bin" 9 10 #define HCI_EV_WMT 0xe4 11 #define HCI_WMT_MAX_EVENT_SIZE 64 12 13 #define BTMTK_WMT_REG_WRITE 0x1 14 #define BTMTK_WMT_REG_READ 0x2 15 16 #define MT7921_BTSYS_RST 0x70002610 17 #define MT7921_BTSYS_RST_WITH_GPIO BIT(7) 18 19 #define MT7921_PINMUX_0 0x70005050 20 #define MT7921_PINMUX_1 0x70005054 21 22 #define MT7921_DLSTATUS 0x7c053c10 23 #define BT_DL_STATE BIT(1) 24 25 enum { 26 BTMTK_WMT_PATCH_DWNLD = 0x1, 27 BTMTK_WMT_TEST = 0x2, 28 BTMTK_WMT_WAKEUP = 0x3, 29 BTMTK_WMT_HIF = 0x4, 30 BTMTK_WMT_FUNC_CTRL = 0x6, 31 BTMTK_WMT_RST = 0x7, 32 BTMTK_WMT_REGISTER = 0x8, 33 BTMTK_WMT_SEMAPHORE = 0x17, 34 }; 35 36 enum { 37 BTMTK_WMT_INVALID, 38 BTMTK_WMT_PATCH_UNDONE, 39 BTMTK_WMT_PATCH_PROGRESS, 40 BTMTK_WMT_PATCH_DONE, 41 BTMTK_WMT_ON_UNDONE, 42 BTMTK_WMT_ON_DONE, 43 BTMTK_WMT_ON_PROGRESS, 44 }; 45 46 struct btmtk_wmt_hdr { 47 u8 dir; 48 u8 op; 49 __le16 dlen; 50 u8 flag; 51 } __packed; 52 53 struct btmtk_hci_wmt_cmd { 54 struct btmtk_wmt_hdr hdr; 55 u8 data[]; 56 } __packed; 57 58 struct btmtk_hci_wmt_evt { 59 struct hci_event_hdr hhdr; 60 struct btmtk_wmt_hdr whdr; 61 } __packed; 62 63 struct btmtk_hci_wmt_evt_funcc { 64 struct btmtk_hci_wmt_evt hwhdr; 65 __be16 status; 66 } __packed; 67 68 struct btmtk_hci_wmt_evt_reg { 69 struct btmtk_hci_wmt_evt hwhdr; 70 u8 rsv[2]; 71 u8 num; 72 __le32 addr; 73 __le32 val; 74 } __packed; 75 76 struct btmtk_tci_sleep { 77 u8 mode; 78 __le16 duration; 79 __le16 host_duration; 80 u8 host_wakeup_pin; 81 u8 time_compensation; 82 } __packed; 83 84 struct btmtk_wakeon { 85 u8 mode; 86 u8 gpo; 87 u8 active_high; 88 __le16 enable_delay; 89 __le16 wakeup_delay; 90 } __packed; 91 92 struct btmtk_sco { 93 u8 clock_config; 94 u8 transmit_format_config; 95 u8 channel_format_config; 96 u8 channel_select_config; 97 } __packed; 98 99 struct reg_read_cmd { 100 u8 type; 101 u8 rsv; 102 u8 num; 103 __le32 addr; 104 } __packed; 105 106 struct reg_write_cmd { 107 u8 type; 108 u8 rsv; 109 u8 num; 110 __le32 addr; 111 __le32 data; 112 __le32 mask; 113 } __packed; 114 115 struct btmtk_hci_wmt_params { 116 u8 op; 117 u8 flag; 118 u16 dlen; 119 const void *data; 120 u32 *status; 121 }; 122 123 typedef int (*btmtk_reset_sync_func_t)(struct hci_dev *, void *); 124 125 struct btmediatek_data { 126 u32 dev_id; 127 btmtk_reset_sync_func_t reset_sync; 128 }; 129 130 typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *, 131 struct btmtk_hci_wmt_params *); 132 133 #if IS_ENABLED(CONFIG_BT_MTK) 134 135 int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); 136 137 int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 138 wmt_cmd_sync_func_t wmt_cmd_sync); 139 140 int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 141 wmt_cmd_sync_func_t wmt_cmd_sync); 142 143 void btmtk_reset_sync(struct hci_dev *hdev); 144 #else 145 146 static inline int btmtk_set_bdaddr(struct hci_dev *hdev, 147 const bdaddr_t *bdaddr) 148 { 149 return -EOPNOTSUPP; 150 } 151 152 static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 153 wmt_cmd_sync_func_t wmt_cmd_sync) 154 { 155 return -EOPNOTSUPP; 156 } 157 158 static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 159 wmt_cmd_sync_func_t wmt_cmd_sync) 160 { 161 return -EOPNOTSUPP; 162 } 163 164 static void btmtk_reset_sync(struct hci_dev *hdev) 165 { 166 } 167 #endif 168