1 /* 2 * Driver for the SWIM3 (Super Woz Integrated Machine 3) 3 * floppy controller found on Power Macintoshes. 4 * 5 * Copyright (C) 1996 Paul Mackerras. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 /* 14 * TODO: 15 * handle 2 drives 16 * handle GCR disks 17 */ 18 19 #undef DEBUG 20 21 #include <linux/stddef.h> 22 #include <linux/kernel.h> 23 #include <linux/sched/signal.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/fd.h> 27 #include <linux/ioctl.h> 28 #include <linux/blk-mq.h> 29 #include <linux/interrupt.h> 30 #include <linux/mutex.h> 31 #include <linux/module.h> 32 #include <linux/spinlock.h> 33 #include <linux/wait.h> 34 #include <asm/io.h> 35 #include <asm/dbdma.h> 36 #include <asm/prom.h> 37 #include <linux/uaccess.h> 38 #include <asm/mediabay.h> 39 #include <asm/machdep.h> 40 #include <asm/pmac_feature.h> 41 42 #define MAX_FLOPPIES 2 43 44 static DEFINE_MUTEX(swim3_mutex); 45 static struct gendisk *disks[MAX_FLOPPIES]; 46 47 enum swim_state { 48 idle, 49 locating, 50 seeking, 51 settling, 52 do_transfer, 53 jogging, 54 available, 55 revalidating, 56 ejecting 57 }; 58 59 #define REG(x) unsigned char x; char x ## _pad[15]; 60 61 /* 62 * The names for these registers mostly represent speculation on my part. 63 * It will be interesting to see how close they are to the names Apple uses. 64 */ 65 struct swim3 { 66 REG(data); 67 REG(timer); /* counts down at 1MHz */ 68 REG(error); 69 REG(mode); 70 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */ 71 REG(setup); 72 REG(control); /* writing bits clears them */ 73 REG(status); /* writing bits sets them in control */ 74 REG(intr); 75 REG(nseek); /* # tracks to seek */ 76 REG(ctrack); /* current track number */ 77 REG(csect); /* current sector number */ 78 REG(gap3); /* size of gap 3 in track format */ 79 REG(sector); /* sector # to read or write */ 80 REG(nsect); /* # sectors to read or write */ 81 REG(intr_enable); 82 }; 83 84 #define control_bic control 85 #define control_bis status 86 87 /* Bits in select register */ 88 #define CA_MASK 7 89 #define LSTRB 8 90 91 /* Bits in control register */ 92 #define DO_SEEK 0x80 93 #define FORMAT 0x40 94 #define SELECT 0x20 95 #define WRITE_SECTORS 0x10 96 #define DO_ACTION 0x08 97 #define DRIVE2_ENABLE 0x04 98 #define DRIVE_ENABLE 0x02 99 #define INTR_ENABLE 0x01 100 101 /* Bits in status register */ 102 #define FIFO_1BYTE 0x80 103 #define FIFO_2BYTE 0x40 104 #define ERROR 0x20 105 #define DATA 0x08 106 #define RDDATA 0x04 107 #define INTR_PENDING 0x02 108 #define MARK_BYTE 0x01 109 110 /* Bits in intr and intr_enable registers */ 111 #define ERROR_INTR 0x20 112 #define DATA_CHANGED 0x10 113 #define TRANSFER_DONE 0x08 114 #define SEEN_SECTOR 0x04 115 #define SEEK_DONE 0x02 116 #define TIMER_DONE 0x01 117 118 /* Bits in error register */ 119 #define ERR_DATA_CRC 0x80 120 #define ERR_ADDR_CRC 0x40 121 #define ERR_OVERRUN 0x04 122 #define ERR_UNDERRUN 0x01 123 124 /* Bits in setup register */ 125 #define S_SW_RESET 0x80 126 #define S_GCR_WRITE 0x40 127 #define S_IBM_DRIVE 0x20 128 #define S_TEST_MODE 0x10 129 #define S_FCLK_DIV2 0x08 130 #define S_GCR 0x04 131 #define S_COPY_PROT 0x02 132 #define S_INV_WDATA 0x01 133 134 /* Select values for swim3_action */ 135 #define SEEK_POSITIVE 0 136 #define SEEK_NEGATIVE 4 137 #define STEP 1 138 #define MOTOR_ON 2 139 #define MOTOR_OFF 6 140 #define INDEX 3 141 #define EJECT 7 142 #define SETMFM 9 143 #define SETGCR 13 144 145 /* Select values for swim3_select and swim3_readbit */ 146 #define STEP_DIR 0 147 #define STEPPING 1 148 #define MOTOR_ON 2 149 #define RELAX 3 /* also eject in progress */ 150 #define READ_DATA_0 4 151 #define ONEMEG_DRIVE 5 152 #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */ 153 #define DRIVE_PRESENT 7 154 #define DISK_IN 8 155 #define WRITE_PROT 9 156 #define TRACK_ZERO 10 157 #define TACHO 11 158 #define READ_DATA_1 12 159 #define GCR_MODE 13 160 #define SEEK_COMPLETE 14 161 #define TWOMEG_MEDIA 15 162 163 /* Definitions of values used in writing and formatting */ 164 #define DATA_ESCAPE 0x99 165 #define GCR_SYNC_EXC 0x3f 166 #define GCR_SYNC_CONV 0x80 167 #define GCR_FIRST_MARK 0xd5 168 #define GCR_SECOND_MARK 0xaa 169 #define GCR_ADDR_MARK "\xd5\xaa\x00" 170 #define GCR_DATA_MARK "\xd5\xaa\x0b" 171 #define GCR_SLIP_BYTE "\x27\xaa" 172 #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f" 173 174 #define DATA_99 "\x99\x99" 175 #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe" 176 #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc" 177 #define MFM_GAP_LEN 12 178 179 struct floppy_state { 180 enum swim_state state; 181 struct swim3 __iomem *swim3; /* hardware registers */ 182 struct dbdma_regs __iomem *dma; /* DMA controller registers */ 183 int swim3_intr; /* interrupt number for SWIM3 */ 184 int dma_intr; /* interrupt number for DMA channel */ 185 int cur_cyl; /* cylinder head is on, or -1 */ 186 int cur_sector; /* last sector we saw go past */ 187 int req_cyl; /* the cylinder for the current r/w request */ 188 int head; /* head number ditto */ 189 int req_sector; /* sector number ditto */ 190 int scount; /* # sectors we're transferring at present */ 191 int retries; 192 int settle_time; 193 int secpercyl; /* disk geometry information */ 194 int secpertrack; 195 int total_secs; 196 int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */ 197 struct dbdma_cmd *dma_cmd; 198 int ref_count; 199 int expect_cyl; 200 struct timer_list timeout; 201 int timeout_pending; 202 int ejected; 203 wait_queue_head_t wait; 204 int wanted; 205 struct macio_dev *mdev; 206 char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)]; 207 int index; 208 struct request *cur_req; 209 struct blk_mq_tag_set tag_set; 210 }; 211 212 #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) 213 #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) 214 #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) 215 216 #ifdef DEBUG 217 #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) 218 #else 219 #define swim3_dbg(fmt, arg...) do { } while(0) 220 #endif 221 222 static struct floppy_state floppy_states[MAX_FLOPPIES]; 223 static int floppy_count = 0; 224 static DEFINE_SPINLOCK(swim3_lock); 225 226 static unsigned short write_preamble[] = { 227 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */ 228 0, 0, 0, 0, 0, 0, /* sync field */ 229 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */ 230 0x990f /* no escape for 512 bytes */ 231 }; 232 233 static unsigned short write_postamble[] = { 234 0x9904, /* insert CRC */ 235 0x4e4e, 0x4e4e, 236 0x9908, /* stop writing */ 237 0, 0, 0, 0, 0, 0 238 }; 239 240 static void seek_track(struct floppy_state *fs, int n); 241 static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count); 242 static void act(struct floppy_state *fs); 243 static void scan_timeout(struct timer_list *t); 244 static void seek_timeout(struct timer_list *t); 245 static void settle_timeout(struct timer_list *t); 246 static void xfer_timeout(struct timer_list *t); 247 static irqreturn_t swim3_interrupt(int irq, void *dev_id); 248 /*static void fd_dma_interrupt(int irq, void *dev_id);*/ 249 static int grab_drive(struct floppy_state *fs, enum swim_state state, 250 int interruptible); 251 static void release_drive(struct floppy_state *fs); 252 static int fd_eject(struct floppy_state *fs); 253 static int floppy_ioctl(struct block_device *bdev, fmode_t mode, 254 unsigned int cmd, unsigned long param); 255 static int floppy_open(struct block_device *bdev, fmode_t mode); 256 static void floppy_release(struct gendisk *disk, fmode_t mode); 257 static unsigned int floppy_check_events(struct gendisk *disk, 258 unsigned int clearing); 259 static int floppy_revalidate(struct gendisk *disk); 260 261 static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes) 262 { 263 struct request *req = fs->cur_req; 264 265 swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n", 266 err, nr_bytes, req); 267 268 if (err) 269 nr_bytes = blk_rq_cur_bytes(req); 270 if (blk_update_request(req, err, nr_bytes)) 271 return true; 272 __blk_mq_end_request(req, err); 273 fs->cur_req = NULL; 274 return false; 275 } 276 277 static void swim3_select(struct floppy_state *fs, int sel) 278 { 279 struct swim3 __iomem *sw = fs->swim3; 280 281 out_8(&sw->select, RELAX); 282 if (sel & 8) 283 out_8(&sw->control_bis, SELECT); 284 else 285 out_8(&sw->control_bic, SELECT); 286 out_8(&sw->select, sel & CA_MASK); 287 } 288 289 static void swim3_action(struct floppy_state *fs, int action) 290 { 291 struct swim3 __iomem *sw = fs->swim3; 292 293 swim3_select(fs, action); 294 udelay(1); 295 out_8(&sw->select, sw->select | LSTRB); 296 udelay(2); 297 out_8(&sw->select, sw->select & ~LSTRB); 298 udelay(1); 299 } 300 301 static int swim3_readbit(struct floppy_state *fs, int bit) 302 { 303 struct swim3 __iomem *sw = fs->swim3; 304 int stat; 305 306 swim3_select(fs, bit); 307 udelay(1); 308 stat = in_8(&sw->status); 309 return (stat & DATA) == 0; 310 } 311 312 static blk_status_t swim3_queue_rq(struct blk_mq_hw_ctx *hctx, 313 const struct blk_mq_queue_data *bd) 314 { 315 struct floppy_state *fs = hctx->queue->queuedata; 316 struct request *req = bd->rq; 317 unsigned long x; 318 319 spin_lock_irq(&swim3_lock); 320 if (fs->cur_req || fs->state != idle) { 321 spin_unlock_irq(&swim3_lock); 322 return BLK_STS_DEV_RESOURCE; 323 } 324 blk_mq_start_request(req); 325 fs->cur_req = req; 326 if (fs->mdev->media_bay && 327 check_media_bay(fs->mdev->media_bay) != MB_FD) { 328 swim3_dbg("%s", " media bay absent, dropping req\n"); 329 swim3_end_request(fs, BLK_STS_IOERR, 0); 330 goto out; 331 } 332 if (fs->ejected) { 333 swim3_dbg("%s", " disk ejected\n"); 334 swim3_end_request(fs, BLK_STS_IOERR, 0); 335 goto out; 336 } 337 if (rq_data_dir(req) == WRITE) { 338 if (fs->write_prot < 0) 339 fs->write_prot = swim3_readbit(fs, WRITE_PROT); 340 if (fs->write_prot) { 341 swim3_dbg("%s", " try to write, disk write protected\n"); 342 swim3_end_request(fs, BLK_STS_IOERR, 0); 343 goto out; 344 } 345 } 346 347 /* 348 * Do not remove the cast. blk_rq_pos(req) is now a sector_t and can be 349 * 64 bits, but it will never go past 32 bits for this driver anyway, so 350 * we can safely cast it down and not have to do a 64/32 division 351 */ 352 fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl; 353 x = ((long)blk_rq_pos(req)) % fs->secpercyl; 354 fs->head = x / fs->secpertrack; 355 fs->req_sector = x % fs->secpertrack + 1; 356 fs->state = do_transfer; 357 fs->retries = 0; 358 359 act(fs); 360 361 out: 362 spin_unlock_irq(&swim3_lock); 363 return BLK_STS_OK; 364 } 365 366 static void set_timeout(struct floppy_state *fs, int nticks, 367 void (*proc)(struct timer_list *t)) 368 { 369 if (fs->timeout_pending) 370 del_timer(&fs->timeout); 371 fs->timeout.expires = jiffies + nticks; 372 fs->timeout.function = proc; 373 add_timer(&fs->timeout); 374 fs->timeout_pending = 1; 375 } 376 377 static inline void scan_track(struct floppy_state *fs) 378 { 379 struct swim3 __iomem *sw = fs->swim3; 380 381 swim3_select(fs, READ_DATA_0); 382 in_8(&sw->intr); /* clear SEEN_SECTOR bit */ 383 in_8(&sw->error); 384 out_8(&sw->intr_enable, SEEN_SECTOR); 385 out_8(&sw->control_bis, DO_ACTION); 386 /* enable intr when track found */ 387 set_timeout(fs, HZ, scan_timeout); /* enable timeout */ 388 } 389 390 static inline void seek_track(struct floppy_state *fs, int n) 391 { 392 struct swim3 __iomem *sw = fs->swim3; 393 394 if (n >= 0) { 395 swim3_action(fs, SEEK_POSITIVE); 396 sw->nseek = n; 397 } else { 398 swim3_action(fs, SEEK_NEGATIVE); 399 sw->nseek = -n; 400 } 401 fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1; 402 swim3_select(fs, STEP); 403 in_8(&sw->error); 404 /* enable intr when seek finished */ 405 out_8(&sw->intr_enable, SEEK_DONE); 406 out_8(&sw->control_bis, DO_SEEK); 407 set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */ 408 fs->settle_time = 0; 409 } 410 411 static inline void init_dma(struct dbdma_cmd *cp, int cmd, 412 void *buf, int count) 413 { 414 cp->req_count = cpu_to_le16(count); 415 cp->command = cpu_to_le16(cmd); 416 cp->phy_addr = cpu_to_le32(virt_to_bus(buf)); 417 cp->xfer_status = 0; 418 } 419 420 static inline void setup_transfer(struct floppy_state *fs) 421 { 422 int n; 423 struct swim3 __iomem *sw = fs->swim3; 424 struct dbdma_cmd *cp = fs->dma_cmd; 425 struct dbdma_regs __iomem *dr = fs->dma; 426 struct request *req = fs->cur_req; 427 428 if (blk_rq_cur_sectors(req) <= 0) { 429 swim3_warn("%s", "Transfer 0 sectors ?\n"); 430 return; 431 } 432 if (rq_data_dir(req) == WRITE) 433 n = 1; 434 else { 435 n = fs->secpertrack - fs->req_sector + 1; 436 if (n > blk_rq_cur_sectors(req)) 437 n = blk_rq_cur_sectors(req); 438 } 439 440 swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n", 441 fs->req_sector, fs->secpertrack, fs->head, n); 442 443 fs->scount = n; 444 swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0); 445 out_8(&sw->sector, fs->req_sector); 446 out_8(&sw->nsect, n); 447 out_8(&sw->gap3, 0); 448 out_le32(&dr->cmdptr, virt_to_bus(cp)); 449 if (rq_data_dir(req) == WRITE) { 450 /* Set up 3 dma commands: write preamble, data, postamble */ 451 init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble)); 452 ++cp; 453 init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512); 454 ++cp; 455 init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble)); 456 } else { 457 init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512); 458 } 459 ++cp; 460 out_le16(&cp->command, DBDMA_STOP); 461 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 462 in_8(&sw->error); 463 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 464 if (rq_data_dir(req) == WRITE) 465 out_8(&sw->control_bis, WRITE_SECTORS); 466 in_8(&sw->intr); 467 out_le32(&dr->control, (RUN << 16) | RUN); 468 /* enable intr when transfer complete */ 469 out_8(&sw->intr_enable, TRANSFER_DONE); 470 out_8(&sw->control_bis, DO_ACTION); 471 set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */ 472 } 473 474 static void act(struct floppy_state *fs) 475 { 476 for (;;) { 477 swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n", 478 fs->state, fs->req_cyl, fs->cur_cyl); 479 480 switch (fs->state) { 481 case idle: 482 return; /* XXX shouldn't get here */ 483 484 case locating: 485 if (swim3_readbit(fs, TRACK_ZERO)) { 486 swim3_dbg("%s", " locate track 0\n"); 487 fs->cur_cyl = 0; 488 if (fs->req_cyl == 0) 489 fs->state = do_transfer; 490 else 491 fs->state = seeking; 492 break; 493 } 494 scan_track(fs); 495 return; 496 497 case seeking: 498 if (fs->cur_cyl < 0) { 499 fs->expect_cyl = -1; 500 fs->state = locating; 501 break; 502 } 503 if (fs->req_cyl == fs->cur_cyl) { 504 swim3_warn("%s", "Whoops, seeking 0\n"); 505 fs->state = do_transfer; 506 break; 507 } 508 seek_track(fs, fs->req_cyl - fs->cur_cyl); 509 return; 510 511 case settling: 512 /* check for SEEK_COMPLETE after 30ms */ 513 fs->settle_time = (HZ + 32) / 33; 514 set_timeout(fs, fs->settle_time, settle_timeout); 515 return; 516 517 case do_transfer: 518 if (fs->cur_cyl != fs->req_cyl) { 519 if (fs->retries > 5) { 520 swim3_err("Wrong cylinder in transfer, want: %d got %d\n", 521 fs->req_cyl, fs->cur_cyl); 522 swim3_end_request(fs, BLK_STS_IOERR, 0); 523 fs->state = idle; 524 return; 525 } 526 fs->state = seeking; 527 break; 528 } 529 setup_transfer(fs); 530 return; 531 532 case jogging: 533 seek_track(fs, -5); 534 return; 535 536 default: 537 swim3_err("Unknown state %d\n", fs->state); 538 return; 539 } 540 } 541 } 542 543 static void scan_timeout(struct timer_list *t) 544 { 545 struct floppy_state *fs = from_timer(fs, t, timeout); 546 struct swim3 __iomem *sw = fs->swim3; 547 unsigned long flags; 548 549 swim3_dbg("* scan timeout, state=%d\n", fs->state); 550 551 spin_lock_irqsave(&swim3_lock, flags); 552 fs->timeout_pending = 0; 553 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 554 out_8(&sw->select, RELAX); 555 out_8(&sw->intr_enable, 0); 556 fs->cur_cyl = -1; 557 if (fs->retries > 5) { 558 swim3_end_request(fs, BLK_STS_IOERR, 0); 559 fs->state = idle; 560 } else { 561 fs->state = jogging; 562 act(fs); 563 } 564 spin_unlock_irqrestore(&swim3_lock, flags); 565 } 566 567 static void seek_timeout(struct timer_list *t) 568 { 569 struct floppy_state *fs = from_timer(fs, t, timeout); 570 struct swim3 __iomem *sw = fs->swim3; 571 unsigned long flags; 572 573 swim3_dbg("* seek timeout, state=%d\n", fs->state); 574 575 spin_lock_irqsave(&swim3_lock, flags); 576 fs->timeout_pending = 0; 577 out_8(&sw->control_bic, DO_SEEK); 578 out_8(&sw->select, RELAX); 579 out_8(&sw->intr_enable, 0); 580 swim3_err("%s", "Seek timeout\n"); 581 swim3_end_request(fs, BLK_STS_IOERR, 0); 582 fs->state = idle; 583 spin_unlock_irqrestore(&swim3_lock, flags); 584 } 585 586 static void settle_timeout(struct timer_list *t) 587 { 588 struct floppy_state *fs = from_timer(fs, t, timeout); 589 struct swim3 __iomem *sw = fs->swim3; 590 unsigned long flags; 591 592 swim3_dbg("* settle timeout, state=%d\n", fs->state); 593 594 spin_lock_irqsave(&swim3_lock, flags); 595 fs->timeout_pending = 0; 596 if (swim3_readbit(fs, SEEK_COMPLETE)) { 597 out_8(&sw->select, RELAX); 598 fs->state = locating; 599 act(fs); 600 goto unlock; 601 } 602 out_8(&sw->select, RELAX); 603 if (fs->settle_time < 2*HZ) { 604 ++fs->settle_time; 605 set_timeout(fs, 1, settle_timeout); 606 goto unlock; 607 } 608 swim3_err("%s", "Seek settle timeout\n"); 609 swim3_end_request(fs, BLK_STS_IOERR, 0); 610 fs->state = idle; 611 unlock: 612 spin_unlock_irqrestore(&swim3_lock, flags); 613 } 614 615 static void xfer_timeout(struct timer_list *t) 616 { 617 struct floppy_state *fs = from_timer(fs, t, timeout); 618 struct swim3 __iomem *sw = fs->swim3; 619 struct dbdma_regs __iomem *dr = fs->dma; 620 unsigned long flags; 621 int n; 622 623 swim3_dbg("* xfer timeout, state=%d\n", fs->state); 624 625 spin_lock_irqsave(&swim3_lock, flags); 626 fs->timeout_pending = 0; 627 out_le32(&dr->control, RUN << 16); 628 /* We must wait a bit for dbdma to stop */ 629 for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++) 630 udelay(1); 631 out_8(&sw->intr_enable, 0); 632 out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); 633 out_8(&sw->select, RELAX); 634 swim3_err("Timeout %sing sector %ld\n", 635 (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"), 636 (long)blk_rq_pos(fs->cur_req)); 637 swim3_end_request(fs, BLK_STS_IOERR, 0); 638 fs->state = idle; 639 spin_unlock_irqrestore(&swim3_lock, flags); 640 } 641 642 static irqreturn_t swim3_interrupt(int irq, void *dev_id) 643 { 644 struct floppy_state *fs = (struct floppy_state *) dev_id; 645 struct swim3 __iomem *sw = fs->swim3; 646 int intr, err, n; 647 int stat, resid; 648 struct dbdma_regs __iomem *dr; 649 struct dbdma_cmd *cp; 650 unsigned long flags; 651 struct request *req = fs->cur_req; 652 653 swim3_dbg("* interrupt, state=%d\n", fs->state); 654 655 spin_lock_irqsave(&swim3_lock, flags); 656 intr = in_8(&sw->intr); 657 err = (intr & ERROR_INTR)? in_8(&sw->error): 0; 658 if ((intr & ERROR_INTR) && fs->state != do_transfer) 659 swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n", 660 fs->state, rq_data_dir(req), intr, err); 661 switch (fs->state) { 662 case locating: 663 if (intr & SEEN_SECTOR) { 664 out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); 665 out_8(&sw->select, RELAX); 666 out_8(&sw->intr_enable, 0); 667 del_timer(&fs->timeout); 668 fs->timeout_pending = 0; 669 if (sw->ctrack == 0xff) { 670 swim3_err("%s", "Seen sector but cyl=ff?\n"); 671 fs->cur_cyl = -1; 672 if (fs->retries > 5) { 673 swim3_end_request(fs, BLK_STS_IOERR, 0); 674 fs->state = idle; 675 } else { 676 fs->state = jogging; 677 act(fs); 678 } 679 break; 680 } 681 fs->cur_cyl = sw->ctrack; 682 fs->cur_sector = sw->csect; 683 if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl) 684 swim3_err("Expected cyl %d, got %d\n", 685 fs->expect_cyl, fs->cur_cyl); 686 fs->state = do_transfer; 687 act(fs); 688 } 689 break; 690 case seeking: 691 case jogging: 692 if (sw->nseek == 0) { 693 out_8(&sw->control_bic, DO_SEEK); 694 out_8(&sw->select, RELAX); 695 out_8(&sw->intr_enable, 0); 696 del_timer(&fs->timeout); 697 fs->timeout_pending = 0; 698 if (fs->state == seeking) 699 ++fs->retries; 700 fs->state = settling; 701 act(fs); 702 } 703 break; 704 case settling: 705 out_8(&sw->intr_enable, 0); 706 del_timer(&fs->timeout); 707 fs->timeout_pending = 0; 708 act(fs); 709 break; 710 case do_transfer: 711 if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0) 712 break; 713 out_8(&sw->intr_enable, 0); 714 out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); 715 out_8(&sw->select, RELAX); 716 del_timer(&fs->timeout); 717 fs->timeout_pending = 0; 718 dr = fs->dma; 719 cp = fs->dma_cmd; 720 if (rq_data_dir(req) == WRITE) 721 ++cp; 722 /* 723 * Check that the main data transfer has finished. 724 * On writing, the swim3 sometimes doesn't use 725 * up all the bytes of the postamble, so we can still 726 * see DMA active here. That doesn't matter as long 727 * as all the sector data has been transferred. 728 */ 729 if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) { 730 /* wait a little while for DMA to complete */ 731 for (n = 0; n < 100; ++n) { 732 if (cp->xfer_status != 0) 733 break; 734 udelay(1); 735 barrier(); 736 } 737 } 738 /* turn off DMA */ 739 out_le32(&dr->control, (RUN | PAUSE) << 16); 740 stat = le16_to_cpu(cp->xfer_status); 741 resid = le16_to_cpu(cp->res_count); 742 if (intr & ERROR_INTR) { 743 n = fs->scount - 1 - resid / 512; 744 if (n > 0) { 745 blk_update_request(req, 0, n << 9); 746 fs->req_sector += n; 747 } 748 if (fs->retries < 5) { 749 ++fs->retries; 750 act(fs); 751 } else { 752 swim3_err("Error %sing block %ld (err=%x)\n", 753 rq_data_dir(req) == WRITE? "writ": "read", 754 (long)blk_rq_pos(req), err); 755 swim3_end_request(fs, BLK_STS_IOERR, 0); 756 fs->state = idle; 757 } 758 } else { 759 if ((stat & ACTIVE) == 0 || resid != 0) { 760 /* musta been an error */ 761 swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid); 762 swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n", 763 fs->state, rq_data_dir(req), intr, err); 764 swim3_end_request(fs, BLK_STS_IOERR, 0); 765 fs->state = idle; 766 break; 767 } 768 fs->retries = 0; 769 if (swim3_end_request(fs, 0, fs->scount << 9)) { 770 fs->req_sector += fs->scount; 771 if (fs->req_sector > fs->secpertrack) { 772 fs->req_sector -= fs->secpertrack; 773 if (++fs->head > 1) { 774 fs->head = 0; 775 ++fs->req_cyl; 776 } 777 } 778 act(fs); 779 } else 780 fs->state = idle; 781 } 782 break; 783 default: 784 swim3_err("Don't know what to do in state %d\n", fs->state); 785 } 786 spin_unlock_irqrestore(&swim3_lock, flags); 787 return IRQ_HANDLED; 788 } 789 790 /* 791 static void fd_dma_interrupt(int irq, void *dev_id) 792 { 793 } 794 */ 795 796 /* Called under the mutex to grab exclusive access to a drive */ 797 static int grab_drive(struct floppy_state *fs, enum swim_state state, 798 int interruptible) 799 { 800 unsigned long flags; 801 802 swim3_dbg("%s", "-> grab drive\n"); 803 804 spin_lock_irqsave(&swim3_lock, flags); 805 if (fs->state != idle && fs->state != available) { 806 ++fs->wanted; 807 /* this will enable irqs in order to sleep */ 808 if (!interruptible) 809 wait_event_lock_irq(fs->wait, 810 fs->state == available, 811 swim3_lock); 812 else if (wait_event_interruptible_lock_irq(fs->wait, 813 fs->state == available, 814 swim3_lock)) { 815 --fs->wanted; 816 spin_unlock_irqrestore(&swim3_lock, flags); 817 return -EINTR; 818 } 819 --fs->wanted; 820 } 821 fs->state = state; 822 spin_unlock_irqrestore(&swim3_lock, flags); 823 824 return 0; 825 } 826 827 static void release_drive(struct floppy_state *fs) 828 { 829 struct request_queue *q = disks[fs->index]->queue; 830 unsigned long flags; 831 832 swim3_dbg("%s", "-> release drive\n"); 833 834 spin_lock_irqsave(&swim3_lock, flags); 835 fs->state = idle; 836 spin_unlock_irqrestore(&swim3_lock, flags); 837 838 blk_mq_freeze_queue(q); 839 blk_mq_quiesce_queue(q); 840 blk_mq_unquiesce_queue(q); 841 blk_mq_unfreeze_queue(q); 842 } 843 844 static int fd_eject(struct floppy_state *fs) 845 { 846 int err, n; 847 848 err = grab_drive(fs, ejecting, 1); 849 if (err) 850 return err; 851 swim3_action(fs, EJECT); 852 for (n = 20; n > 0; --n) { 853 if (signal_pending(current)) { 854 err = -EINTR; 855 break; 856 } 857 swim3_select(fs, RELAX); 858 schedule_timeout_interruptible(1); 859 if (swim3_readbit(fs, DISK_IN) == 0) 860 break; 861 } 862 swim3_select(fs, RELAX); 863 udelay(150); 864 fs->ejected = 1; 865 release_drive(fs); 866 return err; 867 } 868 869 static struct floppy_struct floppy_type = 870 { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */ 871 872 static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode, 873 unsigned int cmd, unsigned long param) 874 { 875 struct floppy_state *fs = bdev->bd_disk->private_data; 876 int err; 877 878 if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN)) 879 return -EPERM; 880 881 if (fs->mdev->media_bay && 882 check_media_bay(fs->mdev->media_bay) != MB_FD) 883 return -ENXIO; 884 885 switch (cmd) { 886 case FDEJECT: 887 if (fs->ref_count != 1) 888 return -EBUSY; 889 err = fd_eject(fs); 890 return err; 891 case FDGETPRM: 892 if (copy_to_user((void __user *) param, &floppy_type, 893 sizeof(struct floppy_struct))) 894 return -EFAULT; 895 return 0; 896 } 897 return -ENOTTY; 898 } 899 900 static int floppy_ioctl(struct block_device *bdev, fmode_t mode, 901 unsigned int cmd, unsigned long param) 902 { 903 int ret; 904 905 mutex_lock(&swim3_mutex); 906 ret = floppy_locked_ioctl(bdev, mode, cmd, param); 907 mutex_unlock(&swim3_mutex); 908 909 return ret; 910 } 911 912 static int floppy_open(struct block_device *bdev, fmode_t mode) 913 { 914 struct floppy_state *fs = bdev->bd_disk->private_data; 915 struct swim3 __iomem *sw = fs->swim3; 916 int n, err = 0; 917 918 if (fs->ref_count == 0) { 919 if (fs->mdev->media_bay && 920 check_media_bay(fs->mdev->media_bay) != MB_FD) 921 return -ENXIO; 922 out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2); 923 out_8(&sw->control_bic, 0xff); 924 out_8(&sw->mode, 0x95); 925 udelay(10); 926 out_8(&sw->intr_enable, 0); 927 out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE); 928 swim3_action(fs, MOTOR_ON); 929 fs->write_prot = -1; 930 fs->cur_cyl = -1; 931 for (n = 0; n < 2 * HZ; ++n) { 932 if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE)) 933 break; 934 if (signal_pending(current)) { 935 err = -EINTR; 936 break; 937 } 938 swim3_select(fs, RELAX); 939 schedule_timeout_interruptible(1); 940 } 941 if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0 942 || swim3_readbit(fs, DISK_IN) == 0)) 943 err = -ENXIO; 944 swim3_action(fs, SETMFM); 945 swim3_select(fs, RELAX); 946 947 } else if (fs->ref_count == -1 || mode & FMODE_EXCL) 948 return -EBUSY; 949 950 if (err == 0 && (mode & FMODE_NDELAY) == 0 951 && (mode & (FMODE_READ|FMODE_WRITE))) { 952 check_disk_change(bdev); 953 if (fs->ejected) 954 err = -ENXIO; 955 } 956 957 if (err == 0 && (mode & FMODE_WRITE)) { 958 if (fs->write_prot < 0) 959 fs->write_prot = swim3_readbit(fs, WRITE_PROT); 960 if (fs->write_prot) 961 err = -EROFS; 962 } 963 964 if (err) { 965 if (fs->ref_count == 0) { 966 swim3_action(fs, MOTOR_OFF); 967 out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE); 968 swim3_select(fs, RELAX); 969 } 970 return err; 971 } 972 973 if (mode & FMODE_EXCL) 974 fs->ref_count = -1; 975 else 976 ++fs->ref_count; 977 978 return 0; 979 } 980 981 static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode) 982 { 983 int ret; 984 985 mutex_lock(&swim3_mutex); 986 ret = floppy_open(bdev, mode); 987 mutex_unlock(&swim3_mutex); 988 989 return ret; 990 } 991 992 static void floppy_release(struct gendisk *disk, fmode_t mode) 993 { 994 struct floppy_state *fs = disk->private_data; 995 struct swim3 __iomem *sw = fs->swim3; 996 997 mutex_lock(&swim3_mutex); 998 if (fs->ref_count > 0) 999 --fs->ref_count; 1000 else if (fs->ref_count == -1) 1001 fs->ref_count = 0; 1002 if (fs->ref_count == 0) { 1003 swim3_action(fs, MOTOR_OFF); 1004 out_8(&sw->control_bic, 0xff); 1005 swim3_select(fs, RELAX); 1006 } 1007 mutex_unlock(&swim3_mutex); 1008 } 1009 1010 static unsigned int floppy_check_events(struct gendisk *disk, 1011 unsigned int clearing) 1012 { 1013 struct floppy_state *fs = disk->private_data; 1014 return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0; 1015 } 1016 1017 static int floppy_revalidate(struct gendisk *disk) 1018 { 1019 struct floppy_state *fs = disk->private_data; 1020 struct swim3 __iomem *sw; 1021 int ret, n; 1022 1023 if (fs->mdev->media_bay && 1024 check_media_bay(fs->mdev->media_bay) != MB_FD) 1025 return -ENXIO; 1026 1027 sw = fs->swim3; 1028 grab_drive(fs, revalidating, 0); 1029 out_8(&sw->intr_enable, 0); 1030 out_8(&sw->control_bis, DRIVE_ENABLE); 1031 swim3_action(fs, MOTOR_ON); /* necessary? */ 1032 fs->write_prot = -1; 1033 fs->cur_cyl = -1; 1034 mdelay(1); 1035 for (n = HZ; n > 0; --n) { 1036 if (swim3_readbit(fs, SEEK_COMPLETE)) 1037 break; 1038 if (signal_pending(current)) 1039 break; 1040 swim3_select(fs, RELAX); 1041 schedule_timeout_interruptible(1); 1042 } 1043 ret = swim3_readbit(fs, SEEK_COMPLETE) == 0 1044 || swim3_readbit(fs, DISK_IN) == 0; 1045 if (ret) 1046 swim3_action(fs, MOTOR_OFF); 1047 else { 1048 fs->ejected = 0; 1049 swim3_action(fs, SETMFM); 1050 } 1051 swim3_select(fs, RELAX); 1052 1053 release_drive(fs); 1054 return ret; 1055 } 1056 1057 static const struct block_device_operations floppy_fops = { 1058 .open = floppy_unlocked_open, 1059 .release = floppy_release, 1060 .ioctl = floppy_ioctl, 1061 .check_events = floppy_check_events, 1062 .revalidate_disk= floppy_revalidate, 1063 }; 1064 1065 static const struct blk_mq_ops swim3_mq_ops = { 1066 .queue_rq = swim3_queue_rq, 1067 }; 1068 1069 static void swim3_mb_event(struct macio_dev* mdev, int mb_state) 1070 { 1071 struct floppy_state *fs = macio_get_drvdata(mdev); 1072 struct swim3 __iomem *sw; 1073 1074 if (!fs) 1075 return; 1076 1077 sw = fs->swim3; 1078 1079 if (mb_state != MB_FD) 1080 return; 1081 1082 /* Clear state */ 1083 out_8(&sw->intr_enable, 0); 1084 in_8(&sw->intr); 1085 in_8(&sw->error); 1086 } 1087 1088 static int swim3_add_device(struct macio_dev *mdev, int index) 1089 { 1090 struct device_node *swim = mdev->ofdev.dev.of_node; 1091 struct floppy_state *fs = &floppy_states[index]; 1092 int rc = -EBUSY; 1093 1094 fs->mdev = mdev; 1095 fs->index = index; 1096 1097 /* Check & Request resources */ 1098 if (macio_resource_count(mdev) < 2) { 1099 swim3_err("%s", "No address in device-tree\n"); 1100 return -ENXIO; 1101 } 1102 if (macio_irq_count(mdev) < 1) { 1103 swim3_err("%s", "No interrupt in device-tree\n"); 1104 return -ENXIO; 1105 } 1106 if (macio_request_resource(mdev, 0, "swim3 (mmio)")) { 1107 swim3_err("%s", "Can't request mmio resource\n"); 1108 return -EBUSY; 1109 } 1110 if (macio_request_resource(mdev, 1, "swim3 (dma)")) { 1111 swim3_err("%s", "Can't request dma resource\n"); 1112 macio_release_resource(mdev, 0); 1113 return -EBUSY; 1114 } 1115 dev_set_drvdata(&mdev->ofdev.dev, fs); 1116 1117 if (mdev->media_bay == NULL) 1118 pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1); 1119 1120 fs->state = idle; 1121 fs->swim3 = (struct swim3 __iomem *) 1122 ioremap(macio_resource_start(mdev, 0), 0x200); 1123 if (fs->swim3 == NULL) { 1124 swim3_err("%s", "Couldn't map mmio registers\n"); 1125 rc = -ENOMEM; 1126 goto out_release; 1127 } 1128 fs->dma = (struct dbdma_regs __iomem *) 1129 ioremap(macio_resource_start(mdev, 1), 0x200); 1130 if (fs->dma == NULL) { 1131 swim3_err("%s", "Couldn't map dma registers\n"); 1132 iounmap(fs->swim3); 1133 rc = -ENOMEM; 1134 goto out_release; 1135 } 1136 fs->swim3_intr = macio_irq(mdev, 0); 1137 fs->dma_intr = macio_irq(mdev, 1); 1138 fs->cur_cyl = -1; 1139 fs->cur_sector = -1; 1140 fs->secpercyl = 36; 1141 fs->secpertrack = 18; 1142 fs->total_secs = 2880; 1143 init_waitqueue_head(&fs->wait); 1144 1145 fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space); 1146 memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd)); 1147 fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP); 1148 1149 if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD) 1150 swim3_mb_event(mdev, MB_FD); 1151 1152 if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) { 1153 swim3_err("%s", "Couldn't request interrupt\n"); 1154 pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0); 1155 goto out_unmap; 1156 } 1157 1158 timer_setup(&fs->timeout, NULL, 0); 1159 1160 swim3_info("SWIM3 floppy controller %s\n", 1161 mdev->media_bay ? "in media bay" : ""); 1162 1163 return 0; 1164 1165 out_unmap: 1166 iounmap(fs->dma); 1167 iounmap(fs->swim3); 1168 1169 out_release: 1170 macio_release_resource(mdev, 0); 1171 macio_release_resource(mdev, 1); 1172 1173 return rc; 1174 } 1175 1176 static int swim3_attach(struct macio_dev *mdev, 1177 const struct of_device_id *match) 1178 { 1179 struct floppy_state *fs; 1180 struct gendisk *disk; 1181 int rc; 1182 1183 if (floppy_count >= MAX_FLOPPIES) 1184 return -ENXIO; 1185 1186 if (floppy_count == 0) { 1187 rc = register_blkdev(FLOPPY_MAJOR, "fd"); 1188 if (rc) 1189 return rc; 1190 } 1191 1192 disk = alloc_disk(1); 1193 if (disk == NULL) { 1194 rc = -ENOMEM; 1195 goto out_unregister; 1196 } 1197 1198 fs = &floppy_states[floppy_count]; 1199 memset(fs, 0, sizeof(*fs)); 1200 1201 disk->queue = blk_mq_init_sq_queue(&fs->tag_set, &swim3_mq_ops, 2, 1202 BLK_MQ_F_SHOULD_MERGE); 1203 if (IS_ERR(disk->queue)) { 1204 rc = PTR_ERR(disk->queue); 1205 disk->queue = NULL; 1206 goto out_put_disk; 1207 } 1208 blk_queue_bounce_limit(disk->queue, BLK_BOUNCE_HIGH); 1209 disk->queue->queuedata = fs; 1210 1211 rc = swim3_add_device(mdev, floppy_count); 1212 if (rc) 1213 goto out_cleanup_queue; 1214 1215 disk->major = FLOPPY_MAJOR; 1216 disk->first_minor = floppy_count; 1217 disk->fops = &floppy_fops; 1218 disk->private_data = fs; 1219 disk->events = DISK_EVENT_MEDIA_CHANGE; 1220 disk->flags |= GENHD_FL_REMOVABLE; 1221 sprintf(disk->disk_name, "fd%d", floppy_count); 1222 set_capacity(disk, 2880); 1223 add_disk(disk); 1224 1225 disks[floppy_count++] = disk; 1226 return 0; 1227 1228 out_cleanup_queue: 1229 blk_cleanup_queue(disk->queue); 1230 disk->queue = NULL; 1231 blk_mq_free_tag_set(&fs->tag_set); 1232 out_put_disk: 1233 put_disk(disk); 1234 out_unregister: 1235 if (floppy_count == 0) 1236 unregister_blkdev(FLOPPY_MAJOR, "fd"); 1237 return rc; 1238 } 1239 1240 static const struct of_device_id swim3_match[] = 1241 { 1242 { 1243 .name = "swim3", 1244 }, 1245 { 1246 .compatible = "ohare-swim3" 1247 }, 1248 { 1249 .compatible = "swim3" 1250 }, 1251 { /* end of list */ } 1252 }; 1253 1254 static struct macio_driver swim3_driver = 1255 { 1256 .driver = { 1257 .name = "swim3", 1258 .of_match_table = swim3_match, 1259 }, 1260 .probe = swim3_attach, 1261 #ifdef CONFIG_PMAC_MEDIABAY 1262 .mediabay_event = swim3_mb_event, 1263 #endif 1264 #if 0 1265 .suspend = swim3_suspend, 1266 .resume = swim3_resume, 1267 #endif 1268 }; 1269 1270 1271 int swim3_init(void) 1272 { 1273 macio_register_driver(&swim3_driver); 1274 return 0; 1275 } 1276 1277 module_init(swim3_init) 1278 1279 MODULE_LICENSE("GPL"); 1280 MODULE_AUTHOR("Paul Mackerras"); 1281 MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR); 1282