1 /* 2 * Broadcom specific AMBA 3 * PCI Core 4 * 5 * Copyright 2005, 2011, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/export.h> 14 #include <linux/bcma/bcma.h> 15 16 /************************************************** 17 * R/W ops. 18 **************************************************/ 19 20 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) 21 { 22 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); 23 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); 24 return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); 25 } 26 27 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) 28 { 29 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); 30 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); 31 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); 32 } 33 34 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy) 35 { 36 u32 v; 37 int i; 38 39 v = BCMA_CORE_PCI_MDIODATA_START; 40 v |= BCMA_CORE_PCI_MDIODATA_WRITE; 41 v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << 42 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); 43 v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << 44 BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); 45 v |= BCMA_CORE_PCI_MDIODATA_TA; 46 v |= (phy << 4); 47 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); 48 49 udelay(10); 50 for (i = 0; i < 200; i++) { 51 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); 52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) 53 break; 54 usleep_range(1000, 2000); 55 } 56 } 57 58 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address) 59 { 60 int max_retries = 10; 61 u16 ret = 0; 62 u32 v; 63 int i; 64 65 /* enable mdio access to SERDES */ 66 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; 67 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; 68 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); 69 70 if (pc->core->id.rev >= 10) { 71 max_retries = 200; 72 bcma_pcie_mdio_set_phy(pc, device); 73 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << 74 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); 75 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); 76 } else { 77 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); 78 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); 79 } 80 81 v = BCMA_CORE_PCI_MDIODATA_START; 82 v |= BCMA_CORE_PCI_MDIODATA_READ; 83 v |= BCMA_CORE_PCI_MDIODATA_TA; 84 85 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); 86 /* Wait for the device to complete the transaction */ 87 udelay(10); 88 for (i = 0; i < max_retries; i++) { 89 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); 90 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { 91 udelay(10); 92 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); 93 break; 94 } 95 usleep_range(1000, 2000); 96 } 97 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); 98 return ret; 99 } 100 101 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device, 102 u8 address, u16 data) 103 { 104 int max_retries = 10; 105 u32 v; 106 int i; 107 108 /* enable mdio access to SERDES */ 109 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; 110 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; 111 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); 112 113 if (pc->core->id.rev >= 10) { 114 max_retries = 200; 115 bcma_pcie_mdio_set_phy(pc, device); 116 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << 117 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); 118 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); 119 } else { 120 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); 121 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); 122 } 123 124 v = BCMA_CORE_PCI_MDIODATA_START; 125 v |= BCMA_CORE_PCI_MDIODATA_WRITE; 126 v |= BCMA_CORE_PCI_MDIODATA_TA; 127 v |= data; 128 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); 129 /* Wait for the device to complete the transaction */ 130 udelay(10); 131 for (i = 0; i < max_retries; i++) { 132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); 133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) 134 break; 135 usleep_range(1000, 2000); 136 } 137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); 138 } 139 140 static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device, 141 u8 address, u16 data) 142 { 143 bcma_pcie_mdio_write(pc, device, address, data); 144 return bcma_pcie_mdio_read(pc, device, address); 145 } 146 147 /************************************************** 148 * Workarounds. 149 **************************************************/ 150 151 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) 152 { 153 u32 tmp; 154 155 tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); 156 if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) 157 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | 158 BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; 159 else 160 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; 161 } 162 163 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) 164 { 165 u16 tmp; 166 167 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, 168 BCMA_CORE_PCI_SERDES_RX_CTRL, 169 bcma_pcicore_polarity_workaround(pc)); 170 tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, 171 BCMA_CORE_PCI_SERDES_PLL_CTRL); 172 if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) 173 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, 174 BCMA_CORE_PCI_SERDES_PLL_CTRL, 175 tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); 176 } 177 178 static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc) 179 { 180 struct bcma_device *core = pc->core; 181 u16 val16, core_index; 182 uint regoff; 183 184 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET); 185 core_index = (u16)core->core_index; 186 187 val16 = pcicore_read16(pc, regoff); 188 if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT) 189 != core_index) { 190 val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) | 191 (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK); 192 pcicore_write16(pc, regoff, val16); 193 } 194 } 195 196 /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */ 197 /* Needs to happen when coming out of 'standby'/'hibernate' */ 198 static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc) 199 { 200 u16 val16; 201 uint regoff; 202 203 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG); 204 205 val16 = pcicore_read16(pc, regoff); 206 207 if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) { 208 val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST; 209 pcicore_write16(pc, regoff, val16); 210 } 211 } 212 213 static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up) 214 { 215 u16 data; 216 217 if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) { 218 data = up ? 0x74 : 0x7C; 219 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, 220 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64); 221 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, 222 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data); 223 } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) { 224 data = up ? 0x75 : 0x7D; 225 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, 226 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65); 227 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, 228 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data); 229 } 230 } 231 232 /************************************************** 233 * Init. 234 **************************************************/ 235 236 static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) 237 { 238 bcma_core_pci_fixcfg(pc); 239 bcma_pcicore_serdes_workaround(pc); 240 bcma_core_pci_config_fixup(pc); 241 } 242 243 void bcma_core_pci_init(struct bcma_drv_pci *pc) 244 { 245 if (pc->setup_done) 246 return; 247 248 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE 249 pc->hostmode = bcma_core_pci_is_in_hostmode(pc); 250 if (pc->hostmode) 251 bcma_core_pci_hostmode_init(pc); 252 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ 253 254 if (!pc->hostmode) 255 bcma_core_pci_clientmode_init(pc); 256 } 257 258 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, 259 bool enable) 260 { 261 struct pci_dev *pdev; 262 u32 coremask, tmp; 263 int err = 0; 264 265 if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) { 266 /* This bcma device is not on a PCI host-bus. So the IRQs are 267 * not routed through the PCI core. 268 * So we must not enable routing through the PCI core. */ 269 goto out; 270 } 271 272 pdev = pc->core->bus->host_pci; 273 274 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); 275 if (err) 276 goto out; 277 278 coremask = BIT(core->core_index) << 8; 279 if (enable) 280 tmp |= coremask; 281 else 282 tmp &= ~coremask; 283 284 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); 285 286 out: 287 return err; 288 } 289 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); 290 291 static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) 292 { 293 u32 w; 294 295 w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); 296 if (extend) 297 w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND; 298 else 299 w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND; 300 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w); 301 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); 302 } 303 304 void bcma_core_pci_up(struct bcma_bus *bus) 305 { 306 struct bcma_drv_pci *pc; 307 308 if (bus->hosttype != BCMA_HOSTTYPE_PCI) 309 return; 310 311 pc = &bus->drv_pci[0]; 312 313 bcma_core_pci_power_save(pc, true); 314 315 bcma_core_pci_extend_L1timer(pc, true); 316 } 317 EXPORT_SYMBOL_GPL(bcma_core_pci_up); 318 319 void bcma_core_pci_down(struct bcma_bus *bus) 320 { 321 struct bcma_drv_pci *pc; 322 323 if (bus->hosttype != BCMA_HOSTTYPE_PCI) 324 return; 325 326 pc = &bus->drv_pci[0]; 327 328 bcma_core_pci_extend_L1timer(pc, false); 329 330 bcma_core_pci_power_save(pc, false); 331 } 332 EXPORT_SYMBOL_GPL(bcma_core_pci_down); 333