1 /* 2 * Broadcom specific AMBA 3 * Broadcom MIPS32 74K core driver 4 * 5 * Copyright 2009, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com> 8 * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de> 9 * 10 * Licensed under the GNU/GPL. See COPYING for details. 11 */ 12 13 #include "bcma_private.h" 14 15 #include <linux/bcma/bcma.h> 16 17 #include <linux/serial.h> 18 #include <linux/serial_core.h> 19 #include <linux/serial_reg.h> 20 #include <linux/time.h> 21 #ifdef CONFIG_BCM47XX 22 #include <linux/bcm47xx_nvram.h> 23 #endif 24 25 enum bcma_boot_dev { 26 BCMA_BOOT_DEV_UNK = 0, 27 BCMA_BOOT_DEV_ROM, 28 BCMA_BOOT_DEV_PARALLEL, 29 BCMA_BOOT_DEV_SERIAL, 30 BCMA_BOOT_DEV_NAND, 31 }; 32 33 /* The 47162a0 hangs when reading MIPS DMP registers registers */ 34 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) 35 { 36 return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 && 37 dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K; 38 } 39 40 /* The 5357b0 hangs when reading USB20H DMP registers */ 41 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev) 42 { 43 return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 44 dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) && 45 dev->bus->chipinfo.pkg == 11 && 46 dev->id.id == BCMA_CORE_USB20_HOST; 47 } 48 49 static inline u32 mips_read32(struct bcma_drv_mips *mcore, 50 u16 offset) 51 { 52 return bcma_read32(mcore->core, offset); 53 } 54 55 static inline void mips_write32(struct bcma_drv_mips *mcore, 56 u16 offset, 57 u32 value) 58 { 59 bcma_write32(mcore->core, offset, value); 60 } 61 62 static const u32 ipsflag_irq_mask[] = { 63 0, 64 BCMA_MIPS_IPSFLAG_IRQ1, 65 BCMA_MIPS_IPSFLAG_IRQ2, 66 BCMA_MIPS_IPSFLAG_IRQ3, 67 BCMA_MIPS_IPSFLAG_IRQ4, 68 }; 69 70 static const u32 ipsflag_irq_shift[] = { 71 0, 72 BCMA_MIPS_IPSFLAG_IRQ1_SHIFT, 73 BCMA_MIPS_IPSFLAG_IRQ2_SHIFT, 74 BCMA_MIPS_IPSFLAG_IRQ3_SHIFT, 75 BCMA_MIPS_IPSFLAG_IRQ4_SHIFT, 76 }; 77 78 static u32 bcma_core_mips_irqflag(struct bcma_device *dev) 79 { 80 u32 flag; 81 82 if (bcma_core_mips_bcm47162a0_quirk(dev)) 83 return dev->core_index; 84 if (bcma_core_mips_bcm5357b0_quirk(dev)) 85 return dev->core_index; 86 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); 87 88 if (flag) 89 return flag & 0x1F; 90 else 91 return 0x3f; 92 } 93 94 /* Get the MIPS IRQ assignment for a specified device. 95 * If unassigned, 0 is returned. 96 * If disabled, 5 is returned. 97 * If not supported, 6 is returned. 98 */ 99 unsigned int bcma_core_mips_irq(struct bcma_device *dev) 100 { 101 struct bcma_device *mdev = dev->bus->drv_mips.core; 102 u32 irqflag; 103 unsigned int irq; 104 105 irqflag = bcma_core_mips_irqflag(dev); 106 if (irqflag == 0x3f) 107 return 6; 108 109 for (irq = 0; irq <= 4; irq++) 110 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & 111 (1 << irqflag)) 112 return irq; 113 114 return 5; 115 } 116 117 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) 118 { 119 unsigned int oldirq = bcma_core_mips_irq(dev); 120 struct bcma_bus *bus = dev->bus; 121 struct bcma_device *mdev = bus->drv_mips.core; 122 u32 irqflag; 123 124 irqflag = bcma_core_mips_irqflag(dev); 125 BUG_ON(oldirq == 6); 126 127 dev->irq = irq + 2; 128 129 /* clear the old irq */ 130 if (oldirq == 0) 131 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), 132 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & 133 ~(1 << irqflag)); 134 else if (oldirq != 5) 135 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); 136 137 /* assign the new one */ 138 if (irq == 0) { 139 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), 140 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | 141 (1 << irqflag)); 142 } else { 143 u32 irqinitmask = bcma_read32(mdev, 144 BCMA_MIPS_MIPS74K_INTMASK(irq)); 145 if (irqinitmask) { 146 struct bcma_device *core; 147 148 /* backplane irq line is in use, find out who uses 149 * it and set user to irq 0 150 */ 151 list_for_each_entry(core, &bus->cores, list) { 152 if ((1 << bcma_core_mips_irqflag(core)) == 153 irqinitmask) { 154 bcma_core_mips_set_irq(core, 0); 155 break; 156 } 157 } 158 } 159 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 160 1 << irqflag); 161 } 162 163 bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", 164 dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); 165 } 166 167 static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, 168 u16 coreid, u8 unit) 169 { 170 struct bcma_device *core; 171 172 core = bcma_find_core_unit(bus, coreid, unit); 173 if (!core) { 174 bcma_warn(bus, 175 "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", 176 coreid, unit); 177 return; 178 } 179 180 bcma_core_mips_set_irq(core, irq); 181 } 182 183 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) 184 { 185 int i; 186 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; 187 char interrupts[20]; 188 char *ints = interrupts; 189 190 for (i = 0; i < ARRAY_SIZE(irq_name); i++) 191 ints += sprintf(ints, " %s%c", 192 irq_name[i], i == irq ? '*' : ' '); 193 194 bcma_debug(dev->bus, "core 0x%04x, irq:%s\n", dev->id.id, interrupts); 195 } 196 197 static void bcma_core_mips_dump_irq(struct bcma_bus *bus) 198 { 199 struct bcma_device *core; 200 201 list_for_each_entry(core, &bus->cores, list) { 202 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); 203 } 204 } 205 206 u32 bcma_cpu_clock(struct bcma_drv_mips *mcore) 207 { 208 struct bcma_bus *bus = mcore->core->bus; 209 210 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) 211 return bcma_pmu_get_cpu_clock(&bus->drv_cc); 212 213 bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); 214 return 0; 215 } 216 EXPORT_SYMBOL(bcma_cpu_clock); 217 218 static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus) 219 { 220 struct bcma_drv_cc *cc = &bus->drv_cc; 221 u8 cc_rev = cc->core->id.rev; 222 223 if (cc_rev == 42) { 224 struct bcma_device *core; 225 226 core = bcma_find_core(bus, BCMA_CORE_NS_ROM); 227 if (core) { 228 switch (bcma_aread32(core, BCMA_IOST) & 229 BCMA_NS_ROM_IOST_BOOT_DEV_MASK) { 230 case BCMA_NS_ROM_IOST_BOOT_DEV_NOR: 231 return BCMA_BOOT_DEV_SERIAL; 232 case BCMA_NS_ROM_IOST_BOOT_DEV_NAND: 233 return BCMA_BOOT_DEV_NAND; 234 case BCMA_NS_ROM_IOST_BOOT_DEV_ROM: 235 default: 236 return BCMA_BOOT_DEV_ROM; 237 } 238 } 239 } else { 240 if (cc_rev == 38) { 241 if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT) 242 return BCMA_BOOT_DEV_NAND; 243 else if (cc->status & BIT(5)) 244 return BCMA_BOOT_DEV_ROM; 245 } 246 247 if ((cc->capabilities & BCMA_CC_CAP_FLASHT) == 248 BCMA_CC_FLASHT_PARA) 249 return BCMA_BOOT_DEV_PARALLEL; 250 else 251 return BCMA_BOOT_DEV_SERIAL; 252 } 253 254 return BCMA_BOOT_DEV_SERIAL; 255 } 256 257 static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore) 258 { 259 struct bcma_bus *bus = mcore->core->bus; 260 enum bcma_boot_dev boot_dev; 261 262 /* Determine flash type this SoC boots from */ 263 boot_dev = bcma_boot_dev(bus); 264 switch (boot_dev) { 265 case BCMA_BOOT_DEV_PARALLEL: 266 case BCMA_BOOT_DEV_SERIAL: 267 #ifdef CONFIG_BCM47XX 268 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2, 269 BCMA_SOC_FLASH2_SZ); 270 #endif 271 break; 272 case BCMA_BOOT_DEV_NAND: 273 #ifdef CONFIG_BCM47XX 274 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1, 275 BCMA_SOC_FLASH1_SZ); 276 #endif 277 break; 278 default: 279 break; 280 } 281 } 282 283 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) 284 { 285 struct bcma_bus *bus = mcore->core->bus; 286 287 if (mcore->early_setup_done) 288 return; 289 290 bcma_chipco_serial_init(&bus->drv_cc); 291 bcma_core_mips_nvram_init(mcore); 292 293 mcore->early_setup_done = true; 294 } 295 296 static void bcma_fix_i2s_irqflag(struct bcma_bus *bus) 297 { 298 struct bcma_device *cpu, *pcie, *i2s; 299 300 /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK) 301 * (IRQ flags > 7 are ignored when setting the interrupt masks) 302 */ 303 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 && 304 bus->chipinfo.id != BCMA_CHIP_ID_BCM4748) 305 return; 306 307 cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K); 308 pcie = bcma_find_core(bus, BCMA_CORE_PCIE); 309 i2s = bcma_find_core(bus, BCMA_CORE_I2S); 310 if (cpu && pcie && i2s && 311 bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 && 312 bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 && 313 bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) { 314 bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504); 315 bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504); 316 bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87); 317 bcma_debug(bus, 318 "Moved i2s interrupt to oob line 7 instead of 8\n"); 319 } 320 } 321 322 void bcma_core_mips_init(struct bcma_drv_mips *mcore) 323 { 324 struct bcma_bus *bus; 325 struct bcma_device *core; 326 bus = mcore->core->bus; 327 328 if (mcore->setup_done) 329 return; 330 331 bcma_debug(bus, "Initializing MIPS core...\n"); 332 333 bcma_core_mips_early_init(mcore); 334 335 bcma_fix_i2s_irqflag(bus); 336 337 switch (bus->chipinfo.id) { 338 case BCMA_CHIP_ID_BCM4716: 339 case BCMA_CHIP_ID_BCM4748: 340 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 341 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 342 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); 343 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); 344 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 345 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); 346 break; 347 case BCMA_CHIP_ID_BCM5356: 348 case BCMA_CHIP_ID_BCM47162: 349 case BCMA_CHIP_ID_BCM53572: 350 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 351 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 352 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 353 break; 354 case BCMA_CHIP_ID_BCM5357: 355 case BCMA_CHIP_ID_BCM4749: 356 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 357 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 358 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); 359 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 360 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); 361 break; 362 case BCMA_CHIP_ID_BCM4706: 363 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); 364 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, 365 0); 366 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); 367 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); 368 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, 369 0); 370 break; 371 default: 372 list_for_each_entry(core, &bus->cores, list) { 373 core->irq = bcma_core_irq(core, 0); 374 } 375 bcma_err(bus, 376 "Unknown device (0x%x) found, can not configure IRQs\n", 377 bus->chipinfo.id); 378 } 379 bcma_debug(bus, "IRQ reconfiguration done\n"); 380 bcma_core_mips_dump_irq(bus); 381 382 mcore->setup_done = true; 383 } 384