1 /* 2 * Broadcom specific AMBA 3 * ChipCommon Power Management Unit driver 4 * 5 * Copyright 2009, Michael Buesch <m@bues.ch> 6 * Copyright 2007, 2011, Broadcom Corporation 7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/export.h> 14 #include <linux/bcma/bcma.h> 15 16 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) 17 { 18 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 19 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 20 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 21 } 22 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); 23 24 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) 25 { 26 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 27 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 28 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); 29 } 30 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write); 31 32 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, 33 u32 set) 34 { 35 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 36 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 37 bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set); 38 } 39 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset); 40 41 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, 42 u32 offset, u32 mask, u32 set) 43 { 44 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset); 45 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); 46 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set); 47 } 48 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset); 49 50 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, 51 u32 set) 52 { 53 bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset); 54 bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR); 55 bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set); 56 } 57 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); 58 59 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) 60 { 61 struct bcma_bus *bus = cc->core->bus; 62 u32 min_msk = 0, max_msk = 0; 63 64 switch (bus->chipinfo.id) { 65 case BCMA_CHIP_ID_BCM4313: 66 min_msk = 0x200D; 67 max_msk = 0xFFFF; 68 break; 69 default: 70 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n", 71 bus->chipinfo.id); 72 } 73 74 /* Set the resource masks. */ 75 if (min_msk) 76 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); 77 if (max_msk) 78 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); 79 80 /* 81 * Add some delay; allow resources to come up and settle. 82 * Delay is required for SoC (early init). 83 */ 84 mdelay(2); 85 } 86 87 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ 88 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) 89 { 90 struct bcma_bus *bus = cc->core->bus; 91 u32 val; 92 93 val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL); 94 if (enable) { 95 val |= BCMA_CHIPCTL_4331_EXTPA_EN; 96 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) 97 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 98 else if (bus->chipinfo.rev > 0) 99 val |= BCMA_CHIPCTL_4331_EXTPA_EN2; 100 } else { 101 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; 102 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2; 103 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 104 } 105 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); 106 } 107 108 static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) 109 { 110 struct bcma_bus *bus = cc->core->bus; 111 112 switch (bus->chipinfo.id) { 113 case BCMA_CHIP_ID_BCM4313: 114 /* enable 12 mA drive strenth for 4313 and set chipControl 115 register bit 1 */ 116 bcma_chipco_chipctl_maskset(cc, 0, 117 ~BCMA_CCTRL_4313_12MA_LED_DRIVE, 118 BCMA_CCTRL_4313_12MA_LED_DRIVE); 119 break; 120 case BCMA_CHIP_ID_BCM4331: 121 case BCMA_CHIP_ID_BCM43431: 122 /* Ext PA lines must be enabled for tx on BCM4331 */ 123 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true); 124 break; 125 case BCMA_CHIP_ID_BCM43224: 126 case BCMA_CHIP_ID_BCM43421: 127 /* enable 12 mA drive strenth for 43224 and set chipControl 128 register bit 15 */ 129 if (bus->chipinfo.rev == 0) { 130 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL, 131 ~BCMA_CCTRL_43224_GPIO_TOGGLE, 132 BCMA_CCTRL_43224_GPIO_TOGGLE); 133 bcma_chipco_chipctl_maskset(cc, 0, 134 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE, 135 BCMA_CCTRL_43224A0_12MA_LED_DRIVE); 136 } else { 137 bcma_chipco_chipctl_maskset(cc, 0, 138 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE, 139 BCMA_CCTRL_43224B0_12MA_LED_DRIVE); 140 } 141 break; 142 default: 143 bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n", 144 bus->chipinfo.id); 145 } 146 } 147 148 void bcma_pmu_early_init(struct bcma_drv_cc *cc) 149 { 150 u32 pmucap; 151 152 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); 153 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); 154 155 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", 156 cc->pmu.rev, pmucap); 157 } 158 159 void bcma_pmu_init(struct bcma_drv_cc *cc) 160 { 161 if (cc->pmu.rev == 1) 162 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, 163 ~BCMA_CC_PMU_CTL_NOILPONW); 164 else 165 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 166 BCMA_CC_PMU_CTL_NOILPONW); 167 168 bcma_pmu_resources_init(cc); 169 bcma_pmu_workarounds(cc); 170 } 171 172 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) 173 { 174 struct bcma_bus *bus = cc->core->bus; 175 176 switch (bus->chipinfo.id) { 177 case BCMA_CHIP_ID_BCM4716: 178 case BCMA_CHIP_ID_BCM4748: 179 case BCMA_CHIP_ID_BCM47162: 180 case BCMA_CHIP_ID_BCM4313: 181 case BCMA_CHIP_ID_BCM5357: 182 case BCMA_CHIP_ID_BCM4749: 183 case BCMA_CHIP_ID_BCM53572: 184 /* always 20Mhz */ 185 return 20000 * 1000; 186 case BCMA_CHIP_ID_BCM5356: 187 case BCMA_CHIP_ID_BCM4706: 188 /* always 25Mhz */ 189 return 25000 * 1000; 190 default: 191 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", 192 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); 193 } 194 return BCMA_CC_PMU_ALP_CLOCK; 195 } 196 197 /* Find the output of the "m" pll divider given pll controls that start with 198 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. 199 */ 200 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) 201 { 202 u32 tmp, div, ndiv, p1, p2, fc; 203 struct bcma_bus *bus = cc->core->bus; 204 205 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); 206 207 BUG_ON(!m || m > 4); 208 209 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 210 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) { 211 /* Detect failure in clock setting */ 212 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 213 if (tmp & 0x40000) 214 return 133 * 1000000; 215 } 216 217 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); 218 p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT; 219 p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT; 220 221 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); 222 div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) & 223 BCMA_CC_PPL_MDIV_MASK; 224 225 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); 226 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; 227 228 /* Do calculation in Mhz */ 229 fc = bcma_pmu_get_alp_clock(cc) / 1000000; 230 fc = (p1 * ndiv * fc) / p2; 231 232 /* Return clock in Hertz */ 233 return (fc / div) * 1000000; 234 } 235 236 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) 237 { 238 u32 tmp, ndiv, p1div, p2div; 239 u32 clock; 240 241 BUG_ON(!m || m > 4); 242 243 /* Get N, P1 and P2 dividers to determine CPU clock */ 244 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); 245 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK) 246 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT; 247 p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK) 248 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT; 249 p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK) 250 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT; 251 252 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 253 if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION) 254 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */ 255 clock = (25000000 / 4) * ndiv * p2div / p1div; 256 else 257 /* Fixed reference clock 25MHz and m = 2 */ 258 clock = (25000000 / 2) * ndiv * p2div / p1div; 259 260 if (m == BCMA_CC_PMU5_MAINPLL_SSB) 261 clock = clock / 4; 262 263 return clock; 264 } 265 266 /* query bus clock frequency for PMU-enabled chipcommon */ 267 u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) 268 { 269 struct bcma_bus *bus = cc->core->bus; 270 271 switch (bus->chipinfo.id) { 272 case BCMA_CHIP_ID_BCM4716: 273 case BCMA_CHIP_ID_BCM4748: 274 case BCMA_CHIP_ID_BCM47162: 275 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, 276 BCMA_CC_PMU5_MAINPLL_SSB); 277 case BCMA_CHIP_ID_BCM5356: 278 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, 279 BCMA_CC_PMU5_MAINPLL_SSB); 280 case BCMA_CHIP_ID_BCM5357: 281 case BCMA_CHIP_ID_BCM4749: 282 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, 283 BCMA_CC_PMU5_MAINPLL_SSB); 284 case BCMA_CHIP_ID_BCM4706: 285 return bcma_pmu_pll_clock_bcm4706(cc, 286 BCMA_CC_PMU4706_MAINPLL_PLL0, 287 BCMA_CC_PMU5_MAINPLL_SSB); 288 case BCMA_CHIP_ID_BCM53572: 289 return 75000000; 290 default: 291 bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n", 292 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); 293 } 294 return BCMA_CC_PMU_HT_CLOCK; 295 } 296 EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock); 297 298 /* query cpu clock frequency for PMU-enabled chipcommon */ 299 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) 300 { 301 struct bcma_bus *bus = cc->core->bus; 302 303 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) 304 return 300000000; 305 306 /* New PMUs can have different clock for bus and CPU */ 307 if (cc->pmu.rev >= 5) { 308 u32 pll; 309 switch (bus->chipinfo.id) { 310 case BCMA_CHIP_ID_BCM4706: 311 return bcma_pmu_pll_clock_bcm4706(cc, 312 BCMA_CC_PMU4706_MAINPLL_PLL0, 313 BCMA_CC_PMU5_MAINPLL_CPU); 314 case BCMA_CHIP_ID_BCM5356: 315 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; 316 break; 317 case BCMA_CHIP_ID_BCM5357: 318 case BCMA_CHIP_ID_BCM4749: 319 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; 320 break; 321 default: 322 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; 323 break; 324 } 325 326 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); 327 } 328 329 /* On old PMUs CPU has the same clock as the bus */ 330 return bcma_pmu_get_bus_clock(cc); 331 } 332 333 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, 334 u32 value) 335 { 336 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 337 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); 338 } 339 340 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) 341 { 342 u32 tmp = 0; 343 u8 phypll_offset = 0; 344 u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5}; 345 u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc}; 346 struct bcma_bus *bus = cc->core->bus; 347 348 switch (bus->chipinfo.id) { 349 case BCMA_CHIP_ID_BCM5357: 350 case BCMA_CHIP_ID_BCM4749: 351 case BCMA_CHIP_ID_BCM53572: 352 /* 5357[ab]0, 43236[ab]0, and 6362b0 */ 353 354 /* BCM5357 needs to touch PLL1_PLLCTL[02], 355 so offset PLL0_PLLCTL[02] by 6 */ 356 phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 357 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 || 358 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0; 359 360 /* RMW only the P1 divider */ 361 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, 362 BCMA_CC_PMU_PLL_CTL0 + phypll_offset); 363 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 364 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK)); 365 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT); 366 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); 367 368 /* RMW only the int feedback divider */ 369 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, 370 BCMA_CC_PMU_PLL_CTL2 + phypll_offset); 371 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 372 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK); 373 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; 374 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); 375 376 tmp = BCMA_CC_PMU_CTL_PLL_UPD; 377 break; 378 379 case BCMA_CHIP_ID_BCM4331: 380 case BCMA_CHIP_ID_BCM43431: 381 if (spuravoid == 2) { 382 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 383 0x11500014); 384 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 385 0x0FC00a08); 386 } else if (spuravoid == 1) { 387 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 388 0x11500014); 389 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 390 0x0F600a08); 391 } else { 392 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 393 0x11100014); 394 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 395 0x03000a08); 396 } 397 tmp = BCMA_CC_PMU_CTL_PLL_UPD; 398 break; 399 400 case BCMA_CHIP_ID_BCM43224: 401 case BCMA_CHIP_ID_BCM43225: 402 case BCMA_CHIP_ID_BCM43421: 403 if (spuravoid == 1) { 404 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 405 0x11500010); 406 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 407 0x000C0C06); 408 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 409 0x0F600a08); 410 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 411 0x00000000); 412 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 413 0x2001E920); 414 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 415 0x88888815); 416 } else { 417 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 418 0x11100010); 419 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 420 0x000c0c06); 421 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 422 0x03000a08); 423 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 424 0x00000000); 425 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 426 0x200005c0); 427 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 428 0x88888815); 429 } 430 tmp = BCMA_CC_PMU_CTL_PLL_UPD; 431 break; 432 433 case BCMA_CHIP_ID_BCM4716: 434 case BCMA_CHIP_ID_BCM4748: 435 case BCMA_CHIP_ID_BCM47162: 436 if (spuravoid == 1) { 437 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 438 0x11500060); 439 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 440 0x080C0C06); 441 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 442 0x0F600000); 443 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 444 0x00000000); 445 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 446 0x2001E924); 447 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 448 0x88888815); 449 } else { 450 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 451 0x11100060); 452 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 453 0x080c0c06); 454 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 455 0x03000000); 456 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 457 0x00000000); 458 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 459 0x200005c0); 460 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 461 0x88888815); 462 } 463 464 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; 465 break; 466 467 case BCMA_CHIP_ID_BCM43227: 468 case BCMA_CHIP_ID_BCM43228: 469 case BCMA_CHIP_ID_BCM43428: 470 /* LCNXN */ 471 /* PLL Settings for spur avoidance on/off mode, 472 no on2 support for 43228A0 */ 473 if (spuravoid == 1) { 474 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 475 0x01100014); 476 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 477 0x040C0C06); 478 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 479 0x03140A08); 480 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 481 0x00333333); 482 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 483 0x202C2820); 484 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 485 0x88888815); 486 } else { 487 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 488 0x11100014); 489 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 490 0x040c0c06); 491 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 492 0x03000a08); 493 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 494 0x00000000); 495 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 496 0x200005c0); 497 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 498 0x88888815); 499 } 500 tmp = BCMA_CC_PMU_CTL_PLL_UPD; 501 break; 502 default: 503 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", 504 bus->chipinfo.id); 505 break; 506 } 507 508 tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL); 509 bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp); 510 } 511 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate); 512