1 /* 2 * Broadcom specific AMBA 3 * ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/bcm47xx_wdt.h> 14 #include <linux/export.h> 15 #include <linux/platform_device.h> 16 #include <linux/bcma/bcma.h> 17 18 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc); 19 20 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 21 u32 mask, u32 value) 22 { 23 value &= mask; 24 value |= bcma_cc_read32(cc, offset) & ~mask; 25 bcma_cc_write32(cc, offset, value); 26 27 return value; 28 } 29 30 u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) 31 { 32 if (cc->capabilities & BCMA_CC_CAP_PMU) 33 return bcma_pmu_get_alp_clock(cc); 34 35 return 20000000; 36 } 37 EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); 38 39 static bool bcma_core_cc_has_pmu_watchdog(struct bcma_drv_cc *cc) 40 { 41 struct bcma_bus *bus = cc->core->bus; 42 43 if (cc->capabilities & BCMA_CC_CAP_PMU) { 44 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573) { 45 WARN(bus->chipinfo.rev <= 1, "No watchdog available\n"); 46 /* 53573B0 and 53573B1 have bugged PMU watchdog. It can 47 * be enabled but timer can't be bumped. Use CC one 48 * instead. 49 */ 50 return false; 51 } 52 return true; 53 } else { 54 return false; 55 } 56 } 57 58 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) 59 { 60 struct bcma_bus *bus = cc->core->bus; 61 u32 nb; 62 63 if (bcma_core_cc_has_pmu_watchdog(cc)) { 64 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 65 nb = 32; 66 else if (cc->core->id.rev < 26) 67 nb = 16; 68 else 69 nb = (cc->core->id.rev >= 37) ? 32 : 24; 70 } else { 71 nb = 28; 72 } 73 if (nb == 32) 74 return 0xffffffff; 75 else 76 return (1 << nb) - 1; 77 } 78 79 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, 80 u32 ticks) 81 { 82 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 83 84 return bcma_chipco_watchdog_timer_set(cc, ticks); 85 } 86 87 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, 88 u32 ms) 89 { 90 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 91 u32 ticks; 92 93 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); 94 return ticks / cc->ticks_per_ms; 95 } 96 97 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) 98 { 99 struct bcma_bus *bus = cc->core->bus; 100 101 if (cc->capabilities & BCMA_CC_CAP_PMU) { 102 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 103 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP 104 * clock 105 */ 106 return bcma_chipco_get_alp_clock(cc) / 4000; 107 else 108 /* based on 32KHz ILP clock */ 109 return 32; 110 } else { 111 return bcma_chipco_get_alp_clock(cc) / 1000; 112 } 113 } 114 115 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 116 { 117 struct bcma_bus *bus = cc->core->bus; 118 struct bcm47xx_wdt wdt = {}; 119 struct platform_device *pdev; 120 121 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573 && 122 bus->chipinfo.rev <= 1) { 123 pr_debug("No watchdog on 53573A0 / 53573A1\n"); 124 return 0; 125 } 126 127 wdt.driver_data = cc; 128 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; 129 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; 130 wdt.max_timer_ms = 131 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; 132 133 pdev = platform_device_register_data(NULL, "bcm47xx-wdt", 134 bus->num, &wdt, 135 sizeof(wdt)); 136 if (IS_ERR(pdev)) 137 return PTR_ERR(pdev); 138 139 cc->watchdog = pdev; 140 141 return 0; 142 } 143 144 static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc) 145 { 146 struct bcma_bus *bus = cc->core->bus; 147 148 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { 149 case BCMA_CC_FLASHT_STSER: 150 case BCMA_CC_FLASHT_ATSER: 151 bcma_debug(bus, "Found serial flash\n"); 152 bcma_sflash_init(cc); 153 break; 154 case BCMA_CC_FLASHT_PARA: 155 bcma_debug(bus, "Found parallel flash\n"); 156 bcma_pflash_init(cc); 157 break; 158 default: 159 bcma_err(bus, "Flash type not supported\n"); 160 } 161 162 if (cc->core->id.rev == 38 || 163 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { 164 if (cc->capabilities & BCMA_CC_CAP_NFLASH) { 165 bcma_debug(bus, "Found NAND flash\n"); 166 bcma_nflash_init(cc); 167 } 168 } 169 } 170 171 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 172 { 173 struct bcma_bus *bus = cc->core->bus; 174 175 if (cc->early_setup_done) 176 return; 177 178 spin_lock_init(&cc->gpio_lock); 179 180 if (cc->core->id.rev >= 11) 181 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 182 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 183 if (cc->core->id.rev >= 35) 184 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 185 186 if (cc->capabilities & BCMA_CC_CAP_PMU) 187 bcma_pmu_early_init(cc); 188 189 if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC) 190 bcma_chipco_serial_init(cc); 191 192 if (bus->hosttype == BCMA_HOSTTYPE_SOC) 193 bcma_core_chipcommon_flash_detect(cc); 194 195 cc->early_setup_done = true; 196 } 197 198 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 199 { 200 u32 leddc_on = 10; 201 u32 leddc_off = 90; 202 203 if (cc->setup_done) 204 return; 205 206 bcma_core_chipcommon_early_init(cc); 207 208 if (cc->core->id.rev >= 20) { 209 u32 pullup = 0, pulldown = 0; 210 211 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) { 212 pullup = 0x402e0; 213 pulldown = 0x20500; 214 } 215 216 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup); 217 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown); 218 } 219 220 if (cc->capabilities & BCMA_CC_CAP_PMU) 221 bcma_pmu_init(cc); 222 if (cc->capabilities & BCMA_CC_CAP_PCTL) 223 bcma_err(cc->core->bus, "Power control not implemented!\n"); 224 225 if (cc->core->id.rev >= 16) { 226 if (cc->core->bus->sprom.leddc_on_time && 227 cc->core->bus->sprom.leddc_off_time) { 228 leddc_on = cc->core->bus->sprom.leddc_on_time; 229 leddc_off = cc->core->bus->sprom.leddc_off_time; 230 } 231 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 232 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 233 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 234 } 235 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); 236 237 cc->setup_done = true; 238 } 239 240 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 241 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 242 { 243 u32 maxt; 244 245 maxt = bcma_chipco_watchdog_get_max_timer(cc); 246 if (bcma_core_cc_has_pmu_watchdog(cc)) { 247 if (ticks == 1) 248 ticks = 2; 249 else if (ticks > maxt) 250 ticks = maxt; 251 bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); 252 } else { 253 struct bcma_bus *bus = cc->core->bus; 254 255 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 && 256 bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 && 257 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018) 258 bcma_core_set_clockmode(cc->core, 259 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC); 260 261 if (ticks > maxt) 262 ticks = maxt; 263 /* instant NMI */ 264 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 265 } 266 return ticks; 267 } 268 269 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 270 { 271 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 272 } 273 274 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 275 { 276 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 277 } 278 279 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 280 { 281 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 282 } 283 284 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 285 { 286 unsigned long flags; 287 u32 res; 288 289 spin_lock_irqsave(&cc->gpio_lock, flags); 290 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 291 spin_unlock_irqrestore(&cc->gpio_lock, flags); 292 293 return res; 294 } 295 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); 296 297 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 298 { 299 unsigned long flags; 300 u32 res; 301 302 spin_lock_irqsave(&cc->gpio_lock, flags); 303 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 304 spin_unlock_irqrestore(&cc->gpio_lock, flags); 305 306 return res; 307 } 308 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); 309 310 /* 311 * If the bit is set to 0, chipcommon controlls this GPIO, 312 * if the bit is set to 1, it is used by some part of the chip and not our code. 313 */ 314 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 315 { 316 unsigned long flags; 317 u32 res; 318 319 spin_lock_irqsave(&cc->gpio_lock, flags); 320 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 321 spin_unlock_irqrestore(&cc->gpio_lock, flags); 322 323 return res; 324 } 325 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 326 327 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 328 { 329 unsigned long flags; 330 u32 res; 331 332 spin_lock_irqsave(&cc->gpio_lock, flags); 333 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 334 spin_unlock_irqrestore(&cc->gpio_lock, flags); 335 336 return res; 337 } 338 339 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 340 { 341 unsigned long flags; 342 u32 res; 343 344 spin_lock_irqsave(&cc->gpio_lock, flags); 345 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 346 spin_unlock_irqrestore(&cc->gpio_lock, flags); 347 348 return res; 349 } 350 351 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) 352 { 353 unsigned long flags; 354 u32 res; 355 356 if (cc->core->id.rev < 20) 357 return 0; 358 359 spin_lock_irqsave(&cc->gpio_lock, flags); 360 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); 361 spin_unlock_irqrestore(&cc->gpio_lock, flags); 362 363 return res; 364 } 365 366 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) 367 { 368 unsigned long flags; 369 u32 res; 370 371 if (cc->core->id.rev < 20) 372 return 0; 373 374 spin_lock_irqsave(&cc->gpio_lock, flags); 375 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); 376 spin_unlock_irqrestore(&cc->gpio_lock, flags); 377 378 return res; 379 } 380 381 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 382 { 383 #if IS_BUILTIN(CONFIG_BCM47XX) 384 unsigned int irq; 385 u32 baud_base; 386 u32 i; 387 unsigned int ccrev = cc->core->id.rev; 388 struct bcma_serial_port *ports = cc->serial_ports; 389 390 if (ccrev >= 11 && ccrev != 15) { 391 baud_base = bcma_chipco_get_alp_clock(cc); 392 if (ccrev >= 21) { 393 /* Turn off UART clock before switching clocksource. */ 394 bcma_cc_write32(cc, BCMA_CC_CORECTL, 395 bcma_cc_read32(cc, BCMA_CC_CORECTL) 396 & ~BCMA_CC_CORECTL_UARTCLKEN); 397 } 398 /* Set the override bit so we don't divide it */ 399 bcma_cc_write32(cc, BCMA_CC_CORECTL, 400 bcma_cc_read32(cc, BCMA_CC_CORECTL) 401 | BCMA_CC_CORECTL_UARTCLK0); 402 if (ccrev >= 21) { 403 /* Re-enable the UART clock. */ 404 bcma_cc_write32(cc, BCMA_CC_CORECTL, 405 bcma_cc_read32(cc, BCMA_CC_CORECTL) 406 | BCMA_CC_CORECTL_UARTCLKEN); 407 } 408 } else { 409 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", 410 ccrev); 411 return; 412 } 413 414 irq = bcma_core_irq(cc->core, 0); 415 416 /* Determine the registers of the UARTs */ 417 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 418 for (i = 0; i < cc->nr_serial_ports; i++) { 419 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 420 (i * 256); 421 ports[i].irq = irq; 422 ports[i].baud_base = baud_base; 423 ports[i].reg_shift = 0; 424 } 425 #endif /* CONFIG_BCM47XX */ 426 } 427