18369ae33SRafał Miłecki /* 28369ae33SRafał Miłecki * Broadcom specific AMBA 38369ae33SRafał Miłecki * ChipCommon core driver 48369ae33SRafał Miłecki * 58369ae33SRafał Miłecki * Copyright 2005, Broadcom Corporation 6eb032b98SMichael Büsch * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 756fd5f07SHauke Mehrtens * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> 88369ae33SRafał Miłecki * 98369ae33SRafał Miłecki * Licensed under the GNU/GPL. See COPYING for details. 108369ae33SRafał Miłecki */ 118369ae33SRafał Miłecki 128369ae33SRafał Miłecki #include "bcma_private.h" 13a22a3114SHauke Mehrtens #include <linux/bcm47xx_wdt.h> 1444a8e377SPaul Gortmaker #include <linux/export.h> 15a4855f39SHauke Mehrtens #include <linux/platform_device.h> 168369ae33SRafał Miłecki #include <linux/bcma/bcma.h> 178369ae33SRafał Miłecki 188369ae33SRafał Miłecki static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 198369ae33SRafał Miłecki u32 mask, u32 value) 208369ae33SRafał Miłecki { 218369ae33SRafał Miłecki value &= mask; 228369ae33SRafał Miłecki value |= bcma_cc_read32(cc, offset) & ~mask; 238369ae33SRafał Miłecki bcma_cc_write32(cc, offset, value); 248369ae33SRafał Miłecki 258369ae33SRafał Miłecki return value; 268369ae33SRafał Miłecki } 278369ae33SRafał Miłecki 285b5ac414SRafał Miłecki static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) 2956fd5f07SHauke Mehrtens { 3056fd5f07SHauke Mehrtens if (cc->capabilities & BCMA_CC_CAP_PMU) 315b5ac414SRafał Miłecki return bcma_pmu_get_alp_clock(cc); 3256fd5f07SHauke Mehrtens 3356fd5f07SHauke Mehrtens return 20000000; 3456fd5f07SHauke Mehrtens } 3556fd5f07SHauke Mehrtens 36f6354c8cSHauke Mehrtens static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) 37f6354c8cSHauke Mehrtens { 38f6354c8cSHauke Mehrtens struct bcma_bus *bus = cc->core->bus; 39f6354c8cSHauke Mehrtens u32 nb; 40f6354c8cSHauke Mehrtens 41f6354c8cSHauke Mehrtens if (cc->capabilities & BCMA_CC_CAP_PMU) { 42f6354c8cSHauke Mehrtens if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 43f6354c8cSHauke Mehrtens nb = 32; 44f6354c8cSHauke Mehrtens else if (cc->core->id.rev < 26) 45f6354c8cSHauke Mehrtens nb = 16; 46f6354c8cSHauke Mehrtens else 47f6354c8cSHauke Mehrtens nb = (cc->core->id.rev >= 37) ? 32 : 24; 48f6354c8cSHauke Mehrtens } else { 49f6354c8cSHauke Mehrtens nb = 28; 50f6354c8cSHauke Mehrtens } 51f6354c8cSHauke Mehrtens if (nb == 32) 52f6354c8cSHauke Mehrtens return 0xffffffff; 53f6354c8cSHauke Mehrtens else 54f6354c8cSHauke Mehrtens return (1 << nb) - 1; 55f6354c8cSHauke Mehrtens } 56f6354c8cSHauke Mehrtens 57a22a3114SHauke Mehrtens static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, 58a22a3114SHauke Mehrtens u32 ticks) 59a22a3114SHauke Mehrtens { 60a22a3114SHauke Mehrtens struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 61a22a3114SHauke Mehrtens 62a22a3114SHauke Mehrtens return bcma_chipco_watchdog_timer_set(cc, ticks); 63a22a3114SHauke Mehrtens } 64a22a3114SHauke Mehrtens 65a22a3114SHauke Mehrtens static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, 66a22a3114SHauke Mehrtens u32 ms) 67a22a3114SHauke Mehrtens { 68a22a3114SHauke Mehrtens struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 69a22a3114SHauke Mehrtens u32 ticks; 70a22a3114SHauke Mehrtens 71a22a3114SHauke Mehrtens ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); 72a22a3114SHauke Mehrtens return ticks / cc->ticks_per_ms; 73a22a3114SHauke Mehrtens } 74a22a3114SHauke Mehrtens 75a22a3114SHauke Mehrtens static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) 76a22a3114SHauke Mehrtens { 77a22a3114SHauke Mehrtens struct bcma_bus *bus = cc->core->bus; 78a22a3114SHauke Mehrtens 79a22a3114SHauke Mehrtens if (cc->capabilities & BCMA_CC_CAP_PMU) { 80a22a3114SHauke Mehrtens if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 81a22a3114SHauke Mehrtens /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ 825b5ac414SRafał Miłecki return bcma_chipco_get_alp_clock(cc) / 4000; 83a22a3114SHauke Mehrtens else 84a22a3114SHauke Mehrtens /* based on 32KHz ILP clock */ 85a22a3114SHauke Mehrtens return 32; 86a22a3114SHauke Mehrtens } else { 875b5ac414SRafał Miłecki return bcma_chipco_get_alp_clock(cc) / 1000; 88a22a3114SHauke Mehrtens } 89a22a3114SHauke Mehrtens } 90f6354c8cSHauke Mehrtens 91a4855f39SHauke Mehrtens int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 92a4855f39SHauke Mehrtens { 93a4855f39SHauke Mehrtens struct bcm47xx_wdt wdt = {}; 94a4855f39SHauke Mehrtens struct platform_device *pdev; 95a4855f39SHauke Mehrtens 96a4855f39SHauke Mehrtens wdt.driver_data = cc; 97a4855f39SHauke Mehrtens wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; 98a4855f39SHauke Mehrtens wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; 99a4855f39SHauke Mehrtens wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; 100a4855f39SHauke Mehrtens 101a4855f39SHauke Mehrtens pdev = platform_device_register_data(NULL, "bcm47xx-wdt", 102a4855f39SHauke Mehrtens cc->core->bus->num, &wdt, 103a4855f39SHauke Mehrtens sizeof(wdt)); 104a4855f39SHauke Mehrtens if (IS_ERR(pdev)) 105a4855f39SHauke Mehrtens return PTR_ERR(pdev); 106a4855f39SHauke Mehrtens 107a4855f39SHauke Mehrtens cc->watchdog = pdev; 108a4855f39SHauke Mehrtens 109a4855f39SHauke Mehrtens return 0; 110a4855f39SHauke Mehrtens } 111a4855f39SHauke Mehrtens 11249655bb8SHauke Mehrtens void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 11349655bb8SHauke Mehrtens { 11449655bb8SHauke Mehrtens if (cc->early_setup_done) 11549655bb8SHauke Mehrtens return; 11649655bb8SHauke Mehrtens 117ef85fb28SHauke Mehrtens spin_lock_init(&cc->gpio_lock); 118ef85fb28SHauke Mehrtens 11949655bb8SHauke Mehrtens if (cc->core->id.rev >= 11) 12049655bb8SHauke Mehrtens cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 12149655bb8SHauke Mehrtens cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 12249655bb8SHauke Mehrtens if (cc->core->id.rev >= 35) 12349655bb8SHauke Mehrtens cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 12449655bb8SHauke Mehrtens 12549655bb8SHauke Mehrtens if (cc->capabilities & BCMA_CC_CAP_PMU) 12649655bb8SHauke Mehrtens bcma_pmu_early_init(cc); 12749655bb8SHauke Mehrtens 12849655bb8SHauke Mehrtens cc->early_setup_done = true; 12949655bb8SHauke Mehrtens } 13049655bb8SHauke Mehrtens 1318369ae33SRafał Miłecki void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 1328369ae33SRafał Miłecki { 13318dfa495SRafał Miłecki u32 leddc_on = 10; 13418dfa495SRafał Miłecki u32 leddc_off = 90; 13518dfa495SRafał Miłecki 136517f43e5SHauke Mehrtens if (cc->setup_done) 137517f43e5SHauke Mehrtens return; 138517f43e5SHauke Mehrtens 13949655bb8SHauke Mehrtens bcma_core_chipcommon_early_init(cc); 1408369ae33SRafał Miłecki 1411073e4eeSRafał Miłecki if (cc->core->id.rev >= 20) { 1421073e4eeSRafał Miłecki bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); 1431073e4eeSRafał Miłecki bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); 1441073e4eeSRafał Miłecki } 1458369ae33SRafał Miłecki 1468369ae33SRafał Miłecki if (cc->capabilities & BCMA_CC_CAP_PMU) 1478369ae33SRafał Miłecki bcma_pmu_init(cc); 1488369ae33SRafał Miłecki if (cc->capabilities & BCMA_CC_CAP_PCTL) 1493d9d8af3SRafał Miłecki bcma_err(cc->core->bus, "Power control not implemented!\n"); 15018dfa495SRafał Miłecki 15118dfa495SRafał Miłecki if (cc->core->id.rev >= 16) { 15218dfa495SRafał Miłecki if (cc->core->bus->sprom.leddc_on_time && 15318dfa495SRafał Miłecki cc->core->bus->sprom.leddc_off_time) { 15418dfa495SRafał Miłecki leddc_on = cc->core->bus->sprom.leddc_on_time; 15518dfa495SRafał Miłecki leddc_off = cc->core->bus->sprom.leddc_off_time; 15618dfa495SRafał Miłecki } 15718dfa495SRafał Miłecki bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 15818dfa495SRafał Miłecki ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 15918dfa495SRafał Miłecki (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 16018dfa495SRafał Miłecki } 161a22a3114SHauke Mehrtens cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); 162517f43e5SHauke Mehrtens 163517f43e5SHauke Mehrtens cc->setup_done = true; 1648369ae33SRafał Miłecki } 1658369ae33SRafał Miłecki 1668369ae33SRafał Miłecki /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 167a22a3114SHauke Mehrtens u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 1688369ae33SRafał Miłecki { 169f6354c8cSHauke Mehrtens u32 maxt; 170f6354c8cSHauke Mehrtens enum bcma_clkmode clkmode; 171f6354c8cSHauke Mehrtens 172f6354c8cSHauke Mehrtens maxt = bcma_chipco_watchdog_get_max_timer(cc); 173f6354c8cSHauke Mehrtens if (cc->capabilities & BCMA_CC_CAP_PMU) { 174f6354c8cSHauke Mehrtens if (ticks == 1) 175f6354c8cSHauke Mehrtens ticks = 2; 176f6354c8cSHauke Mehrtens else if (ticks > maxt) 177f6354c8cSHauke Mehrtens ticks = maxt; 178f6354c8cSHauke Mehrtens bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); 179f6354c8cSHauke Mehrtens } else { 180f6354c8cSHauke Mehrtens clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; 181f6354c8cSHauke Mehrtens bcma_core_set_clockmode(cc->core, clkmode); 182f6354c8cSHauke Mehrtens if (ticks > maxt) 183f6354c8cSHauke Mehrtens ticks = maxt; 1848369ae33SRafał Miłecki /* instant NMI */ 1858369ae33SRafał Miłecki bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 1868369ae33SRafał Miłecki } 187a22a3114SHauke Mehrtens return ticks; 188f6354c8cSHauke Mehrtens } 1898369ae33SRafał Miłecki 1908369ae33SRafał Miłecki void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 1918369ae33SRafał Miłecki { 1928369ae33SRafał Miłecki bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 1938369ae33SRafał Miłecki } 1948369ae33SRafał Miłecki 1958369ae33SRafał Miłecki u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 1968369ae33SRafał Miłecki { 1978369ae33SRafał Miłecki return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 1988369ae33SRafał Miłecki } 1998369ae33SRafał Miłecki 2008369ae33SRafał Miłecki u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 2018369ae33SRafał Miłecki { 2028369ae33SRafał Miłecki return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 2038369ae33SRafał Miłecki } 2048369ae33SRafał Miłecki 2058369ae33SRafał Miłecki u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 2068369ae33SRafał Miłecki { 207ef85fb28SHauke Mehrtens unsigned long flags; 208ef85fb28SHauke Mehrtens u32 res; 209ef85fb28SHauke Mehrtens 210ef85fb28SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 211ef85fb28SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 212ef85fb28SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 213ef85fb28SHauke Mehrtens 214ef85fb28SHauke Mehrtens return res; 2158369ae33SRafał Miłecki } 2168369ae33SRafał Miłecki 2178369ae33SRafał Miłecki u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 2188369ae33SRafał Miłecki { 219ef85fb28SHauke Mehrtens unsigned long flags; 220ef85fb28SHauke Mehrtens u32 res; 221ef85fb28SHauke Mehrtens 222ef85fb28SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 223ef85fb28SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 224ef85fb28SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 225ef85fb28SHauke Mehrtens 226ef85fb28SHauke Mehrtens return res; 2278369ae33SRafał Miłecki } 2288369ae33SRafał Miłecki 2293e8bb507SHauke Mehrtens /* 2303e8bb507SHauke Mehrtens * If the bit is set to 0, chipcommon controlls this GPIO, 2313e8bb507SHauke Mehrtens * if the bit is set to 1, it is used by some part of the chip and not our code. 2323e8bb507SHauke Mehrtens */ 2338369ae33SRafał Miłecki u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 2348369ae33SRafał Miłecki { 235ef85fb28SHauke Mehrtens unsigned long flags; 236ef85fb28SHauke Mehrtens u32 res; 237ef85fb28SHauke Mehrtens 238ef85fb28SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 239ef85fb28SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 240ef85fb28SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 241ef85fb28SHauke Mehrtens 242ef85fb28SHauke Mehrtens return res; 2438369ae33SRafał Miłecki } 2448369ae33SRafał Miłecki EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 2458369ae33SRafał Miłecki 2468369ae33SRafał Miłecki u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 2478369ae33SRafał Miłecki { 248ef85fb28SHauke Mehrtens unsigned long flags; 249ef85fb28SHauke Mehrtens u32 res; 250ef85fb28SHauke Mehrtens 251ef85fb28SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 252ef85fb28SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 253ef85fb28SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 254ef85fb28SHauke Mehrtens 255ef85fb28SHauke Mehrtens return res; 2568369ae33SRafał Miłecki } 2578369ae33SRafał Miłecki 2588369ae33SRafał Miłecki u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 2598369ae33SRafał Miłecki { 260ef85fb28SHauke Mehrtens unsigned long flags; 261ef85fb28SHauke Mehrtens u32 res; 262ef85fb28SHauke Mehrtens 263ef85fb28SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 264ef85fb28SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 265ef85fb28SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 266ef85fb28SHauke Mehrtens 267ef85fb28SHauke Mehrtens return res; 2688369ae33SRafał Miłecki } 269e3afe0e5SHauke Mehrtens 270ea3488f4SHauke Mehrtens u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) 271ea3488f4SHauke Mehrtens { 272ea3488f4SHauke Mehrtens unsigned long flags; 273ea3488f4SHauke Mehrtens u32 res; 274ea3488f4SHauke Mehrtens 275ea3488f4SHauke Mehrtens if (cc->core->id.rev < 20) 276ea3488f4SHauke Mehrtens return 0; 277ea3488f4SHauke Mehrtens 278ea3488f4SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 279ea3488f4SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); 280ea3488f4SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 281ea3488f4SHauke Mehrtens 282ea3488f4SHauke Mehrtens return res; 283ea3488f4SHauke Mehrtens } 284ea3488f4SHauke Mehrtens 285ea3488f4SHauke Mehrtens u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) 286ea3488f4SHauke Mehrtens { 287ea3488f4SHauke Mehrtens unsigned long flags; 288ea3488f4SHauke Mehrtens u32 res; 289ea3488f4SHauke Mehrtens 290ea3488f4SHauke Mehrtens if (cc->core->id.rev < 20) 291ea3488f4SHauke Mehrtens return 0; 292ea3488f4SHauke Mehrtens 293ea3488f4SHauke Mehrtens spin_lock_irqsave(&cc->gpio_lock, flags); 294ea3488f4SHauke Mehrtens res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); 295ea3488f4SHauke Mehrtens spin_unlock_irqrestore(&cc->gpio_lock, flags); 296ea3488f4SHauke Mehrtens 297ea3488f4SHauke Mehrtens return res; 2988369ae33SRafał Miłecki } 299e3afe0e5SHauke Mehrtens 300e3afe0e5SHauke Mehrtens #ifdef CONFIG_BCMA_DRIVER_MIPS 301e3afe0e5SHauke Mehrtens void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 302e3afe0e5SHauke Mehrtens { 303e3afe0e5SHauke Mehrtens unsigned int irq; 304e3afe0e5SHauke Mehrtens u32 baud_base; 305e3afe0e5SHauke Mehrtens u32 i; 306e3afe0e5SHauke Mehrtens unsigned int ccrev = cc->core->id.rev; 307e3afe0e5SHauke Mehrtens struct bcma_serial_port *ports = cc->serial_ports; 308e3afe0e5SHauke Mehrtens 309e3afe0e5SHauke Mehrtens if (ccrev >= 11 && ccrev != 15) { 3105b5ac414SRafał Miłecki baud_base = bcma_chipco_get_alp_clock(cc); 311e3afe0e5SHauke Mehrtens if (ccrev >= 21) { 312e3afe0e5SHauke Mehrtens /* Turn off UART clock before switching clocksource. */ 313e3afe0e5SHauke Mehrtens bcma_cc_write32(cc, BCMA_CC_CORECTL, 314e3afe0e5SHauke Mehrtens bcma_cc_read32(cc, BCMA_CC_CORECTL) 315e3afe0e5SHauke Mehrtens & ~BCMA_CC_CORECTL_UARTCLKEN); 316e3afe0e5SHauke Mehrtens } 317e3afe0e5SHauke Mehrtens /* Set the override bit so we don't divide it */ 318e3afe0e5SHauke Mehrtens bcma_cc_write32(cc, BCMA_CC_CORECTL, 319e3afe0e5SHauke Mehrtens bcma_cc_read32(cc, BCMA_CC_CORECTL) 320e3afe0e5SHauke Mehrtens | BCMA_CC_CORECTL_UARTCLK0); 321e3afe0e5SHauke Mehrtens if (ccrev >= 21) { 322e3afe0e5SHauke Mehrtens /* Re-enable the UART clock. */ 323e3afe0e5SHauke Mehrtens bcma_cc_write32(cc, BCMA_CC_CORECTL, 324e3afe0e5SHauke Mehrtens bcma_cc_read32(cc, BCMA_CC_CORECTL) 325e3afe0e5SHauke Mehrtens | BCMA_CC_CORECTL_UARTCLKEN); 326e3afe0e5SHauke Mehrtens } 327e3afe0e5SHauke Mehrtens } else { 3289a89c3a8SRafał Miłecki bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev); 329e3afe0e5SHauke Mehrtens return; 330e3afe0e5SHauke Mehrtens } 331e3afe0e5SHauke Mehrtens 332e2aa19faSNathan Hintz irq = bcma_core_irq(cc->core); 333e3afe0e5SHauke Mehrtens 334e3afe0e5SHauke Mehrtens /* Determine the registers of the UARTs */ 335e3afe0e5SHauke Mehrtens cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 336e3afe0e5SHauke Mehrtens for (i = 0; i < cc->nr_serial_ports; i++) { 337e3afe0e5SHauke Mehrtens ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 338e3afe0e5SHauke Mehrtens (i * 256); 339e3afe0e5SHauke Mehrtens ports[i].irq = irq; 340e3afe0e5SHauke Mehrtens ports[i].baud_base = baud_base; 341e3afe0e5SHauke Mehrtens ports[i].reg_shift = 0; 342e3afe0e5SHauke Mehrtens } 343e3afe0e5SHauke Mehrtens } 344e3afe0e5SHauke Mehrtens #endif /* CONFIG_BCMA_DRIVER_MIPS */ 345