17f9fb673SXu Yilun // SPDX-License-Identifier: GPL-2.0
27f9fb673SXu Yilun //
37f9fb673SXu Yilun // Register map access API - SPI AVMM support
47f9fb673SXu Yilun //
57f9fb673SXu Yilun // Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
67f9fb673SXu Yilun
77f9fb673SXu Yilun #include <linux/module.h>
87f9fb673SXu Yilun #include <linux/regmap.h>
97f9fb673SXu Yilun #include <linux/spi/spi.h>
1026cc2a78SAndy Shevchenko #include <linux/swab.h>
117f9fb673SXu Yilun
127f9fb673SXu Yilun /*
137f9fb673SXu Yilun * This driver implements the regmap operations for a generic SPI
147f9fb673SXu Yilun * master to access the registers of the spi slave chip which has an
157f9fb673SXu Yilun * Avalone bus in it.
167f9fb673SXu Yilun *
177f9fb673SXu Yilun * The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated
187f9fb673SXu Yilun * in the spi slave chip. The IP acts as a bridge to convert encoded streams of
197f9fb673SXu Yilun * bytes from the host to the internal register read/write on Avalon bus. In
207f9fb673SXu Yilun * order to issue register access requests to the slave chip, the host should
217f9fb673SXu Yilun * send formatted bytes that conform to the transfer protocol.
227f9fb673SXu Yilun * The transfer protocol contains 3 layers: transaction layer, packet layer
237f9fb673SXu Yilun * and physical layer.
247f9fb673SXu Yilun *
257f9fb673SXu Yilun * Reference Documents could be found at:
267f9fb673SXu Yilun * https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html
277f9fb673SXu Yilun *
287f9fb673SXu Yilun * Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general
297f9fb673SXu Yilun * introduction to the protocol.
307f9fb673SXu Yilun *
317f9fb673SXu Yilun * Chapter "Avalon Packets to Transactions Converter Core" describes
327f9fb673SXu Yilun * the transaction layer.
337f9fb673SXu Yilun *
347f9fb673SXu Yilun * Chapter "Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores"
357f9fb673SXu Yilun * describes the packet layer.
367f9fb673SXu Yilun *
377f9fb673SXu Yilun * Chapter "Avalon-ST Serial Peripheral Interface Core" describes the
387f9fb673SXu Yilun * physical layer.
397f9fb673SXu Yilun *
407f9fb673SXu Yilun *
417f9fb673SXu Yilun * When host issues a regmap read/write, the driver will transform the request
427f9fb673SXu Yilun * to byte stream layer by layer. It formats the register addr, value and
437f9fb673SXu Yilun * length to the transaction layer request, then converts the request to packet
447f9fb673SXu Yilun * layer bytes stream and then to physical layer bytes stream. Finally the
457f9fb673SXu Yilun * driver sends the formatted byte stream over SPI bus to the slave chip.
467f9fb673SXu Yilun *
477f9fb673SXu Yilun * The spi-avmm IP on the slave chip decodes the byte stream and initiates
487f9fb673SXu Yilun * register read/write on its internal Avalon bus, and then encodes the
497f9fb673SXu Yilun * response to byte stream and sends back to host.
507f9fb673SXu Yilun *
517f9fb673SXu Yilun * The driver receives the byte stream, reverses the 3 layers transformation,
527f9fb673SXu Yilun * and finally gets the response value (read out data for register read,
537f9fb673SXu Yilun * successful written size for register write).
547f9fb673SXu Yilun */
557f9fb673SXu Yilun
567f9fb673SXu Yilun #define PKT_SOP 0x7a
577f9fb673SXu Yilun #define PKT_EOP 0x7b
587f9fb673SXu Yilun #define PKT_CHANNEL 0x7c
597f9fb673SXu Yilun #define PKT_ESC 0x7d
607f9fb673SXu Yilun
617f9fb673SXu Yilun #define PHY_IDLE 0x4a
627f9fb673SXu Yilun #define PHY_ESC 0x4d
637f9fb673SXu Yilun
647f9fb673SXu Yilun #define TRANS_CODE_WRITE 0x0
657f9fb673SXu Yilun #define TRANS_CODE_SEQ_WRITE 0x4
667f9fb673SXu Yilun #define TRANS_CODE_READ 0x10
677f9fb673SXu Yilun #define TRANS_CODE_SEQ_READ 0x14
687f9fb673SXu Yilun #define TRANS_CODE_NO_TRANS 0x7f
697f9fb673SXu Yilun
707f9fb673SXu Yilun #define SPI_AVMM_XFER_TIMEOUT (msecs_to_jiffies(200))
717f9fb673SXu Yilun
727f9fb673SXu Yilun /* slave's register addr is 32 bits */
737f9fb673SXu Yilun #define SPI_AVMM_REG_SIZE 4UL
747f9fb673SXu Yilun /* slave's register value is 32 bits */
757f9fb673SXu Yilun #define SPI_AVMM_VAL_SIZE 4UL
767f9fb673SXu Yilun
777f9fb673SXu Yilun /*
787f9fb673SXu Yilun * max rx size could be larger. But considering the buffer consuming,
797f9fb673SXu Yilun * it is proper that we limit 1KB xfer at max.
807f9fb673SXu Yilun */
817f9fb673SXu Yilun #define MAX_READ_CNT 256UL
827f9fb673SXu Yilun #define MAX_WRITE_CNT 1UL
837f9fb673SXu Yilun
847f9fb673SXu Yilun struct trans_req_header {
857f9fb673SXu Yilun u8 code;
867f9fb673SXu Yilun u8 rsvd;
877f9fb673SXu Yilun __be16 size;
887f9fb673SXu Yilun __be32 addr;
897f9fb673SXu Yilun } __packed;
907f9fb673SXu Yilun
917f9fb673SXu Yilun struct trans_resp_header {
927f9fb673SXu Yilun u8 r_code;
937f9fb673SXu Yilun u8 rsvd;
947f9fb673SXu Yilun __be16 size;
957f9fb673SXu Yilun } __packed;
967f9fb673SXu Yilun
977f9fb673SXu Yilun #define TRANS_REQ_HD_SIZE (sizeof(struct trans_req_header))
987f9fb673SXu Yilun #define TRANS_RESP_HD_SIZE (sizeof(struct trans_resp_header))
997f9fb673SXu Yilun
1007f9fb673SXu Yilun /*
1017f9fb673SXu Yilun * In transaction layer,
1027f9fb673SXu Yilun * the write request format is: Transaction request header + data
1037f9fb673SXu Yilun * the read request format is: Transaction request header
1047f9fb673SXu Yilun * the write response format is: Transaction response header
1057f9fb673SXu Yilun * the read response format is: pure data, no Transaction response header
1067f9fb673SXu Yilun */
1077f9fb673SXu Yilun #define TRANS_WR_TX_SIZE(n) (TRANS_REQ_HD_SIZE + SPI_AVMM_VAL_SIZE * (n))
1087f9fb673SXu Yilun #define TRANS_RD_TX_SIZE TRANS_REQ_HD_SIZE
1097f9fb673SXu Yilun #define TRANS_TX_MAX TRANS_WR_TX_SIZE(MAX_WRITE_CNT)
1107f9fb673SXu Yilun
1117f9fb673SXu Yilun #define TRANS_RD_RX_SIZE(n) (SPI_AVMM_VAL_SIZE * (n))
1127f9fb673SXu Yilun #define TRANS_WR_RX_SIZE TRANS_RESP_HD_SIZE
1137f9fb673SXu Yilun #define TRANS_RX_MAX TRANS_RD_RX_SIZE(MAX_READ_CNT)
1147f9fb673SXu Yilun
1157f9fb673SXu Yilun /* tx & rx share one transaction layer buffer */
1167f9fb673SXu Yilun #define TRANS_BUF_SIZE ((TRANS_TX_MAX > TRANS_RX_MAX) ? \
1177f9fb673SXu Yilun TRANS_TX_MAX : TRANS_RX_MAX)
1187f9fb673SXu Yilun
1197f9fb673SXu Yilun /*
1207f9fb673SXu Yilun * In tx phase, the host prepares all the phy layer bytes of a request in the
1217f9fb673SXu Yilun * phy buffer and sends them in a batch.
1227f9fb673SXu Yilun *
1237f9fb673SXu Yilun * The packet layer and physical layer defines several special chars for
1247f9fb673SXu Yilun * various purpose, when a transaction layer byte hits one of these special
1257f9fb673SXu Yilun * chars, it should be escaped. The escape rule is, "Escape char first,
1267f9fb673SXu Yilun * following the byte XOR'ed with 0x20".
1277f9fb673SXu Yilun *
1287f9fb673SXu Yilun * This macro defines the max possible length of the phy data. In the worst
1297f9fb673SXu Yilun * case, all transaction layer bytes need to be escaped (so the data length
1307f9fb673SXu Yilun * doubles), plus 4 special chars (SOP, CHANNEL, CHANNEL_NUM, EOP). Finally
1317f9fb673SXu Yilun * we should make sure the length is aligned to SPI BPW.
1327f9fb673SXu Yilun */
1337f9fb673SXu Yilun #define PHY_TX_MAX ALIGN(2 * TRANS_TX_MAX + 4, 4)
1347f9fb673SXu Yilun
1357f9fb673SXu Yilun /*
1367f9fb673SXu Yilun * Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max
1377f9fb673SXu Yilun * length of the rx bit stream is unpredictable. So the driver reads the words
1387f9fb673SXu Yilun * one by one, and parses each word immediately into transaction layer buffer.
1397f9fb673SXu Yilun * Only one word length of phy buffer is used for rx.
1407f9fb673SXu Yilun */
1417f9fb673SXu Yilun #define PHY_BUF_SIZE PHY_TX_MAX
1427f9fb673SXu Yilun
1437f9fb673SXu Yilun /**
1447f9fb673SXu Yilun * struct spi_avmm_bridge - SPI slave to AVMM bus master bridge
1457f9fb673SXu Yilun *
1467f9fb673SXu Yilun * @spi: spi slave associated with this bridge.
1477f9fb673SXu Yilun * @word_len: bytes of word for spi transfer.
1487f9fb673SXu Yilun * @trans_len: length of valid data in trans_buf.
1497f9fb673SXu Yilun * @phy_len: length of valid data in phy_buf.
1507f9fb673SXu Yilun * @trans_buf: the bridge buffer for transaction layer data.
1517f9fb673SXu Yilun * @phy_buf: the bridge buffer for physical layer data.
1527f9fb673SXu Yilun * @swap_words: the word swapping cb for phy data. NULL if not needed.
1537f9fb673SXu Yilun *
1547f9fb673SXu Yilun * As a device's registers are implemented on the AVMM bus address space, it
1557f9fb673SXu Yilun * requires the driver to issue formatted requests to spi slave to AVMM bus
1567f9fb673SXu Yilun * master bridge to perform register access.
1577f9fb673SXu Yilun */
1587f9fb673SXu Yilun struct spi_avmm_bridge {
1597f9fb673SXu Yilun struct spi_device *spi;
1607f9fb673SXu Yilun unsigned char word_len;
1617f9fb673SXu Yilun unsigned int trans_len;
1627f9fb673SXu Yilun unsigned int phy_len;
1637f9fb673SXu Yilun /* bridge buffer used in translation between protocol layers */
1647f9fb673SXu Yilun char trans_buf[TRANS_BUF_SIZE];
1657f9fb673SXu Yilun char phy_buf[PHY_BUF_SIZE];
16626cc2a78SAndy Shevchenko void (*swap_words)(void *buf, unsigned int len);
1677f9fb673SXu Yilun };
1687f9fb673SXu Yilun
br_swap_words_32(void * buf,unsigned int len)16926cc2a78SAndy Shevchenko static void br_swap_words_32(void *buf, unsigned int len)
1707f9fb673SXu Yilun {
17126cc2a78SAndy Shevchenko swab32_array(buf, len / 4);
1727f9fb673SXu Yilun }
1737f9fb673SXu Yilun
1747f9fb673SXu Yilun /*
1757f9fb673SXu Yilun * Format transaction layer data in br->trans_buf according to the register
1767f9fb673SXu Yilun * access request, Store valid transaction layer data length in br->trans_len.
1777f9fb673SXu Yilun */
br_trans_tx_prepare(struct spi_avmm_bridge * br,bool is_read,u32 reg,u32 * wr_val,u32 count)1787f9fb673SXu Yilun static int br_trans_tx_prepare(struct spi_avmm_bridge *br, bool is_read, u32 reg,
1797f9fb673SXu Yilun u32 *wr_val, u32 count)
1807f9fb673SXu Yilun {
1817f9fb673SXu Yilun struct trans_req_header *header;
1827f9fb673SXu Yilun unsigned int trans_len;
1837f9fb673SXu Yilun u8 code;
1847f9fb673SXu Yilun __le32 *data;
1857f9fb673SXu Yilun int i;
1867f9fb673SXu Yilun
1877f9fb673SXu Yilun if (is_read) {
1887f9fb673SXu Yilun if (count == 1)
1897f9fb673SXu Yilun code = TRANS_CODE_READ;
1907f9fb673SXu Yilun else
1917f9fb673SXu Yilun code = TRANS_CODE_SEQ_READ;
1927f9fb673SXu Yilun } else {
1937f9fb673SXu Yilun if (count == 1)
1947f9fb673SXu Yilun code = TRANS_CODE_WRITE;
1957f9fb673SXu Yilun else
1967f9fb673SXu Yilun code = TRANS_CODE_SEQ_WRITE;
1977f9fb673SXu Yilun }
1987f9fb673SXu Yilun
1997f9fb673SXu Yilun header = (struct trans_req_header *)br->trans_buf;
2007f9fb673SXu Yilun header->code = code;
2017f9fb673SXu Yilun header->rsvd = 0;
2027f9fb673SXu Yilun header->size = cpu_to_be16((u16)count * SPI_AVMM_VAL_SIZE);
2037f9fb673SXu Yilun header->addr = cpu_to_be32(reg);
2047f9fb673SXu Yilun
2057f9fb673SXu Yilun trans_len = TRANS_REQ_HD_SIZE;
2067f9fb673SXu Yilun
2077f9fb673SXu Yilun if (!is_read) {
2087f9fb673SXu Yilun trans_len += SPI_AVMM_VAL_SIZE * count;
2097f9fb673SXu Yilun if (trans_len > sizeof(br->trans_buf))
2107f9fb673SXu Yilun return -ENOMEM;
2117f9fb673SXu Yilun
2127f9fb673SXu Yilun data = (__le32 *)(br->trans_buf + TRANS_REQ_HD_SIZE);
2137f9fb673SXu Yilun
2147f9fb673SXu Yilun for (i = 0; i < count; i++)
2157f9fb673SXu Yilun *data++ = cpu_to_le32(*wr_val++);
2167f9fb673SXu Yilun }
2177f9fb673SXu Yilun
2187f9fb673SXu Yilun /* Store valid trans data length for next layer */
2197f9fb673SXu Yilun br->trans_len = trans_len;
2207f9fb673SXu Yilun
2217f9fb673SXu Yilun return 0;
2227f9fb673SXu Yilun }
2237f9fb673SXu Yilun
2247f9fb673SXu Yilun /*
2257f9fb673SXu Yilun * Convert transaction layer data (in br->trans_buf) to phy layer data, store
2267f9fb673SXu Yilun * them in br->phy_buf. Pad the phy_buf aligned with SPI's BPW. Store valid phy
2277f9fb673SXu Yilun * layer data length in br->phy_len.
2287f9fb673SXu Yilun *
2297f9fb673SXu Yilun * phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded
2307f9fb673SXu Yilun * with PHY_IDLE, then the slave will just drop them.
2317f9fb673SXu Yilun *
2327f9fb673SXu Yilun * The driver will not simply pad 4a at the tail. The concern is that driver
2337f9fb673SXu Yilun * will not store MISO data during tx phase, if the driver pads 4a at the tail,
2347f9fb673SXu Yilun * it is possible that if the slave is fast enough to response at the padding
2357f9fb673SXu Yilun * time. As a result these rx bytes are lost. In the following case, 7a,7c,00
2367f9fb673SXu Yilun * will lost.
2377f9fb673SXu Yilun * MOSI ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|4a|4a|4a| |XX|XX|...
2387f9fb673SXu Yilun * MISO ...|4a|4a|4a|4a| |4a|4a|4a|4a| |4a|4a|4a|4a| |4a|7a|7c|00| |78|56|...
2397f9fb673SXu Yilun *
2407f9fb673SXu Yilun * So the driver moves EOP and bytes after EOP to the end of the aligned size,
2417f9fb673SXu Yilun * then fill the hole with PHY_IDLE. As following:
2427f9fb673SXu Yilun * before pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|
2437f9fb673SXu Yilun * after pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|4a| |4a|4a|7b|40|
2447f9fb673SXu Yilun * Then if the slave will not get the entire packet before the tx phase is
2457f9fb673SXu Yilun * over, it can't responsed to anything either.
2467f9fb673SXu Yilun */
br_pkt_phy_tx_prepare(struct spi_avmm_bridge * br)2477f9fb673SXu Yilun static int br_pkt_phy_tx_prepare(struct spi_avmm_bridge *br)
2487f9fb673SXu Yilun {
2497f9fb673SXu Yilun char *tb, *tb_end, *pb, *pb_limit, *pb_eop = NULL;
2507f9fb673SXu Yilun unsigned int aligned_phy_len, move_size;
2517f9fb673SXu Yilun bool need_esc = false;
2527f9fb673SXu Yilun
2537f9fb673SXu Yilun tb = br->trans_buf;
2547f9fb673SXu Yilun tb_end = tb + br->trans_len;
2557f9fb673SXu Yilun pb = br->phy_buf;
2567f9fb673SXu Yilun pb_limit = pb + ARRAY_SIZE(br->phy_buf);
2577f9fb673SXu Yilun
2587f9fb673SXu Yilun *pb++ = PKT_SOP;
2597f9fb673SXu Yilun
2607f9fb673SXu Yilun /*
2617f9fb673SXu Yilun * The driver doesn't support multiple channels so the channel number
2627f9fb673SXu Yilun * is always 0.
2637f9fb673SXu Yilun */
2647f9fb673SXu Yilun *pb++ = PKT_CHANNEL;
2657f9fb673SXu Yilun *pb++ = 0x0;
2667f9fb673SXu Yilun
2677f9fb673SXu Yilun for (; pb < pb_limit && tb < tb_end; pb++) {
2687f9fb673SXu Yilun if (need_esc) {
2697f9fb673SXu Yilun *pb = *tb++ ^ 0x20;
2707f9fb673SXu Yilun need_esc = false;
2717f9fb673SXu Yilun continue;
2727f9fb673SXu Yilun }
2737f9fb673SXu Yilun
2747f9fb673SXu Yilun /* EOP should be inserted before the last valid char */
2757f9fb673SXu Yilun if (tb == tb_end - 1 && !pb_eop) {
2767f9fb673SXu Yilun *pb = PKT_EOP;
2777f9fb673SXu Yilun pb_eop = pb;
2787f9fb673SXu Yilun continue;
2797f9fb673SXu Yilun }
2807f9fb673SXu Yilun
2817f9fb673SXu Yilun /*
2827f9fb673SXu Yilun * insert an ESCAPE char if the data value equals any special
2837f9fb673SXu Yilun * char.
2847f9fb673SXu Yilun */
2857f9fb673SXu Yilun switch (*tb) {
2867f9fb673SXu Yilun case PKT_SOP:
2877f9fb673SXu Yilun case PKT_EOP:
2887f9fb673SXu Yilun case PKT_CHANNEL:
2897f9fb673SXu Yilun case PKT_ESC:
2907f9fb673SXu Yilun *pb = PKT_ESC;
2917f9fb673SXu Yilun need_esc = true;
2927f9fb673SXu Yilun break;
2937f9fb673SXu Yilun case PHY_IDLE:
2947f9fb673SXu Yilun case PHY_ESC:
2957f9fb673SXu Yilun *pb = PHY_ESC;
2967f9fb673SXu Yilun need_esc = true;
2977f9fb673SXu Yilun break;
2987f9fb673SXu Yilun default:
2997f9fb673SXu Yilun *pb = *tb++;
3007f9fb673SXu Yilun break;
3017f9fb673SXu Yilun }
3027f9fb673SXu Yilun }
3037f9fb673SXu Yilun
3047f9fb673SXu Yilun /* The phy buffer is used out but transaction layer data remains */
3057f9fb673SXu Yilun if (tb < tb_end)
3067f9fb673SXu Yilun return -ENOMEM;
3077f9fb673SXu Yilun
3087f9fb673SXu Yilun /* Store valid phy data length for spi transfer */
3097f9fb673SXu Yilun br->phy_len = pb - br->phy_buf;
3107f9fb673SXu Yilun
3117f9fb673SXu Yilun if (br->word_len == 1)
3127f9fb673SXu Yilun return 0;
3137f9fb673SXu Yilun
3147f9fb673SXu Yilun /* Do phy buf padding if word_len > 1 byte. */
3157f9fb673SXu Yilun aligned_phy_len = ALIGN(br->phy_len, br->word_len);
3167f9fb673SXu Yilun if (aligned_phy_len > sizeof(br->phy_buf))
3177f9fb673SXu Yilun return -ENOMEM;
3187f9fb673SXu Yilun
3197f9fb673SXu Yilun if (aligned_phy_len == br->phy_len)
3207f9fb673SXu Yilun return 0;
3217f9fb673SXu Yilun
3227f9fb673SXu Yilun /* move EOP and bytes after EOP to the end of aligned size */
3237f9fb673SXu Yilun move_size = pb - pb_eop;
3247f9fb673SXu Yilun memmove(&br->phy_buf[aligned_phy_len - move_size], pb_eop, move_size);
3257f9fb673SXu Yilun
3267f9fb673SXu Yilun /* fill the hole with PHY_IDLEs */
3277f9fb673SXu Yilun memset(pb_eop, PHY_IDLE, aligned_phy_len - br->phy_len);
3287f9fb673SXu Yilun
3297f9fb673SXu Yilun /* update the phy data length */
3307f9fb673SXu Yilun br->phy_len = aligned_phy_len;
3317f9fb673SXu Yilun
3327f9fb673SXu Yilun return 0;
3337f9fb673SXu Yilun }
3347f9fb673SXu Yilun
3357f9fb673SXu Yilun /*
3367f9fb673SXu Yilun * In tx phase, the slave only returns PHY_IDLE (0x4a). So the driver will
3377f9fb673SXu Yilun * ignore rx in tx phase.
3387f9fb673SXu Yilun */
br_do_tx(struct spi_avmm_bridge * br)3397f9fb673SXu Yilun static int br_do_tx(struct spi_avmm_bridge *br)
3407f9fb673SXu Yilun {
3417f9fb673SXu Yilun /* reorder words for spi transfer */
3427f9fb673SXu Yilun if (br->swap_words)
3437f9fb673SXu Yilun br->swap_words(br->phy_buf, br->phy_len);
3447f9fb673SXu Yilun
3457f9fb673SXu Yilun /* send all data in phy_buf */
3467f9fb673SXu Yilun return spi_write(br->spi, br->phy_buf, br->phy_len);
3477f9fb673SXu Yilun }
3487f9fb673SXu Yilun
3497f9fb673SXu Yilun /*
3507f9fb673SXu Yilun * This function read the rx byte stream from SPI word by word and convert
3517f9fb673SXu Yilun * them to transaction layer data in br->trans_buf. It also stores the length
3527f9fb673SXu Yilun * of rx transaction layer data in br->trans_len
3537f9fb673SXu Yilun *
3547f9fb673SXu Yilun * The slave may send an unknown number of PHY_IDLEs in rx phase, so we cannot
3557f9fb673SXu Yilun * prepare a fixed length buffer to receive all of the rx data in a batch. We
3567f9fb673SXu Yilun * have to read word by word and convert them to transaction layer data at
3577f9fb673SXu Yilun * once.
3587f9fb673SXu Yilun */
br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge * br)3597f9fb673SXu Yilun static int br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge *br)
3607f9fb673SXu Yilun {
3617f9fb673SXu Yilun bool eop_found = false, channel_found = false, esc_found = false;
3627f9fb673SXu Yilun bool valid_word = false, last_try = false;
3637f9fb673SXu Yilun struct device *dev = &br->spi->dev;
3647f9fb673SXu Yilun char *pb, *tb_limit, *tb = NULL;
3657f9fb673SXu Yilun unsigned long poll_timeout;
3667f9fb673SXu Yilun int ret, i;
3677f9fb673SXu Yilun
3687f9fb673SXu Yilun tb_limit = br->trans_buf + ARRAY_SIZE(br->trans_buf);
3697f9fb673SXu Yilun pb = br->phy_buf;
3707f9fb673SXu Yilun poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
3717f9fb673SXu Yilun while (tb < tb_limit) {
3727f9fb673SXu Yilun ret = spi_read(br->spi, pb, br->word_len);
3737f9fb673SXu Yilun if (ret)
3747f9fb673SXu Yilun return ret;
3757f9fb673SXu Yilun
3767f9fb673SXu Yilun /* reorder the word back */
3777f9fb673SXu Yilun if (br->swap_words)
3787f9fb673SXu Yilun br->swap_words(pb, br->word_len);
3797f9fb673SXu Yilun
3807f9fb673SXu Yilun valid_word = false;
3817f9fb673SXu Yilun for (i = 0; i < br->word_len; i++) {
3827f9fb673SXu Yilun /* drop everything before first SOP */
3837f9fb673SXu Yilun if (!tb && pb[i] != PKT_SOP)
3847f9fb673SXu Yilun continue;
3857f9fb673SXu Yilun
3867f9fb673SXu Yilun /* drop PHY_IDLE */
3877f9fb673SXu Yilun if (pb[i] == PHY_IDLE)
3887f9fb673SXu Yilun continue;
3897f9fb673SXu Yilun
3907f9fb673SXu Yilun valid_word = true;
3917f9fb673SXu Yilun
3927f9fb673SXu Yilun /*
3937f9fb673SXu Yilun * We don't support multiple channels, so error out if
3947f9fb673SXu Yilun * a non-zero channel number is found.
3957f9fb673SXu Yilun */
3967f9fb673SXu Yilun if (channel_found) {
3977f9fb673SXu Yilun if (pb[i] != 0) {
3987f9fb673SXu Yilun dev_err(dev, "%s channel num != 0\n",
3997f9fb673SXu Yilun __func__);
4007f9fb673SXu Yilun return -EFAULT;
4017f9fb673SXu Yilun }
4027f9fb673SXu Yilun
4037f9fb673SXu Yilun channel_found = false;
4047f9fb673SXu Yilun continue;
4057f9fb673SXu Yilun }
4067f9fb673SXu Yilun
4077f9fb673SXu Yilun switch (pb[i]) {
4087f9fb673SXu Yilun case PKT_SOP:
4097f9fb673SXu Yilun /*
4107f9fb673SXu Yilun * reset the parsing if a second SOP appears.
4117f9fb673SXu Yilun */
4127f9fb673SXu Yilun tb = br->trans_buf;
4137f9fb673SXu Yilun eop_found = false;
4147f9fb673SXu Yilun channel_found = false;
4157f9fb673SXu Yilun esc_found = false;
4167f9fb673SXu Yilun break;
4177f9fb673SXu Yilun case PKT_EOP:
4187f9fb673SXu Yilun /*
4197f9fb673SXu Yilun * No special char is expected after ESC char.
4207f9fb673SXu Yilun * No special char (except ESC & PHY_IDLE) is
4217f9fb673SXu Yilun * expected after EOP char.
4227f9fb673SXu Yilun *
4237f9fb673SXu Yilun * The special chars are all dropped.
4247f9fb673SXu Yilun */
4257f9fb673SXu Yilun if (esc_found || eop_found)
4267f9fb673SXu Yilun return -EFAULT;
4277f9fb673SXu Yilun
4287f9fb673SXu Yilun eop_found = true;
4297f9fb673SXu Yilun break;
4307f9fb673SXu Yilun case PKT_CHANNEL:
4317f9fb673SXu Yilun if (esc_found || eop_found)
4327f9fb673SXu Yilun return -EFAULT;
4337f9fb673SXu Yilun
4347f9fb673SXu Yilun channel_found = true;
4357f9fb673SXu Yilun break;
4367f9fb673SXu Yilun case PKT_ESC:
4377f9fb673SXu Yilun case PHY_ESC:
4387f9fb673SXu Yilun if (esc_found)
4397f9fb673SXu Yilun return -EFAULT;
4407f9fb673SXu Yilun
4417f9fb673SXu Yilun esc_found = true;
4427f9fb673SXu Yilun break;
4437f9fb673SXu Yilun default:
4447f9fb673SXu Yilun /* Record the normal byte in trans_buf. */
4457f9fb673SXu Yilun if (esc_found) {
4467f9fb673SXu Yilun *tb++ = pb[i] ^ 0x20;
4477f9fb673SXu Yilun esc_found = false;
4487f9fb673SXu Yilun } else {
4497f9fb673SXu Yilun *tb++ = pb[i];
4507f9fb673SXu Yilun }
4517f9fb673SXu Yilun
4527f9fb673SXu Yilun /*
4537f9fb673SXu Yilun * We get the last normal byte after EOP, it is
4547f9fb673SXu Yilun * time we finish. Normally the function should
4557f9fb673SXu Yilun * return here.
4567f9fb673SXu Yilun */
4577f9fb673SXu Yilun if (eop_found) {
4587f9fb673SXu Yilun br->trans_len = tb - br->trans_buf;
4597f9fb673SXu Yilun return 0;
4607f9fb673SXu Yilun }
4617f9fb673SXu Yilun }
4627f9fb673SXu Yilun }
4637f9fb673SXu Yilun
4647f9fb673SXu Yilun if (valid_word) {
4657f9fb673SXu Yilun /* update poll timeout when we get valid word */
4667f9fb673SXu Yilun poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
4677f9fb673SXu Yilun last_try = false;
4687f9fb673SXu Yilun } else {
4697f9fb673SXu Yilun /*
4707f9fb673SXu Yilun * We timeout when rx keeps invalid for some time. But
4717f9fb673SXu Yilun * it is possible we are scheduled out for long time
4727f9fb673SXu Yilun * after a spi_read. So when we are scheduled in, a SW
4737f9fb673SXu Yilun * timeout happens. But actually HW may have worked fine and
4747f9fb673SXu Yilun * has been ready long time ago. So we need to do an extra
4757f9fb673SXu Yilun * read, if we get a valid word then we could continue rx,
4767f9fb673SXu Yilun * otherwise real a HW issue happens.
4777f9fb673SXu Yilun */
4787f9fb673SXu Yilun if (last_try)
4797f9fb673SXu Yilun return -ETIMEDOUT;
4807f9fb673SXu Yilun
4817f9fb673SXu Yilun if (time_after(jiffies, poll_timeout))
4827f9fb673SXu Yilun last_try = true;
4837f9fb673SXu Yilun }
4847f9fb673SXu Yilun }
4857f9fb673SXu Yilun
4867f9fb673SXu Yilun /*
4877f9fb673SXu Yilun * We have used out all transfer layer buffer but cannot find the end
4887f9fb673SXu Yilun * of the byte stream.
4897f9fb673SXu Yilun */
4907f9fb673SXu Yilun dev_err(dev, "%s transfer buffer is full but rx doesn't end\n",
4917f9fb673SXu Yilun __func__);
4927f9fb673SXu Yilun
4937f9fb673SXu Yilun return -EFAULT;
4947f9fb673SXu Yilun }
4957f9fb673SXu Yilun
4967f9fb673SXu Yilun /*
4977f9fb673SXu Yilun * For read transactions, the avmm bus will directly return register values
4987f9fb673SXu Yilun * without transaction response header.
4997f9fb673SXu Yilun */
br_rd_trans_rx_parse(struct spi_avmm_bridge * br,u32 * val,unsigned int expected_count)5007f9fb673SXu Yilun static int br_rd_trans_rx_parse(struct spi_avmm_bridge *br,
5017f9fb673SXu Yilun u32 *val, unsigned int expected_count)
5027f9fb673SXu Yilun {
5037f9fb673SXu Yilun unsigned int i, trans_len = br->trans_len;
5047f9fb673SXu Yilun __le32 *data;
5057f9fb673SXu Yilun
5067f9fb673SXu Yilun if (expected_count * SPI_AVMM_VAL_SIZE != trans_len)
5077f9fb673SXu Yilun return -EFAULT;
5087f9fb673SXu Yilun
5097f9fb673SXu Yilun data = (__le32 *)br->trans_buf;
5107f9fb673SXu Yilun for (i = 0; i < expected_count; i++)
5117f9fb673SXu Yilun *val++ = le32_to_cpu(*data++);
5127f9fb673SXu Yilun
5137f9fb673SXu Yilun return 0;
5147f9fb673SXu Yilun }
5157f9fb673SXu Yilun
5167f9fb673SXu Yilun /*
5177f9fb673SXu Yilun * For write transactions, the slave will return a transaction response
5187f9fb673SXu Yilun * header.
5197f9fb673SXu Yilun */
br_wr_trans_rx_parse(struct spi_avmm_bridge * br,unsigned int expected_count)5207f9fb673SXu Yilun static int br_wr_trans_rx_parse(struct spi_avmm_bridge *br,
5217f9fb673SXu Yilun unsigned int expected_count)
5227f9fb673SXu Yilun {
5237f9fb673SXu Yilun unsigned int trans_len = br->trans_len;
5247f9fb673SXu Yilun struct trans_resp_header *resp;
5257f9fb673SXu Yilun u8 code;
5267f9fb673SXu Yilun u16 val_len;
5277f9fb673SXu Yilun
5287f9fb673SXu Yilun if (trans_len != TRANS_RESP_HD_SIZE)
5297f9fb673SXu Yilun return -EFAULT;
5307f9fb673SXu Yilun
5317f9fb673SXu Yilun resp = (struct trans_resp_header *)br->trans_buf;
5327f9fb673SXu Yilun
5337f9fb673SXu Yilun code = resp->r_code ^ 0x80;
5347f9fb673SXu Yilun val_len = be16_to_cpu(resp->size);
5357f9fb673SXu Yilun if (!val_len || val_len != expected_count * SPI_AVMM_VAL_SIZE)
5367f9fb673SXu Yilun return -EFAULT;
5377f9fb673SXu Yilun
5387f9fb673SXu Yilun /* error out if the trans code doesn't align with the val size */
5397f9fb673SXu Yilun if ((val_len == SPI_AVMM_VAL_SIZE && code != TRANS_CODE_WRITE) ||
5407f9fb673SXu Yilun (val_len > SPI_AVMM_VAL_SIZE && code != TRANS_CODE_SEQ_WRITE))
5417f9fb673SXu Yilun return -EFAULT;
5427f9fb673SXu Yilun
5437f9fb673SXu Yilun return 0;
5447f9fb673SXu Yilun }
5457f9fb673SXu Yilun
do_reg_access(void * context,bool is_read,unsigned int reg,unsigned int * value,unsigned int count)5467f9fb673SXu Yilun static int do_reg_access(void *context, bool is_read, unsigned int reg,
5477f9fb673SXu Yilun unsigned int *value, unsigned int count)
5487f9fb673SXu Yilun {
5497f9fb673SXu Yilun struct spi_avmm_bridge *br = context;
5507f9fb673SXu Yilun int ret;
5517f9fb673SXu Yilun
5527f9fb673SXu Yilun /* invalidate bridge buffers first */
5537f9fb673SXu Yilun br->trans_len = 0;
5547f9fb673SXu Yilun br->phy_len = 0;
5557f9fb673SXu Yilun
5567f9fb673SXu Yilun ret = br_trans_tx_prepare(br, is_read, reg, value, count);
5577f9fb673SXu Yilun if (ret)
5587f9fb673SXu Yilun return ret;
5597f9fb673SXu Yilun
5607f9fb673SXu Yilun ret = br_pkt_phy_tx_prepare(br);
5617f9fb673SXu Yilun if (ret)
5627f9fb673SXu Yilun return ret;
5637f9fb673SXu Yilun
5647f9fb673SXu Yilun ret = br_do_tx(br);
5657f9fb673SXu Yilun if (ret)
5667f9fb673SXu Yilun return ret;
5677f9fb673SXu Yilun
5687f9fb673SXu Yilun ret = br_do_rx_and_pkt_phy_parse(br);
5697f9fb673SXu Yilun if (ret)
5707f9fb673SXu Yilun return ret;
5717f9fb673SXu Yilun
5727f9fb673SXu Yilun if (is_read)
5737f9fb673SXu Yilun return br_rd_trans_rx_parse(br, value, count);
5747f9fb673SXu Yilun else
5757f9fb673SXu Yilun return br_wr_trans_rx_parse(br, count);
5767f9fb673SXu Yilun }
5777f9fb673SXu Yilun
regmap_spi_avmm_gather_write(void * context,const void * reg_buf,size_t reg_len,const void * val_buf,size_t val_len)5787f9fb673SXu Yilun static int regmap_spi_avmm_gather_write(void *context,
5797f9fb673SXu Yilun const void *reg_buf, size_t reg_len,
5807f9fb673SXu Yilun const void *val_buf, size_t val_len)
5817f9fb673SXu Yilun {
5827f9fb673SXu Yilun if (reg_len != SPI_AVMM_REG_SIZE)
5837f9fb673SXu Yilun return -EINVAL;
5847f9fb673SXu Yilun
5857f9fb673SXu Yilun if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE))
5867f9fb673SXu Yilun return -EINVAL;
5877f9fb673SXu Yilun
5887f9fb673SXu Yilun return do_reg_access(context, false, *(u32 *)reg_buf, (u32 *)val_buf,
5897f9fb673SXu Yilun val_len / SPI_AVMM_VAL_SIZE);
5907f9fb673SXu Yilun }
5917f9fb673SXu Yilun
regmap_spi_avmm_write(void * context,const void * data,size_t bytes)5927f9fb673SXu Yilun static int regmap_spi_avmm_write(void *context, const void *data, size_t bytes)
5937f9fb673SXu Yilun {
5947f9fb673SXu Yilun if (bytes < SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE)
5957f9fb673SXu Yilun return -EINVAL;
5967f9fb673SXu Yilun
5977f9fb673SXu Yilun return regmap_spi_avmm_gather_write(context, data, SPI_AVMM_REG_SIZE,
5987f9fb673SXu Yilun data + SPI_AVMM_REG_SIZE,
5997f9fb673SXu Yilun bytes - SPI_AVMM_REG_SIZE);
6007f9fb673SXu Yilun }
6017f9fb673SXu Yilun
regmap_spi_avmm_read(void * context,const void * reg_buf,size_t reg_len,void * val_buf,size_t val_len)6027f9fb673SXu Yilun static int regmap_spi_avmm_read(void *context,
6037f9fb673SXu Yilun const void *reg_buf, size_t reg_len,
6047f9fb673SXu Yilun void *val_buf, size_t val_len)
6057f9fb673SXu Yilun {
6067f9fb673SXu Yilun if (reg_len != SPI_AVMM_REG_SIZE)
6077f9fb673SXu Yilun return -EINVAL;
6087f9fb673SXu Yilun
6097f9fb673SXu Yilun if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE))
6107f9fb673SXu Yilun return -EINVAL;
6117f9fb673SXu Yilun
6127f9fb673SXu Yilun return do_reg_access(context, true, *(u32 *)reg_buf, val_buf,
6137f9fb673SXu Yilun (val_len / SPI_AVMM_VAL_SIZE));
6147f9fb673SXu Yilun }
6157f9fb673SXu Yilun
6167f9fb673SXu Yilun static struct spi_avmm_bridge *
spi_avmm_bridge_ctx_gen(struct spi_device * spi)6177f9fb673SXu Yilun spi_avmm_bridge_ctx_gen(struct spi_device *spi)
6187f9fb673SXu Yilun {
6197f9fb673SXu Yilun struct spi_avmm_bridge *br;
6207f9fb673SXu Yilun
6217f9fb673SXu Yilun if (!spi)
6227f9fb673SXu Yilun return ERR_PTR(-ENODEV);
6237f9fb673SXu Yilun
6247f9fb673SXu Yilun /* Only support BPW == 8 or 32 now. Try 32 BPW first. */
6257f9fb673SXu Yilun spi->mode = SPI_MODE_1;
6267f9fb673SXu Yilun spi->bits_per_word = 32;
6277f9fb673SXu Yilun if (spi_setup(spi)) {
6287f9fb673SXu Yilun spi->bits_per_word = 8;
6297f9fb673SXu Yilun if (spi_setup(spi))
6307f9fb673SXu Yilun return ERR_PTR(-EINVAL);
6317f9fb673SXu Yilun }
6327f9fb673SXu Yilun
6337f9fb673SXu Yilun br = kzalloc(sizeof(*br), GFP_KERNEL);
6347f9fb673SXu Yilun if (!br)
6357f9fb673SXu Yilun return ERR_PTR(-ENOMEM);
6367f9fb673SXu Yilun
6377f9fb673SXu Yilun br->spi = spi;
6387f9fb673SXu Yilun br->word_len = spi->bits_per_word / 8;
6397f9fb673SXu Yilun if (br->word_len == 4) {
6407f9fb673SXu Yilun /*
6417f9fb673SXu Yilun * The protocol requires little endian byte order but MSB
6427f9fb673SXu Yilun * first. So driver needs to swap the byte order word by word
6437f9fb673SXu Yilun * if word length > 1.
6447f9fb673SXu Yilun */
6457f9fb673SXu Yilun br->swap_words = br_swap_words_32;
6467f9fb673SXu Yilun }
6477f9fb673SXu Yilun
6487f9fb673SXu Yilun return br;
6497f9fb673SXu Yilun }
6507f9fb673SXu Yilun
spi_avmm_bridge_ctx_free(void * context)6517f9fb673SXu Yilun static void spi_avmm_bridge_ctx_free(void *context)
6527f9fb673SXu Yilun {
6537f9fb673SXu Yilun kfree(context);
6547f9fb673SXu Yilun }
6557f9fb673SXu Yilun
6567f9fb673SXu Yilun static const struct regmap_bus regmap_spi_avmm_bus = {
6577f9fb673SXu Yilun .write = regmap_spi_avmm_write,
6587f9fb673SXu Yilun .gather_write = regmap_spi_avmm_gather_write,
6597f9fb673SXu Yilun .read = regmap_spi_avmm_read,
6607f9fb673SXu Yilun .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
6617f9fb673SXu Yilun .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
6627f9fb673SXu Yilun .max_raw_read = SPI_AVMM_VAL_SIZE * MAX_READ_CNT,
663*bc647348SMark Brown .max_raw_write = SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT,
6647f9fb673SXu Yilun .free_context = spi_avmm_bridge_ctx_free,
6657f9fb673SXu Yilun };
6667f9fb673SXu Yilun
__regmap_init_spi_avmm(struct spi_device * spi,const struct regmap_config * config,struct lock_class_key * lock_key,const char * lock_name)6677f9fb673SXu Yilun struct regmap *__regmap_init_spi_avmm(struct spi_device *spi,
6687f9fb673SXu Yilun const struct regmap_config *config,
6697f9fb673SXu Yilun struct lock_class_key *lock_key,
6707f9fb673SXu Yilun const char *lock_name)
6717f9fb673SXu Yilun {
6727f9fb673SXu Yilun struct spi_avmm_bridge *bridge;
6737f9fb673SXu Yilun struct regmap *map;
6747f9fb673SXu Yilun
6757f9fb673SXu Yilun bridge = spi_avmm_bridge_ctx_gen(spi);
6767f9fb673SXu Yilun if (IS_ERR(bridge))
6777f9fb673SXu Yilun return ERR_CAST(bridge);
6787f9fb673SXu Yilun
6797f9fb673SXu Yilun map = __regmap_init(&spi->dev, ®map_spi_avmm_bus,
6807f9fb673SXu Yilun bridge, config, lock_key, lock_name);
6817f9fb673SXu Yilun if (IS_ERR(map)) {
6827f9fb673SXu Yilun spi_avmm_bridge_ctx_free(bridge);
6837f9fb673SXu Yilun return ERR_CAST(map);
6847f9fb673SXu Yilun }
6857f9fb673SXu Yilun
6867f9fb673SXu Yilun return map;
6877f9fb673SXu Yilun }
6887f9fb673SXu Yilun EXPORT_SYMBOL_GPL(__regmap_init_spi_avmm);
6897f9fb673SXu Yilun
__devm_regmap_init_spi_avmm(struct spi_device * spi,const struct regmap_config * config,struct lock_class_key * lock_key,const char * lock_name)6907f9fb673SXu Yilun struct regmap *__devm_regmap_init_spi_avmm(struct spi_device *spi,
6917f9fb673SXu Yilun const struct regmap_config *config,
6927f9fb673SXu Yilun struct lock_class_key *lock_key,
6937f9fb673SXu Yilun const char *lock_name)
6947f9fb673SXu Yilun {
6957f9fb673SXu Yilun struct spi_avmm_bridge *bridge;
6967f9fb673SXu Yilun struct regmap *map;
6977f9fb673SXu Yilun
6987f9fb673SXu Yilun bridge = spi_avmm_bridge_ctx_gen(spi);
6997f9fb673SXu Yilun if (IS_ERR(bridge))
7007f9fb673SXu Yilun return ERR_CAST(bridge);
7017f9fb673SXu Yilun
7027f9fb673SXu Yilun map = __devm_regmap_init(&spi->dev, ®map_spi_avmm_bus,
7037f9fb673SXu Yilun bridge, config, lock_key, lock_name);
7047f9fb673SXu Yilun if (IS_ERR(map)) {
7057f9fb673SXu Yilun spi_avmm_bridge_ctx_free(bridge);
7067f9fb673SXu Yilun return ERR_CAST(map);
7077f9fb673SXu Yilun }
7087f9fb673SXu Yilun
7097f9fb673SXu Yilun return map;
7107f9fb673SXu Yilun }
7117f9fb673SXu Yilun EXPORT_SYMBOL_GPL(__devm_regmap_init_spi_avmm);
7127f9fb673SXu Yilun
7137f9fb673SXu Yilun MODULE_LICENSE("GPL v2");
714