1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // regmap based irq_chip 4 // 5 // Copyright 2011 Wolfson Microelectronics plc 6 // 7 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 9 #include <linux/device.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 18 #include "internal.h" 19 20 struct regmap_irq_chip_data { 21 struct mutex lock; 22 struct irq_chip irq_chip; 23 24 struct regmap *map; 25 const struct regmap_irq_chip *chip; 26 27 int irq_base; 28 struct irq_domain *domain; 29 30 int irq; 31 int wake_count; 32 33 void *status_reg_buf; 34 unsigned int *main_status_buf; 35 unsigned int *status_buf; 36 unsigned int *mask_buf; 37 unsigned int *mask_buf_def; 38 unsigned int *wake_buf; 39 unsigned int *type_buf; 40 unsigned int *type_buf_def; 41 42 unsigned int irq_reg_stride; 43 unsigned int type_reg_stride; 44 45 bool clear_status:1; 46 }; 47 48 static inline const 49 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, 50 int irq) 51 { 52 return &data->chip->irqs[irq]; 53 } 54 55 static void regmap_irq_lock(struct irq_data *data) 56 { 57 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 58 59 mutex_lock(&d->lock); 60 } 61 62 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, 63 unsigned int reg, unsigned int mask, 64 unsigned int val) 65 { 66 if (d->chip->mask_writeonly) 67 return regmap_write_bits(d->map, reg, mask, val); 68 else 69 return regmap_update_bits(d->map, reg, mask, val); 70 } 71 72 static void regmap_irq_sync_unlock(struct irq_data *data) 73 { 74 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 75 struct regmap *map = d->map; 76 int i, ret; 77 u32 reg; 78 u32 unmask_offset; 79 u32 val; 80 81 if (d->chip->runtime_pm) { 82 ret = pm_runtime_get_sync(map->dev); 83 if (ret < 0) 84 dev_err(map->dev, "IRQ sync failed to resume: %d\n", 85 ret); 86 } 87 88 if (d->clear_status) { 89 for (i = 0; i < d->chip->num_regs; i++) { 90 reg = d->chip->status_base + 91 (i * map->reg_stride * d->irq_reg_stride); 92 93 ret = regmap_read(map, reg, &val); 94 if (ret) 95 dev_err(d->map->dev, 96 "Failed to clear the interrupt status bits\n"); 97 } 98 99 d->clear_status = false; 100 } 101 102 /* 103 * If there's been a change in the mask write it back to the 104 * hardware. We rely on the use of the regmap core cache to 105 * suppress pointless writes. 106 */ 107 for (i = 0; i < d->chip->num_regs; i++) { 108 if (!d->chip->mask_base) 109 continue; 110 111 reg = d->chip->mask_base + 112 (i * map->reg_stride * d->irq_reg_stride); 113 if (d->chip->mask_invert) { 114 ret = regmap_irq_update_bits(d, reg, 115 d->mask_buf_def[i], ~d->mask_buf[i]); 116 } else if (d->chip->unmask_base) { 117 /* set mask with mask_base register */ 118 ret = regmap_irq_update_bits(d, reg, 119 d->mask_buf_def[i], ~d->mask_buf[i]); 120 if (ret < 0) 121 dev_err(d->map->dev, 122 "Failed to sync unmasks in %x\n", 123 reg); 124 unmask_offset = d->chip->unmask_base - 125 d->chip->mask_base; 126 /* clear mask with unmask_base register */ 127 ret = regmap_irq_update_bits(d, 128 reg + unmask_offset, 129 d->mask_buf_def[i], 130 d->mask_buf[i]); 131 } else { 132 ret = regmap_irq_update_bits(d, reg, 133 d->mask_buf_def[i], d->mask_buf[i]); 134 } 135 if (ret != 0) 136 dev_err(d->map->dev, "Failed to sync masks in %x\n", 137 reg); 138 139 reg = d->chip->wake_base + 140 (i * map->reg_stride * d->irq_reg_stride); 141 if (d->wake_buf) { 142 if (d->chip->wake_invert) 143 ret = regmap_irq_update_bits(d, reg, 144 d->mask_buf_def[i], 145 ~d->wake_buf[i]); 146 else 147 ret = regmap_irq_update_bits(d, reg, 148 d->mask_buf_def[i], 149 d->wake_buf[i]); 150 if (ret != 0) 151 dev_err(d->map->dev, 152 "Failed to sync wakes in %x: %d\n", 153 reg, ret); 154 } 155 156 if (!d->chip->init_ack_masked) 157 continue; 158 /* 159 * Ack all the masked interrupts unconditionally, 160 * OR if there is masked interrupt which hasn't been Acked, 161 * it'll be ignored in irq handler, then may introduce irq storm 162 */ 163 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { 164 reg = d->chip->ack_base + 165 (i * map->reg_stride * d->irq_reg_stride); 166 /* some chips ack by write 0 */ 167 if (d->chip->ack_invert) 168 ret = regmap_write(map, reg, ~d->mask_buf[i]); 169 else 170 ret = regmap_write(map, reg, d->mask_buf[i]); 171 if (ret != 0) 172 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", 173 reg, ret); 174 } 175 } 176 177 /* Don't update the type bits if we're using mask bits for irq type. */ 178 if (!d->chip->type_in_mask) { 179 for (i = 0; i < d->chip->num_type_reg; i++) { 180 if (!d->type_buf_def[i]) 181 continue; 182 reg = d->chip->type_base + 183 (i * map->reg_stride * d->type_reg_stride); 184 if (d->chip->type_invert) 185 ret = regmap_irq_update_bits(d, reg, 186 d->type_buf_def[i], ~d->type_buf[i]); 187 else 188 ret = regmap_irq_update_bits(d, reg, 189 d->type_buf_def[i], d->type_buf[i]); 190 if (ret != 0) 191 dev_err(d->map->dev, "Failed to sync type in %x\n", 192 reg); 193 } 194 } 195 196 if (d->chip->runtime_pm) 197 pm_runtime_put(map->dev); 198 199 /* If we've changed our wakeup count propagate it to the parent */ 200 if (d->wake_count < 0) 201 for (i = d->wake_count; i < 0; i++) 202 irq_set_irq_wake(d->irq, 0); 203 else if (d->wake_count > 0) 204 for (i = 0; i < d->wake_count; i++) 205 irq_set_irq_wake(d->irq, 1); 206 207 d->wake_count = 0; 208 209 mutex_unlock(&d->lock); 210 } 211 212 static void regmap_irq_enable(struct irq_data *data) 213 { 214 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 215 struct regmap *map = d->map; 216 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 217 unsigned int mask, type; 218 219 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; 220 221 /* 222 * The type_in_mask flag means that the underlying hardware uses 223 * separate mask bits for rising and falling edge interrupts, but 224 * we want to make them into a single virtual interrupt with 225 * configurable edge. 226 * 227 * If the interrupt we're enabling defines the falling or rising 228 * masks then instead of using the regular mask bits for this 229 * interrupt, use the value previously written to the type buffer 230 * at the corresponding offset in regmap_irq_set_type(). 231 */ 232 if (d->chip->type_in_mask && type) 233 mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; 234 else 235 mask = irq_data->mask; 236 237 if (d->chip->clear_on_unmask) 238 d->clear_status = true; 239 240 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; 241 } 242 243 static void regmap_irq_disable(struct irq_data *data) 244 { 245 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 246 struct regmap *map = d->map; 247 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 248 249 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; 250 } 251 252 static int regmap_irq_set_type(struct irq_data *data, unsigned int type) 253 { 254 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 255 struct regmap *map = d->map; 256 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 257 int reg; 258 const struct regmap_irq_type *t = &irq_data->type; 259 260 if ((t->types_supported & type) != type) 261 return 0; 262 263 reg = t->type_reg_offset / map->reg_stride; 264 265 if (t->type_reg_mask) 266 d->type_buf[reg] &= ~t->type_reg_mask; 267 else 268 d->type_buf[reg] &= ~(t->type_falling_val | 269 t->type_rising_val | 270 t->type_level_low_val | 271 t->type_level_high_val); 272 switch (type) { 273 case IRQ_TYPE_EDGE_FALLING: 274 d->type_buf[reg] |= t->type_falling_val; 275 break; 276 277 case IRQ_TYPE_EDGE_RISING: 278 d->type_buf[reg] |= t->type_rising_val; 279 break; 280 281 case IRQ_TYPE_EDGE_BOTH: 282 d->type_buf[reg] |= (t->type_falling_val | 283 t->type_rising_val); 284 break; 285 286 case IRQ_TYPE_LEVEL_HIGH: 287 d->type_buf[reg] |= t->type_level_high_val; 288 break; 289 290 case IRQ_TYPE_LEVEL_LOW: 291 d->type_buf[reg] |= t->type_level_low_val; 292 break; 293 default: 294 return -EINVAL; 295 } 296 return 0; 297 } 298 299 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) 300 { 301 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 302 struct regmap *map = d->map; 303 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 304 305 if (on) { 306 if (d->wake_buf) 307 d->wake_buf[irq_data->reg_offset / map->reg_stride] 308 &= ~irq_data->mask; 309 d->wake_count++; 310 } else { 311 if (d->wake_buf) 312 d->wake_buf[irq_data->reg_offset / map->reg_stride] 313 |= irq_data->mask; 314 d->wake_count--; 315 } 316 317 return 0; 318 } 319 320 static const struct irq_chip regmap_irq_chip = { 321 .irq_bus_lock = regmap_irq_lock, 322 .irq_bus_sync_unlock = regmap_irq_sync_unlock, 323 .irq_disable = regmap_irq_disable, 324 .irq_enable = regmap_irq_enable, 325 .irq_set_type = regmap_irq_set_type, 326 .irq_set_wake = regmap_irq_set_wake, 327 }; 328 329 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, 330 unsigned int b) 331 { 332 const struct regmap_irq_chip *chip = data->chip; 333 struct regmap *map = data->map; 334 struct regmap_irq_sub_irq_map *subreg; 335 int i, ret = 0; 336 337 if (!chip->sub_reg_offsets) { 338 /* Assume linear mapping */ 339 ret = regmap_read(map, chip->status_base + 340 (b * map->reg_stride * data->irq_reg_stride), 341 &data->status_buf[b]); 342 } else { 343 subreg = &chip->sub_reg_offsets[b]; 344 for (i = 0; i < subreg->num_regs; i++) { 345 unsigned int offset = subreg->offset[i]; 346 347 ret = regmap_read(map, chip->status_base + offset, 348 &data->status_buf[offset]); 349 if (ret) 350 break; 351 } 352 } 353 return ret; 354 } 355 356 static irqreturn_t regmap_irq_thread(int irq, void *d) 357 { 358 struct regmap_irq_chip_data *data = d; 359 const struct regmap_irq_chip *chip = data->chip; 360 struct regmap *map = data->map; 361 int ret, i; 362 bool handled = false; 363 u32 reg; 364 365 if (chip->handle_pre_irq) 366 chip->handle_pre_irq(chip->irq_drv_data); 367 368 if (chip->runtime_pm) { 369 ret = pm_runtime_get_sync(map->dev); 370 if (ret < 0) { 371 dev_err(map->dev, "IRQ thread failed to resume: %d\n", 372 ret); 373 goto exit; 374 } 375 } 376 377 /* 378 * Read only registers with active IRQs if the chip has 'main status 379 * register'. Else read in the statuses, using a single bulk read if 380 * possible in order to reduce the I/O overheads. 381 */ 382 383 if (chip->num_main_regs) { 384 unsigned int max_main_bits; 385 unsigned long size; 386 387 size = chip->num_regs * sizeof(unsigned int); 388 389 max_main_bits = (chip->num_main_status_bits) ? 390 chip->num_main_status_bits : chip->num_regs; 391 /* Clear the status buf as we don't read all status regs */ 392 memset(data->status_buf, 0, size); 393 394 /* We could support bulk read for main status registers 395 * but I don't expect to see devices with really many main 396 * status registers so let's only support single reads for the 397 * sake of simplicity. and add bulk reads only if needed 398 */ 399 for (i = 0; i < chip->num_main_regs; i++) { 400 ret = regmap_read(map, chip->main_status + 401 (i * map->reg_stride 402 * data->irq_reg_stride), 403 &data->main_status_buf[i]); 404 if (ret) { 405 dev_err(map->dev, 406 "Failed to read IRQ status %d\n", 407 ret); 408 goto exit; 409 } 410 } 411 412 /* Read sub registers with active IRQs */ 413 for (i = 0; i < chip->num_main_regs; i++) { 414 unsigned int b; 415 const unsigned long mreg = data->main_status_buf[i]; 416 417 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { 418 if (i * map->format.val_bytes * 8 + b > 419 max_main_bits) 420 break; 421 ret = read_sub_irq_data(data, b); 422 423 if (ret != 0) { 424 dev_err(map->dev, 425 "Failed to read IRQ status %d\n", 426 ret); 427 goto exit; 428 } 429 } 430 431 } 432 } else if (!map->use_single_read && map->reg_stride == 1 && 433 data->irq_reg_stride == 1) { 434 435 u8 *buf8 = data->status_reg_buf; 436 u16 *buf16 = data->status_reg_buf; 437 u32 *buf32 = data->status_reg_buf; 438 439 BUG_ON(!data->status_reg_buf); 440 441 ret = regmap_bulk_read(map, chip->status_base, 442 data->status_reg_buf, 443 chip->num_regs); 444 if (ret != 0) { 445 dev_err(map->dev, "Failed to read IRQ status: %d\n", 446 ret); 447 goto exit; 448 } 449 450 for (i = 0; i < data->chip->num_regs; i++) { 451 switch (map->format.val_bytes) { 452 case 1: 453 data->status_buf[i] = buf8[i]; 454 break; 455 case 2: 456 data->status_buf[i] = buf16[i]; 457 break; 458 case 4: 459 data->status_buf[i] = buf32[i]; 460 break; 461 default: 462 BUG(); 463 goto exit; 464 } 465 } 466 467 } else { 468 for (i = 0; i < data->chip->num_regs; i++) { 469 ret = regmap_read(map, chip->status_base + 470 (i * map->reg_stride 471 * data->irq_reg_stride), 472 &data->status_buf[i]); 473 474 if (ret != 0) { 475 dev_err(map->dev, 476 "Failed to read IRQ status: %d\n", 477 ret); 478 goto exit; 479 } 480 } 481 } 482 483 /* 484 * Ignore masked IRQs and ack if we need to; we ack early so 485 * there is no race between handling and acknowleding the 486 * interrupt. We assume that typically few of the interrupts 487 * will fire simultaneously so don't worry about overhead from 488 * doing a write per register. 489 */ 490 for (i = 0; i < data->chip->num_regs; i++) { 491 data->status_buf[i] &= ~data->mask_buf[i]; 492 493 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { 494 reg = chip->ack_base + 495 (i * map->reg_stride * data->irq_reg_stride); 496 ret = regmap_write(map, reg, data->status_buf[i]); 497 if (ret != 0) 498 dev_err(map->dev, "Failed to ack 0x%x: %d\n", 499 reg, ret); 500 } 501 } 502 503 for (i = 0; i < chip->num_irqs; i++) { 504 if (data->status_buf[chip->irqs[i].reg_offset / 505 map->reg_stride] & chip->irqs[i].mask) { 506 handle_nested_irq(irq_find_mapping(data->domain, i)); 507 handled = true; 508 } 509 } 510 511 exit: 512 if (chip->runtime_pm) 513 pm_runtime_put(map->dev); 514 515 if (chip->handle_post_irq) 516 chip->handle_post_irq(chip->irq_drv_data); 517 518 if (handled) 519 return IRQ_HANDLED; 520 else 521 return IRQ_NONE; 522 } 523 524 static int regmap_irq_map(struct irq_domain *h, unsigned int virq, 525 irq_hw_number_t hw) 526 { 527 struct regmap_irq_chip_data *data = h->host_data; 528 529 irq_set_chip_data(virq, data); 530 irq_set_chip(virq, &data->irq_chip); 531 irq_set_nested_thread(virq, 1); 532 irq_set_parent(virq, data->irq); 533 irq_set_noprobe(virq); 534 535 return 0; 536 } 537 538 static const struct irq_domain_ops regmap_domain_ops = { 539 .map = regmap_irq_map, 540 .xlate = irq_domain_xlate_onetwocell, 541 }; 542 543 /** 544 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling 545 * 546 * @map: The regmap for the device. 547 * @irq: The IRQ the device uses to signal interrupts. 548 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 549 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 550 * @chip: Configuration for the interrupt controller. 551 * @data: Runtime data structure for the controller, allocated on success. 552 * 553 * Returns 0 on success or an errno on failure. 554 * 555 * In order for this to be efficient the chip really should use a 556 * register cache. The chip driver is responsible for restoring the 557 * register values used by the IRQ controller over suspend and resume. 558 */ 559 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, 560 int irq_base, const struct regmap_irq_chip *chip, 561 struct regmap_irq_chip_data **data) 562 { 563 struct regmap_irq_chip_data *d; 564 int i; 565 int ret = -ENOMEM; 566 int num_type_reg; 567 u32 reg; 568 u32 unmask_offset; 569 570 if (chip->num_regs <= 0) 571 return -EINVAL; 572 573 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) 574 return -EINVAL; 575 576 for (i = 0; i < chip->num_irqs; i++) { 577 if (chip->irqs[i].reg_offset % map->reg_stride) 578 return -EINVAL; 579 if (chip->irqs[i].reg_offset / map->reg_stride >= 580 chip->num_regs) 581 return -EINVAL; 582 } 583 584 if (irq_base) { 585 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); 586 if (irq_base < 0) { 587 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", 588 irq_base); 589 return irq_base; 590 } 591 } 592 593 d = kzalloc(sizeof(*d), GFP_KERNEL); 594 if (!d) 595 return -ENOMEM; 596 597 if (chip->num_main_regs) { 598 d->main_status_buf = kcalloc(chip->num_main_regs, 599 sizeof(unsigned int), 600 GFP_KERNEL); 601 602 if (!d->main_status_buf) 603 goto err_alloc; 604 } 605 606 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int), 607 GFP_KERNEL); 608 if (!d->status_buf) 609 goto err_alloc; 610 611 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int), 612 GFP_KERNEL); 613 if (!d->mask_buf) 614 goto err_alloc; 615 616 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int), 617 GFP_KERNEL); 618 if (!d->mask_buf_def) 619 goto err_alloc; 620 621 if (chip->wake_base) { 622 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int), 623 GFP_KERNEL); 624 if (!d->wake_buf) 625 goto err_alloc; 626 } 627 628 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; 629 if (num_type_reg) { 630 d->type_buf_def = kcalloc(num_type_reg, 631 sizeof(unsigned int), GFP_KERNEL); 632 if (!d->type_buf_def) 633 goto err_alloc; 634 635 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int), 636 GFP_KERNEL); 637 if (!d->type_buf) 638 goto err_alloc; 639 } 640 641 d->irq_chip = regmap_irq_chip; 642 d->irq_chip.name = chip->name; 643 d->irq = irq; 644 d->map = map; 645 d->chip = chip; 646 d->irq_base = irq_base; 647 648 if (chip->irq_reg_stride) 649 d->irq_reg_stride = chip->irq_reg_stride; 650 else 651 d->irq_reg_stride = 1; 652 653 if (chip->type_reg_stride) 654 d->type_reg_stride = chip->type_reg_stride; 655 else 656 d->type_reg_stride = 1; 657 658 if (!map->use_single_read && map->reg_stride == 1 && 659 d->irq_reg_stride == 1) { 660 d->status_reg_buf = kmalloc_array(chip->num_regs, 661 map->format.val_bytes, 662 GFP_KERNEL); 663 if (!d->status_reg_buf) 664 goto err_alloc; 665 } 666 667 mutex_init(&d->lock); 668 669 for (i = 0; i < chip->num_irqs; i++) 670 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] 671 |= chip->irqs[i].mask; 672 673 /* Mask all the interrupts by default */ 674 for (i = 0; i < chip->num_regs; i++) { 675 d->mask_buf[i] = d->mask_buf_def[i]; 676 if (!chip->mask_base) 677 continue; 678 679 reg = chip->mask_base + 680 (i * map->reg_stride * d->irq_reg_stride); 681 if (chip->mask_invert) 682 ret = regmap_irq_update_bits(d, reg, 683 d->mask_buf[i], ~d->mask_buf[i]); 684 else if (d->chip->unmask_base) { 685 unmask_offset = d->chip->unmask_base - 686 d->chip->mask_base; 687 ret = regmap_irq_update_bits(d, 688 reg + unmask_offset, 689 d->mask_buf[i], 690 d->mask_buf[i]); 691 } else 692 ret = regmap_irq_update_bits(d, reg, 693 d->mask_buf[i], d->mask_buf[i]); 694 if (ret != 0) { 695 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 696 reg, ret); 697 goto err_alloc; 698 } 699 700 if (!chip->init_ack_masked) 701 continue; 702 703 /* Ack masked but set interrupts */ 704 reg = chip->status_base + 705 (i * map->reg_stride * d->irq_reg_stride); 706 ret = regmap_read(map, reg, &d->status_buf[i]); 707 if (ret != 0) { 708 dev_err(map->dev, "Failed to read IRQ status: %d\n", 709 ret); 710 goto err_alloc; 711 } 712 713 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { 714 reg = chip->ack_base + 715 (i * map->reg_stride * d->irq_reg_stride); 716 if (chip->ack_invert) 717 ret = regmap_write(map, reg, 718 ~(d->status_buf[i] & d->mask_buf[i])); 719 else 720 ret = regmap_write(map, reg, 721 d->status_buf[i] & d->mask_buf[i]); 722 if (ret != 0) { 723 dev_err(map->dev, "Failed to ack 0x%x: %d\n", 724 reg, ret); 725 goto err_alloc; 726 } 727 } 728 } 729 730 /* Wake is disabled by default */ 731 if (d->wake_buf) { 732 for (i = 0; i < chip->num_regs; i++) { 733 d->wake_buf[i] = d->mask_buf_def[i]; 734 reg = chip->wake_base + 735 (i * map->reg_stride * d->irq_reg_stride); 736 737 if (chip->wake_invert) 738 ret = regmap_irq_update_bits(d, reg, 739 d->mask_buf_def[i], 740 0); 741 else 742 ret = regmap_irq_update_bits(d, reg, 743 d->mask_buf_def[i], 744 d->wake_buf[i]); 745 if (ret != 0) { 746 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 747 reg, ret); 748 goto err_alloc; 749 } 750 } 751 } 752 753 if (chip->num_type_reg && !chip->type_in_mask) { 754 for (i = 0; i < chip->num_type_reg; ++i) { 755 reg = chip->type_base + 756 (i * map->reg_stride * d->type_reg_stride); 757 758 ret = regmap_read(map, reg, &d->type_buf_def[i]); 759 760 if (d->chip->type_invert) 761 d->type_buf_def[i] = ~d->type_buf_def[i]; 762 763 if (ret) { 764 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", 765 reg, ret); 766 goto err_alloc; 767 } 768 } 769 } 770 771 if (irq_base) 772 d->domain = irq_domain_add_legacy(map->dev->of_node, 773 chip->num_irqs, irq_base, 0, 774 ®map_domain_ops, d); 775 else 776 d->domain = irq_domain_add_linear(map->dev->of_node, 777 chip->num_irqs, 778 ®map_domain_ops, d); 779 if (!d->domain) { 780 dev_err(map->dev, "Failed to create IRQ domain\n"); 781 ret = -ENOMEM; 782 goto err_alloc; 783 } 784 785 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, 786 irq_flags | IRQF_ONESHOT, 787 chip->name, d); 788 if (ret != 0) { 789 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", 790 irq, chip->name, ret); 791 goto err_domain; 792 } 793 794 *data = d; 795 796 return 0; 797 798 err_domain: 799 /* Should really dispose of the domain but... */ 800 err_alloc: 801 kfree(d->type_buf); 802 kfree(d->type_buf_def); 803 kfree(d->wake_buf); 804 kfree(d->mask_buf_def); 805 kfree(d->mask_buf); 806 kfree(d->status_buf); 807 kfree(d->status_reg_buf); 808 kfree(d); 809 return ret; 810 } 811 EXPORT_SYMBOL_GPL(regmap_add_irq_chip); 812 813 /** 814 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip 815 * 816 * @irq: Primary IRQ for the device 817 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip() 818 * 819 * This function also disposes of all mapped IRQs on the chip. 820 */ 821 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) 822 { 823 unsigned int virq; 824 int hwirq; 825 826 if (!d) 827 return; 828 829 free_irq(irq, d); 830 831 /* Dispose all virtual irq from irq domain before removing it */ 832 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { 833 /* Ignore hwirq if holes in the IRQ list */ 834 if (!d->chip->irqs[hwirq].mask) 835 continue; 836 837 /* 838 * Find the virtual irq of hwirq on chip and if it is 839 * there then dispose it 840 */ 841 virq = irq_find_mapping(d->domain, hwirq); 842 if (virq) 843 irq_dispose_mapping(virq); 844 } 845 846 irq_domain_remove(d->domain); 847 kfree(d->type_buf); 848 kfree(d->type_buf_def); 849 kfree(d->wake_buf); 850 kfree(d->mask_buf_def); 851 kfree(d->mask_buf); 852 kfree(d->status_reg_buf); 853 kfree(d->status_buf); 854 kfree(d); 855 } 856 EXPORT_SYMBOL_GPL(regmap_del_irq_chip); 857 858 static void devm_regmap_irq_chip_release(struct device *dev, void *res) 859 { 860 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res; 861 862 regmap_del_irq_chip(d->irq, d); 863 } 864 865 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data) 866 867 { 868 struct regmap_irq_chip_data **r = res; 869 870 if (!r || !*r) { 871 WARN_ON(!r || !*r); 872 return 0; 873 } 874 return *r == data; 875 } 876 877 /** 878 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip() 879 * 880 * @dev: The device pointer on which irq_chip belongs to. 881 * @map: The regmap for the device. 882 * @irq: The IRQ the device uses to signal interrupts 883 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 884 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 885 * @chip: Configuration for the interrupt controller. 886 * @data: Runtime data structure for the controller, allocated on success 887 * 888 * Returns 0 on success or an errno on failure. 889 * 890 * The ®map_irq_chip_data will be automatically released when the device is 891 * unbound. 892 */ 893 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq, 894 int irq_flags, int irq_base, 895 const struct regmap_irq_chip *chip, 896 struct regmap_irq_chip_data **data) 897 { 898 struct regmap_irq_chip_data **ptr, *d; 899 int ret; 900 901 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr), 902 GFP_KERNEL); 903 if (!ptr) 904 return -ENOMEM; 905 906 ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base, 907 chip, &d); 908 if (ret < 0) { 909 devres_free(ptr); 910 return ret; 911 } 912 913 *ptr = d; 914 devres_add(dev, ptr); 915 *data = d; 916 return 0; 917 } 918 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip); 919 920 /** 921 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip() 922 * 923 * @dev: Device for which which resource was allocated. 924 * @irq: Primary IRQ for the device. 925 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip(). 926 * 927 * A resource managed version of regmap_del_irq_chip(). 928 */ 929 void devm_regmap_del_irq_chip(struct device *dev, int irq, 930 struct regmap_irq_chip_data *data) 931 { 932 int rc; 933 934 WARN_ON(irq != data->irq); 935 rc = devres_release(dev, devm_regmap_irq_chip_release, 936 devm_regmap_irq_chip_match, data); 937 938 if (rc != 0) 939 WARN_ON(rc); 940 } 941 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip); 942 943 /** 944 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip 945 * 946 * @data: regmap irq controller to operate on. 947 * 948 * Useful for drivers to request their own IRQs. 949 */ 950 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data) 951 { 952 WARN_ON(!data->irq_base); 953 return data->irq_base; 954 } 955 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base); 956 957 /** 958 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ 959 * 960 * @data: regmap irq controller to operate on. 961 * @irq: index of the interrupt requested in the chip IRQs. 962 * 963 * Useful for drivers to request their own IRQs. 964 */ 965 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq) 966 { 967 /* Handle holes in the IRQ list */ 968 if (!data->chip->irqs[irq].mask) 969 return -EINVAL; 970 971 return irq_create_mapping(data->domain, irq); 972 } 973 EXPORT_SYMBOL_GPL(regmap_irq_get_virq); 974 975 /** 976 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip 977 * 978 * @data: regmap_irq controller to operate on. 979 * 980 * Useful for drivers to request their own IRQs and for integration 981 * with subsystems. For ease of integration NULL is accepted as a 982 * domain, allowing devices to just call this even if no domain is 983 * allocated. 984 */ 985 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data) 986 { 987 if (data) 988 return data->domain; 989 else 990 return NULL; 991 } 992 EXPORT_SYMBOL_GPL(regmap_irq_get_domain); 993