11da177e4SLinus Torvalds /* drivers/atm/suni.h - PMC PM5346 SUNI (PHY) declarations */ 21da177e4SLinus Torvalds 31da177e4SLinus Torvalds /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 41da177e4SLinus Torvalds 51da177e4SLinus Torvalds 61da177e4SLinus Torvalds #ifndef DRIVER_ATM_SUNI_H 71da177e4SLinus Torvalds #define DRIVER_ATM_SUNI_H 81da177e4SLinus Torvalds 91da177e4SLinus Torvalds #include <linux/atmdev.h> 101da177e4SLinus Torvalds #include <linux/atmioc.h> 112be63b87SJorge Boncompte [DTI2] #include <linux/sonet.h> 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds /* SUNI registers */ 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds #define SUNI_MRI 0x00 /* Master Reset and Identity / Load 161da177e4SLinus Torvalds Meter */ 171da177e4SLinus Torvalds #define SUNI_MC 0x01 /* Master Configuration */ 181da177e4SLinus Torvalds #define SUNI_MIS 0x02 /* Master Interrupt Status */ 191da177e4SLinus Torvalds /* no 0x03 */ 201da177e4SLinus Torvalds #define SUNI_MCM 0x04 /* Master Clock Monitor */ 211da177e4SLinus Torvalds #define SUNI_MCT 0x05 /* Master Control */ 221da177e4SLinus Torvalds #define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */ 231da177e4SLinus Torvalds #define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */ 241da177e4SLinus Torvalds /* 0x08-0x0F reserved */ 251da177e4SLinus Torvalds #define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */ 261da177e4SLinus Torvalds #define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */ 271da177e4SLinus Torvalds #define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */ 281da177e4SLinus Torvalds #define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */ 291da177e4SLinus Torvalds #define SUNI_TSOP_CTRL 0x14 /* TSOP Control */ 301da177e4SLinus Torvalds #define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */ 311da177e4SLinus Torvalds /* 0x16-0x17 reserved */ 321da177e4SLinus Torvalds #define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */ 331da177e4SLinus Torvalds #define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */ 341da177e4SLinus Torvalds #define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */ 351da177e4SLinus Torvalds #define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */ 361da177e4SLinus Torvalds #define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */ 371da177e4SLinus Torvalds #define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */ 381da177e4SLinus Torvalds #define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */ 391da177e4SLinus Torvalds #define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */ 401da177e4SLinus Torvalds #define SUNI_TLOP_CTRL 0x20 /* TLOP Control */ 411da177e4SLinus Torvalds #define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */ 421da177e4SLinus Torvalds /* 0x22-0x2F reserved */ 431da177e4SLinus Torvalds #define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */ 441da177e4SLinus Torvalds #define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */ 451da177e4SLinus Torvalds /* 0x32 reserved */ 461da177e4SLinus Torvalds #define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */ 471da177e4SLinus Torvalds /* 0x34-0x36 reserved */ 481da177e4SLinus Torvalds #define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */ 491da177e4SLinus Torvalds #define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */ 501da177e4SLinus Torvalds #define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */ 511da177e4SLinus Torvalds #define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */ 521da177e4SLinus Torvalds #define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */ 531da177e4SLinus Torvalds /* 0x3C reserved */ 541da177e4SLinus Torvalds #define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */ 551da177e4SLinus Torvalds /* 0x3E-0x3F reserved */ 561da177e4SLinus Torvalds #define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */ 571da177e4SLinus Torvalds #define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */ 581da177e4SLinus Torvalds /* 0x42-0x44 reserved */ 591da177e4SLinus Torvalds #define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */ 601da177e4SLinus Torvalds #define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */ 611da177e4SLinus Torvalds /* 0x47 reserved */ 621da177e4SLinus Torvalds #define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */ 631da177e4SLinus Torvalds #define SUNI_TPOP_PS 0x49 /* TPOP Path Status */ 641da177e4SLinus Torvalds /* 0x4A-0x4F reserved */ 651da177e4SLinus Torvalds #define SUNI_RACP_CS 0x50 /* RACP Control/Status */ 661da177e4SLinus Torvalds #define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */ 671da177e4SLinus Torvalds #define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */ 681da177e4SLinus Torvalds #define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */ 691da177e4SLinus Torvalds #define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */ 701da177e4SLinus Torvalds #define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */ 711da177e4SLinus Torvalds #define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */ 721da177e4SLinus Torvalds #define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */ 731da177e4SLinus Torvalds #define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */ 741da177e4SLinus Torvalds #define SUNI_RACP_CFG 0x59 /* RACP Configuration */ 751da177e4SLinus Torvalds /* 0x5A-0x5F reserved */ 761da177e4SLinus Torvalds #define SUNI_TACP_CS 0x60 /* TACP Control/Status */ 771da177e4SLinus Torvalds #define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */ 781da177e4SLinus Torvalds #define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload 791da177e4SLinus Torvalds Octet Pattern */ 801da177e4SLinus Torvalds #define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */ 811da177e4SLinus Torvalds #define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */ 821da177e4SLinus Torvalds #define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */ 831da177e4SLinus Torvalds #define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */ 841da177e4SLinus Torvalds #define SUNI_TACP_CFG 0x67 /* TACP Configuration */ 851da177e4SLinus Torvalds /* 0x68-0x7F reserved */ 861da177e4SLinus Torvalds #define SUNI_MT 0x80 /* Master Test */ 871da177e4SLinus Torvalds /* 0x81-0xFF reserved */ 881da177e4SLinus Torvalds 891da177e4SLinus Torvalds /* SUNI register values */ 901da177e4SLinus Torvalds 911da177e4SLinus Torvalds 921da177e4SLinus Torvalds /* MRI is reg 0 */ 931da177e4SLinus Torvalds #define SUNI_MRI_ID 0x0f /* R, SUNI revision number */ 941da177e4SLinus Torvalds #define SUNI_MRI_ID_SHIFT 0 951da177e4SLinus Torvalds #define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */ 961da177e4SLinus Torvalds #define SUNI_MRI_TYPE_SHIFT 4 971da177e4SLinus Torvalds #define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip 981da177e4SLinus Torvalds 0: normal operation 991da177e4SLinus Torvalds 1: reset & low power */ 1001da177e4SLinus Torvalds /* MCT is reg 5 */ 1011da177e4SLinus Torvalds #define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from 1021da177e4SLinus Torvalds TRCLK+/- */ 1031da177e4SLinus Torvalds #define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */ 1041da177e4SLinus Torvalds #define SUNI_MCT_LLE 0x04 /* RW, line loopback */ 1051da177e4SLinus Torvalds #define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer 1061da177e4SLinus Torvalds adjustments 1071da177e4SLinus Torvalds 0: payload ptr controlled by TPOP 1081da177e4SLinus Torvalds ptr control reg 1091da177e4SLinus Torvalds 1: payload pointer fixed at 522 */ 1101da177e4SLinus Torvalds #define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */ 1111da177e4SLinus Torvalds #define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation 1121da177e4SLinus Torvalds interrupt (1: on) */ 1131da177e4SLinus Torvalds /* RSOP_CIE is reg 0x10 */ 1141da177e4SLinus Torvalds #define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm 1151da177e4SLinus Torvalds state change */ 1161da177e4SLinus Torvalds #define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of 1171da177e4SLinus Torvalds frame state change */ 1181da177e4SLinus Torvalds #define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of 1191da177e4SLinus Torvalds signal state change */ 1201da177e4SLinus Torvalds #define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section 1211da177e4SLinus Torvalds BIP-8 error (B1) */ 1221da177e4SLinus Torvalds #define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next 1231da177e4SLinus Torvalds boundary */ 1241da177e4SLinus Torvalds #define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */ 1251da177e4SLinus Torvalds 1261da177e4SLinus Torvalds /* RSOP_SIS is reg 0x11 */ 1271da177e4SLinus Torvalds #define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */ 1281da177e4SLinus Torvalds #define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */ 1291da177e4SLinus Torvalds #define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */ 1301da177e4SLinus Torvalds #define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */ 1311da177e4SLinus Torvalds #define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */ 1321da177e4SLinus Torvalds #define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */ 1331da177e4SLinus Torvalds #define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */ 1341da177e4SLinus Torvalds 1351da177e4SLinus Torvalds /* TSOP_CTRL is reg 0x14 */ 1361da177e4SLinus Torvalds #define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */ 1371da177e4SLinus Torvalds #define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */ 1381da177e4SLinus Torvalds 1391da177e4SLinus Torvalds /* TSOP_DIAG is reg 0x15 */ 1401da177e4SLinus Torvalds #define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */ 1411da177e4SLinus Torvalds #define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */ 1421da177e4SLinus Torvalds #define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */ 1431da177e4SLinus Torvalds 1441da177e4SLinus Torvalds /* TLOP_DIAG is reg 0x21 */ 1451da177e4SLinus Torvalds #define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */ 1461da177e4SLinus Torvalds 1471da177e4SLinus Torvalds /* TPOP_DIAG is reg 0x40 */ 1481da177e4SLinus Torvalds #define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */ 1491da177e4SLinus Torvalds #define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */ 1501da177e4SLinus Torvalds 1511da177e4SLinus Torvalds /* TPOP_APM is reg 0x46 */ 1521da177e4SLinus Torvalds #define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2 1531da177e4SLinus Torvalds bits */ 1541da177e4SLinus Torvalds #define SUNI_TPOP_APM_APTR_SHIFT 0 1551da177e4SLinus Torvalds #define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload 1561da177e4SLinus Torvalds pointer */ 1571da177e4SLinus Torvalds #define SUNI_TPOP_APM_S_SHIFT 2 1581da177e4SLinus Torvalds #define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */ 1591da177e4SLinus Torvalds #define SUNI_TPOP_APM_NDF_SHIFT 4 1601da177e4SLinus Torvalds 1611da177e4SLinus Torvalds #define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */ 1621da177e4SLinus Torvalds #define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */ 1631da177e4SLinus Torvalds 1641da177e4SLinus Torvalds /* RACP_IES is reg 0x51 */ 1651da177e4SLinus Torvalds #define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */ 1661da177e4SLinus Torvalds #define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */ 1671da177e4SLinus Torvalds #define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */ 1681da177e4SLinus Torvalds #define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation 1691da177e4SLinus Torvalds state */ 1701da177e4SLinus Torvalds #define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */ 1711da177e4SLinus Torvalds #define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */ 1721da177e4SLinus Torvalds #define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state 1731da177e4SLinus Torvalds change interrupt */ 1741da177e4SLinus Torvalds 1751da177e4SLinus Torvalds /* TACP_CS is reg 0x60 */ 1761da177e4SLinus Torvalds #define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */ 1771da177e4SLinus Torvalds #define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */ 1781da177e4SLinus Torvalds #define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */ 1791da177e4SLinus Torvalds #define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */ 1801da177e4SLinus Torvalds #define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */ 1811da177e4SLinus Torvalds #define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */ 1821da177e4SLinus Torvalds #define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */ 1831da177e4SLinus Torvalds 1841da177e4SLinus Torvalds /* TACP_IUCHP is reg 0x61 */ 1851da177e4SLinus Torvalds #define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u 1861da177e4SLinus Torvalds pattern */ 1871da177e4SLinus Torvalds #define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u 1881da177e4SLinus Torvalds pattern */ 1891da177e4SLinus Torvalds #define SUNI_TACP_IUCHP_PTI_SHIFT 1 1901da177e4SLinus Torvalds #define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u 1911da177e4SLinus Torvalds pattern */ 1921da177e4SLinus Torvalds #define SUNI_TACP_IUCHP_GFC_SHIFT 4 1931da177e4SLinus Torvalds 1941da177e4SLinus Torvalds /* MT is reg 0x80 */ 1951da177e4SLinus Torvalds #define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface 1961da177e4SLinus Torvalds tri-state */ 1971da177e4SLinus Torvalds #define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */ 1981da177e4SLinus Torvalds #define SUNI_MT_IOTST 0x04 /* RW, enable test mode */ 1991da177e4SLinus Torvalds #define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */ 2001da177e4SLinus Torvalds #define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */ 2011da177e4SLinus Torvalds #define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */ 2021da177e4SLinus Torvalds 2031da177e4SLinus Torvalds 2041da177e4SLinus Torvalds #define SUNI_IDLE_PATTERN 0x6a /* idle pattern */ 2051da177e4SLinus Torvalds 2061da177e4SLinus Torvalds 2071da177e4SLinus Torvalds #ifdef __KERNEL__ 2082be63b87SJorge Boncompte [DTI2] struct suni_priv { 2092be63b87SJorge Boncompte [DTI2] struct k_sonet_stats sonet_stats; /* link diagnostics */ 2102be63b87SJorge Boncompte [DTI2] int loop_mode; /* loopback mode */ 2112be63b87SJorge Boncompte [DTI2] struct atm_dev *dev; /* device back-pointer */ 2122be63b87SJorge Boncompte [DTI2] struct suni_priv *next; /* next SUNI */ 2132be63b87SJorge Boncompte [DTI2] }; 2142be63b87SJorge Boncompte [DTI2] 2151da177e4SLinus Torvalds int suni_init(struct atm_dev *dev); 2161da177e4SLinus Torvalds #endif 2171da177e4SLinus Torvalds 2181da177e4SLinus Torvalds #endif 219