1 /****************************************************************************** 2 * 3 * nicstar.h 4 * 5 * Header file for the nicstar device driver. 6 * 7 * Author: Rui Prior (rprior@inescn.pt) 8 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 9 * 10 * (C) INESC 1998 11 * 12 ******************************************************************************/ 13 14 15 #ifndef _LINUX_NICSTAR_H_ 16 #define _LINUX_NICSTAR_H_ 17 18 19 /* Includes *******************************************************************/ 20 21 #include <linux/types.h> 22 #include <linux/pci.h> 23 #include <linux/uio.h> 24 #include <linux/skbuff.h> 25 #include <linux/atmdev.h> 26 #include <linux/atm_nicstar.h> 27 28 29 /* Options ********************************************************************/ 30 31 #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards 32 controlled by the device driver. Must 33 be <= 5 */ 34 35 #undef RCQ_SUPPORT /* Do not define this for now */ 36 37 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */ 38 #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */ 39 40 #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */ 41 #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */ 42 #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */ 43 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */ 44 45 #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384. 46 Define 4096 only if (all) your card(s) 47 have 32K x 32bit SRAM, in which case 48 setting this to 16384 will just waste a 49 lot of memory. 50 Setting this to 4096 for a card with 51 128K x 32bit SRAM will limit the maximum 52 VCI. */ 53 54 /*#define NS_PCI_LATENCY 64*/ /* Must be a multiple of 32 */ 55 56 /* Number of buffers initially allocated */ 57 #define NUM_SB 32 /* Must be even */ 58 #define NUM_LB 24 /* Must be even */ 59 #define NUM_HB 8 /* Pre-allocated huge buffers */ 60 #define NUM_IOVB 48 /* Iovec buffers */ 61 62 /* Lower level for count of buffers */ 63 #define MIN_SB 8 /* Must be even */ 64 #define MIN_LB 8 /* Must be even */ 65 #define MIN_HB 6 66 #define MIN_IOVB 8 67 68 /* Upper level for count of buffers */ 69 #define MAX_SB 64 /* Must be even, <= 508 */ 70 #define MAX_LB 48 /* Must be even, <= 508 */ 71 #define MAX_HB 10 72 #define MAX_IOVB 80 73 74 /* These are the absolute maximum allowed for the ioctl() */ 75 #define TOP_SB 256 /* Must be even, <= 508 */ 76 #define TOP_LB 128 /* Must be even, <= 508 */ 77 #define TOP_HB 64 78 #define TOP_IOVB 256 79 80 81 #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */ 82 #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */ 83 84 #undef ENABLE_TSQFIE 85 86 #define SCQFULL_TIMEOUT (5 * HZ) 87 88 #define NS_POLL_PERIOD (HZ) 89 90 #define PCR_TOLERANCE (1.0001) 91 92 93 94 /* ESI stuff ******************************************************************/ 95 96 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C 97 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6 98 99 100 /* #defines *******************************************************************/ 101 102 #define NS_IOREMAP_SIZE 4096 103 104 /* 105 * BUF_XX distinguish the Rx buffers depending on their (small/large) size. 106 * BUG_SM and BUG_LG are both used by the driver and the device. 107 * BUF_NONE is only used by the driver. 108 */ 109 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */ 110 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */ 111 #define BUF_NONE 0xffffffff /* Software only: */ 112 113 #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */ 114 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \ 115 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48))) 116 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec))) 117 118 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48) 119 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48) 120 121 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */ 122 123 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER) 124 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE) 125 126 127 /* NICStAR structures located in host memory **********************************/ 128 129 130 131 /* RSQ - Receive Status Queue 132 * 133 * Written by the NICStAR, read by the device driver. 134 */ 135 136 typedef struct ns_rsqe 137 { 138 u32 word_1; 139 u32 buffer_handle; 140 u32 final_aal5_crc32; 141 u32 word_4; 142 } ns_rsqe; 143 144 #define ns_rsqe_vpi(ns_rsqep) \ 145 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16) 146 #define ns_rsqe_vci(ns_rsqep) \ 147 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF) 148 149 #define NS_RSQE_VALID 0x80000000 150 #define NS_RSQE_NZGFC 0x00004000 151 #define NS_RSQE_EOPDU 0x00002000 152 #define NS_RSQE_BUFSIZE 0x00001000 153 #define NS_RSQE_CONGESTION 0x00000800 154 #define NS_RSQE_CLP 0x00000400 155 #define NS_RSQE_CRCERR 0x00000200 156 157 #define NS_RSQE_BUFSIZE_SM 0x00000000 158 #define NS_RSQE_BUFSIZE_LG 0x00001000 159 160 #define ns_rsqe_valid(ns_rsqep) \ 161 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID) 162 #define ns_rsqe_nzgfc(ns_rsqep) \ 163 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC) 164 #define ns_rsqe_eopdu(ns_rsqep) \ 165 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU) 166 #define ns_rsqe_bufsize(ns_rsqep) \ 167 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE) 168 #define ns_rsqe_congestion(ns_rsqep) \ 169 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION) 170 #define ns_rsqe_clp(ns_rsqep) \ 171 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP) 172 #define ns_rsqe_crcerr(ns_rsqep) \ 173 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR) 174 175 #define ns_rsqe_cellcount(ns_rsqep) \ 176 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF) 177 #define ns_rsqe_init(ns_rsqep) \ 178 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000)) 179 180 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16) 181 #define NS_RSQ_ALIGNMENT NS_RSQSIZE 182 183 184 185 /* RCQ - Raw Cell Queue 186 * 187 * Written by the NICStAR, read by the device driver. 188 */ 189 190 typedef struct cell_payload 191 { 192 u32 word[12]; 193 } cell_payload; 194 195 typedef struct ns_rcqe 196 { 197 u32 word_1; 198 u32 word_2; 199 u32 word_3; 200 u32 word_4; 201 cell_payload payload; 202 } ns_rcqe; 203 204 #define NS_RCQE_SIZE 64 /* bytes */ 205 206 #define ns_rcqe_islast(ns_rcqep) \ 207 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000) 208 #define ns_rcqe_cellheader(ns_rcqep) \ 209 (le32_to_cpu((ns_rcqep)->word_1)) 210 #define ns_rcqe_nextbufhandle(ns_rcqep) \ 211 (le32_to_cpu((ns_rcqep)->word_2)) 212 213 214 215 /* SCQ - Segmentation Channel Queue 216 * 217 * Written by the device driver, read by the NICStAR. 218 */ 219 220 typedef struct ns_scqe 221 { 222 u32 word_1; 223 u32 word_2; 224 u32 word_3; 225 u32 word_4; 226 } ns_scqe; 227 228 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors) 229 or TSR (Transmit Status Requests) */ 230 231 #define NS_SCQE_TYPE_TBD 0x00000000 232 #define NS_SCQE_TYPE_TSR 0x80000000 233 234 235 #define NS_TBD_EOPDU 0x40000000 236 #define NS_TBD_AAL0 0x00000000 237 #define NS_TBD_AAL34 0x04000000 238 #define NS_TBD_AAL5 0x08000000 239 240 #define NS_TBD_VPI_MASK 0x0FF00000 241 #define NS_TBD_VCI_MASK 0x000FFFF0 242 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK) 243 244 #define NS_TBD_VPI_SHIFT 20 245 #define NS_TBD_VCI_SHIFT 4 246 247 #define ns_tbd_mkword_1(flags, m, n, buflen) \ 248 (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen))) 249 #define ns_tbd_mkword_1_novbr(flags, buflen) \ 250 (cpu_to_le32((flags) | (buflen) | 0x00810000)) 251 #define ns_tbd_mkword_3(control, pdulen) \ 252 (cpu_to_le32((control) << 16 | (pdulen))) 253 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \ 254 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp))) 255 256 257 #define NS_TSR_INTENABLE 0x20000000 258 259 #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */ 260 261 #define ns_tsr_mkword_1(flags) \ 262 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags))) 263 #define ns_tsr_mkword_2(scdi, scqi) \ 264 (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi))) 265 266 #define ns_scqe_is_tsr(ns_scqep) \ 267 (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR) 268 269 #define VBR_SCQ_NUM_ENTRIES 512 270 #define VBR_SCQSIZE 8192 271 #define CBR_SCQ_NUM_ENTRIES 64 272 #define CBR_SCQSIZE 1024 273 274 #define NS_SCQE_SIZE 16 275 276 277 278 /* TSQ - Transmit Status Queue 279 * 280 * Written by the NICStAR, read by the device driver. 281 */ 282 283 typedef struct ns_tsi 284 { 285 u32 word_1; 286 u32 word_2; 287 } ns_tsi; 288 289 /* NOTE: The first word can be a status word copied from the TSR which 290 originated the TSI, or a timer overflow indicator. In this last 291 case, the value of the first word is all zeroes. */ 292 293 #define NS_TSI_EMPTY 0x80000000 294 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF 295 296 #define ns_tsi_isempty(ns_tsip) \ 297 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY) 298 #define ns_tsi_gettimestamp(ns_tsip) \ 299 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK) 300 301 #define ns_tsi_init(ns_tsip) \ 302 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY)) 303 304 305 #define NS_TSQSIZE 8192 306 #define NS_TSQ_NUM_ENTRIES 1024 307 #define NS_TSQ_ALIGNMENT 8192 308 309 310 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR 311 312 #define ns_tsi_tmrof(ns_tsip) \ 313 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000) 314 #define ns_tsi_getscdindex(ns_tsip) \ 315 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16) 316 #define ns_tsi_getscqpos(ns_tsip) \ 317 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF) 318 319 320 321 /* NICStAR structures located in local SRAM ***********************************/ 322 323 324 325 /* RCT - Receive Connection Table 326 * 327 * Written by both the NICStAR and the device driver. 328 */ 329 330 typedef struct ns_rcte 331 { 332 u32 word_1; 333 u32 buffer_handle; 334 u32 dma_address; 335 u32 aal5_crc32; 336 } ns_rcte; 337 338 #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */ 339 #define NS_RCTE_NZGFC 0x00100000 340 #define NS_RCTE_CONNECTOPEN 0x00080000 341 #define NS_RCTE_AALMASK 0x00070000 342 #define NS_RCTE_AAL0 0x00000000 343 #define NS_RCTE_AAL34 0x00010000 344 #define NS_RCTE_AAL5 0x00020000 345 #define NS_RCTE_RCQ 0x00030000 346 #define NS_RCTE_RAWCELLINTEN 0x00008000 347 #define NS_RCTE_RXCONSTCELLADDR 0x00004000 348 #define NS_RCTE_BUFFVALID 0x00002000 349 #define NS_RCTE_FBDSIZE 0x00001000 350 #define NS_RCTE_EFCI 0x00000800 351 #define NS_RCTE_CLP 0x00000400 352 #define NS_RCTE_CRCERROR 0x00000200 353 #define NS_RCTE_CELLCOUNT_MASK 0x000001FF 354 355 #define NS_RCTE_FBDSIZE_SM 0x00000000 356 #define NS_RCTE_FBDSIZE_LG 0x00001000 357 358 #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */ 359 360 /* NOTE: We could make macros to contruct the first word of the RCTE, 361 but that doesn't seem to make much sense... */ 362 363 364 365 /* FBD - Free Buffer Descriptor 366 * 367 * Written by the device driver using via the command register. 368 */ 369 370 typedef struct ns_fbd 371 { 372 u32 buffer_handle; 373 u32 dma_address; 374 } ns_fbd; 375 376 377 378 379 /* TST - Transmit Schedule Table 380 * 381 * Written by the device driver. 382 */ 383 384 typedef u32 ns_tste; 385 386 #define NS_TST_OPCODE_MASK 0x60000000 387 388 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */ 389 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */ 390 #define NS_TST_OPCODE_VARIABLE 0x40000000 391 #define NS_TST_OPCODE_END 0x60000000 /* Jump */ 392 393 #define ns_tste_make(opcode, sramad) (opcode | sramad) 394 395 /* NOTE: 396 397 - When the opcode is FIXED, sramad specifies the SRAM address of the 398 SCD for that fixed rate channel. 399 - When the opcode is END, sramad specifies the SRAM address of the 400 location of the next TST entry to read. 401 */ 402 403 404 405 /* SCD - Segmentation Channel Descriptor 406 * 407 * Written by both the device driver and the NICStAR 408 */ 409 410 typedef struct ns_scd 411 { 412 u32 word_1; 413 u32 word_2; 414 u32 partial_aal5_crc; 415 u32 reserved; 416 ns_scqe cache_a; 417 ns_scqe cache_b; 418 } ns_scd; 419 420 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */ 421 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */ 422 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0 423 #define NS_SCD_TAIL_MASK_FIX 0x000003F0 424 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0 425 #define NS_SCD_HEAD_MASK_FIX 0x000003F0 426 #define NS_SCD_XMITFOREVER 0x02000000 427 428 /* NOTE: There are other fields in word 2 of the SCD, but as they should 429 not be needed in the device driver they are not defined here. */ 430 431 432 433 434 /* NICStAR local SRAM memory map **********************************************/ 435 436 437 #define NS_RCT 0x00000 438 #define NS_RCT_32_END 0x03FFF 439 #define NS_RCT_128_END 0x0FFFF 440 #define NS_UNUSED_32 0x04000 441 #define NS_UNUSED_128 0x10000 442 #define NS_UNUSED_END 0x1BFFF 443 #define NS_TST_FRSCD 0x1C000 444 #define NS_TST_FRSCD_END 0x1E7DB 445 #define NS_VRSCD2 0x1E7DC 446 #define NS_VRSCD2_END 0x1E7E7 447 #define NS_VRSCD1 0x1E7E8 448 #define NS_VRSCD1_END 0x1E7F3 449 #define NS_VRSCD0 0x1E7F4 450 #define NS_VRSCD0_END 0x1E7FF 451 #define NS_RXFIFO 0x1E800 452 #define NS_RXFIFO_END 0x1F7FF 453 #define NS_SMFBQ 0x1F800 454 #define NS_SMFBQ_END 0x1FBFF 455 #define NS_LGFBQ 0x1FC00 456 #define NS_LGFBQ_END 0x1FFFF 457 458 459 460 /* NISCtAR operation registers ************************************************/ 461 462 463 /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */ 464 465 enum ns_regs 466 { 467 DR0 = 0x00, /* Data Register 0 R/W*/ 468 DR1 = 0x04, /* Data Register 1 W */ 469 DR2 = 0x08, /* Data Register 2 W */ 470 DR3 = 0x0C, /* Data Register 3 W */ 471 CMD = 0x10, /* Command W */ 472 CFG = 0x14, /* Configuration R/W */ 473 STAT = 0x18, /* Status R/W */ 474 RSQB = 0x1C, /* Receive Status Queue Base W */ 475 RSQT = 0x20, /* Receive Status Queue Tail R */ 476 RSQH = 0x24, /* Receive Status Queue Head W */ 477 CDC = 0x28, /* Cell Drop Counter R/clear */ 478 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */ 479 ICC = 0x30, /* Invalid Cell Count R/clear */ 480 RAWCT = 0x34, /* Raw Cell Tail R */ 481 TMR = 0x38, /* Timer R */ 482 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */ 483 TSQB = 0x40, /* Transmit Status Queue Base W */ 484 TSQT = 0x44, /* Transmit Status Queue Tail R */ 485 TSQH = 0x48, /* Transmit Status Queue Head W */ 486 GP = 0x4C, /* General Purpose R/W */ 487 VPM = 0x50 /* VPI/VCI Mask W */ 488 }; 489 490 491 /* NICStAR commands issued to the CMD register ********************************/ 492 493 494 /* Top 4 bits are command opcode, lower 28 are parameters. */ 495 496 #define NS_CMD_NO_OPERATION 0x00000000 497 /* params always 0 */ 498 499 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000 500 /* b19{1=open,0=close} b18-2{SRAM addr} */ 501 502 #define NS_CMD_WRITE_SRAM 0x40000000 503 /* b18-2{SRAM addr} b1-0{burst size} */ 504 505 #define NS_CMD_READ_SRAM 0x50000000 506 /* b18-2{SRAM addr} */ 507 508 #define NS_CMD_WRITE_FREEBUFQ 0x60000000 509 /* b0{large buf indicator} */ 510 511 #define NS_CMD_READ_UTILITY 0x80000000 512 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ 513 514 #define NS_CMD_WRITE_UTILITY 0x90000000 515 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ 516 517 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000) 518 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION 519 520 521 /* NICStAR configuration bits *************************************************/ 522 523 #define NS_CFG_SWRST 0x80000000 /* Software Reset */ 524 #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */ 525 #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */ 526 #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */ 527 #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue 528 Interrupt Enable */ 529 #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */ 530 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */ 531 #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */ 532 #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */ 533 #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */ 534 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */ 535 #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt 536 Handling */ 537 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */ 538 #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full 539 Interrupt Enable */ 540 #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */ 541 #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt 542 Enable */ 543 #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ 544 #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt 545 Enable */ 546 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt 547 Enable */ 548 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */ 549 #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full 550 Interrupt Enable */ 551 #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ 552 553 #define NS_CFG_SMBUFSIZE_48 0x00000000 554 #define NS_CFG_SMBUFSIZE_96 0x08000000 555 #define NS_CFG_SMBUFSIZE_240 0x10000000 556 #define NS_CFG_SMBUFSIZE_2048 0x18000000 557 558 #define NS_CFG_LGBUFSIZE_2048 0x00000000 559 #define NS_CFG_LGBUFSIZE_4096 0x02000000 560 #define NS_CFG_LGBUFSIZE_8192 0x04000000 561 #define NS_CFG_LGBUFSIZE_16384 0x06000000 562 563 #define NS_CFG_RSQSIZE_2048 0x00000000 564 #define NS_CFG_RSQSIZE_4096 0x00400000 565 #define NS_CFG_RSQSIZE_8192 0x00800000 566 567 #define NS_CFG_VPIBITS_0 0x00000000 568 #define NS_CFG_VPIBITS_1 0x00040000 569 #define NS_CFG_VPIBITS_2 0x00080000 570 #define NS_CFG_VPIBITS_8 0x000C0000 571 572 #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000 573 #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000 574 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000 575 576 #define NS_CFG_RXINT_NOINT 0x00000000 577 #define NS_CFG_RXINT_NODELAY 0x00001000 578 #define NS_CFG_RXINT_314US 0x00002000 579 #define NS_CFG_RXINT_624US 0x00003000 580 #define NS_CFG_RXINT_899US 0x00004000 581 582 583 /* NICStAR STATus bits ********************************************************/ 584 585 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */ 586 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */ 587 #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */ 588 #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */ 589 #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */ 590 #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */ 591 #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */ 592 #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */ 593 #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */ 594 #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */ 595 #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */ 596 #define NS_STAT_EOPDU 0x00000020 /* End of PDU */ 597 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ 598 #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */ 599 #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */ 600 #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */ 601 602 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23) 603 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15) 604 605 606 607 /* #defines which depend on other #defines ************************************/ 608 609 610 #define NS_TST0 NS_TST_FRSCD 611 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1) 612 613 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1) 614 #define NS_FRSCD_SIZE 12 /* 12 dwords */ 615 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE) 616 617 #if (NS_SMBUFSIZE == 48) 618 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48 619 #elif (NS_SMBUFSIZE == 96) 620 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96 621 #elif (NS_SMBUFSIZE == 240) 622 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240 623 #elif (NS_SMBUFSIZE == 2048) 624 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048 625 #else 626 #error NS_SMBUFSIZE is incorrect in nicstar.h 627 #endif /* NS_SMBUFSIZE */ 628 629 #if (NS_LGBUFSIZE == 2048) 630 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048 631 #elif (NS_LGBUFSIZE == 4096) 632 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096 633 #elif (NS_LGBUFSIZE == 8192) 634 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192 635 #elif (NS_LGBUFSIZE == 16384) 636 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384 637 #else 638 #error NS_LGBUFSIZE is incorrect in nicstar.h 639 #endif /* NS_LGBUFSIZE */ 640 641 #if (NS_RSQSIZE == 2048) 642 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048 643 #elif (NS_RSQSIZE == 4096) 644 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096 645 #elif (NS_RSQSIZE == 8192) 646 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192 647 #else 648 #error NS_RSQSIZE is incorrect in nicstar.h 649 #endif /* NS_RSQSIZE */ 650 651 #if (NS_VPIBITS == 0) 652 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0 653 #elif (NS_VPIBITS == 1) 654 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1 655 #elif (NS_VPIBITS == 2) 656 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2 657 #elif (NS_VPIBITS == 8) 658 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8 659 #else 660 #error NS_VPIBITS is incorrect in nicstar.h 661 #endif /* NS_VPIBITS */ 662 663 #ifdef RCQ_SUPPORT 664 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE 665 #else 666 #define NS_CFG_RAWIE_OPT 0x00000000 667 #endif /* RCQ_SUPPORT */ 668 669 #ifdef ENABLE_TSQFIE 670 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE 671 #else 672 #define NS_CFG_TSQFIE_OPT 0x00000000 673 #endif /* ENABLE_TSQFIE */ 674 675 676 /* PCI stuff ******************************************************************/ 677 678 #ifndef PCI_VENDOR_ID_IDT 679 #define PCI_VENDOR_ID_IDT 0x111D 680 #endif /* PCI_VENDOR_ID_IDT */ 681 682 #ifndef PCI_DEVICE_ID_IDT_IDT77201 683 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 684 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */ 685 686 687 688 /* Device driver structures ***************************************************/ 689 690 691 struct ns_skb_cb { 692 u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */ 693 }; 694 695 #define NS_SKB_CB(skb) ((struct ns_skb_cb *)((skb)->cb)) 696 697 typedef struct tsq_info 698 { 699 void *org; 700 ns_tsi *base; 701 ns_tsi *next; 702 ns_tsi *last; 703 } tsq_info; 704 705 706 typedef struct scq_info 707 { 708 void *org; 709 ns_scqe *base; 710 ns_scqe *last; 711 ns_scqe *next; 712 volatile ns_scqe *tail; /* Not related to the nicstar register */ 713 unsigned num_entries; 714 struct sk_buff **skb; /* Pointer to an array of pointers 715 to the sk_buffs used for tx */ 716 u32 scd; /* SRAM address of the corresponding 717 SCD */ 718 int tbd_count; /* Only meaningful on variable rate */ 719 wait_queue_head_t scqfull_waitq; 720 volatile char full; /* SCQ full indicator */ 721 spinlock_t lock; /* SCQ spinlock */ 722 } scq_info; 723 724 725 726 typedef struct rsq_info 727 { 728 void *org; 729 ns_rsqe *base; 730 ns_rsqe *next; 731 ns_rsqe *last; 732 } rsq_info; 733 734 735 typedef struct skb_pool 736 { 737 volatile int count; /* number of buffers in the queue */ 738 struct sk_buff_head queue; 739 } skb_pool; 740 741 /* NOTE: for small and large buffer pools, the count is not used, as the 742 actual value used for buffer management is the one read from the 743 card. */ 744 745 746 typedef struct vc_map 747 { 748 volatile unsigned int tx:1; /* TX vc? */ 749 volatile unsigned int rx:1; /* RX vc? */ 750 struct atm_vcc *tx_vcc, *rx_vcc; 751 struct sk_buff *rx_iov; /* RX iovector skb */ 752 scq_info *scq; /* To keep track of the SCQ */ 753 u32 cbr_scd; /* SRAM address of the corresponding 754 SCD. 0x00000000 for UBR/VBR/ABR */ 755 int tbd_count; 756 } vc_map; 757 758 759 struct ns_skb_data 760 { 761 struct atm_vcc *vcc; 762 int iovcnt; 763 }; 764 765 #define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb)) 766 767 768 typedef struct ns_dev 769 { 770 int index; /* Card ID to the device driver */ 771 int sram_size; /* In k x 32bit words. 32 or 128 */ 772 void __iomem *membase; /* Card's memory base address */ 773 unsigned long max_pcr; 774 int rct_size; /* Number of entries */ 775 int vpibits; 776 int vcibits; 777 struct pci_dev *pcidev; 778 struct atm_dev *atmdev; 779 tsq_info tsq; 780 rsq_info rsq; 781 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */ 782 skb_pool sbpool; /* Small buffers */ 783 skb_pool lbpool; /* Large buffers */ 784 skb_pool hbpool; /* Pre-allocated huge buffers */ 785 skb_pool iovpool; /* iovector buffers */ 786 volatile int efbie; /* Empty free buf. queue int. enabled */ 787 volatile u32 tst_addr; /* SRAM address of the TST in use */ 788 volatile int tst_free_entries; 789 vc_map vcmap[NS_MAX_RCTSIZE]; 790 vc_map *tste2vc[NS_TST_NUM_ENTRIES]; 791 vc_map *scd2vc[NS_FRSCD_NUM]; 792 buf_nr sbnr; 793 buf_nr lbnr; 794 buf_nr hbnr; 795 buf_nr iovnr; 796 int sbfqc; 797 int lbfqc; 798 u32 sm_handle; 799 u32 sm_addr; 800 u32 lg_handle; 801 u32 lg_addr; 802 struct sk_buff *rcbuf; /* Current raw cell buffer */ 803 u32 rawch; /* Raw cell queue head */ 804 unsigned intcnt; /* Interrupt counter */ 805 spinlock_t int_lock; /* Interrupt lock */ 806 spinlock_t res_lock; /* Card resource lock */ 807 } ns_dev; 808 809 810 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding 811 CBR vc. If the entry is not allocated, it must be NULL. 812 813 There are two TSTs so the driver can modify them on the fly 814 without stopping the transmission. 815 816 scd2vc allows us to find out unused fixed rate SCDs, because 817 they must have a NULL pointer here. */ 818 819 820 #endif /* _LINUX_NICSTAR_H_ */ 821