1 /* 2 * nicstar.c 3 * 4 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards. 5 * 6 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME. 7 * It was taken from the frle-0.22 device driver. 8 * As the file doesn't have a copyright notice, in the file 9 * nicstarmac.copyright I put the copyright notice from the 10 * frle-0.22 device driver. 11 * Some code is based on the nicstar driver by M. Welsh. 12 * 13 * Author: Rui Prior (rprior@inescn.pt) 14 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 15 * 16 * 17 * (C) INESC 1999 18 */ 19 20 /* 21 * IMPORTANT INFORMATION 22 * 23 * There are currently three types of spinlocks: 24 * 25 * 1 - Per card interrupt spinlock (to protect structures and such) 26 * 2 - Per SCQ scq spinlock 27 * 3 - Per card resource spinlock (to access registers, etc.) 28 * 29 * These must NEVER be grabbed in reverse order. 30 * 31 */ 32 33 /* Header files */ 34 35 #include <linux/module.h> 36 #include <linux/kernel.h> 37 #include <linux/skbuff.h> 38 #include <linux/atmdev.h> 39 #include <linux/atm.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/types.h> 43 #include <linux/string.h> 44 #include <linux/delay.h> 45 #include <linux/init.h> 46 #include <linux/sched.h> 47 #include <linux/timer.h> 48 #include <linux/interrupt.h> 49 #include <linux/bitops.h> 50 #include <linux/slab.h> 51 #include <linux/idr.h> 52 #include <asm/io.h> 53 #include <asm/uaccess.h> 54 #include <linux/atomic.h> 55 #include <linux/etherdevice.h> 56 #include "nicstar.h" 57 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 58 #include "suni.h" 59 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 60 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 61 #include "idt77105.h" 62 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 63 64 /* Additional code */ 65 66 #include "nicstarmac.c" 67 68 /* Configurable parameters */ 69 70 #undef PHY_LOOPBACK 71 #undef TX_DEBUG 72 #undef RX_DEBUG 73 #undef GENERAL_DEBUG 74 #undef EXTRA_DEBUG 75 76 /* Do not touch these */ 77 78 #ifdef TX_DEBUG 79 #define TXPRINTK(args...) printk(args) 80 #else 81 #define TXPRINTK(args...) 82 #endif /* TX_DEBUG */ 83 84 #ifdef RX_DEBUG 85 #define RXPRINTK(args...) printk(args) 86 #else 87 #define RXPRINTK(args...) 88 #endif /* RX_DEBUG */ 89 90 #ifdef GENERAL_DEBUG 91 #define PRINTK(args...) printk(args) 92 #else 93 #define PRINTK(args...) 94 #endif /* GENERAL_DEBUG */ 95 96 #ifdef EXTRA_DEBUG 97 #define XPRINTK(args...) printk(args) 98 #else 99 #define XPRINTK(args...) 100 #endif /* EXTRA_DEBUG */ 101 102 /* Macros */ 103 104 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ) 105 106 #define NS_DELAY mdelay(1) 107 108 #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b))) 109 110 #ifndef ATM_SKB 111 #define ATM_SKB(s) (&(s)->atm) 112 #endif 113 114 #define scq_virt_to_bus(scq, p) \ 115 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org)) 116 117 /* Function declarations */ 118 119 static u32 ns_read_sram(ns_dev * card, u32 sram_address); 120 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 121 int count); 122 static int ns_init_card(int i, struct pci_dev *pcidev); 123 static void ns_init_card_error(ns_dev * card, int error); 124 static scq_info *get_scq(ns_dev *card, int size, u32 scd); 125 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc); 126 static void push_rxbufs(ns_dev *, struct sk_buff *); 127 static irqreturn_t ns_irq_handler(int irq, void *dev_id); 128 static int ns_open(struct atm_vcc *vcc); 129 static void ns_close(struct atm_vcc *vcc); 130 static void fill_tst(ns_dev * card, int n, vc_map * vc); 131 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb); 132 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 133 struct sk_buff *skb); 134 static void process_tsq(ns_dev * card); 135 static void drain_scq(ns_dev * card, scq_info * scq, int pos); 136 static void process_rsq(ns_dev * card); 137 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe); 138 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb); 139 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count); 140 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb); 141 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb); 142 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb); 143 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page); 144 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg); 145 #ifdef EXTRA_DEBUG 146 static void which_list(ns_dev * card, struct sk_buff *skb); 147 #endif 148 static void ns_poll(unsigned long arg); 149 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 150 unsigned long addr); 151 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr); 152 153 /* Global variables */ 154 155 static struct ns_dev *cards[NS_MAX_CARDS]; 156 static unsigned num_cards; 157 static struct atmdev_ops atm_ops = { 158 .open = ns_open, 159 .close = ns_close, 160 .ioctl = ns_ioctl, 161 .send = ns_send, 162 .phy_put = ns_phy_put, 163 .phy_get = ns_phy_get, 164 .proc_read = ns_proc_read, 165 .owner = THIS_MODULE, 166 }; 167 168 static struct timer_list ns_timer; 169 static char *mac[NS_MAX_CARDS]; 170 module_param_array(mac, charp, NULL, 0); 171 MODULE_LICENSE("GPL"); 172 173 /* Functions */ 174 175 static int nicstar_init_one(struct pci_dev *pcidev, 176 const struct pci_device_id *ent) 177 { 178 static int index = -1; 179 unsigned int error; 180 181 index++; 182 cards[index] = NULL; 183 184 error = ns_init_card(index, pcidev); 185 if (error) { 186 cards[index--] = NULL; /* don't increment index */ 187 goto err_out; 188 } 189 190 return 0; 191 err_out: 192 return -ENODEV; 193 } 194 195 static void nicstar_remove_one(struct pci_dev *pcidev) 196 { 197 int i, j; 198 ns_dev *card = pci_get_drvdata(pcidev); 199 struct sk_buff *hb; 200 struct sk_buff *iovb; 201 struct sk_buff *lb; 202 struct sk_buff *sb; 203 204 i = card->index; 205 206 if (cards[i] == NULL) 207 return; 208 209 if (card->atmdev->phy && card->atmdev->phy->stop) 210 card->atmdev->phy->stop(card->atmdev); 211 212 /* Stop everything */ 213 writel(0x00000000, card->membase + CFG); 214 215 /* De-register device */ 216 atm_dev_deregister(card->atmdev); 217 218 /* Disable PCI device */ 219 pci_disable_device(pcidev); 220 221 /* Free up resources */ 222 j = 0; 223 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count); 224 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) { 225 dev_kfree_skb_any(hb); 226 j++; 227 } 228 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j); 229 j = 0; 230 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, 231 card->iovpool.count); 232 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) { 233 dev_kfree_skb_any(iovb); 234 j++; 235 } 236 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j); 237 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 238 dev_kfree_skb_any(lb); 239 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 240 dev_kfree_skb_any(sb); 241 free_scq(card, card->scq0, NULL); 242 for (j = 0; j < NS_FRSCD_NUM; j++) { 243 if (card->scd2vc[j] != NULL) 244 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc); 245 } 246 idr_destroy(&card->idr); 247 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT, 248 card->rsq.org, card->rsq.dma); 249 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT, 250 card->tsq.org, card->tsq.dma); 251 free_irq(card->pcidev->irq, card); 252 iounmap(card->membase); 253 kfree(card); 254 } 255 256 static struct pci_device_id nicstar_pci_tbl[] = { 257 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 }, 258 {0,} /* terminate list */ 259 }; 260 261 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl); 262 263 static struct pci_driver nicstar_driver = { 264 .name = "nicstar", 265 .id_table = nicstar_pci_tbl, 266 .probe = nicstar_init_one, 267 .remove = nicstar_remove_one, 268 }; 269 270 static int __init nicstar_init(void) 271 { 272 unsigned error = 0; /* Initialized to remove compile warning */ 273 274 XPRINTK("nicstar: nicstar_init() called.\n"); 275 276 error = pci_register_driver(&nicstar_driver); 277 278 TXPRINTK("nicstar: TX debug enabled.\n"); 279 RXPRINTK("nicstar: RX debug enabled.\n"); 280 PRINTK("nicstar: General debug enabled.\n"); 281 #ifdef PHY_LOOPBACK 282 printk("nicstar: using PHY loopback.\n"); 283 #endif /* PHY_LOOPBACK */ 284 XPRINTK("nicstar: nicstar_init() returned.\n"); 285 286 if (!error) { 287 init_timer(&ns_timer); 288 ns_timer.expires = jiffies + NS_POLL_PERIOD; 289 ns_timer.data = 0UL; 290 ns_timer.function = ns_poll; 291 add_timer(&ns_timer); 292 } 293 294 return error; 295 } 296 297 static void __exit nicstar_cleanup(void) 298 { 299 XPRINTK("nicstar: nicstar_cleanup() called.\n"); 300 301 del_timer(&ns_timer); 302 303 pci_unregister_driver(&nicstar_driver); 304 305 XPRINTK("nicstar: nicstar_cleanup() returned.\n"); 306 } 307 308 static u32 ns_read_sram(ns_dev * card, u32 sram_address) 309 { 310 unsigned long flags; 311 u32 data; 312 sram_address <<= 2; 313 sram_address &= 0x0007FFFC; /* address must be dword aligned */ 314 sram_address |= 0x50000000; /* SRAM read command */ 315 spin_lock_irqsave(&card->res_lock, flags); 316 while (CMD_BUSY(card)) ; 317 writel(sram_address, card->membase + CMD); 318 while (CMD_BUSY(card)) ; 319 data = readl(card->membase + DR0); 320 spin_unlock_irqrestore(&card->res_lock, flags); 321 return data; 322 } 323 324 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 325 int count) 326 { 327 unsigned long flags; 328 int i, c; 329 count--; /* count range now is 0..3 instead of 1..4 */ 330 c = count; 331 c <<= 2; /* to use increments of 4 */ 332 spin_lock_irqsave(&card->res_lock, flags); 333 while (CMD_BUSY(card)) ; 334 for (i = 0; i <= c; i += 4) 335 writel(*(value++), card->membase + i); 336 /* Note: DR# registers are the first 4 dwords in nicstar's memspace, 337 so card->membase + DR0 == card->membase */ 338 sram_address <<= 2; 339 sram_address &= 0x0007FFFC; 340 sram_address |= (0x40000000 | count); 341 writel(sram_address, card->membase + CMD); 342 spin_unlock_irqrestore(&card->res_lock, flags); 343 } 344 345 static int ns_init_card(int i, struct pci_dev *pcidev) 346 { 347 int j; 348 struct ns_dev *card = NULL; 349 unsigned char pci_latency; 350 unsigned error; 351 u32 data; 352 u32 u32d[4]; 353 u32 ns_cfg_rctsize; 354 int bcount; 355 unsigned long membase; 356 357 error = 0; 358 359 if (pci_enable_device(pcidev)) { 360 printk("nicstar%d: can't enable PCI device\n", i); 361 error = 2; 362 ns_init_card_error(card, error); 363 return error; 364 } 365 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) { 366 printk(KERN_WARNING 367 "nicstar%d: No suitable DMA available.\n", i); 368 error = 2; 369 ns_init_card_error(card, error); 370 return error; 371 } 372 373 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) { 374 printk 375 ("nicstar%d: can't allocate memory for device structure.\n", 376 i); 377 error = 2; 378 ns_init_card_error(card, error); 379 return error; 380 } 381 cards[i] = card; 382 spin_lock_init(&card->int_lock); 383 spin_lock_init(&card->res_lock); 384 385 pci_set_drvdata(pcidev, card); 386 387 card->index = i; 388 card->atmdev = NULL; 389 card->pcidev = pcidev; 390 membase = pci_resource_start(pcidev, 1); 391 card->membase = ioremap(membase, NS_IOREMAP_SIZE); 392 if (!card->membase) { 393 printk("nicstar%d: can't ioremap() membase.\n", i); 394 error = 3; 395 ns_init_card_error(card, error); 396 return error; 397 } 398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase); 399 400 pci_set_master(pcidev); 401 402 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) { 403 printk("nicstar%d: can't read PCI latency timer.\n", i); 404 error = 6; 405 ns_init_card_error(card, error); 406 return error; 407 } 408 #ifdef NS_PCI_LATENCY 409 if (pci_latency < NS_PCI_LATENCY) { 410 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, 411 NS_PCI_LATENCY); 412 for (j = 1; j < 4; j++) { 413 if (pci_write_config_byte 414 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0) 415 break; 416 } 417 if (j == 4) { 418 printk 419 ("nicstar%d: can't set PCI latency timer to %d.\n", 420 i, NS_PCI_LATENCY); 421 error = 7; 422 ns_init_card_error(card, error); 423 return error; 424 } 425 } 426 #endif /* NS_PCI_LATENCY */ 427 428 /* Clear timer overflow */ 429 data = readl(card->membase + STAT); 430 if (data & NS_STAT_TMROF) 431 writel(NS_STAT_TMROF, card->membase + STAT); 432 433 /* Software reset */ 434 writel(NS_CFG_SWRST, card->membase + CFG); 435 NS_DELAY; 436 writel(0x00000000, card->membase + CFG); 437 438 /* PHY reset */ 439 writel(0x00000008, card->membase + GP); 440 NS_DELAY; 441 writel(0x00000001, card->membase + GP); 442 NS_DELAY; 443 while (CMD_BUSY(card)) ; 444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ 445 NS_DELAY; 446 447 /* Detect PHY type */ 448 while (CMD_BUSY(card)) ; 449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); 450 while (CMD_BUSY(card)) ; 451 data = readl(card->membase + DR0); 452 switch (data) { 453 case 0x00000009: 454 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i); 455 card->max_pcr = ATM_25_PCR; 456 while (CMD_BUSY(card)) ; 457 writel(0x00000008, card->membase + DR0); 458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); 459 /* Clear an eventual pending interrupt */ 460 writel(NS_STAT_SFBQF, card->membase + STAT); 461 #ifdef PHY_LOOPBACK 462 while (CMD_BUSY(card)) ; 463 writel(0x00000022, card->membase + DR0); 464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); 465 #endif /* PHY_LOOPBACK */ 466 break; 467 case 0x00000030: 468 case 0x00000031: 469 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i); 470 card->max_pcr = ATM_OC3_PCR; 471 #ifdef PHY_LOOPBACK 472 while (CMD_BUSY(card)) ; 473 writel(0x00000002, card->membase + DR0); 474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); 475 #endif /* PHY_LOOPBACK */ 476 break; 477 default: 478 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data); 479 error = 8; 480 ns_init_card_error(card, error); 481 return error; 482 } 483 writel(0x00000000, card->membase + GP); 484 485 /* Determine SRAM size */ 486 data = 0x76543210; 487 ns_write_sram(card, 0x1C003, &data, 1); 488 data = 0x89ABCDEF; 489 ns_write_sram(card, 0x14003, &data, 1); 490 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF && 491 ns_read_sram(card, 0x1C003) == 0x76543210) 492 card->sram_size = 128; 493 else 494 card->sram_size = 32; 495 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size); 496 497 card->rct_size = NS_MAX_RCTSIZE; 498 499 #if (NS_MAX_RCTSIZE == 4096) 500 if (card->sram_size == 128) 501 printk 502 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", 503 i); 504 #elif (NS_MAX_RCTSIZE == 16384) 505 if (card->sram_size == 32) { 506 printk 507 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", 508 i); 509 card->rct_size = 4096; 510 } 511 #else 512 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c 513 #endif 514 515 card->vpibits = NS_VPIBITS; 516 if (card->rct_size == 4096) 517 card->vcibits = 12 - NS_VPIBITS; 518 else /* card->rct_size == 16384 */ 519 card->vcibits = 14 - NS_VPIBITS; 520 521 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */ 522 if (mac[i] == NULL) 523 nicstar_init_eprom(card->membase); 524 525 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */ 526 writel(0x00000000, card->membase + VPM); 527 528 /* Initialize TSQ */ 529 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev, 530 NS_TSQSIZE + NS_TSQ_ALIGNMENT, 531 &card->tsq.dma, GFP_KERNEL); 532 if (card->tsq.org == NULL) { 533 printk("nicstar%d: can't allocate TSQ.\n", i); 534 error = 10; 535 ns_init_card_error(card, error); 536 return error; 537 } 538 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT); 539 card->tsq.next = card->tsq.base; 540 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); 541 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++) 542 ns_tsi_init(card->tsq.base + j); 543 writel(0x00000000, card->membase + TSQH); 544 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB); 545 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base); 546 547 /* Initialize RSQ */ 548 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev, 549 NS_RSQSIZE + NS_RSQ_ALIGNMENT, 550 &card->rsq.dma, GFP_KERNEL); 551 if (card->rsq.org == NULL) { 552 printk("nicstar%d: can't allocate RSQ.\n", i); 553 error = 11; 554 ns_init_card_error(card, error); 555 return error; 556 } 557 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT); 558 card->rsq.next = card->rsq.base; 559 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); 560 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++) 561 ns_rsqe_init(card->rsq.base + j); 562 writel(0x00000000, card->membase + RSQH); 563 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB); 564 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base); 565 566 /* Initialize SCQ0, the only VBR SCQ used */ 567 card->scq1 = NULL; 568 card->scq2 = NULL; 569 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0); 570 if (card->scq0 == NULL) { 571 printk("nicstar%d: can't get SCQ0.\n", i); 572 error = 12; 573 ns_init_card_error(card, error); 574 return error; 575 } 576 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base); 577 u32d[1] = (u32) 0x00000000; 578 u32d[2] = (u32) 0xffffffff; 579 u32d[3] = (u32) 0x00000000; 580 ns_write_sram(card, NS_VRSCD0, u32d, 4); 581 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */ 582 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */ 583 card->scq0->scd = NS_VRSCD0; 584 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base); 585 586 /* Initialize TSTs */ 587 card->tst_addr = NS_TST0; 588 card->tst_free_entries = NS_TST_NUM_ENTRIES; 589 data = NS_TST_OPCODE_VARIABLE; 590 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 591 ns_write_sram(card, NS_TST0 + j, &data, 1); 592 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0); 593 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1); 594 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 595 ns_write_sram(card, NS_TST1 + j, &data, 1); 596 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1); 597 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1); 598 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 599 card->tste2vc[j] = NULL; 600 writel(NS_TST0 << 2, card->membase + TSTB); 601 602 /* Initialize RCT. AAL type is set on opening the VC. */ 603 #ifdef RCQ_SUPPORT 604 u32d[0] = NS_RCTE_RAWCELLINTEN; 605 #else 606 u32d[0] = 0x00000000; 607 #endif /* RCQ_SUPPORT */ 608 u32d[1] = 0x00000000; 609 u32d[2] = 0x00000000; 610 u32d[3] = 0xFFFFFFFF; 611 for (j = 0; j < card->rct_size; j++) 612 ns_write_sram(card, j * 4, u32d, 4); 613 614 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map)); 615 616 for (j = 0; j < NS_FRSCD_NUM; j++) 617 card->scd2vc[j] = NULL; 618 619 /* Initialize buffer levels */ 620 card->sbnr.min = MIN_SB; 621 card->sbnr.init = NUM_SB; 622 card->sbnr.max = MAX_SB; 623 card->lbnr.min = MIN_LB; 624 card->lbnr.init = NUM_LB; 625 card->lbnr.max = MAX_LB; 626 card->iovnr.min = MIN_IOVB; 627 card->iovnr.init = NUM_IOVB; 628 card->iovnr.max = MAX_IOVB; 629 card->hbnr.min = MIN_HB; 630 card->hbnr.init = NUM_HB; 631 card->hbnr.max = MAX_HB; 632 633 card->sm_handle = NULL; 634 card->sm_addr = 0x00000000; 635 card->lg_handle = NULL; 636 card->lg_addr = 0x00000000; 637 638 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */ 639 640 idr_init(&card->idr); 641 642 /* Pre-allocate some huge buffers */ 643 skb_queue_head_init(&card->hbpool.queue); 644 card->hbpool.count = 0; 645 for (j = 0; j < NUM_HB; j++) { 646 struct sk_buff *hb; 647 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 648 if (hb == NULL) { 649 printk 650 ("nicstar%d: can't allocate %dth of %d huge buffers.\n", 651 i, j, NUM_HB); 652 error = 13; 653 ns_init_card_error(card, error); 654 return error; 655 } 656 NS_PRV_BUFTYPE(hb) = BUF_NONE; 657 skb_queue_tail(&card->hbpool.queue, hb); 658 card->hbpool.count++; 659 } 660 661 /* Allocate large buffers */ 662 skb_queue_head_init(&card->lbpool.queue); 663 card->lbpool.count = 0; /* Not used */ 664 for (j = 0; j < NUM_LB; j++) { 665 struct sk_buff *lb; 666 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 667 if (lb == NULL) { 668 printk 669 ("nicstar%d: can't allocate %dth of %d large buffers.\n", 670 i, j, NUM_LB); 671 error = 14; 672 ns_init_card_error(card, error); 673 return error; 674 } 675 NS_PRV_BUFTYPE(lb) = BUF_LG; 676 skb_queue_tail(&card->lbpool.queue, lb); 677 skb_reserve(lb, NS_SMBUFSIZE); 678 push_rxbufs(card, lb); 679 /* Due to the implementation of push_rxbufs() this is 1, not 0 */ 680 if (j == 1) { 681 card->rcbuf = lb; 682 card->rawcell = (struct ns_rcqe *) lb->data; 683 card->rawch = NS_PRV_DMA(lb); 684 } 685 } 686 /* Test for strange behaviour which leads to crashes */ 687 if ((bcount = 688 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) { 689 printk 690 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n", 691 i, j, bcount); 692 error = 14; 693 ns_init_card_error(card, error); 694 return error; 695 } 696 697 /* Allocate small buffers */ 698 skb_queue_head_init(&card->sbpool.queue); 699 card->sbpool.count = 0; /* Not used */ 700 for (j = 0; j < NUM_SB; j++) { 701 struct sk_buff *sb; 702 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 703 if (sb == NULL) { 704 printk 705 ("nicstar%d: can't allocate %dth of %d small buffers.\n", 706 i, j, NUM_SB); 707 error = 15; 708 ns_init_card_error(card, error); 709 return error; 710 } 711 NS_PRV_BUFTYPE(sb) = BUF_SM; 712 skb_queue_tail(&card->sbpool.queue, sb); 713 skb_reserve(sb, NS_AAL0_HEADER); 714 push_rxbufs(card, sb); 715 } 716 /* Test for strange behaviour which leads to crashes */ 717 if ((bcount = 718 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) { 719 printk 720 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n", 721 i, j, bcount); 722 error = 15; 723 ns_init_card_error(card, error); 724 return error; 725 } 726 727 /* Allocate iovec buffers */ 728 skb_queue_head_init(&card->iovpool.queue); 729 card->iovpool.count = 0; 730 for (j = 0; j < NUM_IOVB; j++) { 731 struct sk_buff *iovb; 732 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 733 if (iovb == NULL) { 734 printk 735 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n", 736 i, j, NUM_IOVB); 737 error = 16; 738 ns_init_card_error(card, error); 739 return error; 740 } 741 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 742 skb_queue_tail(&card->iovpool.queue, iovb); 743 card->iovpool.count++; 744 } 745 746 /* Configure NICStAR */ 747 if (card->rct_size == 4096) 748 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES; 749 else /* (card->rct_size == 16384) */ 750 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES; 751 752 card->efbie = 1; 753 754 card->intcnt = 0; 755 if (request_irq 756 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) { 757 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq); 758 error = 9; 759 ns_init_card_error(card, error); 760 return error; 761 } 762 763 /* Register device */ 764 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops, 765 -1, NULL); 766 if (card->atmdev == NULL) { 767 printk("nicstar%d: can't register device.\n", i); 768 error = 17; 769 ns_init_card_error(card, error); 770 return error; 771 } 772 773 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) { 774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, 775 card->atmdev->esi, 6); 776 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) { 777 nicstar_read_eprom(card->membase, 778 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT, 779 card->atmdev->esi, 6); 780 } 781 } 782 783 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi); 784 785 card->atmdev->dev_data = card; 786 card->atmdev->ci_range.vpi_bits = card->vpibits; 787 card->atmdev->ci_range.vci_bits = card->vcibits; 788 card->atmdev->link_rate = card->max_pcr; 789 card->atmdev->phy = NULL; 790 791 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 792 if (card->max_pcr == ATM_OC3_PCR) 793 suni_init(card->atmdev); 794 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 795 796 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 797 if (card->max_pcr == ATM_25_PCR) 798 idt77105_init(card->atmdev); 799 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 800 801 if (card->atmdev->phy && card->atmdev->phy->start) 802 card->atmdev->phy->start(card->atmdev); 803 804 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */ 805 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */ 806 NS_CFG_PHYIE, card->membase + CFG); 807 808 num_cards++; 809 810 return error; 811 } 812 813 static void ns_init_card_error(ns_dev *card, int error) 814 { 815 if (error >= 17) { 816 writel(0x00000000, card->membase + CFG); 817 } 818 if (error >= 16) { 819 struct sk_buff *iovb; 820 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 821 dev_kfree_skb_any(iovb); 822 } 823 if (error >= 15) { 824 struct sk_buff *sb; 825 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 826 dev_kfree_skb_any(sb); 827 free_scq(card, card->scq0, NULL); 828 } 829 if (error >= 14) { 830 struct sk_buff *lb; 831 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 832 dev_kfree_skb_any(lb); 833 } 834 if (error >= 13) { 835 struct sk_buff *hb; 836 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 837 dev_kfree_skb_any(hb); 838 } 839 if (error >= 12) { 840 kfree(card->rsq.org); 841 } 842 if (error >= 11) { 843 kfree(card->tsq.org); 844 } 845 if (error >= 10) { 846 free_irq(card->pcidev->irq, card); 847 } 848 if (error >= 4) { 849 iounmap(card->membase); 850 } 851 if (error >= 3) { 852 pci_disable_device(card->pcidev); 853 kfree(card); 854 } 855 } 856 857 static scq_info *get_scq(ns_dev *card, int size, u32 scd) 858 { 859 scq_info *scq; 860 int i; 861 862 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE) 863 return NULL; 864 865 scq = kmalloc(sizeof(scq_info), GFP_KERNEL); 866 if (!scq) 867 return NULL; 868 scq->org = dma_alloc_coherent(&card->pcidev->dev, 869 2 * size, &scq->dma, GFP_KERNEL); 870 if (!scq->org) { 871 kfree(scq); 872 return NULL; 873 } 874 scq->skb = kmalloc(sizeof(struct sk_buff *) * 875 (size / NS_SCQE_SIZE), GFP_KERNEL); 876 if (!scq->skb) { 877 kfree(scq->org); 878 kfree(scq); 879 return NULL; 880 } 881 scq->num_entries = size / NS_SCQE_SIZE; 882 scq->base = PTR_ALIGN(scq->org, size); 883 scq->next = scq->base; 884 scq->last = scq->base + (scq->num_entries - 1); 885 scq->tail = scq->last; 886 scq->scd = scd; 887 scq->num_entries = size / NS_SCQE_SIZE; 888 scq->tbd_count = 0; 889 init_waitqueue_head(&scq->scqfull_waitq); 890 scq->full = 0; 891 spin_lock_init(&scq->lock); 892 893 for (i = 0; i < scq->num_entries; i++) 894 scq->skb[i] = NULL; 895 896 return scq; 897 } 898 899 /* For variable rate SCQ vcc must be NULL */ 900 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc) 901 { 902 int i; 903 904 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 905 for (i = 0; i < scq->num_entries; i++) { 906 if (scq->skb[i] != NULL) { 907 vcc = ATM_SKB(scq->skb[i])->vcc; 908 if (vcc->pop != NULL) 909 vcc->pop(vcc, scq->skb[i]); 910 else 911 dev_kfree_skb_any(scq->skb[i]); 912 } 913 } else { /* vcc must be != NULL */ 914 915 if (vcc == NULL) { 916 printk 917 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq."); 918 for (i = 0; i < scq->num_entries; i++) 919 dev_kfree_skb_any(scq->skb[i]); 920 } else 921 for (i = 0; i < scq->num_entries; i++) { 922 if (scq->skb[i] != NULL) { 923 if (vcc->pop != NULL) 924 vcc->pop(vcc, scq->skb[i]); 925 else 926 dev_kfree_skb_any(scq->skb[i]); 927 } 928 } 929 } 930 kfree(scq->skb); 931 dma_free_coherent(&card->pcidev->dev, 932 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ? 933 VBR_SCQSIZE : CBR_SCQSIZE), 934 scq->org, scq->dma); 935 kfree(scq); 936 } 937 938 /* The handles passed must be pointers to the sk_buff containing the small 939 or large buffer(s) cast to u32. */ 940 static void push_rxbufs(ns_dev * card, struct sk_buff *skb) 941 { 942 struct sk_buff *handle1, *handle2; 943 int id1, id2; 944 u32 addr1, addr2; 945 u32 stat; 946 unsigned long flags; 947 948 /* *BARF* */ 949 handle2 = NULL; 950 addr2 = 0; 951 handle1 = skb; 952 addr1 = dma_map_single(&card->pcidev->dev, 953 skb->data, 954 (NS_PRV_BUFTYPE(skb) == BUF_SM 955 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 956 DMA_TO_DEVICE); 957 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */ 958 959 #ifdef GENERAL_DEBUG 960 if (!addr1) 961 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", 962 card->index); 963 #endif /* GENERAL_DEBUG */ 964 965 stat = readl(card->membase + STAT); 966 card->sbfqc = ns_stat_sfbqc_get(stat); 967 card->lbfqc = ns_stat_lfbqc_get(stat); 968 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 969 if (!addr2) { 970 if (card->sm_addr) { 971 addr2 = card->sm_addr; 972 handle2 = card->sm_handle; 973 card->sm_addr = 0x00000000; 974 card->sm_handle = NULL; 975 } else { /* (!sm_addr) */ 976 977 card->sm_addr = addr1; 978 card->sm_handle = handle1; 979 } 980 } 981 } else { /* buf_type == BUF_LG */ 982 983 if (!addr2) { 984 if (card->lg_addr) { 985 addr2 = card->lg_addr; 986 handle2 = card->lg_handle; 987 card->lg_addr = 0x00000000; 988 card->lg_handle = NULL; 989 } else { /* (!lg_addr) */ 990 991 card->lg_addr = addr1; 992 card->lg_handle = handle1; 993 } 994 } 995 } 996 997 if (addr2) { 998 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 999 if (card->sbfqc >= card->sbnr.max) { 1000 skb_unlink(handle1, &card->sbpool.queue); 1001 dev_kfree_skb_any(handle1); 1002 skb_unlink(handle2, &card->sbpool.queue); 1003 dev_kfree_skb_any(handle2); 1004 return; 1005 } else 1006 card->sbfqc += 2; 1007 } else { /* (buf_type == BUF_LG) */ 1008 1009 if (card->lbfqc >= card->lbnr.max) { 1010 skb_unlink(handle1, &card->lbpool.queue); 1011 dev_kfree_skb_any(handle1); 1012 skb_unlink(handle2, &card->lbpool.queue); 1013 dev_kfree_skb_any(handle2); 1014 return; 1015 } else 1016 card->lbfqc += 2; 1017 } 1018 1019 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC); 1020 if (id1 < 0) 1021 goto out; 1022 1023 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC); 1024 if (id2 < 0) 1025 goto out; 1026 1027 spin_lock_irqsave(&card->res_lock, flags); 1028 while (CMD_BUSY(card)) ; 1029 writel(addr2, card->membase + DR3); 1030 writel(id2, card->membase + DR2); 1031 writel(addr1, card->membase + DR1); 1032 writel(id1, card->membase + DR0); 1033 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb), 1034 card->membase + CMD); 1035 spin_unlock_irqrestore(&card->res_lock, flags); 1036 1037 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", 1038 card->index, 1039 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"), 1040 addr1, addr2); 1041 } 1042 1043 if (!card->efbie && card->sbfqc >= card->sbnr.min && 1044 card->lbfqc >= card->lbnr.min) { 1045 card->efbie = 1; 1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), 1047 card->membase + CFG); 1048 } 1049 1050 out: 1051 return; 1052 } 1053 1054 static irqreturn_t ns_irq_handler(int irq, void *dev_id) 1055 { 1056 u32 stat_r; 1057 ns_dev *card; 1058 struct atm_dev *dev; 1059 unsigned long flags; 1060 1061 card = (ns_dev *) dev_id; 1062 dev = card->atmdev; 1063 card->intcnt++; 1064 1065 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index); 1066 1067 spin_lock_irqsave(&card->int_lock, flags); 1068 1069 stat_r = readl(card->membase + STAT); 1070 1071 /* Transmit Status Indicator has been written to T. S. Queue */ 1072 if (stat_r & NS_STAT_TSIF) { 1073 TXPRINTK("nicstar%d: TSI interrupt\n", card->index); 1074 process_tsq(card); 1075 writel(NS_STAT_TSIF, card->membase + STAT); 1076 } 1077 1078 /* Incomplete CS-PDU has been transmitted */ 1079 if (stat_r & NS_STAT_TXICP) { 1080 writel(NS_STAT_TXICP, card->membase + STAT); 1081 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n", 1082 card->index); 1083 } 1084 1085 /* Transmit Status Queue 7/8 full */ 1086 if (stat_r & NS_STAT_TSQF) { 1087 writel(NS_STAT_TSQF, card->membase + STAT); 1088 PRINTK("nicstar%d: TSQ full.\n", card->index); 1089 process_tsq(card); 1090 } 1091 1092 /* Timer overflow */ 1093 if (stat_r & NS_STAT_TMROF) { 1094 writel(NS_STAT_TMROF, card->membase + STAT); 1095 PRINTK("nicstar%d: Timer overflow.\n", card->index); 1096 } 1097 1098 /* PHY device interrupt signal active */ 1099 if (stat_r & NS_STAT_PHYI) { 1100 writel(NS_STAT_PHYI, card->membase + STAT); 1101 PRINTK("nicstar%d: PHY interrupt.\n", card->index); 1102 if (dev->phy && dev->phy->interrupt) { 1103 dev->phy->interrupt(dev); 1104 } 1105 } 1106 1107 /* Small Buffer Queue is full */ 1108 if (stat_r & NS_STAT_SFBQF) { 1109 writel(NS_STAT_SFBQF, card->membase + STAT); 1110 printk("nicstar%d: Small free buffer queue is full.\n", 1111 card->index); 1112 } 1113 1114 /* Large Buffer Queue is full */ 1115 if (stat_r & NS_STAT_LFBQF) { 1116 writel(NS_STAT_LFBQF, card->membase + STAT); 1117 printk("nicstar%d: Large free buffer queue is full.\n", 1118 card->index); 1119 } 1120 1121 /* Receive Status Queue is full */ 1122 if (stat_r & NS_STAT_RSQF) { 1123 writel(NS_STAT_RSQF, card->membase + STAT); 1124 printk("nicstar%d: RSQ full.\n", card->index); 1125 process_rsq(card); 1126 } 1127 1128 /* Complete CS-PDU received */ 1129 if (stat_r & NS_STAT_EOPDU) { 1130 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index); 1131 process_rsq(card); 1132 writel(NS_STAT_EOPDU, card->membase + STAT); 1133 } 1134 1135 /* Raw cell received */ 1136 if (stat_r & NS_STAT_RAWCF) { 1137 writel(NS_STAT_RAWCF, card->membase + STAT); 1138 #ifndef RCQ_SUPPORT 1139 printk("nicstar%d: Raw cell received and no support yet...\n", 1140 card->index); 1141 #endif /* RCQ_SUPPORT */ 1142 /* NOTE: the following procedure may keep a raw cell pending until the 1143 next interrupt. As this preliminary support is only meant to 1144 avoid buffer leakage, this is not an issue. */ 1145 while (readl(card->membase + RAWCT) != card->rawch) { 1146 1147 if (ns_rcqe_islast(card->rawcell)) { 1148 struct sk_buff *oldbuf; 1149 1150 oldbuf = card->rcbuf; 1151 card->rcbuf = idr_find(&card->idr, 1152 ns_rcqe_nextbufhandle(card->rawcell)); 1153 card->rawch = NS_PRV_DMA(card->rcbuf); 1154 card->rawcell = (struct ns_rcqe *) 1155 card->rcbuf->data; 1156 recycle_rx_buf(card, oldbuf); 1157 } else { 1158 card->rawch += NS_RCQE_SIZE; 1159 card->rawcell++; 1160 } 1161 } 1162 } 1163 1164 /* Small buffer queue is empty */ 1165 if (stat_r & NS_STAT_SFBQE) { 1166 int i; 1167 struct sk_buff *sb; 1168 1169 writel(NS_STAT_SFBQE, card->membase + STAT); 1170 printk("nicstar%d: Small free buffer queue empty.\n", 1171 card->index); 1172 for (i = 0; i < card->sbnr.min; i++) { 1173 sb = dev_alloc_skb(NS_SMSKBSIZE); 1174 if (sb == NULL) { 1175 writel(readl(card->membase + CFG) & 1176 ~NS_CFG_EFBIE, card->membase + CFG); 1177 card->efbie = 0; 1178 break; 1179 } 1180 NS_PRV_BUFTYPE(sb) = BUF_SM; 1181 skb_queue_tail(&card->sbpool.queue, sb); 1182 skb_reserve(sb, NS_AAL0_HEADER); 1183 push_rxbufs(card, sb); 1184 } 1185 card->sbfqc = i; 1186 process_rsq(card); 1187 } 1188 1189 /* Large buffer queue empty */ 1190 if (stat_r & NS_STAT_LFBQE) { 1191 int i; 1192 struct sk_buff *lb; 1193 1194 writel(NS_STAT_LFBQE, card->membase + STAT); 1195 printk("nicstar%d: Large free buffer queue empty.\n", 1196 card->index); 1197 for (i = 0; i < card->lbnr.min; i++) { 1198 lb = dev_alloc_skb(NS_LGSKBSIZE); 1199 if (lb == NULL) { 1200 writel(readl(card->membase + CFG) & 1201 ~NS_CFG_EFBIE, card->membase + CFG); 1202 card->efbie = 0; 1203 break; 1204 } 1205 NS_PRV_BUFTYPE(lb) = BUF_LG; 1206 skb_queue_tail(&card->lbpool.queue, lb); 1207 skb_reserve(lb, NS_SMBUFSIZE); 1208 push_rxbufs(card, lb); 1209 } 1210 card->lbfqc = i; 1211 process_rsq(card); 1212 } 1213 1214 /* Receive Status Queue is 7/8 full */ 1215 if (stat_r & NS_STAT_RSQAF) { 1216 writel(NS_STAT_RSQAF, card->membase + STAT); 1217 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index); 1218 process_rsq(card); 1219 } 1220 1221 spin_unlock_irqrestore(&card->int_lock, flags); 1222 PRINTK("nicstar%d: end of interrupt service\n", card->index); 1223 return IRQ_HANDLED; 1224 } 1225 1226 static int ns_open(struct atm_vcc *vcc) 1227 { 1228 ns_dev *card; 1229 vc_map *vc; 1230 unsigned long tmpl, modl; 1231 int tcr, tcra; /* target cell rate, and absolute value */ 1232 int n = 0; /* Number of entries in the TST. Initialized to remove 1233 the compiler warning. */ 1234 u32 u32d[4]; 1235 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler 1236 warning. How I wish compilers were clever enough to 1237 tell which variables can truly be used 1238 uninitialized... */ 1239 int inuse; /* tx or rx vc already in use by another vcc */ 1240 short vpi = vcc->vpi; 1241 int vci = vcc->vci; 1242 1243 card = (ns_dev *) vcc->dev->dev_data; 1244 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi, 1245 vci); 1246 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1247 PRINTK("nicstar%d: unsupported AAL.\n", card->index); 1248 return -EINVAL; 1249 } 1250 1251 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1252 vcc->dev_data = vc; 1253 1254 inuse = 0; 1255 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx) 1256 inuse = 1; 1257 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx) 1258 inuse += 2; 1259 if (inuse) { 1260 printk("nicstar%d: %s vci already in use.\n", card->index, 1261 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 1262 return -EINVAL; 1263 } 1264 1265 set_bit(ATM_VF_ADDR, &vcc->flags); 1266 1267 /* NOTE: You are not allowed to modify an open connection's QOS. To change 1268 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes 1269 needed to do that. */ 1270 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) { 1271 scq_info *scq; 1272 1273 set_bit(ATM_VF_PARTIAL, &vcc->flags); 1274 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1275 /* Check requested cell rate and availability of SCD */ 1276 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 1277 && vcc->qos.txtp.min_pcr == 0) { 1278 PRINTK 1279 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n", 1280 card->index); 1281 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1282 clear_bit(ATM_VF_ADDR, &vcc->flags); 1283 return -EINVAL; 1284 } 1285 1286 tcr = atm_pcr_goal(&(vcc->qos.txtp)); 1287 tcra = tcr >= 0 ? tcr : -tcr; 1288 1289 PRINTK("nicstar%d: target cell rate = %d.\n", 1290 card->index, vcc->qos.txtp.max_pcr); 1291 1292 tmpl = 1293 (unsigned long)tcra *(unsigned long) 1294 NS_TST_NUM_ENTRIES; 1295 modl = tmpl % card->max_pcr; 1296 1297 n = (int)(tmpl / card->max_pcr); 1298 if (tcr > 0) { 1299 if (modl > 0) 1300 n++; 1301 } else if (tcr == 0) { 1302 if ((n = 1303 (card->tst_free_entries - 1304 NS_TST_RESERVED)) <= 0) { 1305 PRINTK 1306 ("nicstar%d: no CBR bandwidth free.\n", 1307 card->index); 1308 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1309 clear_bit(ATM_VF_ADDR, &vcc->flags); 1310 return -EINVAL; 1311 } 1312 } 1313 1314 if (n == 0) { 1315 printk 1316 ("nicstar%d: selected bandwidth < granularity.\n", 1317 card->index); 1318 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1319 clear_bit(ATM_VF_ADDR, &vcc->flags); 1320 return -EINVAL; 1321 } 1322 1323 if (n > (card->tst_free_entries - NS_TST_RESERVED)) { 1324 PRINTK 1325 ("nicstar%d: not enough free CBR bandwidth.\n", 1326 card->index); 1327 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1328 clear_bit(ATM_VF_ADDR, &vcc->flags); 1329 return -EINVAL; 1330 } else 1331 card->tst_free_entries -= n; 1332 1333 XPRINTK("nicstar%d: writing %d tst entries.\n", 1334 card->index, n); 1335 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) { 1336 if (card->scd2vc[frscdi] == NULL) { 1337 card->scd2vc[frscdi] = vc; 1338 break; 1339 } 1340 } 1341 if (frscdi == NS_FRSCD_NUM) { 1342 PRINTK 1343 ("nicstar%d: no SCD available for CBR channel.\n", 1344 card->index); 1345 card->tst_free_entries += n; 1346 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1347 clear_bit(ATM_VF_ADDR, &vcc->flags); 1348 return -EBUSY; 1349 } 1350 1351 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE; 1352 1353 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd); 1354 if (scq == NULL) { 1355 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", 1356 card->index); 1357 card->scd2vc[frscdi] = NULL; 1358 card->tst_free_entries += n; 1359 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1360 clear_bit(ATM_VF_ADDR, &vcc->flags); 1361 return -ENOMEM; 1362 } 1363 vc->scq = scq; 1364 u32d[0] = scq_virt_to_bus(scq, scq->base); 1365 u32d[1] = (u32) 0x00000000; 1366 u32d[2] = (u32) 0xffffffff; 1367 u32d[3] = (u32) 0x00000000; 1368 ns_write_sram(card, vc->cbr_scd, u32d, 4); 1369 1370 fill_tst(card, n, vc); 1371 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) { 1372 vc->cbr_scd = 0x00000000; 1373 vc->scq = card->scq0; 1374 } 1375 1376 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1377 vc->tx = 1; 1378 vc->tx_vcc = vcc; 1379 vc->tbd_count = 0; 1380 } 1381 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1382 u32 status; 1383 1384 vc->rx = 1; 1385 vc->rx_vcc = vcc; 1386 vc->rx_iov = NULL; 1387 1388 /* Open the connection in hardware */ 1389 if (vcc->qos.aal == ATM_AAL5) 1390 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN; 1391 else /* vcc->qos.aal == ATM_AAL0 */ 1392 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN; 1393 #ifdef RCQ_SUPPORT 1394 status |= NS_RCTE_RAWCELLINTEN; 1395 #endif /* RCQ_SUPPORT */ 1396 ns_write_sram(card, 1397 NS_RCT + 1398 (vpi << card->vcibits | vci) * 1399 NS_RCT_ENTRY_SIZE, &status, 1); 1400 } 1401 1402 } 1403 1404 set_bit(ATM_VF_READY, &vcc->flags); 1405 return 0; 1406 } 1407 1408 static void ns_close(struct atm_vcc *vcc) 1409 { 1410 vc_map *vc; 1411 ns_dev *card; 1412 u32 data; 1413 int i; 1414 1415 vc = vcc->dev_data; 1416 card = vcc->dev->dev_data; 1417 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index, 1418 (int)vcc->vpi, vcc->vci); 1419 1420 clear_bit(ATM_VF_READY, &vcc->flags); 1421 1422 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1423 u32 addr; 1424 unsigned long flags; 1425 1426 addr = 1427 NS_RCT + 1428 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE; 1429 spin_lock_irqsave(&card->res_lock, flags); 1430 while (CMD_BUSY(card)) ; 1431 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, 1432 card->membase + CMD); 1433 spin_unlock_irqrestore(&card->res_lock, flags); 1434 1435 vc->rx = 0; 1436 if (vc->rx_iov != NULL) { 1437 struct sk_buff *iovb; 1438 u32 stat; 1439 1440 stat = readl(card->membase + STAT); 1441 card->sbfqc = ns_stat_sfbqc_get(stat); 1442 card->lbfqc = ns_stat_lfbqc_get(stat); 1443 1444 PRINTK 1445 ("nicstar%d: closing a VC with pending rx buffers.\n", 1446 card->index); 1447 iovb = vc->rx_iov; 1448 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 1449 NS_PRV_IOVCNT(iovb)); 1450 NS_PRV_IOVCNT(iovb) = 0; 1451 spin_lock_irqsave(&card->int_lock, flags); 1452 recycle_iov_buf(card, iovb); 1453 spin_unlock_irqrestore(&card->int_lock, flags); 1454 vc->rx_iov = NULL; 1455 } 1456 } 1457 1458 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1459 vc->tx = 0; 1460 } 1461 1462 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1463 unsigned long flags; 1464 ns_scqe *scqep; 1465 scq_info *scq; 1466 1467 scq = vc->scq; 1468 1469 for (;;) { 1470 spin_lock_irqsave(&scq->lock, flags); 1471 scqep = scq->next; 1472 if (scqep == scq->base) 1473 scqep = scq->last; 1474 else 1475 scqep--; 1476 if (scqep == scq->tail) { 1477 spin_unlock_irqrestore(&scq->lock, flags); 1478 break; 1479 } 1480 /* If the last entry is not a TSR, place one in the SCQ in order to 1481 be able to completely drain it and then close. */ 1482 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) { 1483 ns_scqe tsr; 1484 u32 scdi, scqi; 1485 u32 data; 1486 int index; 1487 1488 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1489 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1490 scqi = scq->next - scq->base; 1491 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1492 tsr.word_3 = 0x00000000; 1493 tsr.word_4 = 0x00000000; 1494 *scq->next = tsr; 1495 index = (int)scqi; 1496 scq->skb[index] = NULL; 1497 if (scq->next == scq->last) 1498 scq->next = scq->base; 1499 else 1500 scq->next++; 1501 data = scq_virt_to_bus(scq, scq->next); 1502 ns_write_sram(card, scq->scd, &data, 1); 1503 } 1504 spin_unlock_irqrestore(&scq->lock, flags); 1505 schedule(); 1506 } 1507 1508 /* Free all TST entries */ 1509 data = NS_TST_OPCODE_VARIABLE; 1510 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) { 1511 if (card->tste2vc[i] == vc) { 1512 ns_write_sram(card, card->tst_addr + i, &data, 1513 1); 1514 card->tste2vc[i] = NULL; 1515 card->tst_free_entries++; 1516 } 1517 } 1518 1519 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL; 1520 free_scq(card, vc->scq, vcc); 1521 } 1522 1523 /* remove all references to vcc before deleting it */ 1524 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1525 unsigned long flags; 1526 scq_info *scq = card->scq0; 1527 1528 spin_lock_irqsave(&scq->lock, flags); 1529 1530 for (i = 0; i < scq->num_entries; i++) { 1531 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) { 1532 ATM_SKB(scq->skb[i])->vcc = NULL; 1533 atm_return(vcc, scq->skb[i]->truesize); 1534 PRINTK 1535 ("nicstar: deleted pending vcc mapping\n"); 1536 } 1537 } 1538 1539 spin_unlock_irqrestore(&scq->lock, flags); 1540 } 1541 1542 vcc->dev_data = NULL; 1543 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1544 clear_bit(ATM_VF_ADDR, &vcc->flags); 1545 1546 #ifdef RX_DEBUG 1547 { 1548 u32 stat, cfg; 1549 stat = readl(card->membase + STAT); 1550 cfg = readl(card->membase + CFG); 1551 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); 1552 printk 1553 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n", 1554 card->tsq.base, card->tsq.next, 1555 card->tsq.last, readl(card->membase + TSQT)); 1556 printk 1557 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n", 1558 card->rsq.base, card->rsq.next, 1559 card->rsq.last, readl(card->membase + RSQT)); 1560 printk("Empty free buffer queue interrupt %s \n", 1561 card->efbie ? "enabled" : "disabled"); 1562 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n", 1563 ns_stat_sfbqc_get(stat), card->sbpool.count, 1564 ns_stat_lfbqc_get(stat), card->lbpool.count); 1565 printk("hbpool.count = %d iovpool.count = %d \n", 1566 card->hbpool.count, card->iovpool.count); 1567 } 1568 #endif /* RX_DEBUG */ 1569 } 1570 1571 static void fill_tst(ns_dev * card, int n, vc_map * vc) 1572 { 1573 u32 new_tst; 1574 unsigned long cl; 1575 int e, r; 1576 u32 data; 1577 1578 /* It would be very complicated to keep the two TSTs synchronized while 1579 assuring that writes are only made to the inactive TST. So, for now I 1580 will use only one TST. If problems occur, I will change this again */ 1581 1582 new_tst = card->tst_addr; 1583 1584 /* Fill procedure */ 1585 1586 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) { 1587 if (card->tste2vc[e] == NULL) 1588 break; 1589 } 1590 if (e == NS_TST_NUM_ENTRIES) { 1591 printk("nicstar%d: No free TST entries found. \n", card->index); 1592 return; 1593 } 1594 1595 r = n; 1596 cl = NS_TST_NUM_ENTRIES; 1597 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd); 1598 1599 while (r > 0) { 1600 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) { 1601 card->tste2vc[e] = vc; 1602 ns_write_sram(card, new_tst + e, &data, 1); 1603 cl -= NS_TST_NUM_ENTRIES; 1604 r--; 1605 } 1606 1607 if (++e == NS_TST_NUM_ENTRIES) { 1608 e = 0; 1609 } 1610 cl += n; 1611 } 1612 1613 /* End of fill procedure */ 1614 1615 data = ns_tste_make(NS_TST_OPCODE_END, new_tst); 1616 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1); 1617 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1); 1618 card->tst_addr = new_tst; 1619 } 1620 1621 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb) 1622 { 1623 ns_dev *card; 1624 vc_map *vc; 1625 scq_info *scq; 1626 unsigned long buflen; 1627 ns_scqe scqe; 1628 u32 flags; /* TBD flags, not CPU flags */ 1629 1630 card = vcc->dev->dev_data; 1631 TXPRINTK("nicstar%d: ns_send() called.\n", card->index); 1632 if ((vc = (vc_map *) vcc->dev_data) == NULL) { 1633 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", 1634 card->index); 1635 atomic_inc(&vcc->stats->tx_err); 1636 dev_kfree_skb_any(skb); 1637 return -EINVAL; 1638 } 1639 1640 if (!vc->tx) { 1641 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", 1642 card->index); 1643 atomic_inc(&vcc->stats->tx_err); 1644 dev_kfree_skb_any(skb); 1645 return -EINVAL; 1646 } 1647 1648 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1649 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", 1650 card->index); 1651 atomic_inc(&vcc->stats->tx_err); 1652 dev_kfree_skb_any(skb); 1653 return -EINVAL; 1654 } 1655 1656 if (skb_shinfo(skb)->nr_frags != 0) { 1657 printk("nicstar%d: No scatter-gather yet.\n", card->index); 1658 atomic_inc(&vcc->stats->tx_err); 1659 dev_kfree_skb_any(skb); 1660 return -EINVAL; 1661 } 1662 1663 ATM_SKB(skb)->vcc = vcc; 1664 1665 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data, 1666 skb->len, DMA_TO_DEVICE); 1667 1668 if (vcc->qos.aal == ATM_AAL5) { 1669 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */ 1670 flags = NS_TBD_AAL5; 1671 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb)); 1672 scqe.word_3 = cpu_to_le32(skb->len); 1673 scqe.word_4 = 1674 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0, 1675 ATM_SKB(skb)-> 1676 atm_options & ATM_ATMOPT_CLP ? 1 : 0); 1677 flags |= NS_TBD_EOPDU; 1678 } else { /* (vcc->qos.aal == ATM_AAL0) */ 1679 1680 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */ 1681 flags = NS_TBD_AAL0; 1682 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER); 1683 scqe.word_3 = cpu_to_le32(0x00000000); 1684 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */ 1685 flags |= NS_TBD_EOPDU; 1686 scqe.word_4 = 1687 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK); 1688 /* Force the VPI/VCI to be the same as in VCC struct */ 1689 scqe.word_4 |= 1690 cpu_to_le32((((u32) vcc-> 1691 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc-> 1692 vci) << 1693 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK); 1694 } 1695 1696 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1697 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen); 1698 scq = ((vc_map *) vcc->dev_data)->scq; 1699 } else { 1700 scqe.word_1 = 1701 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen); 1702 scq = card->scq0; 1703 } 1704 1705 if (push_scqe(card, vc, scq, &scqe, skb) != 0) { 1706 atomic_inc(&vcc->stats->tx_err); 1707 dev_kfree_skb_any(skb); 1708 return -EIO; 1709 } 1710 atomic_inc(&vcc->stats->tx); 1711 1712 return 0; 1713 } 1714 1715 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 1716 struct sk_buff *skb) 1717 { 1718 unsigned long flags; 1719 ns_scqe tsr; 1720 u32 scdi, scqi; 1721 int scq_is_vbr; 1722 u32 data; 1723 int index; 1724 1725 spin_lock_irqsave(&scq->lock, flags); 1726 while (scq->tail == scq->next) { 1727 if (in_interrupt()) { 1728 spin_unlock_irqrestore(&scq->lock, flags); 1729 printk("nicstar%d: Error pushing TBD.\n", card->index); 1730 return 1; 1731 } 1732 1733 scq->full = 1; 1734 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq, 1735 scq->tail != scq->next, 1736 scq->lock, 1737 SCQFULL_TIMEOUT); 1738 1739 if (scq->full) { 1740 spin_unlock_irqrestore(&scq->lock, flags); 1741 printk("nicstar%d: Timeout pushing TBD.\n", 1742 card->index); 1743 return 1; 1744 } 1745 } 1746 *scq->next = *tbd; 1747 index = (int)(scq->next - scq->base); 1748 scq->skb[index] = skb; 1749 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n", 1750 card->index, skb, index); 1751 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1752 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2), 1753 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4), 1754 scq->next); 1755 if (scq->next == scq->last) 1756 scq->next = scq->base; 1757 else 1758 scq->next++; 1759 1760 vc->tbd_count++; 1761 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) { 1762 scq->tbd_count++; 1763 scq_is_vbr = 1; 1764 } else 1765 scq_is_vbr = 0; 1766 1767 if (vc->tbd_count >= MAX_TBD_PER_VC 1768 || scq->tbd_count >= MAX_TBD_PER_SCQ) { 1769 int has_run = 0; 1770 1771 while (scq->tail == scq->next) { 1772 if (in_interrupt()) { 1773 data = scq_virt_to_bus(scq, scq->next); 1774 ns_write_sram(card, scq->scd, &data, 1); 1775 spin_unlock_irqrestore(&scq->lock, flags); 1776 printk("nicstar%d: Error pushing TSR.\n", 1777 card->index); 1778 return 0; 1779 } 1780 1781 scq->full = 1; 1782 if (has_run++) 1783 break; 1784 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq, 1785 scq->tail != scq->next, 1786 scq->lock, 1787 SCQFULL_TIMEOUT); 1788 } 1789 1790 if (!scq->full) { 1791 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1792 if (scq_is_vbr) 1793 scdi = NS_TSR_SCDISVBR; 1794 else 1795 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1796 scqi = scq->next - scq->base; 1797 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1798 tsr.word_3 = 0x00000000; 1799 tsr.word_4 = 0x00000000; 1800 1801 *scq->next = tsr; 1802 index = (int)scqi; 1803 scq->skb[index] = NULL; 1804 XPRINTK 1805 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1806 card->index, le32_to_cpu(tsr.word_1), 1807 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3), 1808 le32_to_cpu(tsr.word_4), scq->next); 1809 if (scq->next == scq->last) 1810 scq->next = scq->base; 1811 else 1812 scq->next++; 1813 vc->tbd_count = 0; 1814 scq->tbd_count = 0; 1815 } else 1816 PRINTK("nicstar%d: Timeout pushing TSR.\n", 1817 card->index); 1818 } 1819 data = scq_virt_to_bus(scq, scq->next); 1820 ns_write_sram(card, scq->scd, &data, 1); 1821 1822 spin_unlock_irqrestore(&scq->lock, flags); 1823 1824 return 0; 1825 } 1826 1827 static void process_tsq(ns_dev * card) 1828 { 1829 u32 scdi; 1830 scq_info *scq; 1831 ns_tsi *previous = NULL, *one_ahead, *two_ahead; 1832 int serviced_entries; /* flag indicating at least on entry was serviced */ 1833 1834 serviced_entries = 0; 1835 1836 if (card->tsq.next == card->tsq.last) 1837 one_ahead = card->tsq.base; 1838 else 1839 one_ahead = card->tsq.next + 1; 1840 1841 if (one_ahead == card->tsq.last) 1842 two_ahead = card->tsq.base; 1843 else 1844 two_ahead = one_ahead + 1; 1845 1846 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) || 1847 !ns_tsi_isempty(two_ahead)) 1848 /* At most two empty, as stated in the 77201 errata */ 1849 { 1850 serviced_entries = 1; 1851 1852 /* Skip the one or two possible empty entries */ 1853 while (ns_tsi_isempty(card->tsq.next)) { 1854 if (card->tsq.next == card->tsq.last) 1855 card->tsq.next = card->tsq.base; 1856 else 1857 card->tsq.next++; 1858 } 1859 1860 if (!ns_tsi_tmrof(card->tsq.next)) { 1861 scdi = ns_tsi_getscdindex(card->tsq.next); 1862 if (scdi == NS_TSI_SCDISVBR) 1863 scq = card->scq0; 1864 else { 1865 if (card->scd2vc[scdi] == NULL) { 1866 printk 1867 ("nicstar%d: could not find VC from SCD index.\n", 1868 card->index); 1869 ns_tsi_init(card->tsq.next); 1870 return; 1871 } 1872 scq = card->scd2vc[scdi]->scq; 1873 } 1874 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next)); 1875 scq->full = 0; 1876 wake_up_interruptible(&(scq->scqfull_waitq)); 1877 } 1878 1879 ns_tsi_init(card->tsq.next); 1880 previous = card->tsq.next; 1881 if (card->tsq.next == card->tsq.last) 1882 card->tsq.next = card->tsq.base; 1883 else 1884 card->tsq.next++; 1885 1886 if (card->tsq.next == card->tsq.last) 1887 one_ahead = card->tsq.base; 1888 else 1889 one_ahead = card->tsq.next + 1; 1890 1891 if (one_ahead == card->tsq.last) 1892 two_ahead = card->tsq.base; 1893 else 1894 two_ahead = one_ahead + 1; 1895 } 1896 1897 if (serviced_entries) 1898 writel(PTR_DIFF(previous, card->tsq.base), 1899 card->membase + TSQH); 1900 } 1901 1902 static void drain_scq(ns_dev * card, scq_info * scq, int pos) 1903 { 1904 struct atm_vcc *vcc; 1905 struct sk_buff *skb; 1906 int i; 1907 unsigned long flags; 1908 1909 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n", 1910 card->index, scq, pos); 1911 if (pos >= scq->num_entries) { 1912 printk("nicstar%d: Bad index on drain_scq().\n", card->index); 1913 return; 1914 } 1915 1916 spin_lock_irqsave(&scq->lock, flags); 1917 i = (int)(scq->tail - scq->base); 1918 if (++i == scq->num_entries) 1919 i = 0; 1920 while (i != pos) { 1921 skb = scq->skb[i]; 1922 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n", 1923 card->index, skb, i); 1924 if (skb != NULL) { 1925 dma_unmap_single(&card->pcidev->dev, 1926 NS_PRV_DMA(skb), 1927 skb->len, 1928 DMA_TO_DEVICE); 1929 vcc = ATM_SKB(skb)->vcc; 1930 if (vcc && vcc->pop != NULL) { 1931 vcc->pop(vcc, skb); 1932 } else { 1933 dev_kfree_skb_irq(skb); 1934 } 1935 scq->skb[i] = NULL; 1936 } 1937 if (++i == scq->num_entries) 1938 i = 0; 1939 } 1940 scq->tail = scq->base + pos; 1941 spin_unlock_irqrestore(&scq->lock, flags); 1942 } 1943 1944 static void process_rsq(ns_dev * card) 1945 { 1946 ns_rsqe *previous; 1947 1948 if (!ns_rsqe_valid(card->rsq.next)) 1949 return; 1950 do { 1951 dequeue_rx(card, card->rsq.next); 1952 ns_rsqe_init(card->rsq.next); 1953 previous = card->rsq.next; 1954 if (card->rsq.next == card->rsq.last) 1955 card->rsq.next = card->rsq.base; 1956 else 1957 card->rsq.next++; 1958 } while (ns_rsqe_valid(card->rsq.next)); 1959 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH); 1960 } 1961 1962 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe) 1963 { 1964 u32 vpi, vci; 1965 vc_map *vc; 1966 struct sk_buff *iovb; 1967 struct iovec *iov; 1968 struct atm_vcc *vcc; 1969 struct sk_buff *skb; 1970 unsigned short aal5_len; 1971 int len; 1972 u32 stat; 1973 u32 id; 1974 1975 stat = readl(card->membase + STAT); 1976 card->sbfqc = ns_stat_sfbqc_get(stat); 1977 card->lbfqc = ns_stat_lfbqc_get(stat); 1978 1979 id = le32_to_cpu(rsqe->buffer_handle); 1980 skb = idr_find(&card->idr, id); 1981 if (!skb) { 1982 RXPRINTK(KERN_ERR 1983 "nicstar%d: idr_find() failed!\n", card->index); 1984 return; 1985 } 1986 idr_remove(&card->idr, id); 1987 dma_sync_single_for_cpu(&card->pcidev->dev, 1988 NS_PRV_DMA(skb), 1989 (NS_PRV_BUFTYPE(skb) == BUF_SM 1990 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 1991 DMA_FROM_DEVICE); 1992 dma_unmap_single(&card->pcidev->dev, 1993 NS_PRV_DMA(skb), 1994 (NS_PRV_BUFTYPE(skb) == BUF_SM 1995 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 1996 DMA_FROM_DEVICE); 1997 vpi = ns_rsqe_vpi(rsqe); 1998 vci = ns_rsqe_vci(rsqe); 1999 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) { 2000 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n", 2001 card->index, vpi, vci); 2002 recycle_rx_buf(card, skb); 2003 return; 2004 } 2005 2006 vc = &(card->vcmap[vpi << card->vcibits | vci]); 2007 if (!vc->rx) { 2008 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n", 2009 card->index, vpi, vci); 2010 recycle_rx_buf(card, skb); 2011 return; 2012 } 2013 2014 vcc = vc->rx_vcc; 2015 2016 if (vcc->qos.aal == ATM_AAL0) { 2017 struct sk_buff *sb; 2018 unsigned char *cell; 2019 int i; 2020 2021 cell = skb->data; 2022 for (i = ns_rsqe_cellcount(rsqe); i; i--) { 2023 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) { 2024 printk 2025 ("nicstar%d: Can't allocate buffers for aal0.\n", 2026 card->index); 2027 atomic_add(i, &vcc->stats->rx_drop); 2028 break; 2029 } 2030 if (!atm_charge(vcc, sb->truesize)) { 2031 RXPRINTK 2032 ("nicstar%d: atm_charge() dropped aal0 packets.\n", 2033 card->index); 2034 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */ 2035 dev_kfree_skb_any(sb); 2036 break; 2037 } 2038 /* Rebuild the header */ 2039 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 | 2040 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000); 2041 if (i == 1 && ns_rsqe_eopdu(rsqe)) 2042 *((u32 *) sb->data) |= 0x00000002; 2043 skb_put(sb, NS_AAL0_HEADER); 2044 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD); 2045 skb_put(sb, ATM_CELL_PAYLOAD); 2046 ATM_SKB(sb)->vcc = vcc; 2047 __net_timestamp(sb); 2048 vcc->push(vcc, sb); 2049 atomic_inc(&vcc->stats->rx); 2050 cell += ATM_CELL_PAYLOAD; 2051 } 2052 2053 recycle_rx_buf(card, skb); 2054 return; 2055 } 2056 2057 /* To reach this point, the AAL layer can only be AAL5 */ 2058 2059 if ((iovb = vc->rx_iov) == NULL) { 2060 iovb = skb_dequeue(&(card->iovpool.queue)); 2061 if (iovb == NULL) { /* No buffers in the queue */ 2062 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC); 2063 if (iovb == NULL) { 2064 printk("nicstar%d: Out of iovec buffers.\n", 2065 card->index); 2066 atomic_inc(&vcc->stats->rx_drop); 2067 recycle_rx_buf(card, skb); 2068 return; 2069 } 2070 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2071 } else if (--card->iovpool.count < card->iovnr.min) { 2072 struct sk_buff *new_iovb; 2073 if ((new_iovb = 2074 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) { 2075 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2076 skb_queue_tail(&card->iovpool.queue, new_iovb); 2077 card->iovpool.count++; 2078 } 2079 } 2080 vc->rx_iov = iovb; 2081 NS_PRV_IOVCNT(iovb) = 0; 2082 iovb->len = 0; 2083 iovb->data = iovb->head; 2084 skb_reset_tail_pointer(iovb); 2085 /* IMPORTANT: a pointer to the sk_buff containing the small or large 2086 buffer is stored as iovec base, NOT a pointer to the 2087 small or large buffer itself. */ 2088 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) { 2089 printk("nicstar%d: received too big AAL5 SDU.\n", card->index); 2090 atomic_inc(&vcc->stats->rx_err); 2091 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2092 NS_MAX_IOVECS); 2093 NS_PRV_IOVCNT(iovb) = 0; 2094 iovb->len = 0; 2095 iovb->data = iovb->head; 2096 skb_reset_tail_pointer(iovb); 2097 } 2098 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++]; 2099 iov->iov_base = (void *)skb; 2100 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48; 2101 iovb->len += iov->iov_len; 2102 2103 #ifdef EXTRA_DEBUG 2104 if (NS_PRV_IOVCNT(iovb) == 1) { 2105 if (NS_PRV_BUFTYPE(skb) != BUF_SM) { 2106 printk 2107 ("nicstar%d: Expected a small buffer, and this is not one.\n", 2108 card->index); 2109 which_list(card, skb); 2110 atomic_inc(&vcc->stats->rx_err); 2111 recycle_rx_buf(card, skb); 2112 vc->rx_iov = NULL; 2113 recycle_iov_buf(card, iovb); 2114 return; 2115 } 2116 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */ 2117 2118 if (NS_PRV_BUFTYPE(skb) != BUF_LG) { 2119 printk 2120 ("nicstar%d: Expected a large buffer, and this is not one.\n", 2121 card->index); 2122 which_list(card, skb); 2123 atomic_inc(&vcc->stats->rx_err); 2124 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2125 NS_PRV_IOVCNT(iovb)); 2126 vc->rx_iov = NULL; 2127 recycle_iov_buf(card, iovb); 2128 return; 2129 } 2130 } 2131 #endif /* EXTRA_DEBUG */ 2132 2133 if (ns_rsqe_eopdu(rsqe)) { 2134 /* This works correctly regardless of the endianness of the host */ 2135 unsigned char *L1L2 = (unsigned char *) 2136 (skb->data + iov->iov_len - 6); 2137 aal5_len = L1L2[0] << 8 | L1L2[1]; 2138 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len; 2139 if (ns_rsqe_crcerr(rsqe) || 2140 len + 8 > iovb->len || len + (47 + 8) < iovb->len) { 2141 printk("nicstar%d: AAL5 CRC error", card->index); 2142 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2143 printk(" - PDU size mismatch.\n"); 2144 else 2145 printk(".\n"); 2146 atomic_inc(&vcc->stats->rx_err); 2147 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2148 NS_PRV_IOVCNT(iovb)); 2149 vc->rx_iov = NULL; 2150 recycle_iov_buf(card, iovb); 2151 return; 2152 } 2153 2154 /* By this point we (hopefully) have a complete SDU without errors. */ 2155 2156 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */ 2157 /* skb points to a small buffer */ 2158 if (!atm_charge(vcc, skb->truesize)) { 2159 push_rxbufs(card, skb); 2160 atomic_inc(&vcc->stats->rx_drop); 2161 } else { 2162 skb_put(skb, len); 2163 dequeue_sm_buf(card, skb); 2164 ATM_SKB(skb)->vcc = vcc; 2165 __net_timestamp(skb); 2166 vcc->push(vcc, skb); 2167 atomic_inc(&vcc->stats->rx); 2168 } 2169 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */ 2170 struct sk_buff *sb; 2171 2172 sb = (struct sk_buff *)(iov - 1)->iov_base; 2173 /* skb points to a large buffer */ 2174 2175 if (len <= NS_SMBUFSIZE) { 2176 if (!atm_charge(vcc, sb->truesize)) { 2177 push_rxbufs(card, sb); 2178 atomic_inc(&vcc->stats->rx_drop); 2179 } else { 2180 skb_put(sb, len); 2181 dequeue_sm_buf(card, sb); 2182 ATM_SKB(sb)->vcc = vcc; 2183 __net_timestamp(sb); 2184 vcc->push(vcc, sb); 2185 atomic_inc(&vcc->stats->rx); 2186 } 2187 2188 push_rxbufs(card, skb); 2189 2190 } else { /* len > NS_SMBUFSIZE, the usual case */ 2191 2192 if (!atm_charge(vcc, skb->truesize)) { 2193 push_rxbufs(card, skb); 2194 atomic_inc(&vcc->stats->rx_drop); 2195 } else { 2196 dequeue_lg_buf(card, skb); 2197 skb_push(skb, NS_SMBUFSIZE); 2198 skb_copy_from_linear_data(sb, skb->data, 2199 NS_SMBUFSIZE); 2200 skb_put(skb, len - NS_SMBUFSIZE); 2201 ATM_SKB(skb)->vcc = vcc; 2202 __net_timestamp(skb); 2203 vcc->push(vcc, skb); 2204 atomic_inc(&vcc->stats->rx); 2205 } 2206 2207 push_rxbufs(card, sb); 2208 2209 } 2210 2211 } else { /* Must push a huge buffer */ 2212 2213 struct sk_buff *hb, *sb, *lb; 2214 int remaining, tocopy; 2215 int j; 2216 2217 hb = skb_dequeue(&(card->hbpool.queue)); 2218 if (hb == NULL) { /* No buffers in the queue */ 2219 2220 hb = dev_alloc_skb(NS_HBUFSIZE); 2221 if (hb == NULL) { 2222 printk 2223 ("nicstar%d: Out of huge buffers.\n", 2224 card->index); 2225 atomic_inc(&vcc->stats->rx_drop); 2226 recycle_iovec_rx_bufs(card, 2227 (struct iovec *) 2228 iovb->data, 2229 NS_PRV_IOVCNT(iovb)); 2230 vc->rx_iov = NULL; 2231 recycle_iov_buf(card, iovb); 2232 return; 2233 } else if (card->hbpool.count < card->hbnr.min) { 2234 struct sk_buff *new_hb; 2235 if ((new_hb = 2236 dev_alloc_skb(NS_HBUFSIZE)) != 2237 NULL) { 2238 skb_queue_tail(&card->hbpool. 2239 queue, new_hb); 2240 card->hbpool.count++; 2241 } 2242 } 2243 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2244 } else if (--card->hbpool.count < card->hbnr.min) { 2245 struct sk_buff *new_hb; 2246 if ((new_hb = 2247 dev_alloc_skb(NS_HBUFSIZE)) != NULL) { 2248 NS_PRV_BUFTYPE(new_hb) = BUF_NONE; 2249 skb_queue_tail(&card->hbpool.queue, 2250 new_hb); 2251 card->hbpool.count++; 2252 } 2253 if (card->hbpool.count < card->hbnr.min) { 2254 if ((new_hb = 2255 dev_alloc_skb(NS_HBUFSIZE)) != 2256 NULL) { 2257 NS_PRV_BUFTYPE(new_hb) = 2258 BUF_NONE; 2259 skb_queue_tail(&card->hbpool. 2260 queue, new_hb); 2261 card->hbpool.count++; 2262 } 2263 } 2264 } 2265 2266 iov = (struct iovec *)iovb->data; 2267 2268 if (!atm_charge(vcc, hb->truesize)) { 2269 recycle_iovec_rx_bufs(card, iov, 2270 NS_PRV_IOVCNT(iovb)); 2271 if (card->hbpool.count < card->hbnr.max) { 2272 skb_queue_tail(&card->hbpool.queue, hb); 2273 card->hbpool.count++; 2274 } else 2275 dev_kfree_skb_any(hb); 2276 atomic_inc(&vcc->stats->rx_drop); 2277 } else { 2278 /* Copy the small buffer to the huge buffer */ 2279 sb = (struct sk_buff *)iov->iov_base; 2280 skb_copy_from_linear_data(sb, hb->data, 2281 iov->iov_len); 2282 skb_put(hb, iov->iov_len); 2283 remaining = len - iov->iov_len; 2284 iov++; 2285 /* Free the small buffer */ 2286 push_rxbufs(card, sb); 2287 2288 /* Copy all large buffers to the huge buffer and free them */ 2289 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) { 2290 lb = (struct sk_buff *)iov->iov_base; 2291 tocopy = 2292 min_t(int, remaining, iov->iov_len); 2293 skb_copy_from_linear_data(lb, 2294 skb_tail_pointer 2295 (hb), tocopy); 2296 skb_put(hb, tocopy); 2297 iov++; 2298 remaining -= tocopy; 2299 push_rxbufs(card, lb); 2300 } 2301 #ifdef EXTRA_DEBUG 2302 if (remaining != 0 || hb->len != len) 2303 printk 2304 ("nicstar%d: Huge buffer len mismatch.\n", 2305 card->index); 2306 #endif /* EXTRA_DEBUG */ 2307 ATM_SKB(hb)->vcc = vcc; 2308 __net_timestamp(hb); 2309 vcc->push(vcc, hb); 2310 atomic_inc(&vcc->stats->rx); 2311 } 2312 } 2313 2314 vc->rx_iov = NULL; 2315 recycle_iov_buf(card, iovb); 2316 } 2317 2318 } 2319 2320 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb) 2321 { 2322 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) { 2323 printk("nicstar%d: What kind of rx buffer is this?\n", 2324 card->index); 2325 dev_kfree_skb_any(skb); 2326 } else 2327 push_rxbufs(card, skb); 2328 } 2329 2330 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count) 2331 { 2332 while (count-- > 0) 2333 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base); 2334 } 2335 2336 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb) 2337 { 2338 if (card->iovpool.count < card->iovnr.max) { 2339 skb_queue_tail(&card->iovpool.queue, iovb); 2340 card->iovpool.count++; 2341 } else 2342 dev_kfree_skb_any(iovb); 2343 } 2344 2345 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb) 2346 { 2347 skb_unlink(sb, &card->sbpool.queue); 2348 if (card->sbfqc < card->sbnr.init) { 2349 struct sk_buff *new_sb; 2350 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2351 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2352 skb_queue_tail(&card->sbpool.queue, new_sb); 2353 skb_reserve(new_sb, NS_AAL0_HEADER); 2354 push_rxbufs(card, new_sb); 2355 } 2356 } 2357 if (card->sbfqc < card->sbnr.init) 2358 { 2359 struct sk_buff *new_sb; 2360 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2361 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2362 skb_queue_tail(&card->sbpool.queue, new_sb); 2363 skb_reserve(new_sb, NS_AAL0_HEADER); 2364 push_rxbufs(card, new_sb); 2365 } 2366 } 2367 } 2368 2369 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb) 2370 { 2371 skb_unlink(lb, &card->lbpool.queue); 2372 if (card->lbfqc < card->lbnr.init) { 2373 struct sk_buff *new_lb; 2374 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2375 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2376 skb_queue_tail(&card->lbpool.queue, new_lb); 2377 skb_reserve(new_lb, NS_SMBUFSIZE); 2378 push_rxbufs(card, new_lb); 2379 } 2380 } 2381 if (card->lbfqc < card->lbnr.init) 2382 { 2383 struct sk_buff *new_lb; 2384 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2385 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2386 skb_queue_tail(&card->lbpool.queue, new_lb); 2387 skb_reserve(new_lb, NS_SMBUFSIZE); 2388 push_rxbufs(card, new_lb); 2389 } 2390 } 2391 } 2392 2393 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2394 { 2395 u32 stat; 2396 ns_dev *card; 2397 int left; 2398 2399 left = (int)*pos; 2400 card = (ns_dev *) dev->dev_data; 2401 stat = readl(card->membase + STAT); 2402 if (!left--) 2403 return sprintf(page, "Pool count min init max \n"); 2404 if (!left--) 2405 return sprintf(page, "Small %5d %5d %5d %5d \n", 2406 ns_stat_sfbqc_get(stat), card->sbnr.min, 2407 card->sbnr.init, card->sbnr.max); 2408 if (!left--) 2409 return sprintf(page, "Large %5d %5d %5d %5d \n", 2410 ns_stat_lfbqc_get(stat), card->lbnr.min, 2411 card->lbnr.init, card->lbnr.max); 2412 if (!left--) 2413 return sprintf(page, "Huge %5d %5d %5d %5d \n", 2414 card->hbpool.count, card->hbnr.min, 2415 card->hbnr.init, card->hbnr.max); 2416 if (!left--) 2417 return sprintf(page, "Iovec %5d %5d %5d %5d \n", 2418 card->iovpool.count, card->iovnr.min, 2419 card->iovnr.init, card->iovnr.max); 2420 if (!left--) { 2421 int retval; 2422 retval = 2423 sprintf(page, "Interrupt counter: %u \n", card->intcnt); 2424 card->intcnt = 0; 2425 return retval; 2426 } 2427 #if 0 2428 /* Dump 25.6 Mbps PHY registers */ 2429 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it 2430 here just in case it's needed for debugging. */ 2431 if (card->max_pcr == ATM_25_PCR && !left--) { 2432 u32 phy_regs[4]; 2433 u32 i; 2434 2435 for (i = 0; i < 4; i++) { 2436 while (CMD_BUSY(card)) ; 2437 writel(NS_CMD_READ_UTILITY | 0x00000200 | i, 2438 card->membase + CMD); 2439 while (CMD_BUSY(card)) ; 2440 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; 2441 } 2442 2443 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n", 2444 phy_regs[0], phy_regs[1], phy_regs[2], 2445 phy_regs[3]); 2446 } 2447 #endif /* 0 - Dump 25.6 Mbps PHY registers */ 2448 #if 0 2449 /* Dump TST */ 2450 if (left-- < NS_TST_NUM_ENTRIES) { 2451 if (card->tste2vc[left + 1] == NULL) 2452 return sprintf(page, "%5d - VBR/UBR \n", left + 1); 2453 else 2454 return sprintf(page, "%5d - %d %d \n", left + 1, 2455 card->tste2vc[left + 1]->tx_vcc->vpi, 2456 card->tste2vc[left + 1]->tx_vcc->vci); 2457 } 2458 #endif /* 0 */ 2459 return 0; 2460 } 2461 2462 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg) 2463 { 2464 ns_dev *card; 2465 pool_levels pl; 2466 long btype; 2467 unsigned long flags; 2468 2469 card = dev->dev_data; 2470 switch (cmd) { 2471 case NS_GETPSTAT: 2472 if (get_user 2473 (pl.buftype, &((pool_levels __user *) arg)->buftype)) 2474 return -EFAULT; 2475 switch (pl.buftype) { 2476 case NS_BUFTYPE_SMALL: 2477 pl.count = 2478 ns_stat_sfbqc_get(readl(card->membase + STAT)); 2479 pl.level.min = card->sbnr.min; 2480 pl.level.init = card->sbnr.init; 2481 pl.level.max = card->sbnr.max; 2482 break; 2483 2484 case NS_BUFTYPE_LARGE: 2485 pl.count = 2486 ns_stat_lfbqc_get(readl(card->membase + STAT)); 2487 pl.level.min = card->lbnr.min; 2488 pl.level.init = card->lbnr.init; 2489 pl.level.max = card->lbnr.max; 2490 break; 2491 2492 case NS_BUFTYPE_HUGE: 2493 pl.count = card->hbpool.count; 2494 pl.level.min = card->hbnr.min; 2495 pl.level.init = card->hbnr.init; 2496 pl.level.max = card->hbnr.max; 2497 break; 2498 2499 case NS_BUFTYPE_IOVEC: 2500 pl.count = card->iovpool.count; 2501 pl.level.min = card->iovnr.min; 2502 pl.level.init = card->iovnr.init; 2503 pl.level.max = card->iovnr.max; 2504 break; 2505 2506 default: 2507 return -ENOIOCTLCMD; 2508 2509 } 2510 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl))) 2511 return (sizeof(pl)); 2512 else 2513 return -EFAULT; 2514 2515 case NS_SETBUFLEV: 2516 if (!capable(CAP_NET_ADMIN)) 2517 return -EPERM; 2518 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl))) 2519 return -EFAULT; 2520 if (pl.level.min >= pl.level.init 2521 || pl.level.init >= pl.level.max) 2522 return -EINVAL; 2523 if (pl.level.min == 0) 2524 return -EINVAL; 2525 switch (pl.buftype) { 2526 case NS_BUFTYPE_SMALL: 2527 if (pl.level.max > TOP_SB) 2528 return -EINVAL; 2529 card->sbnr.min = pl.level.min; 2530 card->sbnr.init = pl.level.init; 2531 card->sbnr.max = pl.level.max; 2532 break; 2533 2534 case NS_BUFTYPE_LARGE: 2535 if (pl.level.max > TOP_LB) 2536 return -EINVAL; 2537 card->lbnr.min = pl.level.min; 2538 card->lbnr.init = pl.level.init; 2539 card->lbnr.max = pl.level.max; 2540 break; 2541 2542 case NS_BUFTYPE_HUGE: 2543 if (pl.level.max > TOP_HB) 2544 return -EINVAL; 2545 card->hbnr.min = pl.level.min; 2546 card->hbnr.init = pl.level.init; 2547 card->hbnr.max = pl.level.max; 2548 break; 2549 2550 case NS_BUFTYPE_IOVEC: 2551 if (pl.level.max > TOP_IOVB) 2552 return -EINVAL; 2553 card->iovnr.min = pl.level.min; 2554 card->iovnr.init = pl.level.init; 2555 card->iovnr.max = pl.level.max; 2556 break; 2557 2558 default: 2559 return -EINVAL; 2560 2561 } 2562 return 0; 2563 2564 case NS_ADJBUFLEV: 2565 if (!capable(CAP_NET_ADMIN)) 2566 return -EPERM; 2567 btype = (long)arg; /* a long is the same size as a pointer or bigger */ 2568 switch (btype) { 2569 case NS_BUFTYPE_SMALL: 2570 while (card->sbfqc < card->sbnr.init) { 2571 struct sk_buff *sb; 2572 2573 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2574 if (sb == NULL) 2575 return -ENOMEM; 2576 NS_PRV_BUFTYPE(sb) = BUF_SM; 2577 skb_queue_tail(&card->sbpool.queue, sb); 2578 skb_reserve(sb, NS_AAL0_HEADER); 2579 push_rxbufs(card, sb); 2580 } 2581 break; 2582 2583 case NS_BUFTYPE_LARGE: 2584 while (card->lbfqc < card->lbnr.init) { 2585 struct sk_buff *lb; 2586 2587 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2588 if (lb == NULL) 2589 return -ENOMEM; 2590 NS_PRV_BUFTYPE(lb) = BUF_LG; 2591 skb_queue_tail(&card->lbpool.queue, lb); 2592 skb_reserve(lb, NS_SMBUFSIZE); 2593 push_rxbufs(card, lb); 2594 } 2595 break; 2596 2597 case NS_BUFTYPE_HUGE: 2598 while (card->hbpool.count > card->hbnr.init) { 2599 struct sk_buff *hb; 2600 2601 spin_lock_irqsave(&card->int_lock, flags); 2602 hb = skb_dequeue(&card->hbpool.queue); 2603 card->hbpool.count--; 2604 spin_unlock_irqrestore(&card->int_lock, flags); 2605 if (hb == NULL) 2606 printk 2607 ("nicstar%d: huge buffer count inconsistent.\n", 2608 card->index); 2609 else 2610 dev_kfree_skb_any(hb); 2611 2612 } 2613 while (card->hbpool.count < card->hbnr.init) { 2614 struct sk_buff *hb; 2615 2616 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2617 if (hb == NULL) 2618 return -ENOMEM; 2619 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2620 spin_lock_irqsave(&card->int_lock, flags); 2621 skb_queue_tail(&card->hbpool.queue, hb); 2622 card->hbpool.count++; 2623 spin_unlock_irqrestore(&card->int_lock, flags); 2624 } 2625 break; 2626 2627 case NS_BUFTYPE_IOVEC: 2628 while (card->iovpool.count > card->iovnr.init) { 2629 struct sk_buff *iovb; 2630 2631 spin_lock_irqsave(&card->int_lock, flags); 2632 iovb = skb_dequeue(&card->iovpool.queue); 2633 card->iovpool.count--; 2634 spin_unlock_irqrestore(&card->int_lock, flags); 2635 if (iovb == NULL) 2636 printk 2637 ("nicstar%d: iovec buffer count inconsistent.\n", 2638 card->index); 2639 else 2640 dev_kfree_skb_any(iovb); 2641 2642 } 2643 while (card->iovpool.count < card->iovnr.init) { 2644 struct sk_buff *iovb; 2645 2646 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 2647 if (iovb == NULL) 2648 return -ENOMEM; 2649 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2650 spin_lock_irqsave(&card->int_lock, flags); 2651 skb_queue_tail(&card->iovpool.queue, iovb); 2652 card->iovpool.count++; 2653 spin_unlock_irqrestore(&card->int_lock, flags); 2654 } 2655 break; 2656 2657 default: 2658 return -EINVAL; 2659 2660 } 2661 return 0; 2662 2663 default: 2664 if (dev->phy && dev->phy->ioctl) { 2665 return dev->phy->ioctl(dev, cmd, arg); 2666 } else { 2667 printk("nicstar%d: %s == NULL \n", card->index, 2668 dev->phy ? "dev->phy->ioctl" : "dev->phy"); 2669 return -ENOIOCTLCMD; 2670 } 2671 } 2672 } 2673 2674 #ifdef EXTRA_DEBUG 2675 static void which_list(ns_dev * card, struct sk_buff *skb) 2676 { 2677 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb)); 2678 } 2679 #endif /* EXTRA_DEBUG */ 2680 2681 static void ns_poll(unsigned long arg) 2682 { 2683 int i; 2684 ns_dev *card; 2685 unsigned long flags; 2686 u32 stat_r, stat_w; 2687 2688 PRINTK("nicstar: Entering ns_poll().\n"); 2689 for (i = 0; i < num_cards; i++) { 2690 card = cards[i]; 2691 if (spin_is_locked(&card->int_lock)) { 2692 /* Probably it isn't worth spinning */ 2693 continue; 2694 } 2695 spin_lock_irqsave(&card->int_lock, flags); 2696 2697 stat_w = 0; 2698 stat_r = readl(card->membase + STAT); 2699 if (stat_r & NS_STAT_TSIF) 2700 stat_w |= NS_STAT_TSIF; 2701 if (stat_r & NS_STAT_EOPDU) 2702 stat_w |= NS_STAT_EOPDU; 2703 2704 process_tsq(card); 2705 process_rsq(card); 2706 2707 writel(stat_w, card->membase + STAT); 2708 spin_unlock_irqrestore(&card->int_lock, flags); 2709 } 2710 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD); 2711 PRINTK("nicstar: Leaving ns_poll().\n"); 2712 } 2713 2714 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 2715 unsigned long addr) 2716 { 2717 ns_dev *card; 2718 unsigned long flags; 2719 2720 card = dev->dev_data; 2721 spin_lock_irqsave(&card->res_lock, flags); 2722 while (CMD_BUSY(card)) ; 2723 writel((u32) value, card->membase + DR0); 2724 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF), 2725 card->membase + CMD); 2726 spin_unlock_irqrestore(&card->res_lock, flags); 2727 } 2728 2729 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr) 2730 { 2731 ns_dev *card; 2732 unsigned long flags; 2733 u32 data; 2734 2735 card = dev->dev_data; 2736 spin_lock_irqsave(&card->res_lock, flags); 2737 while (CMD_BUSY(card)) ; 2738 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF), 2739 card->membase + CMD); 2740 while (CMD_BUSY(card)) ; 2741 data = readl(card->membase + DR0) & 0x000000FF; 2742 spin_unlock_irqrestore(&card->res_lock, flags); 2743 return (unsigned char)data; 2744 } 2745 2746 module_init(nicstar_init); 2747 module_exit(nicstar_cleanup); 2748