1 /****************************************************************************** 2 * 3 * nicstar.c 4 * 5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards. 6 * 7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME. 8 * It was taken from the frle-0.22 device driver. 9 * As the file doesn't have a copyright notice, in the file 10 * nicstarmac.copyright I put the copyright notice from the 11 * frle-0.22 device driver. 12 * Some code is based on the nicstar driver by M. Welsh. 13 * 14 * Author: Rui Prior (rprior@inescn.pt) 15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 16 * 17 * 18 * (C) INESC 1999 19 * 20 * 21 ******************************************************************************/ 22 23 24 /**** IMPORTANT INFORMATION *************************************************** 25 * 26 * There are currently three types of spinlocks: 27 * 28 * 1 - Per card interrupt spinlock (to protect structures and such) 29 * 2 - Per SCQ scq spinlock 30 * 3 - Per card resource spinlock (to access registers, etc.) 31 * 32 * These must NEVER be grabbed in reverse order. 33 * 34 ******************************************************************************/ 35 36 /* Header files ***************************************************************/ 37 38 #include <linux/module.h> 39 #include <linux/kernel.h> 40 #include <linux/skbuff.h> 41 #include <linux/atmdev.h> 42 #include <linux/atm.h> 43 #include <linux/pci.h> 44 #include <linux/types.h> 45 #include <linux/string.h> 46 #include <linux/delay.h> 47 #include <linux/init.h> 48 #include <linux/sched.h> 49 #include <linux/timer.h> 50 #include <linux/interrupt.h> 51 #include <linux/bitops.h> 52 #include <asm/io.h> 53 #include <asm/uaccess.h> 54 #include <asm/atomic.h> 55 #include "nicstar.h" 56 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 57 #include "suni.h" 58 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 59 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 60 #include "idt77105.h" 61 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 62 63 #if BITS_PER_LONG != 32 64 # error FIXME: this driver requires a 32-bit platform 65 #endif 66 67 /* Additional code ************************************************************/ 68 69 #include "nicstarmac.c" 70 71 72 /* Configurable parameters ****************************************************/ 73 74 #undef PHY_LOOPBACK 75 #undef TX_DEBUG 76 #undef RX_DEBUG 77 #undef GENERAL_DEBUG 78 #undef EXTRA_DEBUG 79 80 #undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know 81 you're going to use only raw ATM */ 82 83 84 /* Do not touch these *********************************************************/ 85 86 #ifdef TX_DEBUG 87 #define TXPRINTK(args...) printk(args) 88 #else 89 #define TXPRINTK(args...) 90 #endif /* TX_DEBUG */ 91 92 #ifdef RX_DEBUG 93 #define RXPRINTK(args...) printk(args) 94 #else 95 #define RXPRINTK(args...) 96 #endif /* RX_DEBUG */ 97 98 #ifdef GENERAL_DEBUG 99 #define PRINTK(args...) printk(args) 100 #else 101 #define PRINTK(args...) 102 #endif /* GENERAL_DEBUG */ 103 104 #ifdef EXTRA_DEBUG 105 #define XPRINTK(args...) printk(args) 106 #else 107 #define XPRINTK(args...) 108 #endif /* EXTRA_DEBUG */ 109 110 111 /* Macros *********************************************************************/ 112 113 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ) 114 115 #define NS_DELAY mdelay(1) 116 117 #define ALIGN_BUS_ADDR(addr, alignment) \ 118 ((((u32) (addr)) + (((u32) (alignment)) - 1)) & ~(((u32) (alignment)) - 1)) 119 #define ALIGN_ADDRESS(addr, alignment) \ 120 bus_to_virt(ALIGN_BUS_ADDR(virt_to_bus(addr), alignment)) 121 122 #undef CEIL 123 124 #ifndef ATM_SKB 125 #define ATM_SKB(s) (&(s)->atm) 126 #endif 127 128 129 /* Function declarations ******************************************************/ 130 131 static u32 ns_read_sram(ns_dev *card, u32 sram_address); 132 static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count); 133 static int __devinit ns_init_card(int i, struct pci_dev *pcidev); 134 static void __devinit ns_init_card_error(ns_dev *card, int error); 135 static scq_info *get_scq(int size, u32 scd); 136 static void free_scq(scq_info *scq, struct atm_vcc *vcc); 137 static void push_rxbufs(ns_dev *, struct sk_buff *); 138 static irqreturn_t ns_irq_handler(int irq, void *dev_id); 139 static int ns_open(struct atm_vcc *vcc); 140 static void ns_close(struct atm_vcc *vcc); 141 static void fill_tst(ns_dev *card, int n, vc_map *vc); 142 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb); 143 static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd, 144 struct sk_buff *skb); 145 static void process_tsq(ns_dev *card); 146 static void drain_scq(ns_dev *card, scq_info *scq, int pos); 147 static void process_rsq(ns_dev *card); 148 static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe); 149 #ifdef NS_USE_DESTRUCTORS 150 static void ns_sb_destructor(struct sk_buff *sb); 151 static void ns_lb_destructor(struct sk_buff *lb); 152 static void ns_hb_destructor(struct sk_buff *hb); 153 #endif /* NS_USE_DESTRUCTORS */ 154 static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb); 155 static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count); 156 static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb); 157 static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb); 158 static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb); 159 static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page); 160 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg); 161 static void which_list(ns_dev *card, struct sk_buff *skb); 162 static void ns_poll(unsigned long arg); 163 static int ns_parse_mac(char *mac, unsigned char *esi); 164 static short ns_h2i(char c); 165 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 166 unsigned long addr); 167 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr); 168 169 170 171 /* Global variables ***********************************************************/ 172 173 static struct ns_dev *cards[NS_MAX_CARDS]; 174 static unsigned num_cards; 175 static struct atmdev_ops atm_ops = 176 { 177 .open = ns_open, 178 .close = ns_close, 179 .ioctl = ns_ioctl, 180 .send = ns_send, 181 .phy_put = ns_phy_put, 182 .phy_get = ns_phy_get, 183 .proc_read = ns_proc_read, 184 .owner = THIS_MODULE, 185 }; 186 static struct timer_list ns_timer; 187 static char *mac[NS_MAX_CARDS]; 188 module_param_array(mac, charp, NULL, 0); 189 MODULE_LICENSE("GPL"); 190 191 192 /* Functions*******************************************************************/ 193 194 static int __devinit nicstar_init_one(struct pci_dev *pcidev, 195 const struct pci_device_id *ent) 196 { 197 static int index = -1; 198 unsigned int error; 199 200 index++; 201 cards[index] = NULL; 202 203 error = ns_init_card(index, pcidev); 204 if (error) { 205 cards[index--] = NULL; /* don't increment index */ 206 goto err_out; 207 } 208 209 return 0; 210 err_out: 211 return -ENODEV; 212 } 213 214 215 216 static void __devexit nicstar_remove_one(struct pci_dev *pcidev) 217 { 218 int i, j; 219 ns_dev *card = pci_get_drvdata(pcidev); 220 struct sk_buff *hb; 221 struct sk_buff *iovb; 222 struct sk_buff *lb; 223 struct sk_buff *sb; 224 225 i = card->index; 226 227 if (cards[i] == NULL) 228 return; 229 230 if (card->atmdev->phy && card->atmdev->phy->stop) 231 card->atmdev->phy->stop(card->atmdev); 232 233 /* Stop everything */ 234 writel(0x00000000, card->membase + CFG); 235 236 /* De-register device */ 237 atm_dev_deregister(card->atmdev); 238 239 /* Disable PCI device */ 240 pci_disable_device(pcidev); 241 242 /* Free up resources */ 243 j = 0; 244 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count); 245 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 246 { 247 dev_kfree_skb_any(hb); 248 j++; 249 } 250 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j); 251 j = 0; 252 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, card->iovpool.count); 253 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 254 { 255 dev_kfree_skb_any(iovb); 256 j++; 257 } 258 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j); 259 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 260 dev_kfree_skb_any(lb); 261 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 262 dev_kfree_skb_any(sb); 263 free_scq(card->scq0, NULL); 264 for (j = 0; j < NS_FRSCD_NUM; j++) 265 { 266 if (card->scd2vc[j] != NULL) 267 free_scq(card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc); 268 } 269 kfree(card->rsq.org); 270 kfree(card->tsq.org); 271 free_irq(card->pcidev->irq, card); 272 iounmap(card->membase); 273 kfree(card); 274 } 275 276 277 278 static struct pci_device_id nicstar_pci_tbl[] __devinitdata = 279 { 280 {PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77201, 281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 282 {0,} /* terminate list */ 283 }; 284 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl); 285 286 287 288 static struct pci_driver nicstar_driver = { 289 .name = "nicstar", 290 .id_table = nicstar_pci_tbl, 291 .probe = nicstar_init_one, 292 .remove = __devexit_p(nicstar_remove_one), 293 }; 294 295 296 297 static int __init nicstar_init(void) 298 { 299 unsigned error = 0; /* Initialized to remove compile warning */ 300 301 XPRINTK("nicstar: nicstar_init() called.\n"); 302 303 error = pci_register_driver(&nicstar_driver); 304 305 TXPRINTK("nicstar: TX debug enabled.\n"); 306 RXPRINTK("nicstar: RX debug enabled.\n"); 307 PRINTK("nicstar: General debug enabled.\n"); 308 #ifdef PHY_LOOPBACK 309 printk("nicstar: using PHY loopback.\n"); 310 #endif /* PHY_LOOPBACK */ 311 XPRINTK("nicstar: nicstar_init() returned.\n"); 312 313 if (!error) { 314 init_timer(&ns_timer); 315 ns_timer.expires = jiffies + NS_POLL_PERIOD; 316 ns_timer.data = 0UL; 317 ns_timer.function = ns_poll; 318 add_timer(&ns_timer); 319 } 320 321 return error; 322 } 323 324 325 326 static void __exit nicstar_cleanup(void) 327 { 328 XPRINTK("nicstar: nicstar_cleanup() called.\n"); 329 330 del_timer(&ns_timer); 331 332 pci_unregister_driver(&nicstar_driver); 333 334 XPRINTK("nicstar: nicstar_cleanup() returned.\n"); 335 } 336 337 338 339 static u32 ns_read_sram(ns_dev *card, u32 sram_address) 340 { 341 unsigned long flags; 342 u32 data; 343 sram_address <<= 2; 344 sram_address &= 0x0007FFFC; /* address must be dword aligned */ 345 sram_address |= 0x50000000; /* SRAM read command */ 346 spin_lock_irqsave(&card->res_lock, flags); 347 while (CMD_BUSY(card)); 348 writel(sram_address, card->membase + CMD); 349 while (CMD_BUSY(card)); 350 data = readl(card->membase + DR0); 351 spin_unlock_irqrestore(&card->res_lock, flags); 352 return data; 353 } 354 355 356 357 static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count) 358 { 359 unsigned long flags; 360 int i, c; 361 count--; /* count range now is 0..3 instead of 1..4 */ 362 c = count; 363 c <<= 2; /* to use increments of 4 */ 364 spin_lock_irqsave(&card->res_lock, flags); 365 while (CMD_BUSY(card)); 366 for (i = 0; i <= c; i += 4) 367 writel(*(value++), card->membase + i); 368 /* Note: DR# registers are the first 4 dwords in nicstar's memspace, 369 so card->membase + DR0 == card->membase */ 370 sram_address <<= 2; 371 sram_address &= 0x0007FFFC; 372 sram_address |= (0x40000000 | count); 373 writel(sram_address, card->membase + CMD); 374 spin_unlock_irqrestore(&card->res_lock, flags); 375 } 376 377 378 static int __devinit ns_init_card(int i, struct pci_dev *pcidev) 379 { 380 int j; 381 struct ns_dev *card = NULL; 382 unsigned char pci_latency; 383 unsigned error; 384 u32 data; 385 u32 u32d[4]; 386 u32 ns_cfg_rctsize; 387 int bcount; 388 unsigned long membase; 389 390 error = 0; 391 392 if (pci_enable_device(pcidev)) 393 { 394 printk("nicstar%d: can't enable PCI device\n", i); 395 error = 2; 396 ns_init_card_error(card, error); 397 return error; 398 } 399 400 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) 401 { 402 printk("nicstar%d: can't allocate memory for device structure.\n", i); 403 error = 2; 404 ns_init_card_error(card, error); 405 return error; 406 } 407 cards[i] = card; 408 spin_lock_init(&card->int_lock); 409 spin_lock_init(&card->res_lock); 410 411 pci_set_drvdata(pcidev, card); 412 413 card->index = i; 414 card->atmdev = NULL; 415 card->pcidev = pcidev; 416 membase = pci_resource_start(pcidev, 1); 417 card->membase = ioremap(membase, NS_IOREMAP_SIZE); 418 if (!card->membase) 419 { 420 printk("nicstar%d: can't ioremap() membase.\n",i); 421 error = 3; 422 ns_init_card_error(card, error); 423 return error; 424 } 425 PRINTK("nicstar%d: membase at 0x%x.\n", i, card->membase); 426 427 pci_set_master(pcidev); 428 429 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) 430 { 431 printk("nicstar%d: can't read PCI latency timer.\n", i); 432 error = 6; 433 ns_init_card_error(card, error); 434 return error; 435 } 436 #ifdef NS_PCI_LATENCY 437 if (pci_latency < NS_PCI_LATENCY) 438 { 439 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, NS_PCI_LATENCY); 440 for (j = 1; j < 4; j++) 441 { 442 if (pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0) 443 break; 444 } 445 if (j == 4) 446 { 447 printk("nicstar%d: can't set PCI latency timer to %d.\n", i, NS_PCI_LATENCY); 448 error = 7; 449 ns_init_card_error(card, error); 450 return error; 451 } 452 } 453 #endif /* NS_PCI_LATENCY */ 454 455 /* Clear timer overflow */ 456 data = readl(card->membase + STAT); 457 if (data & NS_STAT_TMROF) 458 writel(NS_STAT_TMROF, card->membase + STAT); 459 460 /* Software reset */ 461 writel(NS_CFG_SWRST, card->membase + CFG); 462 NS_DELAY; 463 writel(0x00000000, card->membase + CFG); 464 465 /* PHY reset */ 466 writel(0x00000008, card->membase + GP); 467 NS_DELAY; 468 writel(0x00000001, card->membase + GP); 469 NS_DELAY; 470 while (CMD_BUSY(card)); 471 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ 472 NS_DELAY; 473 474 /* Detect PHY type */ 475 while (CMD_BUSY(card)); 476 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); 477 while (CMD_BUSY(card)); 478 data = readl(card->membase + DR0); 479 switch(data) { 480 case 0x00000009: 481 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i); 482 card->max_pcr = ATM_25_PCR; 483 while(CMD_BUSY(card)); 484 writel(0x00000008, card->membase + DR0); 485 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); 486 /* Clear an eventual pending interrupt */ 487 writel(NS_STAT_SFBQF, card->membase + STAT); 488 #ifdef PHY_LOOPBACK 489 while(CMD_BUSY(card)); 490 writel(0x00000022, card->membase + DR0); 491 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); 492 #endif /* PHY_LOOPBACK */ 493 break; 494 case 0x00000030: 495 case 0x00000031: 496 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i); 497 card->max_pcr = ATM_OC3_PCR; 498 #ifdef PHY_LOOPBACK 499 while(CMD_BUSY(card)); 500 writel(0x00000002, card->membase + DR0); 501 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); 502 #endif /* PHY_LOOPBACK */ 503 break; 504 default: 505 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data); 506 error = 8; 507 ns_init_card_error(card, error); 508 return error; 509 } 510 writel(0x00000000, card->membase + GP); 511 512 /* Determine SRAM size */ 513 data = 0x76543210; 514 ns_write_sram(card, 0x1C003, &data, 1); 515 data = 0x89ABCDEF; 516 ns_write_sram(card, 0x14003, &data, 1); 517 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF && 518 ns_read_sram(card, 0x1C003) == 0x76543210) 519 card->sram_size = 128; 520 else 521 card->sram_size = 32; 522 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size); 523 524 card->rct_size = NS_MAX_RCTSIZE; 525 526 #if (NS_MAX_RCTSIZE == 4096) 527 if (card->sram_size == 128) 528 printk("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", i); 529 #elif (NS_MAX_RCTSIZE == 16384) 530 if (card->sram_size == 32) 531 { 532 printk("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", i); 533 card->rct_size = 4096; 534 } 535 #else 536 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c 537 #endif 538 539 card->vpibits = NS_VPIBITS; 540 if (card->rct_size == 4096) 541 card->vcibits = 12 - NS_VPIBITS; 542 else /* card->rct_size == 16384 */ 543 card->vcibits = 14 - NS_VPIBITS; 544 545 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */ 546 if (mac[i] == NULL) 547 nicstar_init_eprom(card->membase); 548 549 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */ 550 writel(0x00000000, card->membase + VPM); 551 552 /* Initialize TSQ */ 553 card->tsq.org = kmalloc(NS_TSQSIZE + NS_TSQ_ALIGNMENT, GFP_KERNEL); 554 if (card->tsq.org == NULL) 555 { 556 printk("nicstar%d: can't allocate TSQ.\n", i); 557 error = 10; 558 ns_init_card_error(card, error); 559 return error; 560 } 561 card->tsq.base = (ns_tsi *) ALIGN_ADDRESS(card->tsq.org, NS_TSQ_ALIGNMENT); 562 card->tsq.next = card->tsq.base; 563 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); 564 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++) 565 ns_tsi_init(card->tsq.base + j); 566 writel(0x00000000, card->membase + TSQH); 567 writel((u32) virt_to_bus(card->tsq.base), card->membase + TSQB); 568 PRINTK("nicstar%d: TSQ base at 0x%x 0x%x 0x%x.\n", i, (u32) card->tsq.base, 569 (u32) virt_to_bus(card->tsq.base), readl(card->membase + TSQB)); 570 571 /* Initialize RSQ */ 572 card->rsq.org = kmalloc(NS_RSQSIZE + NS_RSQ_ALIGNMENT, GFP_KERNEL); 573 if (card->rsq.org == NULL) 574 { 575 printk("nicstar%d: can't allocate RSQ.\n", i); 576 error = 11; 577 ns_init_card_error(card, error); 578 return error; 579 } 580 card->rsq.base = (ns_rsqe *) ALIGN_ADDRESS(card->rsq.org, NS_RSQ_ALIGNMENT); 581 card->rsq.next = card->rsq.base; 582 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); 583 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++) 584 ns_rsqe_init(card->rsq.base + j); 585 writel(0x00000000, card->membase + RSQH); 586 writel((u32) virt_to_bus(card->rsq.base), card->membase + RSQB); 587 PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base); 588 589 /* Initialize SCQ0, the only VBR SCQ used */ 590 card->scq1 = NULL; 591 card->scq2 = NULL; 592 card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0); 593 if (card->scq0 == NULL) 594 { 595 printk("nicstar%d: can't get SCQ0.\n", i); 596 error = 12; 597 ns_init_card_error(card, error); 598 return error; 599 } 600 u32d[0] = (u32) virt_to_bus(card->scq0->base); 601 u32d[1] = (u32) 0x00000000; 602 u32d[2] = (u32) 0xffffffff; 603 u32d[3] = (u32) 0x00000000; 604 ns_write_sram(card, NS_VRSCD0, u32d, 4); 605 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */ 606 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */ 607 card->scq0->scd = NS_VRSCD0; 608 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%x.\n", i, (u32) card->scq0->base); 609 610 /* Initialize TSTs */ 611 card->tst_addr = NS_TST0; 612 card->tst_free_entries = NS_TST_NUM_ENTRIES; 613 data = NS_TST_OPCODE_VARIABLE; 614 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 615 ns_write_sram(card, NS_TST0 + j, &data, 1); 616 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0); 617 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1); 618 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 619 ns_write_sram(card, NS_TST1 + j, &data, 1); 620 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1); 621 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1); 622 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 623 card->tste2vc[j] = NULL; 624 writel(NS_TST0 << 2, card->membase + TSTB); 625 626 627 /* Initialize RCT. AAL type is set on opening the VC. */ 628 #ifdef RCQ_SUPPORT 629 u32d[0] = NS_RCTE_RAWCELLINTEN; 630 #else 631 u32d[0] = 0x00000000; 632 #endif /* RCQ_SUPPORT */ 633 u32d[1] = 0x00000000; 634 u32d[2] = 0x00000000; 635 u32d[3] = 0xFFFFFFFF; 636 for (j = 0; j < card->rct_size; j++) 637 ns_write_sram(card, j * 4, u32d, 4); 638 639 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map)); 640 641 for (j = 0; j < NS_FRSCD_NUM; j++) 642 card->scd2vc[j] = NULL; 643 644 /* Initialize buffer levels */ 645 card->sbnr.min = MIN_SB; 646 card->sbnr.init = NUM_SB; 647 card->sbnr.max = MAX_SB; 648 card->lbnr.min = MIN_LB; 649 card->lbnr.init = NUM_LB; 650 card->lbnr.max = MAX_LB; 651 card->iovnr.min = MIN_IOVB; 652 card->iovnr.init = NUM_IOVB; 653 card->iovnr.max = MAX_IOVB; 654 card->hbnr.min = MIN_HB; 655 card->hbnr.init = NUM_HB; 656 card->hbnr.max = MAX_HB; 657 658 card->sm_handle = 0x00000000; 659 card->sm_addr = 0x00000000; 660 card->lg_handle = 0x00000000; 661 card->lg_addr = 0x00000000; 662 663 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */ 664 665 /* Pre-allocate some huge buffers */ 666 skb_queue_head_init(&card->hbpool.queue); 667 card->hbpool.count = 0; 668 for (j = 0; j < NUM_HB; j++) 669 { 670 struct sk_buff *hb; 671 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 672 if (hb == NULL) 673 { 674 printk("nicstar%d: can't allocate %dth of %d huge buffers.\n", 675 i, j, NUM_HB); 676 error = 13; 677 ns_init_card_error(card, error); 678 return error; 679 } 680 NS_SKB_CB(hb)->buf_type = BUF_NONE; 681 skb_queue_tail(&card->hbpool.queue, hb); 682 card->hbpool.count++; 683 } 684 685 686 /* Allocate large buffers */ 687 skb_queue_head_init(&card->lbpool.queue); 688 card->lbpool.count = 0; /* Not used */ 689 for (j = 0; j < NUM_LB; j++) 690 { 691 struct sk_buff *lb; 692 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 693 if (lb == NULL) 694 { 695 printk("nicstar%d: can't allocate %dth of %d large buffers.\n", 696 i, j, NUM_LB); 697 error = 14; 698 ns_init_card_error(card, error); 699 return error; 700 } 701 NS_SKB_CB(lb)->buf_type = BUF_LG; 702 skb_queue_tail(&card->lbpool.queue, lb); 703 skb_reserve(lb, NS_SMBUFSIZE); 704 push_rxbufs(card, lb); 705 /* Due to the implementation of push_rxbufs() this is 1, not 0 */ 706 if (j == 1) 707 { 708 card->rcbuf = lb; 709 card->rawch = (u32) virt_to_bus(lb->data); 710 } 711 } 712 /* Test for strange behaviour which leads to crashes */ 713 if ((bcount = ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) 714 { 715 printk("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n", 716 i, j, bcount); 717 error = 14; 718 ns_init_card_error(card, error); 719 return error; 720 } 721 722 723 /* Allocate small buffers */ 724 skb_queue_head_init(&card->sbpool.queue); 725 card->sbpool.count = 0; /* Not used */ 726 for (j = 0; j < NUM_SB; j++) 727 { 728 struct sk_buff *sb; 729 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 730 if (sb == NULL) 731 { 732 printk("nicstar%d: can't allocate %dth of %d small buffers.\n", 733 i, j, NUM_SB); 734 error = 15; 735 ns_init_card_error(card, error); 736 return error; 737 } 738 NS_SKB_CB(sb)->buf_type = BUF_SM; 739 skb_queue_tail(&card->sbpool.queue, sb); 740 skb_reserve(sb, NS_AAL0_HEADER); 741 push_rxbufs(card, sb); 742 } 743 /* Test for strange behaviour which leads to crashes */ 744 if ((bcount = ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) 745 { 746 printk("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n", 747 i, j, bcount); 748 error = 15; 749 ns_init_card_error(card, error); 750 return error; 751 } 752 753 754 /* Allocate iovec buffers */ 755 skb_queue_head_init(&card->iovpool.queue); 756 card->iovpool.count = 0; 757 for (j = 0; j < NUM_IOVB; j++) 758 { 759 struct sk_buff *iovb; 760 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 761 if (iovb == NULL) 762 { 763 printk("nicstar%d: can't allocate %dth of %d iovec buffers.\n", 764 i, j, NUM_IOVB); 765 error = 16; 766 ns_init_card_error(card, error); 767 return error; 768 } 769 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 770 skb_queue_tail(&card->iovpool.queue, iovb); 771 card->iovpool.count++; 772 } 773 774 /* Configure NICStAR */ 775 if (card->rct_size == 4096) 776 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES; 777 else /* (card->rct_size == 16384) */ 778 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES; 779 780 card->efbie = 1; 781 782 card->intcnt = 0; 783 if (request_irq(pcidev->irq, &ns_irq_handler, IRQF_DISABLED | IRQF_SHARED, "nicstar", card) != 0) 784 { 785 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq); 786 error = 9; 787 ns_init_card_error(card, error); 788 return error; 789 } 790 791 /* Register device */ 792 card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL); 793 if (card->atmdev == NULL) 794 { 795 printk("nicstar%d: can't register device.\n", i); 796 error = 17; 797 ns_init_card_error(card, error); 798 return error; 799 } 800 801 if (ns_parse_mac(mac[i], card->atmdev->esi)) { 802 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, 803 card->atmdev->esi, 6); 804 if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) == 0) { 805 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT, 806 card->atmdev->esi, 6); 807 } 808 } 809 810 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi); 811 812 card->atmdev->dev_data = card; 813 card->atmdev->ci_range.vpi_bits = card->vpibits; 814 card->atmdev->ci_range.vci_bits = card->vcibits; 815 card->atmdev->link_rate = card->max_pcr; 816 card->atmdev->phy = NULL; 817 818 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 819 if (card->max_pcr == ATM_OC3_PCR) 820 suni_init(card->atmdev); 821 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 822 823 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 824 if (card->max_pcr == ATM_25_PCR) 825 idt77105_init(card->atmdev); 826 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 827 828 if (card->atmdev->phy && card->atmdev->phy->start) 829 card->atmdev->phy->start(card->atmdev); 830 831 writel(NS_CFG_RXPATH | 832 NS_CFG_SMBUFSIZE | 833 NS_CFG_LGBUFSIZE | 834 NS_CFG_EFBIE | 835 NS_CFG_RSQSIZE | 836 NS_CFG_VPIBITS | 837 ns_cfg_rctsize | 838 NS_CFG_RXINT_NODELAY | 839 NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */ 840 NS_CFG_RSQAFIE | 841 NS_CFG_TXEN | 842 NS_CFG_TXIE | 843 NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */ 844 NS_CFG_PHYIE, 845 card->membase + CFG); 846 847 num_cards++; 848 849 return error; 850 } 851 852 853 854 static void __devinit ns_init_card_error(ns_dev *card, int error) 855 { 856 if (error >= 17) 857 { 858 writel(0x00000000, card->membase + CFG); 859 } 860 if (error >= 16) 861 { 862 struct sk_buff *iovb; 863 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 864 dev_kfree_skb_any(iovb); 865 } 866 if (error >= 15) 867 { 868 struct sk_buff *sb; 869 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 870 dev_kfree_skb_any(sb); 871 free_scq(card->scq0, NULL); 872 } 873 if (error >= 14) 874 { 875 struct sk_buff *lb; 876 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 877 dev_kfree_skb_any(lb); 878 } 879 if (error >= 13) 880 { 881 struct sk_buff *hb; 882 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 883 dev_kfree_skb_any(hb); 884 } 885 if (error >= 12) 886 { 887 kfree(card->rsq.org); 888 } 889 if (error >= 11) 890 { 891 kfree(card->tsq.org); 892 } 893 if (error >= 10) 894 { 895 free_irq(card->pcidev->irq, card); 896 } 897 if (error >= 4) 898 { 899 iounmap(card->membase); 900 } 901 if (error >= 3) 902 { 903 pci_disable_device(card->pcidev); 904 kfree(card); 905 } 906 } 907 908 909 910 static scq_info *get_scq(int size, u32 scd) 911 { 912 scq_info *scq; 913 int i; 914 915 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE) 916 return NULL; 917 918 scq = kmalloc(sizeof(scq_info), GFP_KERNEL); 919 if (scq == NULL) 920 return NULL; 921 scq->org = kmalloc(2 * size, GFP_KERNEL); 922 if (scq->org == NULL) 923 { 924 kfree(scq); 925 return NULL; 926 } 927 scq->skb = kmalloc(sizeof(struct sk_buff *) * 928 (size / NS_SCQE_SIZE), GFP_KERNEL); 929 if (scq->skb == NULL) 930 { 931 kfree(scq->org); 932 kfree(scq); 933 return NULL; 934 } 935 scq->num_entries = size / NS_SCQE_SIZE; 936 scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size); 937 scq->next = scq->base; 938 scq->last = scq->base + (scq->num_entries - 1); 939 scq->tail = scq->last; 940 scq->scd = scd; 941 scq->num_entries = size / NS_SCQE_SIZE; 942 scq->tbd_count = 0; 943 init_waitqueue_head(&scq->scqfull_waitq); 944 scq->full = 0; 945 spin_lock_init(&scq->lock); 946 947 for (i = 0; i < scq->num_entries; i++) 948 scq->skb[i] = NULL; 949 950 return scq; 951 } 952 953 954 955 /* For variable rate SCQ vcc must be NULL */ 956 static void free_scq(scq_info *scq, struct atm_vcc *vcc) 957 { 958 int i; 959 960 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 961 for (i = 0; i < scq->num_entries; i++) 962 { 963 if (scq->skb[i] != NULL) 964 { 965 vcc = ATM_SKB(scq->skb[i])->vcc; 966 if (vcc->pop != NULL) 967 vcc->pop(vcc, scq->skb[i]); 968 else 969 dev_kfree_skb_any(scq->skb[i]); 970 } 971 } 972 else /* vcc must be != NULL */ 973 { 974 if (vcc == NULL) 975 { 976 printk("nicstar: free_scq() called with vcc == NULL for fixed rate scq."); 977 for (i = 0; i < scq->num_entries; i++) 978 dev_kfree_skb_any(scq->skb[i]); 979 } 980 else 981 for (i = 0; i < scq->num_entries; i++) 982 { 983 if (scq->skb[i] != NULL) 984 { 985 if (vcc->pop != NULL) 986 vcc->pop(vcc, scq->skb[i]); 987 else 988 dev_kfree_skb_any(scq->skb[i]); 989 } 990 } 991 } 992 kfree(scq->skb); 993 kfree(scq->org); 994 kfree(scq); 995 } 996 997 998 999 /* The handles passed must be pointers to the sk_buff containing the small 1000 or large buffer(s) cast to u32. */ 1001 static void push_rxbufs(ns_dev *card, struct sk_buff *skb) 1002 { 1003 struct ns_skb_cb *cb = NS_SKB_CB(skb); 1004 u32 handle1, addr1; 1005 u32 handle2, addr2; 1006 u32 stat; 1007 unsigned long flags; 1008 1009 /* *BARF* */ 1010 handle2 = addr2 = 0; 1011 handle1 = (u32)skb; 1012 addr1 = (u32)virt_to_bus(skb->data); 1013 1014 #ifdef GENERAL_DEBUG 1015 if (!addr1) 1016 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", card->index); 1017 #endif /* GENERAL_DEBUG */ 1018 1019 stat = readl(card->membase + STAT); 1020 card->sbfqc = ns_stat_sfbqc_get(stat); 1021 card->lbfqc = ns_stat_lfbqc_get(stat); 1022 if (cb->buf_type == BUF_SM) 1023 { 1024 if (!addr2) 1025 { 1026 if (card->sm_addr) 1027 { 1028 addr2 = card->sm_addr; 1029 handle2 = card->sm_handle; 1030 card->sm_addr = 0x00000000; 1031 card->sm_handle = 0x00000000; 1032 } 1033 else /* (!sm_addr) */ 1034 { 1035 card->sm_addr = addr1; 1036 card->sm_handle = handle1; 1037 } 1038 } 1039 } 1040 else /* buf_type == BUF_LG */ 1041 { 1042 if (!addr2) 1043 { 1044 if (card->lg_addr) 1045 { 1046 addr2 = card->lg_addr; 1047 handle2 = card->lg_handle; 1048 card->lg_addr = 0x00000000; 1049 card->lg_handle = 0x00000000; 1050 } 1051 else /* (!lg_addr) */ 1052 { 1053 card->lg_addr = addr1; 1054 card->lg_handle = handle1; 1055 } 1056 } 1057 } 1058 1059 if (addr2) 1060 { 1061 if (cb->buf_type == BUF_SM) 1062 { 1063 if (card->sbfqc >= card->sbnr.max) 1064 { 1065 skb_unlink((struct sk_buff *) handle1, &card->sbpool.queue); 1066 dev_kfree_skb_any((struct sk_buff *) handle1); 1067 skb_unlink((struct sk_buff *) handle2, &card->sbpool.queue); 1068 dev_kfree_skb_any((struct sk_buff *) handle2); 1069 return; 1070 } 1071 else 1072 card->sbfqc += 2; 1073 } 1074 else /* (buf_type == BUF_LG) */ 1075 { 1076 if (card->lbfqc >= card->lbnr.max) 1077 { 1078 skb_unlink((struct sk_buff *) handle1, &card->lbpool.queue); 1079 dev_kfree_skb_any((struct sk_buff *) handle1); 1080 skb_unlink((struct sk_buff *) handle2, &card->lbpool.queue); 1081 dev_kfree_skb_any((struct sk_buff *) handle2); 1082 return; 1083 } 1084 else 1085 card->lbfqc += 2; 1086 } 1087 1088 spin_lock_irqsave(&card->res_lock, flags); 1089 1090 while (CMD_BUSY(card)); 1091 writel(addr2, card->membase + DR3); 1092 writel(handle2, card->membase + DR2); 1093 writel(addr1, card->membase + DR1); 1094 writel(handle1, card->membase + DR0); 1095 writel(NS_CMD_WRITE_FREEBUFQ | cb->buf_type, card->membase + CMD); 1096 1097 spin_unlock_irqrestore(&card->res_lock, flags); 1098 1099 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", card->index, 1100 (cb->buf_type == BUF_SM ? "small" : "large"), addr1, addr2); 1101 } 1102 1103 if (!card->efbie && card->sbfqc >= card->sbnr.min && 1104 card->lbfqc >= card->lbnr.min) 1105 { 1106 card->efbie = 1; 1107 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), card->membase + CFG); 1108 } 1109 1110 return; 1111 } 1112 1113 1114 1115 static irqreturn_t ns_irq_handler(int irq, void *dev_id) 1116 { 1117 u32 stat_r; 1118 ns_dev *card; 1119 struct atm_dev *dev; 1120 unsigned long flags; 1121 1122 card = (ns_dev *) dev_id; 1123 dev = card->atmdev; 1124 card->intcnt++; 1125 1126 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index); 1127 1128 spin_lock_irqsave(&card->int_lock, flags); 1129 1130 stat_r = readl(card->membase + STAT); 1131 1132 /* Transmit Status Indicator has been written to T. S. Queue */ 1133 if (stat_r & NS_STAT_TSIF) 1134 { 1135 TXPRINTK("nicstar%d: TSI interrupt\n", card->index); 1136 process_tsq(card); 1137 writel(NS_STAT_TSIF, card->membase + STAT); 1138 } 1139 1140 /* Incomplete CS-PDU has been transmitted */ 1141 if (stat_r & NS_STAT_TXICP) 1142 { 1143 writel(NS_STAT_TXICP, card->membase + STAT); 1144 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n", 1145 card->index); 1146 } 1147 1148 /* Transmit Status Queue 7/8 full */ 1149 if (stat_r & NS_STAT_TSQF) 1150 { 1151 writel(NS_STAT_TSQF, card->membase + STAT); 1152 PRINTK("nicstar%d: TSQ full.\n", card->index); 1153 process_tsq(card); 1154 } 1155 1156 /* Timer overflow */ 1157 if (stat_r & NS_STAT_TMROF) 1158 { 1159 writel(NS_STAT_TMROF, card->membase + STAT); 1160 PRINTK("nicstar%d: Timer overflow.\n", card->index); 1161 } 1162 1163 /* PHY device interrupt signal active */ 1164 if (stat_r & NS_STAT_PHYI) 1165 { 1166 writel(NS_STAT_PHYI, card->membase + STAT); 1167 PRINTK("nicstar%d: PHY interrupt.\n", card->index); 1168 if (dev->phy && dev->phy->interrupt) { 1169 dev->phy->interrupt(dev); 1170 } 1171 } 1172 1173 /* Small Buffer Queue is full */ 1174 if (stat_r & NS_STAT_SFBQF) 1175 { 1176 writel(NS_STAT_SFBQF, card->membase + STAT); 1177 printk("nicstar%d: Small free buffer queue is full.\n", card->index); 1178 } 1179 1180 /* Large Buffer Queue is full */ 1181 if (stat_r & NS_STAT_LFBQF) 1182 { 1183 writel(NS_STAT_LFBQF, card->membase + STAT); 1184 printk("nicstar%d: Large free buffer queue is full.\n", card->index); 1185 } 1186 1187 /* Receive Status Queue is full */ 1188 if (stat_r & NS_STAT_RSQF) 1189 { 1190 writel(NS_STAT_RSQF, card->membase + STAT); 1191 printk("nicstar%d: RSQ full.\n", card->index); 1192 process_rsq(card); 1193 } 1194 1195 /* Complete CS-PDU received */ 1196 if (stat_r & NS_STAT_EOPDU) 1197 { 1198 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index); 1199 process_rsq(card); 1200 writel(NS_STAT_EOPDU, card->membase + STAT); 1201 } 1202 1203 /* Raw cell received */ 1204 if (stat_r & NS_STAT_RAWCF) 1205 { 1206 writel(NS_STAT_RAWCF, card->membase + STAT); 1207 #ifndef RCQ_SUPPORT 1208 printk("nicstar%d: Raw cell received and no support yet...\n", 1209 card->index); 1210 #endif /* RCQ_SUPPORT */ 1211 /* NOTE: the following procedure may keep a raw cell pending until the 1212 next interrupt. As this preliminary support is only meant to 1213 avoid buffer leakage, this is not an issue. */ 1214 while (readl(card->membase + RAWCT) != card->rawch) 1215 { 1216 ns_rcqe *rawcell; 1217 1218 rawcell = (ns_rcqe *) bus_to_virt(card->rawch); 1219 if (ns_rcqe_islast(rawcell)) 1220 { 1221 struct sk_buff *oldbuf; 1222 1223 oldbuf = card->rcbuf; 1224 card->rcbuf = (struct sk_buff *) ns_rcqe_nextbufhandle(rawcell); 1225 card->rawch = (u32) virt_to_bus(card->rcbuf->data); 1226 recycle_rx_buf(card, oldbuf); 1227 } 1228 else 1229 card->rawch += NS_RCQE_SIZE; 1230 } 1231 } 1232 1233 /* Small buffer queue is empty */ 1234 if (stat_r & NS_STAT_SFBQE) 1235 { 1236 int i; 1237 struct sk_buff *sb; 1238 1239 writel(NS_STAT_SFBQE, card->membase + STAT); 1240 printk("nicstar%d: Small free buffer queue empty.\n", 1241 card->index); 1242 for (i = 0; i < card->sbnr.min; i++) 1243 { 1244 sb = dev_alloc_skb(NS_SMSKBSIZE); 1245 if (sb == NULL) 1246 { 1247 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG); 1248 card->efbie = 0; 1249 break; 1250 } 1251 NS_SKB_CB(sb)->buf_type = BUF_SM; 1252 skb_queue_tail(&card->sbpool.queue, sb); 1253 skb_reserve(sb, NS_AAL0_HEADER); 1254 push_rxbufs(card, sb); 1255 } 1256 card->sbfqc = i; 1257 process_rsq(card); 1258 } 1259 1260 /* Large buffer queue empty */ 1261 if (stat_r & NS_STAT_LFBQE) 1262 { 1263 int i; 1264 struct sk_buff *lb; 1265 1266 writel(NS_STAT_LFBQE, card->membase + STAT); 1267 printk("nicstar%d: Large free buffer queue empty.\n", 1268 card->index); 1269 for (i = 0; i < card->lbnr.min; i++) 1270 { 1271 lb = dev_alloc_skb(NS_LGSKBSIZE); 1272 if (lb == NULL) 1273 { 1274 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG); 1275 card->efbie = 0; 1276 break; 1277 } 1278 NS_SKB_CB(lb)->buf_type = BUF_LG; 1279 skb_queue_tail(&card->lbpool.queue, lb); 1280 skb_reserve(lb, NS_SMBUFSIZE); 1281 push_rxbufs(card, lb); 1282 } 1283 card->lbfqc = i; 1284 process_rsq(card); 1285 } 1286 1287 /* Receive Status Queue is 7/8 full */ 1288 if (stat_r & NS_STAT_RSQAF) 1289 { 1290 writel(NS_STAT_RSQAF, card->membase + STAT); 1291 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index); 1292 process_rsq(card); 1293 } 1294 1295 spin_unlock_irqrestore(&card->int_lock, flags); 1296 PRINTK("nicstar%d: end of interrupt service\n", card->index); 1297 return IRQ_HANDLED; 1298 } 1299 1300 1301 1302 static int ns_open(struct atm_vcc *vcc) 1303 { 1304 ns_dev *card; 1305 vc_map *vc; 1306 unsigned long tmpl, modl; 1307 int tcr, tcra; /* target cell rate, and absolute value */ 1308 int n = 0; /* Number of entries in the TST. Initialized to remove 1309 the compiler warning. */ 1310 u32 u32d[4]; 1311 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler 1312 warning. How I wish compilers were clever enough to 1313 tell which variables can truly be used 1314 uninitialized... */ 1315 int inuse; /* tx or rx vc already in use by another vcc */ 1316 short vpi = vcc->vpi; 1317 int vci = vcc->vci; 1318 1319 card = (ns_dev *) vcc->dev->dev_data; 1320 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int) vpi, vci); 1321 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) 1322 { 1323 PRINTK("nicstar%d: unsupported AAL.\n", card->index); 1324 return -EINVAL; 1325 } 1326 1327 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1328 vcc->dev_data = vc; 1329 1330 inuse = 0; 1331 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx) 1332 inuse = 1; 1333 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx) 1334 inuse += 2; 1335 if (inuse) 1336 { 1337 printk("nicstar%d: %s vci already in use.\n", card->index, 1338 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 1339 return -EINVAL; 1340 } 1341 1342 set_bit(ATM_VF_ADDR,&vcc->flags); 1343 1344 /* NOTE: You are not allowed to modify an open connection's QOS. To change 1345 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes 1346 needed to do that. */ 1347 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) 1348 { 1349 scq_info *scq; 1350 1351 set_bit(ATM_VF_PARTIAL,&vcc->flags); 1352 if (vcc->qos.txtp.traffic_class == ATM_CBR) 1353 { 1354 /* Check requested cell rate and availability of SCD */ 1355 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 && 1356 vcc->qos.txtp.min_pcr == 0) 1357 { 1358 PRINTK("nicstar%d: trying to open a CBR vc with cell rate = 0 \n", 1359 card->index); 1360 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1361 clear_bit(ATM_VF_ADDR,&vcc->flags); 1362 return -EINVAL; 1363 } 1364 1365 tcr = atm_pcr_goal(&(vcc->qos.txtp)); 1366 tcra = tcr >= 0 ? tcr : -tcr; 1367 1368 PRINTK("nicstar%d: target cell rate = %d.\n", card->index, 1369 vcc->qos.txtp.max_pcr); 1370 1371 tmpl = (unsigned long)tcra * (unsigned long)NS_TST_NUM_ENTRIES; 1372 modl = tmpl % card->max_pcr; 1373 1374 n = (int)(tmpl / card->max_pcr); 1375 if (tcr > 0) 1376 { 1377 if (modl > 0) n++; 1378 } 1379 else if (tcr == 0) 1380 { 1381 if ((n = (card->tst_free_entries - NS_TST_RESERVED)) <= 0) 1382 { 1383 PRINTK("nicstar%d: no CBR bandwidth free.\n", card->index); 1384 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1385 clear_bit(ATM_VF_ADDR,&vcc->flags); 1386 return -EINVAL; 1387 } 1388 } 1389 1390 if (n == 0) 1391 { 1392 printk("nicstar%d: selected bandwidth < granularity.\n", card->index); 1393 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1394 clear_bit(ATM_VF_ADDR,&vcc->flags); 1395 return -EINVAL; 1396 } 1397 1398 if (n > (card->tst_free_entries - NS_TST_RESERVED)) 1399 { 1400 PRINTK("nicstar%d: not enough free CBR bandwidth.\n", card->index); 1401 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1402 clear_bit(ATM_VF_ADDR,&vcc->flags); 1403 return -EINVAL; 1404 } 1405 else 1406 card->tst_free_entries -= n; 1407 1408 XPRINTK("nicstar%d: writing %d tst entries.\n", card->index, n); 1409 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) 1410 { 1411 if (card->scd2vc[frscdi] == NULL) 1412 { 1413 card->scd2vc[frscdi] = vc; 1414 break; 1415 } 1416 } 1417 if (frscdi == NS_FRSCD_NUM) 1418 { 1419 PRINTK("nicstar%d: no SCD available for CBR channel.\n", card->index); 1420 card->tst_free_entries += n; 1421 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1422 clear_bit(ATM_VF_ADDR,&vcc->flags); 1423 return -EBUSY; 1424 } 1425 1426 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE; 1427 1428 scq = get_scq(CBR_SCQSIZE, vc->cbr_scd); 1429 if (scq == NULL) 1430 { 1431 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", card->index); 1432 card->scd2vc[frscdi] = NULL; 1433 card->tst_free_entries += n; 1434 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1435 clear_bit(ATM_VF_ADDR,&vcc->flags); 1436 return -ENOMEM; 1437 } 1438 vc->scq = scq; 1439 u32d[0] = (u32) virt_to_bus(scq->base); 1440 u32d[1] = (u32) 0x00000000; 1441 u32d[2] = (u32) 0xffffffff; 1442 u32d[3] = (u32) 0x00000000; 1443 ns_write_sram(card, vc->cbr_scd, u32d, 4); 1444 1445 fill_tst(card, n, vc); 1446 } 1447 else if (vcc->qos.txtp.traffic_class == ATM_UBR) 1448 { 1449 vc->cbr_scd = 0x00000000; 1450 vc->scq = card->scq0; 1451 } 1452 1453 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1454 { 1455 vc->tx = 1; 1456 vc->tx_vcc = vcc; 1457 vc->tbd_count = 0; 1458 } 1459 if (vcc->qos.rxtp.traffic_class != ATM_NONE) 1460 { 1461 u32 status; 1462 1463 vc->rx = 1; 1464 vc->rx_vcc = vcc; 1465 vc->rx_iov = NULL; 1466 1467 /* Open the connection in hardware */ 1468 if (vcc->qos.aal == ATM_AAL5) 1469 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN; 1470 else /* vcc->qos.aal == ATM_AAL0 */ 1471 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN; 1472 #ifdef RCQ_SUPPORT 1473 status |= NS_RCTE_RAWCELLINTEN; 1474 #endif /* RCQ_SUPPORT */ 1475 ns_write_sram(card, NS_RCT + (vpi << card->vcibits | vci) * 1476 NS_RCT_ENTRY_SIZE, &status, 1); 1477 } 1478 1479 } 1480 1481 set_bit(ATM_VF_READY,&vcc->flags); 1482 return 0; 1483 } 1484 1485 1486 1487 static void ns_close(struct atm_vcc *vcc) 1488 { 1489 vc_map *vc; 1490 ns_dev *card; 1491 u32 data; 1492 int i; 1493 1494 vc = vcc->dev_data; 1495 card = vcc->dev->dev_data; 1496 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index, 1497 (int) vcc->vpi, vcc->vci); 1498 1499 clear_bit(ATM_VF_READY,&vcc->flags); 1500 1501 if (vcc->qos.rxtp.traffic_class != ATM_NONE) 1502 { 1503 u32 addr; 1504 unsigned long flags; 1505 1506 addr = NS_RCT + (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE; 1507 spin_lock_irqsave(&card->res_lock, flags); 1508 while(CMD_BUSY(card)); 1509 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, card->membase + CMD); 1510 spin_unlock_irqrestore(&card->res_lock, flags); 1511 1512 vc->rx = 0; 1513 if (vc->rx_iov != NULL) 1514 { 1515 struct sk_buff *iovb; 1516 u32 stat; 1517 1518 stat = readl(card->membase + STAT); 1519 card->sbfqc = ns_stat_sfbqc_get(stat); 1520 card->lbfqc = ns_stat_lfbqc_get(stat); 1521 1522 PRINTK("nicstar%d: closing a VC with pending rx buffers.\n", 1523 card->index); 1524 iovb = vc->rx_iov; 1525 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 1526 NS_SKB(iovb)->iovcnt); 1527 NS_SKB(iovb)->iovcnt = 0; 1528 NS_SKB(iovb)->vcc = NULL; 1529 spin_lock_irqsave(&card->int_lock, flags); 1530 recycle_iov_buf(card, iovb); 1531 spin_unlock_irqrestore(&card->int_lock, flags); 1532 vc->rx_iov = NULL; 1533 } 1534 } 1535 1536 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1537 { 1538 vc->tx = 0; 1539 } 1540 1541 if (vcc->qos.txtp.traffic_class == ATM_CBR) 1542 { 1543 unsigned long flags; 1544 ns_scqe *scqep; 1545 scq_info *scq; 1546 1547 scq = vc->scq; 1548 1549 for (;;) 1550 { 1551 spin_lock_irqsave(&scq->lock, flags); 1552 scqep = scq->next; 1553 if (scqep == scq->base) 1554 scqep = scq->last; 1555 else 1556 scqep--; 1557 if (scqep == scq->tail) 1558 { 1559 spin_unlock_irqrestore(&scq->lock, flags); 1560 break; 1561 } 1562 /* If the last entry is not a TSR, place one in the SCQ in order to 1563 be able to completely drain it and then close. */ 1564 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) 1565 { 1566 ns_scqe tsr; 1567 u32 scdi, scqi; 1568 u32 data; 1569 int index; 1570 1571 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1572 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1573 scqi = scq->next - scq->base; 1574 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1575 tsr.word_3 = 0x00000000; 1576 tsr.word_4 = 0x00000000; 1577 *scq->next = tsr; 1578 index = (int) scqi; 1579 scq->skb[index] = NULL; 1580 if (scq->next == scq->last) 1581 scq->next = scq->base; 1582 else 1583 scq->next++; 1584 data = (u32) virt_to_bus(scq->next); 1585 ns_write_sram(card, scq->scd, &data, 1); 1586 } 1587 spin_unlock_irqrestore(&scq->lock, flags); 1588 schedule(); 1589 } 1590 1591 /* Free all TST entries */ 1592 data = NS_TST_OPCODE_VARIABLE; 1593 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) 1594 { 1595 if (card->tste2vc[i] == vc) 1596 { 1597 ns_write_sram(card, card->tst_addr + i, &data, 1); 1598 card->tste2vc[i] = NULL; 1599 card->tst_free_entries++; 1600 } 1601 } 1602 1603 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL; 1604 free_scq(vc->scq, vcc); 1605 } 1606 1607 /* remove all references to vcc before deleting it */ 1608 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1609 { 1610 unsigned long flags; 1611 scq_info *scq = card->scq0; 1612 1613 spin_lock_irqsave(&scq->lock, flags); 1614 1615 for(i = 0; i < scq->num_entries; i++) { 1616 if(scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) { 1617 ATM_SKB(scq->skb[i])->vcc = NULL; 1618 atm_return(vcc, scq->skb[i]->truesize); 1619 PRINTK("nicstar: deleted pending vcc mapping\n"); 1620 } 1621 } 1622 1623 spin_unlock_irqrestore(&scq->lock, flags); 1624 } 1625 1626 vcc->dev_data = NULL; 1627 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1628 clear_bit(ATM_VF_ADDR,&vcc->flags); 1629 1630 #ifdef RX_DEBUG 1631 { 1632 u32 stat, cfg; 1633 stat = readl(card->membase + STAT); 1634 cfg = readl(card->membase + CFG); 1635 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); 1636 printk("TSQ: base = 0x%08X next = 0x%08X last = 0x%08X TSQT = 0x%08X \n", 1637 (u32) card->tsq.base, (u32) card->tsq.next,(u32) card->tsq.last, 1638 readl(card->membase + TSQT)); 1639 printk("RSQ: base = 0x%08X next = 0x%08X last = 0x%08X RSQT = 0x%08X \n", 1640 (u32) card->rsq.base, (u32) card->rsq.next,(u32) card->rsq.last, 1641 readl(card->membase + RSQT)); 1642 printk("Empty free buffer queue interrupt %s \n", 1643 card->efbie ? "enabled" : "disabled"); 1644 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n", 1645 ns_stat_sfbqc_get(stat), card->sbpool.count, 1646 ns_stat_lfbqc_get(stat), card->lbpool.count); 1647 printk("hbpool.count = %d iovpool.count = %d \n", 1648 card->hbpool.count, card->iovpool.count); 1649 } 1650 #endif /* RX_DEBUG */ 1651 } 1652 1653 1654 1655 static void fill_tst(ns_dev *card, int n, vc_map *vc) 1656 { 1657 u32 new_tst; 1658 unsigned long cl; 1659 int e, r; 1660 u32 data; 1661 1662 /* It would be very complicated to keep the two TSTs synchronized while 1663 assuring that writes are only made to the inactive TST. So, for now I 1664 will use only one TST. If problems occur, I will change this again */ 1665 1666 new_tst = card->tst_addr; 1667 1668 /* Fill procedure */ 1669 1670 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) 1671 { 1672 if (card->tste2vc[e] == NULL) 1673 break; 1674 } 1675 if (e == NS_TST_NUM_ENTRIES) { 1676 printk("nicstar%d: No free TST entries found. \n", card->index); 1677 return; 1678 } 1679 1680 r = n; 1681 cl = NS_TST_NUM_ENTRIES; 1682 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd); 1683 1684 while (r > 0) 1685 { 1686 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) 1687 { 1688 card->tste2vc[e] = vc; 1689 ns_write_sram(card, new_tst + e, &data, 1); 1690 cl -= NS_TST_NUM_ENTRIES; 1691 r--; 1692 } 1693 1694 if (++e == NS_TST_NUM_ENTRIES) { 1695 e = 0; 1696 } 1697 cl += n; 1698 } 1699 1700 /* End of fill procedure */ 1701 1702 data = ns_tste_make(NS_TST_OPCODE_END, new_tst); 1703 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1); 1704 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1); 1705 card->tst_addr = new_tst; 1706 } 1707 1708 1709 1710 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb) 1711 { 1712 ns_dev *card; 1713 vc_map *vc; 1714 scq_info *scq; 1715 unsigned long buflen; 1716 ns_scqe scqe; 1717 u32 flags; /* TBD flags, not CPU flags */ 1718 1719 card = vcc->dev->dev_data; 1720 TXPRINTK("nicstar%d: ns_send() called.\n", card->index); 1721 if ((vc = (vc_map *) vcc->dev_data) == NULL) 1722 { 1723 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", card->index); 1724 atomic_inc(&vcc->stats->tx_err); 1725 dev_kfree_skb_any(skb); 1726 return -EINVAL; 1727 } 1728 1729 if (!vc->tx) 1730 { 1731 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", card->index); 1732 atomic_inc(&vcc->stats->tx_err); 1733 dev_kfree_skb_any(skb); 1734 return -EINVAL; 1735 } 1736 1737 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) 1738 { 1739 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", card->index); 1740 atomic_inc(&vcc->stats->tx_err); 1741 dev_kfree_skb_any(skb); 1742 return -EINVAL; 1743 } 1744 1745 if (skb_shinfo(skb)->nr_frags != 0) 1746 { 1747 printk("nicstar%d: No scatter-gather yet.\n", card->index); 1748 atomic_inc(&vcc->stats->tx_err); 1749 dev_kfree_skb_any(skb); 1750 return -EINVAL; 1751 } 1752 1753 ATM_SKB(skb)->vcc = vcc; 1754 1755 if (vcc->qos.aal == ATM_AAL5) 1756 { 1757 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */ 1758 flags = NS_TBD_AAL5; 1759 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data)); 1760 scqe.word_3 = cpu_to_le32((u32) skb->len); 1761 scqe.word_4 = ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0, 1762 ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ? 1 : 0); 1763 flags |= NS_TBD_EOPDU; 1764 } 1765 else /* (vcc->qos.aal == ATM_AAL0) */ 1766 { 1767 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */ 1768 flags = NS_TBD_AAL0; 1769 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data) + NS_AAL0_HEADER); 1770 scqe.word_3 = cpu_to_le32(0x00000000); 1771 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */ 1772 flags |= NS_TBD_EOPDU; 1773 scqe.word_4 = cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK); 1774 /* Force the VPI/VCI to be the same as in VCC struct */ 1775 scqe.word_4 |= cpu_to_le32((((u32) vcc->vpi) << NS_TBD_VPI_SHIFT | 1776 ((u32) vcc->vci) << NS_TBD_VCI_SHIFT) & 1777 NS_TBD_VC_MASK); 1778 } 1779 1780 if (vcc->qos.txtp.traffic_class == ATM_CBR) 1781 { 1782 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen); 1783 scq = ((vc_map *) vcc->dev_data)->scq; 1784 } 1785 else 1786 { 1787 scqe.word_1 = ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen); 1788 scq = card->scq0; 1789 } 1790 1791 if (push_scqe(card, vc, scq, &scqe, skb) != 0) 1792 { 1793 atomic_inc(&vcc->stats->tx_err); 1794 dev_kfree_skb_any(skb); 1795 return -EIO; 1796 } 1797 atomic_inc(&vcc->stats->tx); 1798 1799 return 0; 1800 } 1801 1802 1803 1804 static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd, 1805 struct sk_buff *skb) 1806 { 1807 unsigned long flags; 1808 ns_scqe tsr; 1809 u32 scdi, scqi; 1810 int scq_is_vbr; 1811 u32 data; 1812 int index; 1813 1814 spin_lock_irqsave(&scq->lock, flags); 1815 while (scq->tail == scq->next) 1816 { 1817 if (in_interrupt()) { 1818 spin_unlock_irqrestore(&scq->lock, flags); 1819 printk("nicstar%d: Error pushing TBD.\n", card->index); 1820 return 1; 1821 } 1822 1823 scq->full = 1; 1824 spin_unlock_irqrestore(&scq->lock, flags); 1825 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT); 1826 spin_lock_irqsave(&scq->lock, flags); 1827 1828 if (scq->full) { 1829 spin_unlock_irqrestore(&scq->lock, flags); 1830 printk("nicstar%d: Timeout pushing TBD.\n", card->index); 1831 return 1; 1832 } 1833 } 1834 *scq->next = *tbd; 1835 index = (int) (scq->next - scq->base); 1836 scq->skb[index] = skb; 1837 XPRINTK("nicstar%d: sending skb at 0x%x (pos %d).\n", 1838 card->index, (u32) skb, index); 1839 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n", 1840 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2), 1841 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4), 1842 (u32) scq->next); 1843 if (scq->next == scq->last) 1844 scq->next = scq->base; 1845 else 1846 scq->next++; 1847 1848 vc->tbd_count++; 1849 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 1850 { 1851 scq->tbd_count++; 1852 scq_is_vbr = 1; 1853 } 1854 else 1855 scq_is_vbr = 0; 1856 1857 if (vc->tbd_count >= MAX_TBD_PER_VC || scq->tbd_count >= MAX_TBD_PER_SCQ) 1858 { 1859 int has_run = 0; 1860 1861 while (scq->tail == scq->next) 1862 { 1863 if (in_interrupt()) { 1864 data = (u32) virt_to_bus(scq->next); 1865 ns_write_sram(card, scq->scd, &data, 1); 1866 spin_unlock_irqrestore(&scq->lock, flags); 1867 printk("nicstar%d: Error pushing TSR.\n", card->index); 1868 return 0; 1869 } 1870 1871 scq->full = 1; 1872 if (has_run++) break; 1873 spin_unlock_irqrestore(&scq->lock, flags); 1874 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT); 1875 spin_lock_irqsave(&scq->lock, flags); 1876 } 1877 1878 if (!scq->full) 1879 { 1880 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1881 if (scq_is_vbr) 1882 scdi = NS_TSR_SCDISVBR; 1883 else 1884 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1885 scqi = scq->next - scq->base; 1886 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1887 tsr.word_3 = 0x00000000; 1888 tsr.word_4 = 0x00000000; 1889 1890 *scq->next = tsr; 1891 index = (int) scqi; 1892 scq->skb[index] = NULL; 1893 XPRINTK("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n", 1894 card->index, le32_to_cpu(tsr.word_1), le32_to_cpu(tsr.word_2), 1895 le32_to_cpu(tsr.word_3), le32_to_cpu(tsr.word_4), 1896 (u32) scq->next); 1897 if (scq->next == scq->last) 1898 scq->next = scq->base; 1899 else 1900 scq->next++; 1901 vc->tbd_count = 0; 1902 scq->tbd_count = 0; 1903 } 1904 else 1905 PRINTK("nicstar%d: Timeout pushing TSR.\n", card->index); 1906 } 1907 data = (u32) virt_to_bus(scq->next); 1908 ns_write_sram(card, scq->scd, &data, 1); 1909 1910 spin_unlock_irqrestore(&scq->lock, flags); 1911 1912 return 0; 1913 } 1914 1915 1916 1917 static void process_tsq(ns_dev *card) 1918 { 1919 u32 scdi; 1920 scq_info *scq; 1921 ns_tsi *previous = NULL, *one_ahead, *two_ahead; 1922 int serviced_entries; /* flag indicating at least on entry was serviced */ 1923 1924 serviced_entries = 0; 1925 1926 if (card->tsq.next == card->tsq.last) 1927 one_ahead = card->tsq.base; 1928 else 1929 one_ahead = card->tsq.next + 1; 1930 1931 if (one_ahead == card->tsq.last) 1932 two_ahead = card->tsq.base; 1933 else 1934 two_ahead = one_ahead + 1; 1935 1936 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) || 1937 !ns_tsi_isempty(two_ahead)) 1938 /* At most two empty, as stated in the 77201 errata */ 1939 { 1940 serviced_entries = 1; 1941 1942 /* Skip the one or two possible empty entries */ 1943 while (ns_tsi_isempty(card->tsq.next)) { 1944 if (card->tsq.next == card->tsq.last) 1945 card->tsq.next = card->tsq.base; 1946 else 1947 card->tsq.next++; 1948 } 1949 1950 if (!ns_tsi_tmrof(card->tsq.next)) 1951 { 1952 scdi = ns_tsi_getscdindex(card->tsq.next); 1953 if (scdi == NS_TSI_SCDISVBR) 1954 scq = card->scq0; 1955 else 1956 { 1957 if (card->scd2vc[scdi] == NULL) 1958 { 1959 printk("nicstar%d: could not find VC from SCD index.\n", 1960 card->index); 1961 ns_tsi_init(card->tsq.next); 1962 return; 1963 } 1964 scq = card->scd2vc[scdi]->scq; 1965 } 1966 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next)); 1967 scq->full = 0; 1968 wake_up_interruptible(&(scq->scqfull_waitq)); 1969 } 1970 1971 ns_tsi_init(card->tsq.next); 1972 previous = card->tsq.next; 1973 if (card->tsq.next == card->tsq.last) 1974 card->tsq.next = card->tsq.base; 1975 else 1976 card->tsq.next++; 1977 1978 if (card->tsq.next == card->tsq.last) 1979 one_ahead = card->tsq.base; 1980 else 1981 one_ahead = card->tsq.next + 1; 1982 1983 if (one_ahead == card->tsq.last) 1984 two_ahead = card->tsq.base; 1985 else 1986 two_ahead = one_ahead + 1; 1987 } 1988 1989 if (serviced_entries) { 1990 writel((((u32) previous) - ((u32) card->tsq.base)), 1991 card->membase + TSQH); 1992 } 1993 } 1994 1995 1996 1997 static void drain_scq(ns_dev *card, scq_info *scq, int pos) 1998 { 1999 struct atm_vcc *vcc; 2000 struct sk_buff *skb; 2001 int i; 2002 unsigned long flags; 2003 2004 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%x, pos %d.\n", 2005 card->index, (u32) scq, pos); 2006 if (pos >= scq->num_entries) 2007 { 2008 printk("nicstar%d: Bad index on drain_scq().\n", card->index); 2009 return; 2010 } 2011 2012 spin_lock_irqsave(&scq->lock, flags); 2013 i = (int) (scq->tail - scq->base); 2014 if (++i == scq->num_entries) 2015 i = 0; 2016 while (i != pos) 2017 { 2018 skb = scq->skb[i]; 2019 XPRINTK("nicstar%d: freeing skb at 0x%x (index %d).\n", 2020 card->index, (u32) skb, i); 2021 if (skb != NULL) 2022 { 2023 vcc = ATM_SKB(skb)->vcc; 2024 if (vcc && vcc->pop != NULL) { 2025 vcc->pop(vcc, skb); 2026 } else { 2027 dev_kfree_skb_irq(skb); 2028 } 2029 scq->skb[i] = NULL; 2030 } 2031 if (++i == scq->num_entries) 2032 i = 0; 2033 } 2034 scq->tail = scq->base + pos; 2035 spin_unlock_irqrestore(&scq->lock, flags); 2036 } 2037 2038 2039 2040 static void process_rsq(ns_dev *card) 2041 { 2042 ns_rsqe *previous; 2043 2044 if (!ns_rsqe_valid(card->rsq.next)) 2045 return; 2046 do { 2047 dequeue_rx(card, card->rsq.next); 2048 ns_rsqe_init(card->rsq.next); 2049 previous = card->rsq.next; 2050 if (card->rsq.next == card->rsq.last) 2051 card->rsq.next = card->rsq.base; 2052 else 2053 card->rsq.next++; 2054 } while (ns_rsqe_valid(card->rsq.next)); 2055 writel((((u32) previous) - ((u32) card->rsq.base)), 2056 card->membase + RSQH); 2057 } 2058 2059 2060 2061 static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe) 2062 { 2063 u32 vpi, vci; 2064 vc_map *vc; 2065 struct sk_buff *iovb; 2066 struct iovec *iov; 2067 struct atm_vcc *vcc; 2068 struct sk_buff *skb; 2069 unsigned short aal5_len; 2070 int len; 2071 u32 stat; 2072 2073 stat = readl(card->membase + STAT); 2074 card->sbfqc = ns_stat_sfbqc_get(stat); 2075 card->lbfqc = ns_stat_lfbqc_get(stat); 2076 2077 skb = (struct sk_buff *) le32_to_cpu(rsqe->buffer_handle); 2078 vpi = ns_rsqe_vpi(rsqe); 2079 vci = ns_rsqe_vci(rsqe); 2080 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) 2081 { 2082 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n", 2083 card->index, vpi, vci); 2084 recycle_rx_buf(card, skb); 2085 return; 2086 } 2087 2088 vc = &(card->vcmap[vpi << card->vcibits | vci]); 2089 if (!vc->rx) 2090 { 2091 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n", 2092 card->index, vpi, vci); 2093 recycle_rx_buf(card, skb); 2094 return; 2095 } 2096 2097 vcc = vc->rx_vcc; 2098 2099 if (vcc->qos.aal == ATM_AAL0) 2100 { 2101 struct sk_buff *sb; 2102 unsigned char *cell; 2103 int i; 2104 2105 cell = skb->data; 2106 for (i = ns_rsqe_cellcount(rsqe); i; i--) 2107 { 2108 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) 2109 { 2110 printk("nicstar%d: Can't allocate buffers for aal0.\n", 2111 card->index); 2112 atomic_add(i,&vcc->stats->rx_drop); 2113 break; 2114 } 2115 if (!atm_charge(vcc, sb->truesize)) 2116 { 2117 RXPRINTK("nicstar%d: atm_charge() dropped aal0 packets.\n", 2118 card->index); 2119 atomic_add(i-1,&vcc->stats->rx_drop); /* already increased by 1 */ 2120 dev_kfree_skb_any(sb); 2121 break; 2122 } 2123 /* Rebuild the header */ 2124 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 | 2125 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000); 2126 if (i == 1 && ns_rsqe_eopdu(rsqe)) 2127 *((u32 *) sb->data) |= 0x00000002; 2128 skb_put(sb, NS_AAL0_HEADER); 2129 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD); 2130 skb_put(sb, ATM_CELL_PAYLOAD); 2131 ATM_SKB(sb)->vcc = vcc; 2132 __net_timestamp(sb); 2133 vcc->push(vcc, sb); 2134 atomic_inc(&vcc->stats->rx); 2135 cell += ATM_CELL_PAYLOAD; 2136 } 2137 2138 recycle_rx_buf(card, skb); 2139 return; 2140 } 2141 2142 /* To reach this point, the AAL layer can only be AAL5 */ 2143 2144 if ((iovb = vc->rx_iov) == NULL) 2145 { 2146 iovb = skb_dequeue(&(card->iovpool.queue)); 2147 if (iovb == NULL) /* No buffers in the queue */ 2148 { 2149 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC); 2150 if (iovb == NULL) 2151 { 2152 printk("nicstar%d: Out of iovec buffers.\n", card->index); 2153 atomic_inc(&vcc->stats->rx_drop); 2154 recycle_rx_buf(card, skb); 2155 return; 2156 } 2157 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2158 } 2159 else 2160 if (--card->iovpool.count < card->iovnr.min) 2161 { 2162 struct sk_buff *new_iovb; 2163 if ((new_iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) 2164 { 2165 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2166 skb_queue_tail(&card->iovpool.queue, new_iovb); 2167 card->iovpool.count++; 2168 } 2169 } 2170 vc->rx_iov = iovb; 2171 NS_SKB(iovb)->iovcnt = 0; 2172 iovb->len = 0; 2173 iovb->data = iovb->head; 2174 skb_reset_tail_pointer(iovb); 2175 NS_SKB(iovb)->vcc = vcc; 2176 /* IMPORTANT: a pointer to the sk_buff containing the small or large 2177 buffer is stored as iovec base, NOT a pointer to the 2178 small or large buffer itself. */ 2179 } 2180 else if (NS_SKB(iovb)->iovcnt >= NS_MAX_IOVECS) 2181 { 2182 printk("nicstar%d: received too big AAL5 SDU.\n", card->index); 2183 atomic_inc(&vcc->stats->rx_err); 2184 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, NS_MAX_IOVECS); 2185 NS_SKB(iovb)->iovcnt = 0; 2186 iovb->len = 0; 2187 iovb->data = iovb->head; 2188 skb_reset_tail_pointer(iovb); 2189 NS_SKB(iovb)->vcc = vcc; 2190 } 2191 iov = &((struct iovec *) iovb->data)[NS_SKB(iovb)->iovcnt++]; 2192 iov->iov_base = (void *) skb; 2193 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48; 2194 iovb->len += iov->iov_len; 2195 2196 if (NS_SKB(iovb)->iovcnt == 1) 2197 { 2198 if (NS_SKB_CB(skb)->buf_type != BUF_SM) 2199 { 2200 printk("nicstar%d: Expected a small buffer, and this is not one.\n", 2201 card->index); 2202 which_list(card, skb); 2203 atomic_inc(&vcc->stats->rx_err); 2204 recycle_rx_buf(card, skb); 2205 vc->rx_iov = NULL; 2206 recycle_iov_buf(card, iovb); 2207 return; 2208 } 2209 } 2210 else /* NS_SKB(iovb)->iovcnt >= 2 */ 2211 { 2212 if (NS_SKB_CB(skb)->buf_type != BUF_LG) 2213 { 2214 printk("nicstar%d: Expected a large buffer, and this is not one.\n", 2215 card->index); 2216 which_list(card, skb); 2217 atomic_inc(&vcc->stats->rx_err); 2218 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2219 NS_SKB(iovb)->iovcnt); 2220 vc->rx_iov = NULL; 2221 recycle_iov_buf(card, iovb); 2222 return; 2223 } 2224 } 2225 2226 if (ns_rsqe_eopdu(rsqe)) 2227 { 2228 /* This works correctly regardless of the endianness of the host */ 2229 unsigned char *L1L2 = (unsigned char *)((u32)skb->data + 2230 iov->iov_len - 6); 2231 aal5_len = L1L2[0] << 8 | L1L2[1]; 2232 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len; 2233 if (ns_rsqe_crcerr(rsqe) || 2234 len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2235 { 2236 printk("nicstar%d: AAL5 CRC error", card->index); 2237 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2238 printk(" - PDU size mismatch.\n"); 2239 else 2240 printk(".\n"); 2241 atomic_inc(&vcc->stats->rx_err); 2242 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2243 NS_SKB(iovb)->iovcnt); 2244 vc->rx_iov = NULL; 2245 recycle_iov_buf(card, iovb); 2246 return; 2247 } 2248 2249 /* By this point we (hopefully) have a complete SDU without errors. */ 2250 2251 if (NS_SKB(iovb)->iovcnt == 1) /* Just a small buffer */ 2252 { 2253 /* skb points to a small buffer */ 2254 if (!atm_charge(vcc, skb->truesize)) 2255 { 2256 push_rxbufs(card, skb); 2257 atomic_inc(&vcc->stats->rx_drop); 2258 } 2259 else 2260 { 2261 skb_put(skb, len); 2262 dequeue_sm_buf(card, skb); 2263 #ifdef NS_USE_DESTRUCTORS 2264 skb->destructor = ns_sb_destructor; 2265 #endif /* NS_USE_DESTRUCTORS */ 2266 ATM_SKB(skb)->vcc = vcc; 2267 __net_timestamp(skb); 2268 vcc->push(vcc, skb); 2269 atomic_inc(&vcc->stats->rx); 2270 } 2271 } 2272 else if (NS_SKB(iovb)->iovcnt == 2) /* One small plus one large buffer */ 2273 { 2274 struct sk_buff *sb; 2275 2276 sb = (struct sk_buff *) (iov - 1)->iov_base; 2277 /* skb points to a large buffer */ 2278 2279 if (len <= NS_SMBUFSIZE) 2280 { 2281 if (!atm_charge(vcc, sb->truesize)) 2282 { 2283 push_rxbufs(card, sb); 2284 atomic_inc(&vcc->stats->rx_drop); 2285 } 2286 else 2287 { 2288 skb_put(sb, len); 2289 dequeue_sm_buf(card, sb); 2290 #ifdef NS_USE_DESTRUCTORS 2291 sb->destructor = ns_sb_destructor; 2292 #endif /* NS_USE_DESTRUCTORS */ 2293 ATM_SKB(sb)->vcc = vcc; 2294 __net_timestamp(sb); 2295 vcc->push(vcc, sb); 2296 atomic_inc(&vcc->stats->rx); 2297 } 2298 2299 push_rxbufs(card, skb); 2300 2301 } 2302 else /* len > NS_SMBUFSIZE, the usual case */ 2303 { 2304 if (!atm_charge(vcc, skb->truesize)) 2305 { 2306 push_rxbufs(card, skb); 2307 atomic_inc(&vcc->stats->rx_drop); 2308 } 2309 else 2310 { 2311 dequeue_lg_buf(card, skb); 2312 #ifdef NS_USE_DESTRUCTORS 2313 skb->destructor = ns_lb_destructor; 2314 #endif /* NS_USE_DESTRUCTORS */ 2315 skb_push(skb, NS_SMBUFSIZE); 2316 skb_copy_from_linear_data(sb, skb->data, NS_SMBUFSIZE); 2317 skb_put(skb, len - NS_SMBUFSIZE); 2318 ATM_SKB(skb)->vcc = vcc; 2319 __net_timestamp(skb); 2320 vcc->push(vcc, skb); 2321 atomic_inc(&vcc->stats->rx); 2322 } 2323 2324 push_rxbufs(card, sb); 2325 2326 } 2327 2328 } 2329 else /* Must push a huge buffer */ 2330 { 2331 struct sk_buff *hb, *sb, *lb; 2332 int remaining, tocopy; 2333 int j; 2334 2335 hb = skb_dequeue(&(card->hbpool.queue)); 2336 if (hb == NULL) /* No buffers in the queue */ 2337 { 2338 2339 hb = dev_alloc_skb(NS_HBUFSIZE); 2340 if (hb == NULL) 2341 { 2342 printk("nicstar%d: Out of huge buffers.\n", card->index); 2343 atomic_inc(&vcc->stats->rx_drop); 2344 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2345 NS_SKB(iovb)->iovcnt); 2346 vc->rx_iov = NULL; 2347 recycle_iov_buf(card, iovb); 2348 return; 2349 } 2350 else if (card->hbpool.count < card->hbnr.min) 2351 { 2352 struct sk_buff *new_hb; 2353 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2354 { 2355 skb_queue_tail(&card->hbpool.queue, new_hb); 2356 card->hbpool.count++; 2357 } 2358 } 2359 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2360 } 2361 else 2362 if (--card->hbpool.count < card->hbnr.min) 2363 { 2364 struct sk_buff *new_hb; 2365 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2366 { 2367 NS_SKB_CB(new_hb)->buf_type = BUF_NONE; 2368 skb_queue_tail(&card->hbpool.queue, new_hb); 2369 card->hbpool.count++; 2370 } 2371 if (card->hbpool.count < card->hbnr.min) 2372 { 2373 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2374 { 2375 NS_SKB_CB(new_hb)->buf_type = BUF_NONE; 2376 skb_queue_tail(&card->hbpool.queue, new_hb); 2377 card->hbpool.count++; 2378 } 2379 } 2380 } 2381 2382 iov = (struct iovec *) iovb->data; 2383 2384 if (!atm_charge(vcc, hb->truesize)) 2385 { 2386 recycle_iovec_rx_bufs(card, iov, NS_SKB(iovb)->iovcnt); 2387 if (card->hbpool.count < card->hbnr.max) 2388 { 2389 skb_queue_tail(&card->hbpool.queue, hb); 2390 card->hbpool.count++; 2391 } 2392 else 2393 dev_kfree_skb_any(hb); 2394 atomic_inc(&vcc->stats->rx_drop); 2395 } 2396 else 2397 { 2398 /* Copy the small buffer to the huge buffer */ 2399 sb = (struct sk_buff *) iov->iov_base; 2400 skb_copy_from_linear_data(sb, hb->data, iov->iov_len); 2401 skb_put(hb, iov->iov_len); 2402 remaining = len - iov->iov_len; 2403 iov++; 2404 /* Free the small buffer */ 2405 push_rxbufs(card, sb); 2406 2407 /* Copy all large buffers to the huge buffer and free them */ 2408 for (j = 1; j < NS_SKB(iovb)->iovcnt; j++) 2409 { 2410 lb = (struct sk_buff *) iov->iov_base; 2411 tocopy = min_t(int, remaining, iov->iov_len); 2412 skb_copy_from_linear_data(lb, skb_tail_pointer(hb), tocopy); 2413 skb_put(hb, tocopy); 2414 iov++; 2415 remaining -= tocopy; 2416 push_rxbufs(card, lb); 2417 } 2418 #ifdef EXTRA_DEBUG 2419 if (remaining != 0 || hb->len != len) 2420 printk("nicstar%d: Huge buffer len mismatch.\n", card->index); 2421 #endif /* EXTRA_DEBUG */ 2422 ATM_SKB(hb)->vcc = vcc; 2423 #ifdef NS_USE_DESTRUCTORS 2424 hb->destructor = ns_hb_destructor; 2425 #endif /* NS_USE_DESTRUCTORS */ 2426 __net_timestamp(hb); 2427 vcc->push(vcc, hb); 2428 atomic_inc(&vcc->stats->rx); 2429 } 2430 } 2431 2432 vc->rx_iov = NULL; 2433 recycle_iov_buf(card, iovb); 2434 } 2435 2436 } 2437 2438 2439 2440 #ifdef NS_USE_DESTRUCTORS 2441 2442 static void ns_sb_destructor(struct sk_buff *sb) 2443 { 2444 ns_dev *card; 2445 u32 stat; 2446 2447 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data; 2448 stat = readl(card->membase + STAT); 2449 card->sbfqc = ns_stat_sfbqc_get(stat); 2450 card->lbfqc = ns_stat_lfbqc_get(stat); 2451 2452 do 2453 { 2454 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2455 if (sb == NULL) 2456 break; 2457 NS_SKB_CB(sb)->buf_type = BUF_SM; 2458 skb_queue_tail(&card->sbpool.queue, sb); 2459 skb_reserve(sb, NS_AAL0_HEADER); 2460 push_rxbufs(card, sb); 2461 } while (card->sbfqc < card->sbnr.min); 2462 } 2463 2464 2465 2466 static void ns_lb_destructor(struct sk_buff *lb) 2467 { 2468 ns_dev *card; 2469 u32 stat; 2470 2471 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data; 2472 stat = readl(card->membase + STAT); 2473 card->sbfqc = ns_stat_sfbqc_get(stat); 2474 card->lbfqc = ns_stat_lfbqc_get(stat); 2475 2476 do 2477 { 2478 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2479 if (lb == NULL) 2480 break; 2481 NS_SKB_CB(lb)->buf_type = BUF_LG; 2482 skb_queue_tail(&card->lbpool.queue, lb); 2483 skb_reserve(lb, NS_SMBUFSIZE); 2484 push_rxbufs(card, lb); 2485 } while (card->lbfqc < card->lbnr.min); 2486 } 2487 2488 2489 2490 static void ns_hb_destructor(struct sk_buff *hb) 2491 { 2492 ns_dev *card; 2493 2494 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data; 2495 2496 while (card->hbpool.count < card->hbnr.init) 2497 { 2498 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2499 if (hb == NULL) 2500 break; 2501 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2502 skb_queue_tail(&card->hbpool.queue, hb); 2503 card->hbpool.count++; 2504 } 2505 } 2506 2507 #endif /* NS_USE_DESTRUCTORS */ 2508 2509 2510 static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb) 2511 { 2512 struct ns_skb_cb *cb = NS_SKB_CB(skb); 2513 2514 if (unlikely(cb->buf_type == BUF_NONE)) { 2515 printk("nicstar%d: What kind of rx buffer is this?\n", card->index); 2516 dev_kfree_skb_any(skb); 2517 } else 2518 push_rxbufs(card, skb); 2519 } 2520 2521 2522 static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count) 2523 { 2524 while (count-- > 0) 2525 recycle_rx_buf(card, (struct sk_buff *) (iov++)->iov_base); 2526 } 2527 2528 2529 static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb) 2530 { 2531 if (card->iovpool.count < card->iovnr.max) 2532 { 2533 skb_queue_tail(&card->iovpool.queue, iovb); 2534 card->iovpool.count++; 2535 } 2536 else 2537 dev_kfree_skb_any(iovb); 2538 } 2539 2540 2541 2542 static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb) 2543 { 2544 skb_unlink(sb, &card->sbpool.queue); 2545 #ifdef NS_USE_DESTRUCTORS 2546 if (card->sbfqc < card->sbnr.min) 2547 #else 2548 if (card->sbfqc < card->sbnr.init) 2549 { 2550 struct sk_buff *new_sb; 2551 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) 2552 { 2553 NS_SKB_CB(new_sb)->buf_type = BUF_SM; 2554 skb_queue_tail(&card->sbpool.queue, new_sb); 2555 skb_reserve(new_sb, NS_AAL0_HEADER); 2556 push_rxbufs(card, new_sb); 2557 } 2558 } 2559 if (card->sbfqc < card->sbnr.init) 2560 #endif /* NS_USE_DESTRUCTORS */ 2561 { 2562 struct sk_buff *new_sb; 2563 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) 2564 { 2565 NS_SKB_CB(new_sb)->buf_type = BUF_SM; 2566 skb_queue_tail(&card->sbpool.queue, new_sb); 2567 skb_reserve(new_sb, NS_AAL0_HEADER); 2568 push_rxbufs(card, new_sb); 2569 } 2570 } 2571 } 2572 2573 2574 2575 static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb) 2576 { 2577 skb_unlink(lb, &card->lbpool.queue); 2578 #ifdef NS_USE_DESTRUCTORS 2579 if (card->lbfqc < card->lbnr.min) 2580 #else 2581 if (card->lbfqc < card->lbnr.init) 2582 { 2583 struct sk_buff *new_lb; 2584 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) 2585 { 2586 NS_SKB_CB(new_lb)->buf_type = BUF_LG; 2587 skb_queue_tail(&card->lbpool.queue, new_lb); 2588 skb_reserve(new_lb, NS_SMBUFSIZE); 2589 push_rxbufs(card, new_lb); 2590 } 2591 } 2592 if (card->lbfqc < card->lbnr.init) 2593 #endif /* NS_USE_DESTRUCTORS */ 2594 { 2595 struct sk_buff *new_lb; 2596 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) 2597 { 2598 NS_SKB_CB(new_lb)->buf_type = BUF_LG; 2599 skb_queue_tail(&card->lbpool.queue, new_lb); 2600 skb_reserve(new_lb, NS_SMBUFSIZE); 2601 push_rxbufs(card, new_lb); 2602 } 2603 } 2604 } 2605 2606 2607 2608 static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page) 2609 { 2610 u32 stat; 2611 ns_dev *card; 2612 int left; 2613 2614 left = (int) *pos; 2615 card = (ns_dev *) dev->dev_data; 2616 stat = readl(card->membase + STAT); 2617 if (!left--) 2618 return sprintf(page, "Pool count min init max \n"); 2619 if (!left--) 2620 return sprintf(page, "Small %5d %5d %5d %5d \n", 2621 ns_stat_sfbqc_get(stat), card->sbnr.min, card->sbnr.init, 2622 card->sbnr.max); 2623 if (!left--) 2624 return sprintf(page, "Large %5d %5d %5d %5d \n", 2625 ns_stat_lfbqc_get(stat), card->lbnr.min, card->lbnr.init, 2626 card->lbnr.max); 2627 if (!left--) 2628 return sprintf(page, "Huge %5d %5d %5d %5d \n", card->hbpool.count, 2629 card->hbnr.min, card->hbnr.init, card->hbnr.max); 2630 if (!left--) 2631 return sprintf(page, "Iovec %5d %5d %5d %5d \n", card->iovpool.count, 2632 card->iovnr.min, card->iovnr.init, card->iovnr.max); 2633 if (!left--) 2634 { 2635 int retval; 2636 retval = sprintf(page, "Interrupt counter: %u \n", card->intcnt); 2637 card->intcnt = 0; 2638 return retval; 2639 } 2640 #if 0 2641 /* Dump 25.6 Mbps PHY registers */ 2642 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it 2643 here just in case it's needed for debugging. */ 2644 if (card->max_pcr == ATM_25_PCR && !left--) 2645 { 2646 u32 phy_regs[4]; 2647 u32 i; 2648 2649 for (i = 0; i < 4; i++) 2650 { 2651 while (CMD_BUSY(card)); 2652 writel(NS_CMD_READ_UTILITY | 0x00000200 | i, card->membase + CMD); 2653 while (CMD_BUSY(card)); 2654 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; 2655 } 2656 2657 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n", 2658 phy_regs[0], phy_regs[1], phy_regs[2], phy_regs[3]); 2659 } 2660 #endif /* 0 - Dump 25.6 Mbps PHY registers */ 2661 #if 0 2662 /* Dump TST */ 2663 if (left-- < NS_TST_NUM_ENTRIES) 2664 { 2665 if (card->tste2vc[left + 1] == NULL) 2666 return sprintf(page, "%5d - VBR/UBR \n", left + 1); 2667 else 2668 return sprintf(page, "%5d - %d %d \n", left + 1, 2669 card->tste2vc[left + 1]->tx_vcc->vpi, 2670 card->tste2vc[left + 1]->tx_vcc->vci); 2671 } 2672 #endif /* 0 */ 2673 return 0; 2674 } 2675 2676 2677 2678 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg) 2679 { 2680 ns_dev *card; 2681 pool_levels pl; 2682 long btype; 2683 unsigned long flags; 2684 2685 card = dev->dev_data; 2686 switch (cmd) 2687 { 2688 case NS_GETPSTAT: 2689 if (get_user(pl.buftype, &((pool_levels __user *) arg)->buftype)) 2690 return -EFAULT; 2691 switch (pl.buftype) 2692 { 2693 case NS_BUFTYPE_SMALL: 2694 pl.count = ns_stat_sfbqc_get(readl(card->membase + STAT)); 2695 pl.level.min = card->sbnr.min; 2696 pl.level.init = card->sbnr.init; 2697 pl.level.max = card->sbnr.max; 2698 break; 2699 2700 case NS_BUFTYPE_LARGE: 2701 pl.count = ns_stat_lfbqc_get(readl(card->membase + STAT)); 2702 pl.level.min = card->lbnr.min; 2703 pl.level.init = card->lbnr.init; 2704 pl.level.max = card->lbnr.max; 2705 break; 2706 2707 case NS_BUFTYPE_HUGE: 2708 pl.count = card->hbpool.count; 2709 pl.level.min = card->hbnr.min; 2710 pl.level.init = card->hbnr.init; 2711 pl.level.max = card->hbnr.max; 2712 break; 2713 2714 case NS_BUFTYPE_IOVEC: 2715 pl.count = card->iovpool.count; 2716 pl.level.min = card->iovnr.min; 2717 pl.level.init = card->iovnr.init; 2718 pl.level.max = card->iovnr.max; 2719 break; 2720 2721 default: 2722 return -ENOIOCTLCMD; 2723 2724 } 2725 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl))) 2726 return (sizeof(pl)); 2727 else 2728 return -EFAULT; 2729 2730 case NS_SETBUFLEV: 2731 if (!capable(CAP_NET_ADMIN)) 2732 return -EPERM; 2733 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl))) 2734 return -EFAULT; 2735 if (pl.level.min >= pl.level.init || pl.level.init >= pl.level.max) 2736 return -EINVAL; 2737 if (pl.level.min == 0) 2738 return -EINVAL; 2739 switch (pl.buftype) 2740 { 2741 case NS_BUFTYPE_SMALL: 2742 if (pl.level.max > TOP_SB) 2743 return -EINVAL; 2744 card->sbnr.min = pl.level.min; 2745 card->sbnr.init = pl.level.init; 2746 card->sbnr.max = pl.level.max; 2747 break; 2748 2749 case NS_BUFTYPE_LARGE: 2750 if (pl.level.max > TOP_LB) 2751 return -EINVAL; 2752 card->lbnr.min = pl.level.min; 2753 card->lbnr.init = pl.level.init; 2754 card->lbnr.max = pl.level.max; 2755 break; 2756 2757 case NS_BUFTYPE_HUGE: 2758 if (pl.level.max > TOP_HB) 2759 return -EINVAL; 2760 card->hbnr.min = pl.level.min; 2761 card->hbnr.init = pl.level.init; 2762 card->hbnr.max = pl.level.max; 2763 break; 2764 2765 case NS_BUFTYPE_IOVEC: 2766 if (pl.level.max > TOP_IOVB) 2767 return -EINVAL; 2768 card->iovnr.min = pl.level.min; 2769 card->iovnr.init = pl.level.init; 2770 card->iovnr.max = pl.level.max; 2771 break; 2772 2773 default: 2774 return -EINVAL; 2775 2776 } 2777 return 0; 2778 2779 case NS_ADJBUFLEV: 2780 if (!capable(CAP_NET_ADMIN)) 2781 return -EPERM; 2782 btype = (long) arg; /* a long is the same size as a pointer or bigger */ 2783 switch (btype) 2784 { 2785 case NS_BUFTYPE_SMALL: 2786 while (card->sbfqc < card->sbnr.init) 2787 { 2788 struct sk_buff *sb; 2789 2790 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2791 if (sb == NULL) 2792 return -ENOMEM; 2793 NS_SKB_CB(sb)->buf_type = BUF_SM; 2794 skb_queue_tail(&card->sbpool.queue, sb); 2795 skb_reserve(sb, NS_AAL0_HEADER); 2796 push_rxbufs(card, sb); 2797 } 2798 break; 2799 2800 case NS_BUFTYPE_LARGE: 2801 while (card->lbfqc < card->lbnr.init) 2802 { 2803 struct sk_buff *lb; 2804 2805 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2806 if (lb == NULL) 2807 return -ENOMEM; 2808 NS_SKB_CB(lb)->buf_type = BUF_LG; 2809 skb_queue_tail(&card->lbpool.queue, lb); 2810 skb_reserve(lb, NS_SMBUFSIZE); 2811 push_rxbufs(card, lb); 2812 } 2813 break; 2814 2815 case NS_BUFTYPE_HUGE: 2816 while (card->hbpool.count > card->hbnr.init) 2817 { 2818 struct sk_buff *hb; 2819 2820 spin_lock_irqsave(&card->int_lock, flags); 2821 hb = skb_dequeue(&card->hbpool.queue); 2822 card->hbpool.count--; 2823 spin_unlock_irqrestore(&card->int_lock, flags); 2824 if (hb == NULL) 2825 printk("nicstar%d: huge buffer count inconsistent.\n", 2826 card->index); 2827 else 2828 dev_kfree_skb_any(hb); 2829 2830 } 2831 while (card->hbpool.count < card->hbnr.init) 2832 { 2833 struct sk_buff *hb; 2834 2835 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2836 if (hb == NULL) 2837 return -ENOMEM; 2838 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2839 spin_lock_irqsave(&card->int_lock, flags); 2840 skb_queue_tail(&card->hbpool.queue, hb); 2841 card->hbpool.count++; 2842 spin_unlock_irqrestore(&card->int_lock, flags); 2843 } 2844 break; 2845 2846 case NS_BUFTYPE_IOVEC: 2847 while (card->iovpool.count > card->iovnr.init) 2848 { 2849 struct sk_buff *iovb; 2850 2851 spin_lock_irqsave(&card->int_lock, flags); 2852 iovb = skb_dequeue(&card->iovpool.queue); 2853 card->iovpool.count--; 2854 spin_unlock_irqrestore(&card->int_lock, flags); 2855 if (iovb == NULL) 2856 printk("nicstar%d: iovec buffer count inconsistent.\n", 2857 card->index); 2858 else 2859 dev_kfree_skb_any(iovb); 2860 2861 } 2862 while (card->iovpool.count < card->iovnr.init) 2863 { 2864 struct sk_buff *iovb; 2865 2866 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 2867 if (iovb == NULL) 2868 return -ENOMEM; 2869 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2870 spin_lock_irqsave(&card->int_lock, flags); 2871 skb_queue_tail(&card->iovpool.queue, iovb); 2872 card->iovpool.count++; 2873 spin_unlock_irqrestore(&card->int_lock, flags); 2874 } 2875 break; 2876 2877 default: 2878 return -EINVAL; 2879 2880 } 2881 return 0; 2882 2883 default: 2884 if (dev->phy && dev->phy->ioctl) { 2885 return dev->phy->ioctl(dev, cmd, arg); 2886 } 2887 else { 2888 printk("nicstar%d: %s == NULL \n", card->index, 2889 dev->phy ? "dev->phy->ioctl" : "dev->phy"); 2890 return -ENOIOCTLCMD; 2891 } 2892 } 2893 } 2894 2895 2896 static void which_list(ns_dev *card, struct sk_buff *skb) 2897 { 2898 printk("skb buf_type: 0x%08x\n", NS_SKB_CB(skb)->buf_type); 2899 } 2900 2901 2902 static void ns_poll(unsigned long arg) 2903 { 2904 int i; 2905 ns_dev *card; 2906 unsigned long flags; 2907 u32 stat_r, stat_w; 2908 2909 PRINTK("nicstar: Entering ns_poll().\n"); 2910 for (i = 0; i < num_cards; i++) 2911 { 2912 card = cards[i]; 2913 if (spin_is_locked(&card->int_lock)) { 2914 /* Probably it isn't worth spinning */ 2915 continue; 2916 } 2917 spin_lock_irqsave(&card->int_lock, flags); 2918 2919 stat_w = 0; 2920 stat_r = readl(card->membase + STAT); 2921 if (stat_r & NS_STAT_TSIF) 2922 stat_w |= NS_STAT_TSIF; 2923 if (stat_r & NS_STAT_EOPDU) 2924 stat_w |= NS_STAT_EOPDU; 2925 2926 process_tsq(card); 2927 process_rsq(card); 2928 2929 writel(stat_w, card->membase + STAT); 2930 spin_unlock_irqrestore(&card->int_lock, flags); 2931 } 2932 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD); 2933 PRINTK("nicstar: Leaving ns_poll().\n"); 2934 } 2935 2936 2937 2938 static int ns_parse_mac(char *mac, unsigned char *esi) 2939 { 2940 int i, j; 2941 short byte1, byte0; 2942 2943 if (mac == NULL || esi == NULL) 2944 return -1; 2945 j = 0; 2946 for (i = 0; i < 6; i++) 2947 { 2948 if ((byte1 = ns_h2i(mac[j++])) < 0) 2949 return -1; 2950 if ((byte0 = ns_h2i(mac[j++])) < 0) 2951 return -1; 2952 esi[i] = (unsigned char) (byte1 * 16 + byte0); 2953 if (i < 5) 2954 { 2955 if (mac[j++] != ':') 2956 return -1; 2957 } 2958 } 2959 return 0; 2960 } 2961 2962 2963 2964 static short ns_h2i(char c) 2965 { 2966 if (c >= '0' && c <= '9') 2967 return (short) (c - '0'); 2968 if (c >= 'A' && c <= 'F') 2969 return (short) (c - 'A' + 10); 2970 if (c >= 'a' && c <= 'f') 2971 return (short) (c - 'a' + 10); 2972 return -1; 2973 } 2974 2975 2976 2977 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 2978 unsigned long addr) 2979 { 2980 ns_dev *card; 2981 unsigned long flags; 2982 2983 card = dev->dev_data; 2984 spin_lock_irqsave(&card->res_lock, flags); 2985 while(CMD_BUSY(card)); 2986 writel((unsigned long) value, card->membase + DR0); 2987 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF), 2988 card->membase + CMD); 2989 spin_unlock_irqrestore(&card->res_lock, flags); 2990 } 2991 2992 2993 2994 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr) 2995 { 2996 ns_dev *card; 2997 unsigned long flags; 2998 unsigned long data; 2999 3000 card = dev->dev_data; 3001 spin_lock_irqsave(&card->res_lock, flags); 3002 while(CMD_BUSY(card)); 3003 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF), 3004 card->membase + CMD); 3005 while(CMD_BUSY(card)); 3006 data = readl(card->membase + DR0) & 0x000000FF; 3007 spin_unlock_irqrestore(&card->res_lock, flags); 3008 return (unsigned char) data; 3009 } 3010 3011 3012 3013 module_init(nicstar_init); 3014 module_exit(nicstar_cleanup); 3015