1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */ 31da177e4SLinus Torvalds 41da177e4SLinus Torvalds /* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.h */ 51da177e4SLinus Torvalds 61da177e4SLinus Torvalds 71da177e4SLinus Torvalds #ifndef DRIVER_ATM_IDT77105_H 81da177e4SLinus Torvalds #define DRIVER_ATM_IDT77105_H 91da177e4SLinus Torvalds 101da177e4SLinus Torvalds #include <linux/atmdev.h> 111da177e4SLinus Torvalds #include <linux/atmioc.h> 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds 141da177e4SLinus Torvalds /* IDT77105 registers */ 151da177e4SLinus Torvalds 161da177e4SLinus Torvalds #define IDT77105_MCR 0x0 /* Master Control Register */ 171da177e4SLinus Torvalds #define IDT77105_ISTAT 0x1 /* Interrupt Status */ 181da177e4SLinus Torvalds #define IDT77105_DIAG 0x2 /* Diagnostic Control */ 191da177e4SLinus Torvalds #define IDT77105_LEDHEC 0x3 /* LED Driver & HEC Status/Control */ 201da177e4SLinus Torvalds #define IDT77105_CTRLO 0x4 /* Low Byte Counter Register */ 211da177e4SLinus Torvalds #define IDT77105_CTRHI 0x5 /* High Byte Counter Register */ 221da177e4SLinus Torvalds #define IDT77105_CTRSEL 0x6 /* Counter Register Read Select */ 231da177e4SLinus Torvalds 241da177e4SLinus Torvalds /* IDT77105 register values */ 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds /* MCR */ 271da177e4SLinus Torvalds #define IDT77105_MCR_UPLO 0x80 /* R/W, User Prog'le Output Latch */ 281da177e4SLinus Torvalds #define IDT77105_MCR_DREC 0x40 /* R/W, Discard Receive Error Cells */ 291da177e4SLinus Torvalds #define IDT77105_MCR_ECEIO 0x20 /* R/W, Enable Cell Error Interrupts 301da177e4SLinus Torvalds * Only */ 311da177e4SLinus Torvalds #define IDT77105_MCR_TDPC 0x10 /* R/W, Transmit Data Parity Check */ 321da177e4SLinus Torvalds #define IDT77105_MCR_DRIC 0x08 /* R/W, Discard Received Idle Cells */ 331da177e4SLinus Torvalds #define IDT77105_MCR_HALTTX 0x04 /* R/W, Halt Tx */ 341da177e4SLinus Torvalds #define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */ 351da177e4SLinus Torvalds #define IDT77105_MCR_EIP 0x01 /* R/W, Enable Interrupt Pin */ 361da177e4SLinus Torvalds 371da177e4SLinus Torvalds /* ISTAT */ 381da177e4SLinus Torvalds #define IDT77105_ISTAT_GOODSIG 0x40 /* R, Good Signal Bit */ 391da177e4SLinus Torvalds #define IDT77105_ISTAT_HECERR 0x20 /* sticky, HEC Error*/ 401da177e4SLinus Torvalds #define IDT77105_ISTAT_SCR 0x10 /* sticky, Short Cell Received */ 411da177e4SLinus Torvalds #define IDT77105_ISTAT_TPE 0x08 /* sticky, Transmit Parity Error */ 421da177e4SLinus Torvalds #define IDT77105_ISTAT_RSCC 0x04 /* sticky, Rx Signal Condition Change */ 431da177e4SLinus Torvalds #define IDT77105_ISTAT_RSE 0x02 /* sticky, Rx Symbol Error */ 441da177e4SLinus Torvalds #define IDT77105_ISTAT_RFO 0x01 /* sticky, Rx FIFO Overrun */ 451da177e4SLinus Torvalds 461da177e4SLinus Torvalds /* DIAG */ 471da177e4SLinus Torvalds #define IDT77105_DIAG_FTD 0x80 /* R/W, Force TxClav deassert */ 481da177e4SLinus Torvalds #define IDT77105_DIAG_ROS 0x40 /* R/W, RxClav operation select */ 491da177e4SLinus Torvalds #define IDT77105_DIAG_MPCS 0x20 /* R/W, Multi-PHY config'n select */ 501da177e4SLinus Torvalds #define IDT77105_DIAG_RFLUSH 0x10 /* R/W, clear receive FIFO */ 511da177e4SLinus Torvalds #define IDT77105_DIAG_ITPE 0x08 /* R/W, Insert Tx payload error */ 521da177e4SLinus Torvalds #define IDT77105_DIAG_ITHE 0x04 /* R/W, Insert Tx HEC error */ 531da177e4SLinus Torvalds #define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */ 541da177e4SLinus Torvalds #define IDT77105_DIAG_LCMASK 0x03 /* R/W, Loopback Control */ 551da177e4SLinus Torvalds 561da177e4SLinus Torvalds #define IDT77105_DIAG_LC_NORMAL 0x00 /* Receive from network */ 571da177e4SLinus Torvalds #define IDT77105_DIAG_LC_PHY_LOOPBACK 0x02 581da177e4SLinus Torvalds #define IDT77105_DIAG_LC_LINE_LOOPBACK 0x03 591da177e4SLinus Torvalds 601da177e4SLinus Torvalds /* LEDHEC */ 611da177e4SLinus Torvalds #define IDT77105_LEDHEC_DRHC 0x40 /* R/W, Disable Rx HEC check */ 621da177e4SLinus Torvalds #define IDT77105_LEDHEC_DTHC 0x20 /* R/W, Disable Tx HEC calculation */ 631da177e4SLinus Torvalds #define IDT77105_LEDHEC_RPWMASK 0x18 /* R/W, RxRef pulse width select */ 641da177e4SLinus Torvalds #define IDT77105_LEDHEC_TFS 0x04 /* R, Tx FIFO Status (1=empty) */ 651da177e4SLinus Torvalds #define IDT77105_LEDHEC_TLS 0x02 /* R, Tx LED Status (1=lit) */ 661da177e4SLinus Torvalds #define IDT77105_LEDHEC_RLS 0x01 /* R, Rx LED Status (1=lit) */ 671da177e4SLinus Torvalds 681da177e4SLinus Torvalds #define IDT77105_LEDHEC_RPW_1 0x00 /* RxRef active for 1 RxClk cycle */ 691da177e4SLinus Torvalds #define IDT77105_LEDHEC_RPW_2 0x08 /* RxRef active for 2 RxClk cycle */ 701da177e4SLinus Torvalds #define IDT77105_LEDHEC_RPW_4 0x10 /* RxRef active for 4 RxClk cycle */ 711da177e4SLinus Torvalds #define IDT77105_LEDHEC_RPW_8 0x18 /* RxRef active for 8 RxClk cycle */ 721da177e4SLinus Torvalds 731da177e4SLinus Torvalds /* CTRSEL */ 741da177e4SLinus Torvalds #define IDT77105_CTRSEL_SEC 0x08 /* W, Symbol Error Counter */ 751da177e4SLinus Torvalds #define IDT77105_CTRSEL_TCC 0x04 /* W, Tx Cell Counter */ 761da177e4SLinus Torvalds #define IDT77105_CTRSEL_RCC 0x02 /* W, Rx Cell Counter */ 771da177e4SLinus Torvalds #define IDT77105_CTRSEL_RHEC 0x01 /* W, Rx HEC Error Counter */ 781da177e4SLinus Torvalds 791da177e4SLinus Torvalds #ifdef __KERNEL__ 80b47eb0ebSChas Williams int idt77105_init(struct atm_dev *dev); 811da177e4SLinus Torvalds #endif 821da177e4SLinus Torvalds 831da177e4SLinus Torvalds /* 841da177e4SLinus Torvalds * Tunable parameters 851da177e4SLinus Torvalds */ 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds /* Time between samples of the hardware cell counters. Should be <= 1 sec */ 881da177e4SLinus Torvalds #define IDT77105_STATS_TIMER_PERIOD (HZ) 891da177e4SLinus Torvalds /* Time between checks to see if the signal has been found again */ 901da177e4SLinus Torvalds #define IDT77105_RESTART_TIMER_PERIOD (5 * HZ) 911da177e4SLinus Torvalds 921da177e4SLinus Torvalds #endif 93