1 /* 2 3 he.h 4 5 ForeRunnerHE ATM Adapter driver for ATM on Linux 6 Copyright (C) 1999-2001 Naval Research Laboratory 7 8 This library is free software; you can redistribute it and/or 9 modify it under the terms of the GNU Lesser General Public 10 License as published by the Free Software Foundation; either 11 version 2.1 of the License, or (at your option) any later version. 12 13 This library is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 Lesser General Public License for more details. 17 18 You should have received a copy of the GNU Lesser General Public 19 License along with this library; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 22 */ 23 24 /* 25 26 he.h 27 28 ForeRunnerHE ATM Adapter driver for ATM on Linux 29 Copyright (C) 1999-2000 Naval Research Laboratory 30 31 Permission to use, copy, modify and distribute this software and its 32 documentation is hereby granted, provided that both the copyright 33 notice and this permission notice appear in all copies of the software, 34 derivative works or modified versions, and any portions thereof, and 35 that both notices appear in supporting documentation. 36 37 NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND 38 DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER 39 RESULTING FROM THE USE OF THIS SOFTWARE. 40 41 */ 42 43 #ifndef _HE_H_ 44 #define _HE_H_ 45 46 #define DEV_LABEL "he" 47 48 #define CONFIG_DEFAULT_VCIBITS 12 49 #define CONFIG_DEFAULT_VPIBITS 0 50 51 #define CONFIG_IRQ_SIZE 128 52 #define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2) 53 54 #define CONFIG_NUMTPDS 256 55 56 #define CONFIG_TPDRQ_SIZE 512 57 #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) 58 59 #define CONFIG_RBRQ_SIZE 512 60 #define CONFIG_RBRQ_THRESH 400 61 #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) 62 63 #define CONFIG_TBRQ_SIZE 512 64 #define CONFIG_TBRQ_THRESH 400 65 #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) 66 67 #define CONFIG_RBPL_SIZE 512 68 #define CONFIG_RBPL_THRESH 64 69 #define CONFIG_RBPL_BUFSIZE 4096 70 #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) 71 72 #define CONFIG_RBPS_SIZE 1024 73 #define CONFIG_RBPS_THRESH 64 74 #define CONFIG_RBPS_BUFSIZE 128 75 #define RBPS_MASK(x) (((unsigned long)(x))&((CONFIG_RBPS_SIZE<<3)-1)) 76 77 /* 5.1.3 initialize connection memory */ 78 79 #define CONFIG_RSRA 0x00000 80 #define CONFIG_RCMLBM 0x08000 81 #define CONFIG_RCMABR 0x0d800 82 #define CONFIG_RSRB 0x0e000 83 84 #define CONFIG_TSRA 0x00000 85 #define CONFIG_TSRB 0x08000 86 #define CONFIG_TSRC 0x0c000 87 #define CONFIG_TSRD 0x0e000 88 #define CONFIG_TMABR 0x0f000 89 #define CONFIG_TPDBA 0x10000 90 91 #define HE_MAXCIDBITS 12 92 93 /* 2.9.3.3 interrupt encodings */ 94 95 struct he_irq { 96 volatile u32 isw; 97 }; 98 99 #define IRQ_ALIGNMENT 0x1000 100 101 #define NEXT_ENTRY(base, tail, mask) \ 102 (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) 103 104 #define ITYPE_INVALID 0xffffffff 105 #define ITYPE_TBRQ_THRESH (0<<3) 106 #define ITYPE_TPD_COMPLETE (1<<3) 107 #define ITYPE_RBPS_THRESH (2<<3) 108 #define ITYPE_RBPL_THRESH (3<<3) 109 #define ITYPE_RBRQ_THRESH (4<<3) 110 #define ITYPE_RBRQ_TIMER (5<<3) 111 #define ITYPE_PHY (6<<3) 112 #define ITYPE_OTHER 0x80 113 #define ITYPE_PARITY 0x81 114 #define ITYPE_ABORT 0x82 115 116 #define ITYPE_GROUP(x) (x & 0x7) 117 #define ITYPE_TYPE(x) (x & 0xf8) 118 119 #define HE_NUM_GROUPS 8 120 121 /* 2.1.4 transmit packet descriptor */ 122 123 struct he_tpd { 124 125 /* read by the adapter */ 126 127 volatile u32 status; 128 volatile u32 reserved; 129 130 #define TPD_MAXIOV 3 131 struct { 132 u32 addr, len; 133 } iovec[TPD_MAXIOV]; 134 135 #define address0 iovec[0].addr 136 #define length0 iovec[0].len 137 138 /* linux-atm extensions */ 139 140 struct sk_buff *skb; 141 struct atm_vcc *vcc; 142 143 #ifdef USE_TPD_POOL 144 struct list_head entry; 145 #else 146 u32 inuse; 147 char padding[32 - sizeof(u32) - (2*sizeof(void*))]; 148 #endif 149 }; 150 151 #define TPD_ALIGNMENT 64 152 #define TPD_LEN_MASK 0xffff 153 154 #define TPD_ADDR_SHIFT 6 155 #define TPD_MASK 0xffffffc0 156 #define TPD_ADDR(x) ((x) & TPD_MASK) 157 #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) 158 159 160 /* table 2.3 transmit buffer return elements */ 161 162 struct he_tbrq { 163 volatile u32 tbre; 164 }; 165 166 #define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE 167 168 #define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0) 169 #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3)) 170 #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1)) 171 172 /* table 2.21 receive buffer return queue element field organization */ 173 174 struct he_rbrq { 175 volatile u32 addr; 176 volatile u32 cidlen; 177 }; 178 179 #define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE 180 181 #define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0) 182 #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5)) 183 #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4)) 184 #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3)) 185 #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2)) 186 #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1)) 187 #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1) 188 #define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff) 189 #define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff) 190 191 /* figure 2.3 transmit packet descriptor ready queue */ 192 193 struct he_tpdrq { 194 volatile u32 tpd; 195 volatile u32 cid; 196 }; 197 198 #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE 199 200 /* table 2.30 host status page detail */ 201 202 #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */ 203 204 struct he_hsp { 205 struct he_hsp_entry { 206 volatile u32 tbrq_tail; 207 volatile u32 reserved1[15]; 208 volatile u32 rbrq_tail; 209 volatile u32 reserved2[15]; 210 } group[HE_NUM_GROUPS]; 211 }; 212 213 /* figure 2.9 receive buffer pools */ 214 215 struct he_rbp { 216 volatile u32 phys; 217 volatile u32 status; 218 }; 219 220 /* NOTE: it is suggested that virt be the virtual address of the host 221 buffer. on a 64-bit machine, this would not work. Instead, we 222 store the real virtual address in another list, and store an index 223 (and buffer status) in the virt member. 224 */ 225 226 #define RBP_INDEX_OFF 6 227 #define RBP_INDEX(x) (((long)(x) >> RBP_INDEX_OFF) & 0xffff) 228 #define RBP_LOANED 0x80000000 229 #define RBP_SMALLBUF 0x40000000 230 231 struct he_virt { 232 void *virt; 233 }; 234 235 #define RBPL_ALIGNMENT CONFIG_RBPL_SIZE 236 #define RBPS_ALIGNMENT CONFIG_RBPS_SIZE 237 238 #ifdef notyet 239 struct he_group { 240 u32 rpbs_size, rpbs_qsize; 241 struct he_rbp rbps_ba; 242 243 u32 rpbl_size, rpbl_qsize; 244 struct he_rpb_entry *rbpl_ba; 245 }; 246 #endif 247 248 #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc) 249 250 struct he_vcc_table 251 { 252 struct atm_vcc *vcc; 253 }; 254 255 struct he_cs_stper 256 { 257 long pcr; 258 int inuse; 259 }; 260 261 #define HE_NUM_CS_STPER 16 262 263 struct he_dev { 264 unsigned int number; 265 unsigned int irq; 266 void __iomem *membase; 267 268 char prod_id[30]; 269 char mac_addr[6]; 270 int media; 271 272 unsigned int vcibits, vpibits; 273 unsigned int cells_per_row; 274 unsigned int bytes_per_row; 275 unsigned int cells_per_lbuf; 276 unsigned int r0_numrows, r0_startrow, r0_numbuffs; 277 unsigned int r1_numrows, r1_startrow, r1_numbuffs; 278 unsigned int tx_numrows, tx_startrow, tx_numbuffs; 279 unsigned int buffer_limit; 280 281 struct he_vcc_table *he_vcc_table; 282 283 #ifdef notyet 284 struct he_group group[HE_NUM_GROUPS]; 285 #endif 286 struct he_cs_stper cs_stper[HE_NUM_CS_STPER]; 287 unsigned total_bw; 288 289 dma_addr_t irq_phys; 290 struct he_irq *irq_base, *irq_head, *irq_tail; 291 volatile unsigned *irq_tailoffset; 292 int irq_peak; 293 294 #ifdef USE_TASKLET 295 struct tasklet_struct tasklet; 296 #endif 297 #ifdef USE_TPD_POOL 298 struct pci_pool *tpd_pool; 299 struct list_head outstanding_tpds; 300 #else 301 struct he_tpd *tpd_head, *tpd_base, *tpd_end; 302 dma_addr_t tpd_base_phys; 303 #endif 304 305 dma_addr_t tpdrq_phys; 306 struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head; 307 308 spinlock_t global_lock; /* 8.1.5 pci transaction ordering 309 error problem */ 310 dma_addr_t rbrq_phys; 311 struct he_rbrq *rbrq_base, *rbrq_head; 312 int rbrq_peak; 313 314 #ifdef USE_RBPL_POOL 315 struct pci_pool *rbpl_pool; 316 #else 317 void *rbpl_pages; 318 dma_addr_t rbpl_pages_phys; 319 #endif 320 dma_addr_t rbpl_phys; 321 struct he_rbp *rbpl_base, *rbpl_tail; 322 struct he_virt *rbpl_virt; 323 int rbpl_peak; 324 325 #ifdef USE_RBPS 326 #ifdef USE_RBPS_POOL 327 struct pci_pool *rbps_pool; 328 #else 329 void *rbps_pages; 330 dma_addr_t rbps_pages_phys; 331 #endif 332 #endif 333 dma_addr_t rbps_phys; 334 struct he_rbp *rbps_base, *rbps_tail; 335 struct he_virt *rbps_virt; 336 int rbps_peak; 337 338 dma_addr_t tbrq_phys; 339 struct he_tbrq *tbrq_base, *tbrq_head; 340 int tbrq_peak; 341 342 dma_addr_t hsp_phys; 343 struct he_hsp *hsp; 344 345 struct pci_dev *pci_dev; 346 struct atm_dev *atm_dev; 347 struct he_dev *next; 348 }; 349 350 struct he_iovec 351 { 352 u32 iov_base; 353 u32 iov_len; 354 }; 355 356 #define HE_MAXIOV 20 357 358 struct he_vcc 359 { 360 struct he_iovec iov_head[HE_MAXIOV]; 361 struct he_iovec *iov_tail; 362 int pdu_len; 363 364 int rc_index; 365 366 wait_queue_head_t rx_waitq; 367 wait_queue_head_t tx_waitq; 368 }; 369 370 #define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data)) 371 372 #define PCI_VENDOR_ID_FORE 0x1127 373 #define PCI_DEVICE_ID_FORE_HE 0x400 374 375 #define GEN_CNTL_0 0x40 376 #define INT_PROC_ENBL (1<<25) 377 #define SLAVE_ENDIAN_MODE (1<<16) 378 #define MRL_ENB (1<<5) 379 #define MRM_ENB (1<<4) 380 #define INIT_ENB (1<<2) 381 #define IGNORE_TIMEOUT (1<<1) 382 #define ENBL_64 (1<<0) 383 384 #define MIN_PCI_LATENCY 32 /* errata 8.1.3 */ 385 386 #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data) 387 388 #define he_is622(dev) ((dev)->media & 0x1) 389 #define he_isMM(dev) ((dev)->media & 0x20) 390 391 #define HE_REGMAP_SIZE 0x100000 392 393 #define RESET_CNTL 0x80000 394 #define BOARD_RST_STATUS (1<<6) 395 396 #define HOST_CNTL 0x80004 397 #define PCI_BUS_SIZE64 (1<<27) 398 #define DESC_RD_STATIC_64 (1<<26) 399 #define DATA_RD_STATIC_64 (1<<25) 400 #define DATA_WR_STATIC_64 (1<<24) 401 #define ID_CS (1<<12) 402 #define ID_WREN (1<<11) 403 #define ID_DOUT (1<<10) 404 #define ID_DOFFSET 10 405 #define ID_DIN (1<<9) 406 #define ID_CLOCK (1<<8) 407 #define QUICK_RD_RETRY (1<<7) 408 #define QUICK_WR_RETRY (1<<6) 409 #define OUTFF_ENB (1<<5) 410 #define CMDFF_ENB (1<<4) 411 #define PERR_INT_ENB (1<<2) 412 #define IGNORE_INTR (1<<0) 413 414 #define LB_SWAP 0x80008 415 #define SWAP_RNUM_MAX(x) (x<<27) 416 #define DATA_WR_SWAP (1<<20) 417 #define DESC_RD_SWAP (1<<19) 418 #define DATA_RD_SWAP (1<<18) 419 #define INTR_SWAP (1<<17) 420 #define DESC_WR_SWAP (1<<16) 421 #define SDRAM_INIT (1<<15) 422 #define BIG_ENDIAN_HOST (1<<14) 423 #define XFER_SIZE (1<<7) 424 425 #define LB_MEM_ADDR 0x8000c 426 #define LB_MEM_DATA 0x80010 427 428 #define LB_MEM_ACCESS 0x80014 429 #define LB_MEM_HNDSHK (1<<30) 430 #define LM_MEM_WRITE (0x7) 431 #define LM_MEM_READ (0x3) 432 433 #define SDRAM_CTL 0x80018 434 #define LB_64_ENB (1<<3) 435 #define LB_TWR (1<<2) 436 #define LB_TRP (1<<1) 437 #define LB_TRAS (1<<0) 438 439 #define INT_FIFO 0x8001c 440 #define INT_MASK_D (1<<15) 441 #define INT_MASK_C (1<<14) 442 #define INT_MASK_B (1<<13) 443 #define INT_MASK_A (1<<12) 444 #define INT_CLEAR_D (1<<11) 445 #define INT_CLEAR_C (1<<10) 446 #define INT_CLEAR_B (1<<9) 447 #define INT_CLEAR_A (1<<8) 448 449 #define ABORT_ADDR 0x80020 450 451 #define IRQ0_BASE 0x80080 452 #define IRQ_BASE(x) (x<<12) 453 #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */ 454 #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK) 455 #define IRQ0_HEAD 0x80084 456 #define IRQ_SIZE(x) (x<<22) 457 #define IRQ_THRESH(x) (x<<12) 458 #define IRQ_HEAD(x) (x<<2) 459 /* #define IRQ_PENDING (1) conflict with linux/irq.h */ 460 #define IRQ0_CNTL 0x80088 461 #define IRQ_ADDRSEL(x) (x<<2) 462 #define IRQ_INT_A (0<<2) 463 #define IRQ_INT_B (1<<2) 464 #define IRQ_INT_C (2<<2) 465 #define IRQ_INT_D (3<<2) 466 #define IRQ_TYPE_ADDR 0x1 467 #define IRQ_TYPE_LINE 0x0 468 #define IRQ0_DATA 0x8008c 469 470 #define IRQ1_BASE 0x80090 471 #define IRQ1_HEAD 0x80094 472 #define IRQ1_CNTL 0x80098 473 #define IRQ1_DATA 0x8009c 474 475 #define IRQ2_BASE 0x800a0 476 #define IRQ2_HEAD 0x800a4 477 #define IRQ2_CNTL 0x800a8 478 #define IRQ2_DATA 0x800ac 479 480 #define IRQ3_BASE 0x800b0 481 #define IRQ3_HEAD 0x800b4 482 #define IRQ3_CNTL 0x800b8 483 #define IRQ3_DATA 0x800bc 484 485 #define GRP_10_MAP 0x800c0 486 #define GRP_32_MAP 0x800c4 487 #define GRP_54_MAP 0x800c8 488 #define GRP_76_MAP 0x800cc 489 490 #define G0_RBPS_S 0x80400 491 #define G0_RBPS_T 0x80404 492 #define RBP_TAIL(x) ((x)<<3) 493 #define RBP_MASK(x) ((x)|0x1fff) 494 #define G0_RBPS_QI 0x80408 495 #define RBP_QSIZE(x) ((x)<<14) 496 #define RBP_INT_ENB (1<<13) 497 #define RBP_THRESH(x) (x) 498 #define G0_RBPS_BS 0x8040c 499 #define G0_RBPL_S 0x80410 500 #define G0_RBPL_T 0x80414 501 #define G0_RBPL_QI 0x80418 502 #define G0_RBPL_BS 0x8041c 503 504 #define G1_RBPS_S 0x80420 505 #define G1_RBPS_T 0x80424 506 #define G1_RBPS_QI 0x80428 507 #define G1_RBPS_BS 0x8042c 508 #define G1_RBPL_S 0x80430 509 #define G1_RBPL_T 0x80434 510 #define G1_RBPL_QI 0x80438 511 #define G1_RBPL_BS 0x8043c 512 513 #define G2_RBPS_S 0x80440 514 #define G2_RBPS_T 0x80444 515 #define G2_RBPS_QI 0x80448 516 #define G2_RBPS_BS 0x8044c 517 #define G2_RBPL_S 0x80450 518 #define G2_RBPL_T 0x80454 519 #define G2_RBPL_QI 0x80458 520 #define G2_RBPL_BS 0x8045c 521 522 #define G3_RBPS_S 0x80460 523 #define G3_RBPS_T 0x80464 524 #define G3_RBPS_QI 0x80468 525 #define G3_RBPS_BS 0x8046c 526 #define G3_RBPL_S 0x80470 527 #define G3_RBPL_T 0x80474 528 #define G3_RBPL_QI 0x80478 529 #define G3_RBPL_BS 0x8047c 530 531 #define G4_RBPS_S 0x80480 532 #define G4_RBPS_T 0x80484 533 #define G4_RBPS_QI 0x80488 534 #define G4_RBPS_BS 0x8048c 535 #define G4_RBPL_S 0x80490 536 #define G4_RBPL_T 0x80494 537 #define G4_RBPL_QI 0x80498 538 #define G4_RBPL_BS 0x8049c 539 540 #define G5_RBPS_S 0x804a0 541 #define G5_RBPS_T 0x804a4 542 #define G5_RBPS_QI 0x804a8 543 #define G5_RBPS_BS 0x804ac 544 #define G5_RBPL_S 0x804b0 545 #define G5_RBPL_T 0x804b4 546 #define G5_RBPL_QI 0x804b8 547 #define G5_RBPL_BS 0x804bc 548 549 #define G6_RBPS_S 0x804c0 550 #define G6_RBPS_T 0x804c4 551 #define G6_RBPS_QI 0x804c8 552 #define G6_RBPS_BS 0x804cc 553 #define G6_RBPL_S 0x804d0 554 #define G6_RBPL_T 0x804d4 555 #define G6_RBPL_QI 0x804d8 556 #define G6_RBPL_BS 0x804dc 557 558 #define G7_RBPS_S 0x804e0 559 #define G7_RBPS_T 0x804e4 560 #define G7_RBPS_QI 0x804e8 561 #define G7_RBPS_BS 0x804ec 562 563 #define G7_RBPL_S 0x804f0 564 #define G7_RBPL_T 0x804f4 565 #define G7_RBPL_QI 0x804f8 566 #define G7_RBPL_BS 0x804fc 567 568 #define G0_RBRQ_ST 0x80500 569 #define G0_RBRQ_H 0x80504 570 #define G0_RBRQ_Q 0x80508 571 #define RBRQ_THRESH(x) ((x)<<13) 572 #define RBRQ_SIZE(x) (x) 573 #define G0_RBRQ_I 0x8050c 574 #define RBRQ_TIME(x) ((x)<<8) 575 #define RBRQ_COUNT(x) (x) 576 577 /* fill in 1 ... 7 later */ 578 579 #define G0_TBRQ_B_T 0x80600 580 #define G0_TBRQ_H 0x80604 581 #define G0_TBRQ_S 0x80608 582 #define G0_TBRQ_THRESH 0x8060c 583 #define TBRQ_THRESH(x) (x) 584 585 /* fill in 1 ... 7 later */ 586 587 #define RH_CONFIG 0x805c0 588 #define PHY_INT_ENB (1<<10) 589 #define OAM_GID(x) (x<<7) 590 #define PTMR_PRE(x) (x) 591 592 #define G0_INMQ_S 0x80580 593 #define G0_INMQ_L 0x80584 594 #define G1_INMQ_S 0x80588 595 #define G1_INMQ_L 0x8058c 596 #define G2_INMQ_S 0x80590 597 #define G2_INMQ_L 0x80594 598 #define G3_INMQ_S 0x80598 599 #define G3_INMQ_L 0x8059c 600 #define G4_INMQ_S 0x805a0 601 #define G4_INMQ_L 0x805a4 602 #define G5_INMQ_S 0x805a8 603 #define G5_INMQ_L 0x805ac 604 #define G6_INMQ_S 0x805b0 605 #define G6_INMQ_L 0x805b4 606 #define G7_INMQ_S 0x805b8 607 #define G7_INMQ_L 0x805bc 608 609 #define TPDRQ_B_H 0x80680 610 #define TPDRQ_T 0x80684 611 #define TPDRQ_S 0x80688 612 613 #define UBUFF_BA 0x8068c 614 615 #define RLBF0_H 0x806c0 616 #define RLBF0_T 0x806c4 617 #define RLBF1_H 0x806c8 618 #define RLBF1_T 0x806cc 619 #define RLBC_H 0x806d0 620 #define RLBC_T 0x806d4 621 #define RLBC_H2 0x806d8 622 #define TLBF_H 0x806e0 623 #define TLBF_T 0x806e4 624 #define RLBF0_C 0x806e8 625 #define RLBF1_C 0x806ec 626 #define RXTHRSH 0x806f0 627 #define LITHRSH 0x806f4 628 629 #define LBARB 0x80700 630 #define SLICE_X(x) (x<<28) 631 #define ARB_RNUM_MAX(x) (x<<23) 632 #define TH_PRTY(x) (x<<21) 633 #define RH_PRTY(x) (x<<19) 634 #define TL_PRTY(x) (x<<17) 635 #define RL_PRTY(x) (x<<15) 636 #define BUS_MULTI(x) (x<<8) 637 #define NET_PREF(x) (x) 638 639 #define SDRAMCON 0x80704 640 #define BANK_ON (1<<14) 641 #define WIDE_DATA (1<<13) 642 #define TWR_WAIT (1<<12) 643 #define TRP_WAIT (1<<11) 644 #define TRAS_WAIT (1<<10) 645 #define REF_RATE(x) (x) 646 647 #define LBSTAT 0x80708 648 649 #define RCC_STAT 0x8070c 650 #define RCC_BUSY (1) 651 652 #define TCMCONFIG 0x80740 653 #define TM_DESL2 (1<<10) 654 #define TM_BANK_WAIT(x) (x<<6) 655 #define TM_ADD_BANK4(x) (x<<4) 656 #define TM_PAR_CHECK(x) (x<<3) 657 #define TM_RW_WAIT(x) (x<<2) 658 #define TM_SRAM_TYPE(x) (x) 659 660 #define TSRB_BA 0x80744 661 #define TSRC_BA 0x80748 662 #define TMABR_BA 0x8074c 663 #define TPD_BA 0x80750 664 #define TSRD_BA 0x80758 665 666 #define TX_CONFIG 0x80760 667 #define DRF_THRESH(x) (x<<22) 668 #define TX_UT_MODE(x) (x<<21) 669 #define TX_VCI_MASK(x) (x<<17) 670 #define LBFREE_CNT(x) (x) 671 672 #define TXAAL5_PROTO 0x80764 673 #define CPCS_UU(x) (x<<8) 674 #define CPI(x) (x) 675 676 #define RCMCONFIG 0x80780 677 #define RM_DESL2(x) (x<<10) 678 #define RM_BANK_WAIT(x) (x<<6) 679 #define RM_ADD_BANK(x) (x<<4) 680 #define RM_PAR_CHECK(x) (x<<3) 681 #define RM_RW_WAIT(x) (x<<2) 682 #define RM_SRAM_TYPE(x) (x) 683 684 #define RCMRSRB_BA 0x80784 685 #define RCMLBM_BA 0x80788 686 #define RCMABR_BA 0x8078c 687 688 #define RC_CONFIG 0x807c0 689 #define UT_RD_DELAY(x) (x<<11) 690 #define WRAP_MODE(x) (x<<10) 691 #define RC_UT_MODE(x) (x<<9) 692 #define RX_ENABLE (1<<8) 693 #define RX_VALVP(x) (x<<4) 694 #define RX_VALVC(x) (x) 695 696 #define MCC 0x807c4 697 #define OEC 0x807c8 698 #define DCC 0x807cc 699 #define CEC 0x807d0 700 701 #define HSP_BA 0x807f0 702 703 #define LB_CONFIG 0x807f4 704 #define LB_SIZE(x) (x) 705 706 #define CON_DAT 0x807f8 707 #define CON_CTL 0x807fc 708 #define CON_CTL_MBOX (2<<30) 709 #define CON_CTL_TCM (1<<30) 710 #define CON_CTL_RCM (0<<30) 711 #define CON_CTL_WRITE (1<<29) 712 #define CON_CTL_READ (0<<29) 713 #define CON_CTL_BUSY (1<<28) 714 #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */ 715 #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */ 716 #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */ 717 #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */ 718 #define CON_CTL_ADDR(x) (x) 719 720 #define FRAMER 0x80800 /* to 0x80bfc */ 721 722 /* 3.3 network controller (internal) mailbox registers */ 723 724 #define CS_STPER0 0x0 725 /* ... */ 726 #define CS_STPER31 0x01f 727 728 #define CS_STTIM0 0x020 729 /* ... */ 730 #define CS_STTIM31 0x03f 731 732 #define CS_TGRLD0 0x040 733 /* ... */ 734 #define CS_TGRLD15 0x04f 735 736 #define CS_ERTHR0 0x050 737 #define CS_ERTHR1 0x051 738 #define CS_ERTHR2 0x052 739 #define CS_ERTHR3 0x053 740 #define CS_ERTHR4 0x054 741 #define CS_ERCTL0 0x055 742 #define TX_ENABLE (1<<28) 743 #define ER_ENABLE (1<<27) 744 #define CS_ERCTL1 0x056 745 #define CS_ERCTL2 0x057 746 #define CS_ERSTAT0 0x058 747 #define CS_ERSTAT1 0x059 748 749 #define CS_RTCCT 0x060 750 #define CS_RTFWC 0x061 751 #define CS_RTFWR 0x062 752 #define CS_RTFTC 0x063 753 #define CS_RTATR 0x064 754 755 #define CS_TFBSET 0x070 756 #define CS_TFBADD 0x071 757 #define CS_TFBSUB 0x072 758 #define CS_WCRMAX 0x073 759 #define CS_WCRMIN 0x074 760 #define CS_WCRINC 0x075 761 #define CS_WCRDEC 0x076 762 #define CS_WCRCEIL 0x077 763 #define CS_BWDCNT 0x078 764 765 #define CS_OTPPER 0x080 766 #define CS_OTWPER 0x081 767 #define CS_OTTLIM 0x082 768 #define CS_OTTCNT 0x083 769 770 #define CS_HGRRT0 0x090 771 /* ... */ 772 #define CS_HGRRT7 0x097 773 774 #define CS_ORPTRS 0x0a0 775 776 #define RXCON_CLOSE 0x100 777 778 779 #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */ 780 #define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */ 781 782 /* 2.5 transmit connection memory registers */ 783 784 #define TSR0_CONN_STATE(x) ((x>>28) & 0x7) 785 #define TSR0_USE_WMIN (1<<23) 786 #define TSR0_GROUP(x) ((x & 0x7)<<18) 787 #define TSR0_ABR (2<<16) 788 #define TSR0_UBR (1<<16) 789 #define TSR0_CBR (0<<16) 790 #define TSR0_PROT (1<<15) 791 #define TSR0_AAL0_SDU (2<<12) 792 #define TSR0_AAL0 (1<<12) 793 #define TSR0_AAL5 (0<<12) 794 #define TSR0_HALT_ER (1<<11) 795 #define TSR0_MARK_CI (1<<10) 796 #define TSR0_MARK_ER (1<<9) 797 #define TSR0_UPDATE_GER (1<<8) 798 #define TSR0_RC_INDEX(x) (x & 0x1F) 799 800 #define TSR1_PCR(x) ((x & 0x7FFF)<<16) 801 #define TSR1_MCR(x) (x & 0x7FFF) 802 803 #define TSR2_ACR(x) ((x & 0x7FFF)<<16) 804 805 #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24) 806 #define TSR3_CRM_CNT(x) (x & 0xFFFF) 807 808 #define TSR4_FLUSH_CONN (1<<31) 809 #define TSR4_SESSION_ENDED (1<<30) 810 #define TSR4_CRC10 (1<<28) 811 #define TSR4_NULL_CRC10 (1<<27) 812 #define TSR4_PROT (1<<26) 813 #define TSR4_AAL0_SDU (2<<23) 814 #define TSR4_AAL0 (1<<23) 815 #define TSR4_AAL5 (0<<23) 816 817 #define TSR9_OPEN_CONN (1<<20) 818 819 #define TSR11_ICR(x) ((x & 0x7FFF)<<16) 820 #define TSR11_TRM(x) ((x & 0x7)<<13) 821 #define TSR11_NRM(x) ((x & 0x7)<<10) 822 #define TSR11_ADTF(x) (x & 0x3FF) 823 824 #define TSR13_RDF(x) ((x & 0xF)<<23) 825 #define TSR13_RIF(x) ((x & 0xF)<<19) 826 #define TSR13_CDF(x) ((x & 0x7)<<16) 827 #define TSR13_CRM(x) (x & 0xFFFF) 828 829 #define TSR14_DELETE (1<<31) 830 #define TSR14_ABR_CLOSE (1<<16) 831 832 /* 2.7.1 per connection receieve state registers */ 833 834 #define RSR0_START_PDU (1<<10) 835 #define RSR0_OPEN_CONN (1<<6) 836 #define RSR0_CLOSE_CONN (0<<6) 837 #define RSR0_PPD_ENABLE (1<<5) 838 #define RSR0_EPD_ENABLE (1<<4) 839 #define RSR0_TCP_CKSUM (1<<3) 840 #define RSR0_AAL5 (0) 841 #define RSR0_AAL0 (1) 842 #define RSR0_AAL0_SDU (2) 843 #define RSR0_RAWCELL (3) 844 #define RSR0_RAWCELL_CRC10 (4) 845 846 #define RSR1_AQI_ENABLE (1<<20) 847 #define RSR1_RBPL_ONLY (1<<19) 848 #define RSR1_GROUP(x) ((x)<<16) 849 850 #define RSR4_AQI_ENABLE (1<<30) 851 #define RSR4_GROUP(x) ((x)<<27) 852 #define RSR4_RBPL_ONLY (1<<26) 853 854 /* 2.1.4 transmit packet descriptor */ 855 856 #define TPD_USERCELL 0x0 857 #define TPD_SEGMENT_OAMF5 0x4 858 #define TPD_END2END_OAMF5 0x5 859 #define TPD_RMCELL 0x6 860 #define TPD_CELLTYPE(x) (x<<3) 861 #define TPD_EOS (1<<2) 862 #define TPD_CLP (1<<1) 863 #define TPD_INT (1<<0) 864 #define TPD_LST (1<<31) 865 866 /* table 4.3 serial eeprom information */ 867 868 #define PROD_ID 0x08 /* char[] */ 869 #define PROD_ID_LEN 30 870 #define HW_REV 0x26 /* char[] */ 871 #define M_SN 0x3a /* integer */ 872 #define MEDIA 0x3e /* integer */ 873 #define HE155MM 0x26 874 #define HE622MM 0x27 875 #define HE155SM 0x46 876 #define HE622SM 0x47 877 #define MAC_ADDR 0x42 /* char[] */ 878 879 #define CS_LOW 0x0 880 #define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */ 881 #define CLK_LOW 0x0 882 #define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */ 883 #define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */ 884 #define EEPROM_DELAY 400 /* microseconds */ 885 886 #endif /* _HE_H_ */ 887