1 /* 2 3 he.h 4 5 ForeRunnerHE ATM Adapter driver for ATM on Linux 6 Copyright (C) 1999-2001 Naval Research Laboratory 7 8 This library is free software; you can redistribute it and/or 9 modify it under the terms of the GNU Lesser General Public 10 License as published by the Free Software Foundation; either 11 version 2.1 of the License, or (at your option) any later version. 12 13 This library is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 Lesser General Public License for more details. 17 18 You should have received a copy of the GNU Lesser General Public 19 License along with this library; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 22 */ 23 24 /* 25 26 he.h 27 28 ForeRunnerHE ATM Adapter driver for ATM on Linux 29 Copyright (C) 1999-2000 Naval Research Laboratory 30 31 Permission to use, copy, modify and distribute this software and its 32 documentation is hereby granted, provided that both the copyright 33 notice and this permission notice appear in all copies of the software, 34 derivative works or modified versions, and any portions thereof, and 35 that both notices appear in supporting documentation. 36 37 NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND 38 DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER 39 RESULTING FROM THE USE OF THIS SOFTWARE. 40 41 */ 42 43 #ifndef _HE_H_ 44 #define _HE_H_ 45 46 #define DEV_LABEL "he" 47 48 #define CONFIG_DEFAULT_VCIBITS 12 49 #define CONFIG_DEFAULT_VPIBITS 0 50 51 #define CONFIG_IRQ_SIZE 128 52 #define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2) 53 54 #define CONFIG_NUMTPDS 256 55 56 #define CONFIG_TPDRQ_SIZE 512 57 #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) 58 59 #define CONFIG_RBRQ_SIZE 512 60 #define CONFIG_RBRQ_THRESH 400 61 #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) 62 63 #define CONFIG_TBRQ_SIZE 512 64 #define CONFIG_TBRQ_THRESH 400 65 #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) 66 67 #define CONFIG_RBPL_SIZE 512 68 #define CONFIG_RBPL_THRESH 64 69 #define CONFIG_RBPL_BUFSIZE 4096 70 #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) 71 72 #define CONFIG_RBPS_SIZE 1024 73 #define CONFIG_RBPS_THRESH 64 74 #define CONFIG_RBPS_BUFSIZE 128 75 #define RBPS_MASK(x) (((unsigned long)(x))&((CONFIG_RBPS_SIZE<<3)-1)) 76 77 /* 5.1.3 initialize connection memory */ 78 79 #define CONFIG_RSRA 0x00000 80 #define CONFIG_RCMLBM 0x08000 81 #define CONFIG_RCMABR 0x0d800 82 #define CONFIG_RSRB 0x0e000 83 84 #define CONFIG_TSRA 0x00000 85 #define CONFIG_TSRB 0x08000 86 #define CONFIG_TSRC 0x0c000 87 #define CONFIG_TSRD 0x0e000 88 #define CONFIG_TMABR 0x0f000 89 #define CONFIG_TPDBA 0x10000 90 91 #define HE_MAXCIDBITS 12 92 93 /* 2.9.3.3 interrupt encodings */ 94 95 struct he_irq { 96 volatile u32 isw; 97 }; 98 99 #define IRQ_ALIGNMENT 0x1000 100 101 #define NEXT_ENTRY(base, tail, mask) \ 102 (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) 103 104 #define ITYPE_INVALID 0xffffffff 105 #define ITYPE_TBRQ_THRESH (0<<3) 106 #define ITYPE_TPD_COMPLETE (1<<3) 107 #define ITYPE_RBPS_THRESH (2<<3) 108 #define ITYPE_RBPL_THRESH (3<<3) 109 #define ITYPE_RBRQ_THRESH (4<<3) 110 #define ITYPE_RBRQ_TIMER (5<<3) 111 #define ITYPE_PHY (6<<3) 112 #define ITYPE_OTHER 0x80 113 #define ITYPE_PARITY 0x81 114 #define ITYPE_ABORT 0x82 115 116 #define ITYPE_GROUP(x) (x & 0x7) 117 #define ITYPE_TYPE(x) (x & 0xf8) 118 119 #define HE_NUM_GROUPS 8 120 121 /* 2.1.4 transmit packet descriptor */ 122 123 struct he_tpd { 124 125 /* read by the adapter */ 126 127 volatile u32 status; 128 volatile u32 reserved; 129 130 #define TPD_MAXIOV 3 131 struct { 132 u32 addr, len; 133 } iovec[TPD_MAXIOV]; 134 135 #define address0 iovec[0].addr 136 #define length0 iovec[0].len 137 138 /* linux-atm extensions */ 139 140 struct sk_buff *skb; 141 struct atm_vcc *vcc; 142 143 #ifdef USE_TPD_POOL 144 struct list_head entry; 145 #else 146 u32 inuse; 147 char padding[32 - sizeof(u32) - (2*sizeof(void*))]; 148 #endif 149 }; 150 151 #define TPD_ALIGNMENT 64 152 #define TPD_LEN_MASK 0xffff 153 154 #define TPD_ADDR_SHIFT 6 155 #define TPD_MASK 0xffffffc0 156 #define TPD_ADDR(x) ((x) & TPD_MASK) 157 #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) 158 159 160 /* table 2.3 transmit buffer return elements */ 161 162 struct he_tbrq { 163 volatile u32 tbre; 164 }; 165 166 #define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE 167 168 #define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0) 169 #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3)) 170 #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1)) 171 172 /* table 2.21 receive buffer return queue element field organization */ 173 174 struct he_rbrq { 175 volatile u32 addr; 176 volatile u32 cidlen; 177 }; 178 179 #define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE 180 181 #define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0) 182 #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5)) 183 #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4)) 184 #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3)) 185 #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2)) 186 #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1)) 187 #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1) 188 #define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff) 189 #define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff) 190 191 /* figure 2.3 transmit packet descriptor ready queue */ 192 193 struct he_tpdrq { 194 volatile u32 tpd; 195 volatile u32 cid; 196 }; 197 198 #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE 199 200 /* table 2.30 host status page detail */ 201 202 #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */ 203 204 struct he_hsp { 205 struct he_hsp_entry { 206 volatile u32 tbrq_tail; 207 volatile u32 reserved1[15]; 208 volatile u32 rbrq_tail; 209 volatile u32 reserved2[15]; 210 } group[HE_NUM_GROUPS]; 211 }; 212 213 /* figure 2.9 receive buffer pools */ 214 215 struct he_rbp { 216 volatile u32 phys; 217 volatile u32 status; 218 }; 219 220 /* NOTE: it is suggested that virt be the virtual address of the host 221 buffer. on a 64-bit machine, this would not work. Instead, we 222 store the real virtual address in another list, and store an index 223 (and buffer status) in the virt member. 224 */ 225 226 #define RBP_INDEX_OFF 6 227 #define RBP_INDEX(x) (((long)(x) >> RBP_INDEX_OFF) & 0xffff) 228 #define RBP_LOANED 0x80000000 229 #define RBP_SMALLBUF 0x40000000 230 231 struct he_virt { 232 void *virt; 233 }; 234 235 #define RBPL_ALIGNMENT CONFIG_RBPL_SIZE 236 #define RBPS_ALIGNMENT CONFIG_RBPS_SIZE 237 238 #ifdef notyet 239 struct he_group { 240 u32 rpbs_size, rpbs_qsize; 241 struct he_rbp rbps_ba; 242 243 u32 rpbl_size, rpbl_qsize; 244 struct he_rpb_entry *rbpl_ba; 245 }; 246 #endif 247 248 #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc) 249 250 struct he_vcc_table 251 { 252 struct atm_vcc *vcc; 253 }; 254 255 struct he_cs_stper 256 { 257 long pcr; 258 int inuse; 259 }; 260 261 #define HE_NUM_CS_STPER 16 262 263 struct he_dev { 264 unsigned int number; 265 unsigned int irq; 266 void __iomem *membase; 267 268 char prod_id[30]; 269 char mac_addr[6]; 270 int media; /* 271 * 0x26 = HE155 MM 272 * 0x27 = HE622 MM 273 * 0x46 = HE155 SM 274 * 0x47 = HE622 SM 275 */ 276 277 278 unsigned int vcibits, vpibits; 279 unsigned int cells_per_row; 280 unsigned int bytes_per_row; 281 unsigned int cells_per_lbuf; 282 unsigned int r0_numrows, r0_startrow, r0_numbuffs; 283 unsigned int r1_numrows, r1_startrow, r1_numbuffs; 284 unsigned int tx_numrows, tx_startrow, tx_numbuffs; 285 unsigned int buffer_limit; 286 287 struct he_vcc_table *he_vcc_table; 288 289 #ifdef notyet 290 struct he_group group[HE_NUM_GROUPS]; 291 #endif 292 struct he_cs_stper cs_stper[HE_NUM_CS_STPER]; 293 unsigned total_bw; 294 295 dma_addr_t irq_phys; 296 struct he_irq *irq_base, *irq_head, *irq_tail; 297 volatile unsigned *irq_tailoffset; 298 int irq_peak; 299 300 #ifdef USE_TASKLET 301 struct tasklet_struct tasklet; 302 #endif 303 #ifdef USE_TPD_POOL 304 struct pci_pool *tpd_pool; 305 struct list_head outstanding_tpds; 306 #else 307 struct he_tpd *tpd_head, *tpd_base, *tpd_end; 308 dma_addr_t tpd_base_phys; 309 #endif 310 311 dma_addr_t tpdrq_phys; 312 struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head; 313 314 spinlock_t global_lock; /* 8.1.5 pci transaction ordering 315 error problem */ 316 dma_addr_t rbrq_phys; 317 struct he_rbrq *rbrq_base, *rbrq_head; 318 int rbrq_peak; 319 320 #ifdef USE_RBPL_POOL 321 struct pci_pool *rbpl_pool; 322 #else 323 void *rbpl_pages; 324 dma_addr_t rbpl_pages_phys; 325 #endif 326 dma_addr_t rbpl_phys; 327 struct he_rbp *rbpl_base, *rbpl_tail; 328 struct he_virt *rbpl_virt; 329 int rbpl_peak; 330 331 #ifdef USE_RBPS 332 #ifdef USE_RBPS_POOL 333 struct pci_pool *rbps_pool; 334 #else 335 void *rbps_pages; 336 dma_addr_t rbps_pages_phys; 337 #endif 338 #endif 339 dma_addr_t rbps_phys; 340 struct he_rbp *rbps_base, *rbps_tail; 341 struct he_virt *rbps_virt; 342 int rbps_peak; 343 344 dma_addr_t tbrq_phys; 345 struct he_tbrq *tbrq_base, *tbrq_head; 346 int tbrq_peak; 347 348 dma_addr_t hsp_phys; 349 struct he_hsp *hsp; 350 351 struct pci_dev *pci_dev; 352 struct atm_dev *atm_dev; 353 struct he_dev *next; 354 }; 355 356 struct he_iovec 357 { 358 u32 iov_base; 359 u32 iov_len; 360 }; 361 362 #define HE_MAXIOV 20 363 364 struct he_vcc 365 { 366 struct he_iovec iov_head[HE_MAXIOV]; 367 struct he_iovec *iov_tail; 368 int pdu_len; 369 370 int rc_index; 371 372 wait_queue_head_t rx_waitq; 373 wait_queue_head_t tx_waitq; 374 }; 375 376 #define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data)) 377 378 #define PCI_VENDOR_ID_FORE 0x1127 379 #define PCI_DEVICE_ID_FORE_HE 0x400 380 381 #define GEN_CNTL_0 0x40 382 #define INT_PROC_ENBL (1<<25) 383 #define SLAVE_ENDIAN_MODE (1<<16) 384 #define MRL_ENB (1<<5) 385 #define MRM_ENB (1<<4) 386 #define INIT_ENB (1<<2) 387 #define IGNORE_TIMEOUT (1<<1) 388 #define ENBL_64 (1<<0) 389 390 #define MIN_PCI_LATENCY 32 /* errata 8.1.3 */ 391 392 #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data) 393 394 #define he_is622(dev) ((dev)->media & 0x1) 395 396 #define HE_REGMAP_SIZE 0x100000 397 398 #define RESET_CNTL 0x80000 399 #define BOARD_RST_STATUS (1<<6) 400 401 #define HOST_CNTL 0x80004 402 #define PCI_BUS_SIZE64 (1<<27) 403 #define DESC_RD_STATIC_64 (1<<26) 404 #define DATA_RD_STATIC_64 (1<<25) 405 #define DATA_WR_STATIC_64 (1<<24) 406 #define ID_CS (1<<12) 407 #define ID_WREN (1<<11) 408 #define ID_DOUT (1<<10) 409 #define ID_DOFFSET 10 410 #define ID_DIN (1<<9) 411 #define ID_CLOCK (1<<8) 412 #define QUICK_RD_RETRY (1<<7) 413 #define QUICK_WR_RETRY (1<<6) 414 #define OUTFF_ENB (1<<5) 415 #define CMDFF_ENB (1<<4) 416 #define PERR_INT_ENB (1<<2) 417 #define IGNORE_INTR (1<<0) 418 419 #define LB_SWAP 0x80008 420 #define SWAP_RNUM_MAX(x) (x<<27) 421 #define DATA_WR_SWAP (1<<20) 422 #define DESC_RD_SWAP (1<<19) 423 #define DATA_RD_SWAP (1<<18) 424 #define INTR_SWAP (1<<17) 425 #define DESC_WR_SWAP (1<<16) 426 #define SDRAM_INIT (1<<15) 427 #define BIG_ENDIAN_HOST (1<<14) 428 #define XFER_SIZE (1<<7) 429 430 #define LB_MEM_ADDR 0x8000c 431 #define LB_MEM_DATA 0x80010 432 433 #define LB_MEM_ACCESS 0x80014 434 #define LB_MEM_HNDSHK (1<<30) 435 #define LM_MEM_WRITE (0x7) 436 #define LM_MEM_READ (0x3) 437 438 #define SDRAM_CTL 0x80018 439 #define LB_64_ENB (1<<3) 440 #define LB_TWR (1<<2) 441 #define LB_TRP (1<<1) 442 #define LB_TRAS (1<<0) 443 444 #define INT_FIFO 0x8001c 445 #define INT_MASK_D (1<<15) 446 #define INT_MASK_C (1<<14) 447 #define INT_MASK_B (1<<13) 448 #define INT_MASK_A (1<<12) 449 #define INT_CLEAR_D (1<<11) 450 #define INT_CLEAR_C (1<<10) 451 #define INT_CLEAR_B (1<<9) 452 #define INT_CLEAR_A (1<<8) 453 454 #define ABORT_ADDR 0x80020 455 456 #define IRQ0_BASE 0x80080 457 #define IRQ_BASE(x) (x<<12) 458 #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */ 459 #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK) 460 #define IRQ0_HEAD 0x80084 461 #define IRQ_SIZE(x) (x<<22) 462 #define IRQ_THRESH(x) (x<<12) 463 #define IRQ_HEAD(x) (x<<2) 464 /* #define IRQ_PENDING (1) conflict with linux/irq.h */ 465 #define IRQ0_CNTL 0x80088 466 #define IRQ_ADDRSEL(x) (x<<2) 467 #define IRQ_INT_A (0<<2) 468 #define IRQ_INT_B (1<<2) 469 #define IRQ_INT_C (2<<2) 470 #define IRQ_INT_D (3<<2) 471 #define IRQ_TYPE_ADDR 0x1 472 #define IRQ_TYPE_LINE 0x0 473 #define IRQ0_DATA 0x8008c 474 475 #define IRQ1_BASE 0x80090 476 #define IRQ1_HEAD 0x80094 477 #define IRQ1_CNTL 0x80098 478 #define IRQ1_DATA 0x8009c 479 480 #define IRQ2_BASE 0x800a0 481 #define IRQ2_HEAD 0x800a4 482 #define IRQ2_CNTL 0x800a8 483 #define IRQ2_DATA 0x800ac 484 485 #define IRQ3_BASE 0x800b0 486 #define IRQ3_HEAD 0x800b4 487 #define IRQ3_CNTL 0x800b8 488 #define IRQ3_DATA 0x800bc 489 490 #define GRP_10_MAP 0x800c0 491 #define GRP_32_MAP 0x800c4 492 #define GRP_54_MAP 0x800c8 493 #define GRP_76_MAP 0x800cc 494 495 #define G0_RBPS_S 0x80400 496 #define G0_RBPS_T 0x80404 497 #define RBP_TAIL(x) ((x)<<3) 498 #define RBP_MASK(x) ((x)|0x1fff) 499 #define G0_RBPS_QI 0x80408 500 #define RBP_QSIZE(x) ((x)<<14) 501 #define RBP_INT_ENB (1<<13) 502 #define RBP_THRESH(x) (x) 503 #define G0_RBPS_BS 0x8040c 504 #define G0_RBPL_S 0x80410 505 #define G0_RBPL_T 0x80414 506 #define G0_RBPL_QI 0x80418 507 #define G0_RBPL_BS 0x8041c 508 509 #define G1_RBPS_S 0x80420 510 #define G1_RBPS_T 0x80424 511 #define G1_RBPS_QI 0x80428 512 #define G1_RBPS_BS 0x8042c 513 #define G1_RBPL_S 0x80430 514 #define G1_RBPL_T 0x80434 515 #define G1_RBPL_QI 0x80438 516 #define G1_RBPL_BS 0x8043c 517 518 #define G2_RBPS_S 0x80440 519 #define G2_RBPS_T 0x80444 520 #define G2_RBPS_QI 0x80448 521 #define G2_RBPS_BS 0x8044c 522 #define G2_RBPL_S 0x80450 523 #define G2_RBPL_T 0x80454 524 #define G2_RBPL_QI 0x80458 525 #define G2_RBPL_BS 0x8045c 526 527 #define G3_RBPS_S 0x80460 528 #define G3_RBPS_T 0x80464 529 #define G3_RBPS_QI 0x80468 530 #define G3_RBPS_BS 0x8046c 531 #define G3_RBPL_S 0x80470 532 #define G3_RBPL_T 0x80474 533 #define G3_RBPL_QI 0x80478 534 #define G3_RBPL_BS 0x8047c 535 536 #define G4_RBPS_S 0x80480 537 #define G4_RBPS_T 0x80484 538 #define G4_RBPS_QI 0x80488 539 #define G4_RBPS_BS 0x8048c 540 #define G4_RBPL_S 0x80490 541 #define G4_RBPL_T 0x80494 542 #define G4_RBPL_QI 0x80498 543 #define G4_RBPL_BS 0x8049c 544 545 #define G5_RBPS_S 0x804a0 546 #define G5_RBPS_T 0x804a4 547 #define G5_RBPS_QI 0x804a8 548 #define G5_RBPS_BS 0x804ac 549 #define G5_RBPL_S 0x804b0 550 #define G5_RBPL_T 0x804b4 551 #define G5_RBPL_QI 0x804b8 552 #define G5_RBPL_BS 0x804bc 553 554 #define G6_RBPS_S 0x804c0 555 #define G6_RBPS_T 0x804c4 556 #define G6_RBPS_QI 0x804c8 557 #define G6_RBPS_BS 0x804cc 558 #define G6_RBPL_S 0x804d0 559 #define G6_RBPL_T 0x804d4 560 #define G6_RBPL_QI 0x804d8 561 #define G6_RBPL_BS 0x804dc 562 563 #define G7_RBPS_S 0x804e0 564 #define G7_RBPS_T 0x804e4 565 #define G7_RBPS_QI 0x804e8 566 #define G7_RBPS_BS 0x804ec 567 568 #define G7_RBPL_S 0x804f0 569 #define G7_RBPL_T 0x804f4 570 #define G7_RBPL_QI 0x804f8 571 #define G7_RBPL_BS 0x804fc 572 573 #define G0_RBRQ_ST 0x80500 574 #define G0_RBRQ_H 0x80504 575 #define G0_RBRQ_Q 0x80508 576 #define RBRQ_THRESH(x) ((x)<<13) 577 #define RBRQ_SIZE(x) (x) 578 #define G0_RBRQ_I 0x8050c 579 #define RBRQ_TIME(x) ((x)<<8) 580 #define RBRQ_COUNT(x) (x) 581 582 /* fill in 1 ... 7 later */ 583 584 #define G0_TBRQ_B_T 0x80600 585 #define G0_TBRQ_H 0x80604 586 #define G0_TBRQ_S 0x80608 587 #define G0_TBRQ_THRESH 0x8060c 588 #define TBRQ_THRESH(x) (x) 589 590 /* fill in 1 ... 7 later */ 591 592 #define RH_CONFIG 0x805c0 593 #define PHY_INT_ENB (1<<10) 594 #define OAM_GID(x) (x<<7) 595 #define PTMR_PRE(x) (x) 596 597 #define G0_INMQ_S 0x80580 598 #define G0_INMQ_L 0x80584 599 #define G1_INMQ_S 0x80588 600 #define G1_INMQ_L 0x8058c 601 #define G2_INMQ_S 0x80590 602 #define G2_INMQ_L 0x80594 603 #define G3_INMQ_S 0x80598 604 #define G3_INMQ_L 0x8059c 605 #define G4_INMQ_S 0x805a0 606 #define G4_INMQ_L 0x805a4 607 #define G5_INMQ_S 0x805a8 608 #define G5_INMQ_L 0x805ac 609 #define G6_INMQ_S 0x805b0 610 #define G6_INMQ_L 0x805b4 611 #define G7_INMQ_S 0x805b8 612 #define G7_INMQ_L 0x805bc 613 614 #define TPDRQ_B_H 0x80680 615 #define TPDRQ_T 0x80684 616 #define TPDRQ_S 0x80688 617 618 #define UBUFF_BA 0x8068c 619 620 #define RLBF0_H 0x806c0 621 #define RLBF0_T 0x806c4 622 #define RLBF1_H 0x806c8 623 #define RLBF1_T 0x806cc 624 #define RLBC_H 0x806d0 625 #define RLBC_T 0x806d4 626 #define RLBC_H2 0x806d8 627 #define TLBF_H 0x806e0 628 #define TLBF_T 0x806e4 629 #define RLBF0_C 0x806e8 630 #define RLBF1_C 0x806ec 631 #define RXTHRSH 0x806f0 632 #define LITHRSH 0x806f4 633 634 #define LBARB 0x80700 635 #define SLICE_X(x) (x<<28) 636 #define ARB_RNUM_MAX(x) (x<<23) 637 #define TH_PRTY(x) (x<<21) 638 #define RH_PRTY(x) (x<<19) 639 #define TL_PRTY(x) (x<<17) 640 #define RL_PRTY(x) (x<<15) 641 #define BUS_MULTI(x) (x<<8) 642 #define NET_PREF(x) (x) 643 644 #define SDRAMCON 0x80704 645 #define BANK_ON (1<<14) 646 #define WIDE_DATA (1<<13) 647 #define TWR_WAIT (1<<12) 648 #define TRP_WAIT (1<<11) 649 #define TRAS_WAIT (1<<10) 650 #define REF_RATE(x) (x) 651 652 #define LBSTAT 0x80708 653 654 #define RCC_STAT 0x8070c 655 #define RCC_BUSY (1) 656 657 #define TCMCONFIG 0x80740 658 #define TM_DESL2 (1<<10) 659 #define TM_BANK_WAIT(x) (x<<6) 660 #define TM_ADD_BANK4(x) (x<<4) 661 #define TM_PAR_CHECK(x) (x<<3) 662 #define TM_RW_WAIT(x) (x<<2) 663 #define TM_SRAM_TYPE(x) (x) 664 665 #define TSRB_BA 0x80744 666 #define TSRC_BA 0x80748 667 #define TMABR_BA 0x8074c 668 #define TPD_BA 0x80750 669 #define TSRD_BA 0x80758 670 671 #define TX_CONFIG 0x80760 672 #define DRF_THRESH(x) (x<<22) 673 #define TX_UT_MODE(x) (x<<21) 674 #define TX_VCI_MASK(x) (x<<17) 675 #define LBFREE_CNT(x) (x) 676 677 #define TXAAL5_PROTO 0x80764 678 #define CPCS_UU(x) (x<<8) 679 #define CPI(x) (x) 680 681 #define RCMCONFIG 0x80780 682 #define RM_DESL2(x) (x<<10) 683 #define RM_BANK_WAIT(x) (x<<6) 684 #define RM_ADD_BANK(x) (x<<4) 685 #define RM_PAR_CHECK(x) (x<<3) 686 #define RM_RW_WAIT(x) (x<<2) 687 #define RM_SRAM_TYPE(x) (x) 688 689 #define RCMRSRB_BA 0x80784 690 #define RCMLBM_BA 0x80788 691 #define RCMABR_BA 0x8078c 692 693 #define RC_CONFIG 0x807c0 694 #define UT_RD_DELAY(x) (x<<11) 695 #define WRAP_MODE(x) (x<<10) 696 #define RC_UT_MODE(x) (x<<9) 697 #define RX_ENABLE (1<<8) 698 #define RX_VALVP(x) (x<<4) 699 #define RX_VALVC(x) (x) 700 701 #define MCC 0x807c4 702 #define OEC 0x807c8 703 #define DCC 0x807cc 704 #define CEC 0x807d0 705 706 #define HSP_BA 0x807f0 707 708 #define LB_CONFIG 0x807f4 709 #define LB_SIZE(x) (x) 710 711 #define CON_DAT 0x807f8 712 #define CON_CTL 0x807fc 713 #define CON_CTL_MBOX (2<<30) 714 #define CON_CTL_TCM (1<<30) 715 #define CON_CTL_RCM (0<<30) 716 #define CON_CTL_WRITE (1<<29) 717 #define CON_CTL_READ (0<<29) 718 #define CON_CTL_BUSY (1<<28) 719 #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */ 720 #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */ 721 #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */ 722 #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */ 723 #define CON_CTL_ADDR(x) (x) 724 725 #define FRAMER 0x80800 /* to 0x80bfc */ 726 727 /* 3.3 network controller (internal) mailbox registers */ 728 729 #define CS_STPER0 0x0 730 /* ... */ 731 #define CS_STPER31 0x01f 732 733 #define CS_STTIM0 0x020 734 /* ... */ 735 #define CS_STTIM31 0x03f 736 737 #define CS_TGRLD0 0x040 738 /* ... */ 739 #define CS_TGRLD15 0x04f 740 741 #define CS_ERTHR0 0x050 742 #define CS_ERTHR1 0x051 743 #define CS_ERTHR2 0x052 744 #define CS_ERTHR3 0x053 745 #define CS_ERTHR4 0x054 746 #define CS_ERCTL0 0x055 747 #define TX_ENABLE (1<<28) 748 #define ER_ENABLE (1<<27) 749 #define CS_ERCTL1 0x056 750 #define CS_ERCTL2 0x057 751 #define CS_ERSTAT0 0x058 752 #define CS_ERSTAT1 0x059 753 754 #define CS_RTCCT 0x060 755 #define CS_RTFWC 0x061 756 #define CS_RTFWR 0x062 757 #define CS_RTFTC 0x063 758 #define CS_RTATR 0x064 759 760 #define CS_TFBSET 0x070 761 #define CS_TFBADD 0x071 762 #define CS_TFBSUB 0x072 763 #define CS_WCRMAX 0x073 764 #define CS_WCRMIN 0x074 765 #define CS_WCRINC 0x075 766 #define CS_WCRDEC 0x076 767 #define CS_WCRCEIL 0x077 768 #define CS_BWDCNT 0x078 769 770 #define CS_OTPPER 0x080 771 #define CS_OTWPER 0x081 772 #define CS_OTTLIM 0x082 773 #define CS_OTTCNT 0x083 774 775 #define CS_HGRRT0 0x090 776 /* ... */ 777 #define CS_HGRRT7 0x097 778 779 #define CS_ORPTRS 0x0a0 780 781 #define RXCON_CLOSE 0x100 782 783 784 #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */ 785 #define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */ 786 787 /* 2.5 transmit connection memory registers */ 788 789 #define TSR0_CONN_STATE(x) ((x>>28) & 0x7) 790 #define TSR0_USE_WMIN (1<<23) 791 #define TSR0_GROUP(x) ((x & 0x7)<<18) 792 #define TSR0_ABR (2<<16) 793 #define TSR0_UBR (1<<16) 794 #define TSR0_CBR (0<<16) 795 #define TSR0_PROT (1<<15) 796 #define TSR0_AAL0_SDU (2<<12) 797 #define TSR0_AAL0 (1<<12) 798 #define TSR0_AAL5 (0<<12) 799 #define TSR0_HALT_ER (1<<11) 800 #define TSR0_MARK_CI (1<<10) 801 #define TSR0_MARK_ER (1<<9) 802 #define TSR0_UPDATE_GER (1<<8) 803 #define TSR0_RC_INDEX(x) (x & 0x1F) 804 805 #define TSR1_PCR(x) ((x & 0x7FFF)<<16) 806 #define TSR1_MCR(x) (x & 0x7FFF) 807 808 #define TSR2_ACR(x) ((x & 0x7FFF)<<16) 809 810 #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24) 811 #define TSR3_CRM_CNT(x) (x & 0xFFFF) 812 813 #define TSR4_FLUSH_CONN (1<<31) 814 #define TSR4_SESSION_ENDED (1<<30) 815 #define TSR4_CRC10 (1<<28) 816 #define TSR4_NULL_CRC10 (1<<27) 817 #define TSR4_PROT (1<<26) 818 #define TSR4_AAL0_SDU (2<<23) 819 #define TSR4_AAL0 (1<<23) 820 #define TSR4_AAL5 (0<<23) 821 822 #define TSR9_OPEN_CONN (1<<20) 823 824 #define TSR11_ICR(x) ((x & 0x7FFF)<<16) 825 #define TSR11_TRM(x) ((x & 0x7)<<13) 826 #define TSR11_NRM(x) ((x & 0x7)<<10) 827 #define TSR11_ADTF(x) (x & 0x3FF) 828 829 #define TSR13_RDF(x) ((x & 0xF)<<23) 830 #define TSR13_RIF(x) ((x & 0xF)<<19) 831 #define TSR13_CDF(x) ((x & 0x7)<<16) 832 #define TSR13_CRM(x) (x & 0xFFFF) 833 834 #define TSR14_DELETE (1<<31) 835 #define TSR14_ABR_CLOSE (1<<16) 836 837 /* 2.7.1 per connection receieve state registers */ 838 839 #define RSR0_START_PDU (1<<10) 840 #define RSR0_OPEN_CONN (1<<6) 841 #define RSR0_CLOSE_CONN (0<<6) 842 #define RSR0_PPD_ENABLE (1<<5) 843 #define RSR0_EPD_ENABLE (1<<4) 844 #define RSR0_TCP_CKSUM (1<<3) 845 #define RSR0_AAL5 (0) 846 #define RSR0_AAL0 (1) 847 #define RSR0_AAL0_SDU (2) 848 #define RSR0_RAWCELL (3) 849 #define RSR0_RAWCELL_CRC10 (4) 850 851 #define RSR1_AQI_ENABLE (1<<20) 852 #define RSR1_RBPL_ONLY (1<<19) 853 #define RSR1_GROUP(x) ((x)<<16) 854 855 #define RSR4_AQI_ENABLE (1<<30) 856 #define RSR4_GROUP(x) ((x)<<27) 857 #define RSR4_RBPL_ONLY (1<<26) 858 859 /* 2.1.4 transmit packet descriptor */ 860 861 #define TPD_USERCELL 0x0 862 #define TPD_SEGMENT_OAMF5 0x4 863 #define TPD_END2END_OAMF5 0x5 864 #define TPD_RMCELL 0x6 865 #define TPD_CELLTYPE(x) (x<<3) 866 #define TPD_EOS (1<<2) 867 #define TPD_CLP (1<<1) 868 #define TPD_INT (1<<0) 869 #define TPD_LST (1<<31) 870 871 /* table 4.3 serial eeprom information */ 872 873 #define PROD_ID 0x08 /* char[] */ 874 #define PROD_ID_LEN 30 875 #define HW_REV 0x26 /* char[] */ 876 #define M_SN 0x3a /* integer */ 877 #define MEDIA 0x3e /* integer */ 878 #define HE155MM 0x26 879 #define HE155SM 0x27 880 #define HE622MM 0x46 881 #define HE622SM 0x47 882 #define MAC_ADDR 0x42 /* char[] */ 883 884 #define CS_LOW 0x0 885 #define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */ 886 #define CLK_LOW 0x0 887 #define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */ 888 #define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */ 889 #define EEPROM_DELAY 400 /* microseconds */ 890 891 #endif /* _HE_H_ */ 892