1 /* 2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA 3 * 4 * Maintained by: Jeremy Higdon @ SGI 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004 SGI 9 * 10 * Bits from Jeff Garzik, Copyright RedHat, Inc. 11 * 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; see the file COPYING. If not, write to 25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * 28 * libata documentation is available via 'make {ps|pdf}docs', 29 * as Documentation/DocBook/libata.* 30 * 31 * Vitesse hardware documentation presumably available under NDA. 32 * Intel 31244 (same hardware interface) documentation presumably 33 * available from http://developer.intel.com/ 34 * 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/init.h> 41 #include <linux/blkdev.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/device.h> 46 #include <scsi/scsi_host.h> 47 #include <linux/libata.h> 48 49 #define DRV_NAME "sata_vsc" 50 #define DRV_VERSION "2.3" 51 52 enum { 53 VSC_MMIO_BAR = 0, 54 55 /* Interrupt register offsets (from chip base address) */ 56 VSC_SATA_INT_STAT_OFFSET = 0x00, 57 VSC_SATA_INT_MASK_OFFSET = 0x04, 58 59 /* Taskfile registers offsets */ 60 VSC_SATA_TF_CMD_OFFSET = 0x00, 61 VSC_SATA_TF_DATA_OFFSET = 0x00, 62 VSC_SATA_TF_ERROR_OFFSET = 0x04, 63 VSC_SATA_TF_FEATURE_OFFSET = 0x06, 64 VSC_SATA_TF_NSECT_OFFSET = 0x08, 65 VSC_SATA_TF_LBAL_OFFSET = 0x0c, 66 VSC_SATA_TF_LBAM_OFFSET = 0x10, 67 VSC_SATA_TF_LBAH_OFFSET = 0x14, 68 VSC_SATA_TF_DEVICE_OFFSET = 0x18, 69 VSC_SATA_TF_STATUS_OFFSET = 0x1c, 70 VSC_SATA_TF_COMMAND_OFFSET = 0x1d, 71 VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28, 72 VSC_SATA_TF_CTL_OFFSET = 0x29, 73 74 /* DMA base */ 75 VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64, 76 VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C, 77 VSC_SATA_DMA_CMD_OFFSET = 0x70, 78 79 /* SCRs base */ 80 VSC_SATA_SCR_STATUS_OFFSET = 0x100, 81 VSC_SATA_SCR_ERROR_OFFSET = 0x104, 82 VSC_SATA_SCR_CONTROL_OFFSET = 0x108, 83 84 /* Port stride */ 85 VSC_SATA_PORT_OFFSET = 0x200, 86 87 /* Error interrupt status bit offsets */ 88 VSC_SATA_INT_ERROR_CRC = 0x40, 89 VSC_SATA_INT_ERROR_T = 0x20, 90 VSC_SATA_INT_ERROR_P = 0x10, 91 VSC_SATA_INT_ERROR_R = 0x8, 92 VSC_SATA_INT_ERROR_E = 0x4, 93 VSC_SATA_INT_ERROR_M = 0x2, 94 VSC_SATA_INT_PHY_CHANGE = 0x1, 95 VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \ 96 VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \ 97 VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \ 98 VSC_SATA_INT_PHY_CHANGE), 99 }; 100 101 static int vsc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 102 { 103 if (sc_reg > SCR_CONTROL) 104 return -EINVAL; 105 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 106 return 0; 107 } 108 109 110 static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 111 { 112 if (sc_reg > SCR_CONTROL) 113 return -EINVAL; 114 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 115 return 0; 116 } 117 118 119 static void vsc_freeze(struct ata_port *ap) 120 { 121 void __iomem *mask_addr; 122 123 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + 124 VSC_SATA_INT_MASK_OFFSET + ap->port_no; 125 126 writeb(0, mask_addr); 127 } 128 129 130 static void vsc_thaw(struct ata_port *ap) 131 { 132 void __iomem *mask_addr; 133 134 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + 135 VSC_SATA_INT_MASK_OFFSET + ap->port_no; 136 137 writeb(0xff, mask_addr); 138 } 139 140 141 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl) 142 { 143 void __iomem *mask_addr; 144 u8 mask; 145 146 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + 147 VSC_SATA_INT_MASK_OFFSET + ap->port_no; 148 mask = readb(mask_addr); 149 if (ctl & ATA_NIEN) 150 mask |= 0x80; 151 else 152 mask &= 0x7F; 153 writeb(mask, mask_addr); 154 } 155 156 157 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 158 { 159 struct ata_ioports *ioaddr = &ap->ioaddr; 160 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 161 162 /* 163 * The only thing the ctl register is used for is SRST. 164 * That is not enabled or disabled via tf_load. 165 * However, if ATA_NIEN is changed, then we need to change 166 * the interrupt register. 167 */ 168 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) { 169 ap->last_ctl = tf->ctl; 170 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN); 171 } 172 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 173 writew(tf->feature | (((u16)tf->hob_feature) << 8), 174 ioaddr->feature_addr); 175 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), 176 ioaddr->nsect_addr); 177 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), 178 ioaddr->lbal_addr); 179 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), 180 ioaddr->lbam_addr); 181 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), 182 ioaddr->lbah_addr); 183 } else if (is_addr) { 184 writew(tf->feature, ioaddr->feature_addr); 185 writew(tf->nsect, ioaddr->nsect_addr); 186 writew(tf->lbal, ioaddr->lbal_addr); 187 writew(tf->lbam, ioaddr->lbam_addr); 188 writew(tf->lbah, ioaddr->lbah_addr); 189 } 190 191 if (tf->flags & ATA_TFLAG_DEVICE) 192 writeb(tf->device, ioaddr->device_addr); 193 194 ata_wait_idle(ap); 195 } 196 197 198 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 199 { 200 struct ata_ioports *ioaddr = &ap->ioaddr; 201 u16 nsect, lbal, lbam, lbah, feature; 202 203 tf->command = ata_sff_check_status(ap); 204 tf->device = readw(ioaddr->device_addr); 205 feature = readw(ioaddr->error_addr); 206 nsect = readw(ioaddr->nsect_addr); 207 lbal = readw(ioaddr->lbal_addr); 208 lbam = readw(ioaddr->lbam_addr); 209 lbah = readw(ioaddr->lbah_addr); 210 211 tf->feature = feature; 212 tf->nsect = nsect; 213 tf->lbal = lbal; 214 tf->lbam = lbam; 215 tf->lbah = lbah; 216 217 if (tf->flags & ATA_TFLAG_LBA48) { 218 tf->hob_feature = feature >> 8; 219 tf->hob_nsect = nsect >> 8; 220 tf->hob_lbal = lbal >> 8; 221 tf->hob_lbam = lbam >> 8; 222 tf->hob_lbah = lbah >> 8; 223 } 224 } 225 226 static inline void vsc_error_intr(u8 port_status, struct ata_port *ap) 227 { 228 if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M)) 229 ata_port_freeze(ap); 230 else 231 ata_port_abort(ap); 232 } 233 234 static void vsc_port_intr(u8 port_status, struct ata_port *ap) 235 { 236 struct ata_queued_cmd *qc; 237 int handled = 0; 238 239 if (unlikely(port_status & VSC_SATA_INT_ERROR)) { 240 vsc_error_intr(port_status, ap); 241 return; 242 } 243 244 qc = ata_qc_from_tag(ap, ap->link.active_tag); 245 if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING))) 246 handled = ata_sff_host_intr(ap, qc); 247 248 /* We received an interrupt during a polled command, 249 * or some other spurious condition. Interrupt reporting 250 * with this hardware is fairly reliable so it is safe to 251 * simply clear the interrupt 252 */ 253 if (unlikely(!handled)) 254 ap->ops->sff_check_status(ap); 255 } 256 257 /* 258 * vsc_sata_interrupt 259 * 260 * Read the interrupt register and process for the devices that have 261 * them pending. 262 */ 263 static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance) 264 { 265 struct ata_host *host = dev_instance; 266 unsigned int i; 267 unsigned int handled = 0; 268 u32 status; 269 270 status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET); 271 272 if (unlikely(status == 0xffffffff || status == 0)) { 273 if (status) 274 dev_printk(KERN_ERR, host->dev, 275 ": IRQ status == 0xffffffff, " 276 "PCI fault or device removal?\n"); 277 goto out; 278 } 279 280 spin_lock(&host->lock); 281 282 for (i = 0; i < host->n_ports; i++) { 283 u8 port_status = (status >> (8 * i)) & 0xff; 284 if (port_status) { 285 struct ata_port *ap = host->ports[i]; 286 287 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 288 vsc_port_intr(port_status, ap); 289 handled++; 290 } else 291 dev_printk(KERN_ERR, host->dev, 292 "interrupt from disabled port %d\n", i); 293 } 294 } 295 296 spin_unlock(&host->lock); 297 out: 298 return IRQ_RETVAL(handled); 299 } 300 301 302 static struct scsi_host_template vsc_sata_sht = { 303 ATA_BMDMA_SHT(DRV_NAME), 304 }; 305 306 307 static struct ata_port_operations vsc_sata_ops = { 308 .inherits = &ata_bmdma_port_ops, 309 .sff_tf_load = vsc_sata_tf_load, 310 .sff_tf_read = vsc_sata_tf_read, 311 .freeze = vsc_freeze, 312 .thaw = vsc_thaw, 313 .scr_read = vsc_sata_scr_read, 314 .scr_write = vsc_sata_scr_write, 315 }; 316 317 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, 318 void __iomem *base) 319 { 320 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; 321 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; 322 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; 323 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; 324 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; 325 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET; 326 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET; 327 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET; 328 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET; 329 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET; 330 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET; 331 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET; 332 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; 333 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; 334 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; 335 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET); 336 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET); 337 } 338 339 340 static int __devinit vsc_sata_init_one(struct pci_dev *pdev, 341 const struct pci_device_id *ent) 342 { 343 static const struct ata_port_info pi = { 344 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 345 ATA_FLAG_MMIO, 346 .pio_mask = 0x1f, 347 .mwdma_mask = 0x07, 348 .udma_mask = ATA_UDMA6, 349 .port_ops = &vsc_sata_ops, 350 }; 351 const struct ata_port_info *ppi[] = { &pi, NULL }; 352 static int printed_version; 353 struct ata_host *host; 354 void __iomem *mmio_base; 355 int i, rc; 356 u8 cls; 357 358 if (!printed_version++) 359 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 360 361 /* allocate host */ 362 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4); 363 if (!host) 364 return -ENOMEM; 365 366 rc = pcim_enable_device(pdev); 367 if (rc) 368 return rc; 369 370 /* check if we have needed resource mapped */ 371 if (pci_resource_len(pdev, 0) == 0) 372 return -ENODEV; 373 374 /* map IO regions and intialize host accordingly */ 375 rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME); 376 if (rc == -EBUSY) 377 pcim_pin_device(pdev); 378 if (rc) 379 return rc; 380 host->iomap = pcim_iomap_table(pdev); 381 382 mmio_base = host->iomap[VSC_MMIO_BAR]; 383 384 for (i = 0; i < host->n_ports; i++) { 385 struct ata_port *ap = host->ports[i]; 386 unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET; 387 388 vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset); 389 390 ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio"); 391 ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port"); 392 } 393 394 /* 395 * Use 32 bit DMA mask, because 64 bit address support is poor. 396 */ 397 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 398 if (rc) 399 return rc; 400 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 401 if (rc) 402 return rc; 403 404 /* 405 * Due to a bug in the chip, the default cache line size can't be 406 * used (unless the default is non-zero). 407 */ 408 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls); 409 if (cls == 0x00) 410 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80); 411 412 if (pci_enable_msi(pdev) == 0) 413 pci_intx(pdev, 0); 414 415 /* 416 * Config offset 0x98 is "Extended Control and Status Register 0" 417 * Default value is (1 << 28). All bits except bit 28 are reserved in 418 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity. 419 * If bit 28 is clear, each port has its own LED. 420 */ 421 pci_write_config_dword(pdev, 0x98, 0); 422 423 pci_set_master(pdev); 424 return ata_host_activate(host, pdev->irq, vsc_sata_interrupt, 425 IRQF_SHARED, &vsc_sata_sht); 426 } 427 428 static const struct pci_device_id vsc_sata_pci_tbl[] = { 429 { PCI_VENDOR_ID_VITESSE, 0x7174, 430 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, 431 { PCI_VENDOR_ID_INTEL, 0x3200, 432 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, 433 434 { } /* terminate list */ 435 }; 436 437 static struct pci_driver vsc_sata_pci_driver = { 438 .name = DRV_NAME, 439 .id_table = vsc_sata_pci_tbl, 440 .probe = vsc_sata_init_one, 441 .remove = ata_pci_remove_one, 442 }; 443 444 static int __init vsc_sata_init(void) 445 { 446 return pci_register_driver(&vsc_sata_pci_driver); 447 } 448 449 static void __exit vsc_sata_exit(void) 450 { 451 pci_unregister_driver(&vsc_sata_pci_driver); 452 } 453 454 MODULE_AUTHOR("Jeremy Higdon"); 455 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller"); 456 MODULE_LICENSE("GPL"); 457 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl); 458 MODULE_VERSION(DRV_VERSION); 459 460 module_init(vsc_sata_init); 461 module_exit(vsc_sata_exit); 462