1 /* 2 * sata_svw.c - ServerWorks / Apple K2 SATA 3 * 4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and 5 * Jeff Garzik <jgarzik@pobox.com> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 10 * 11 * Bits from Jeff Garzik, Copyright RedHat, Inc. 12 * 13 * This driver probably works with non-Apple versions of the 14 * Broadcom chipset... 15 * 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; see the file COPYING. If not, write to 29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 * 32 * libata documentation is available via 'make {ps|pdf}docs', 33 * as Documentation/DocBook/libata.* 34 * 35 * Hardware documentation available under NDA. 36 * 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/pci.h> 42 #include <linux/blkdev.h> 43 #include <linux/delay.h> 44 #include <linux/interrupt.h> 45 #include <linux/device.h> 46 #include <scsi/scsi_host.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <scsi/scsi.h> 49 #include <linux/libata.h> 50 51 #ifdef CONFIG_PPC_OF 52 #include <asm/prom.h> 53 #include <asm/pci-bridge.h> 54 #endif /* CONFIG_PPC_OF */ 55 56 #define DRV_NAME "sata_svw" 57 #define DRV_VERSION "2.3" 58 59 enum { 60 /* ap->flags bits */ 61 K2_FLAG_SATA_8_PORTS = (1 << 24), 62 K2_FLAG_NO_ATAPI_DMA = (1 << 25), 63 K2_FLAG_BAR_POS_3 = (1 << 26), 64 65 /* Taskfile registers offsets */ 66 K2_SATA_TF_CMD_OFFSET = 0x00, 67 K2_SATA_TF_DATA_OFFSET = 0x00, 68 K2_SATA_TF_ERROR_OFFSET = 0x04, 69 K2_SATA_TF_NSECT_OFFSET = 0x08, 70 K2_SATA_TF_LBAL_OFFSET = 0x0c, 71 K2_SATA_TF_LBAM_OFFSET = 0x10, 72 K2_SATA_TF_LBAH_OFFSET = 0x14, 73 K2_SATA_TF_DEVICE_OFFSET = 0x18, 74 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, 75 K2_SATA_TF_CTL_OFFSET = 0x20, 76 77 /* DMA base */ 78 K2_SATA_DMA_CMD_OFFSET = 0x30, 79 80 /* SCRs base */ 81 K2_SATA_SCR_STATUS_OFFSET = 0x40, 82 K2_SATA_SCR_ERROR_OFFSET = 0x44, 83 K2_SATA_SCR_CONTROL_OFFSET = 0x48, 84 85 /* Others */ 86 K2_SATA_SICR1_OFFSET = 0x80, 87 K2_SATA_SICR2_OFFSET = 0x84, 88 K2_SATA_SIM_OFFSET = 0x88, 89 90 /* Port stride */ 91 K2_SATA_PORT_OFFSET = 0x100, 92 93 chip_svw4 = 0, 94 chip_svw8 = 1, 95 chip_svw42 = 2, /* bar 3 */ 96 chip_svw43 = 3, /* bar 5 */ 97 }; 98 99 static u8 k2_stat_check_status(struct ata_port *ap); 100 101 102 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) 103 { 104 u8 cmnd = qc->scsicmd->cmnd[0]; 105 106 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) 107 return -1; /* ATAPI DMA not supported */ 108 else { 109 switch (cmnd) { 110 case READ_10: 111 case READ_12: 112 case READ_16: 113 case WRITE_10: 114 case WRITE_12: 115 case WRITE_16: 116 return 0; 117 118 default: 119 return -1; 120 } 121 122 } 123 } 124 125 static int k2_sata_scr_read(struct ata_link *link, 126 unsigned int sc_reg, u32 *val) 127 { 128 if (sc_reg > SCR_CONTROL) 129 return -EINVAL; 130 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 131 return 0; 132 } 133 134 135 static int k2_sata_scr_write(struct ata_link *link, 136 unsigned int sc_reg, u32 val) 137 { 138 if (sc_reg > SCR_CONTROL) 139 return -EINVAL; 140 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 141 return 0; 142 } 143 144 static int k2_sata_softreset(struct ata_link *link, 145 unsigned int *class, unsigned long deadline) 146 { 147 u8 dmactl; 148 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; 149 150 dmactl = readb(mmio + ATA_DMA_CMD); 151 152 /* Clear the start bit */ 153 if (dmactl & ATA_DMA_START) { 154 dmactl &= ~ATA_DMA_START; 155 writeb(dmactl, mmio + ATA_DMA_CMD); 156 } 157 158 return ata_sff_softreset(link, class, deadline); 159 } 160 161 static int k2_sata_hardreset(struct ata_link *link, 162 unsigned int *class, unsigned long deadline) 163 { 164 u8 dmactl; 165 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; 166 167 dmactl = readb(mmio + ATA_DMA_CMD); 168 169 /* Clear the start bit */ 170 if (dmactl & ATA_DMA_START) { 171 dmactl &= ~ATA_DMA_START; 172 writeb(dmactl, mmio + ATA_DMA_CMD); 173 } 174 175 return sata_sff_hardreset(link, class, deadline); 176 } 177 178 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 179 { 180 struct ata_ioports *ioaddr = &ap->ioaddr; 181 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 182 183 if (tf->ctl != ap->last_ctl) { 184 writeb(tf->ctl, ioaddr->ctl_addr); 185 ap->last_ctl = tf->ctl; 186 ata_wait_idle(ap); 187 } 188 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 189 writew(tf->feature | (((u16)tf->hob_feature) << 8), 190 ioaddr->feature_addr); 191 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), 192 ioaddr->nsect_addr); 193 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), 194 ioaddr->lbal_addr); 195 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), 196 ioaddr->lbam_addr); 197 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), 198 ioaddr->lbah_addr); 199 } else if (is_addr) { 200 writew(tf->feature, ioaddr->feature_addr); 201 writew(tf->nsect, ioaddr->nsect_addr); 202 writew(tf->lbal, ioaddr->lbal_addr); 203 writew(tf->lbam, ioaddr->lbam_addr); 204 writew(tf->lbah, ioaddr->lbah_addr); 205 } 206 207 if (tf->flags & ATA_TFLAG_DEVICE) 208 writeb(tf->device, ioaddr->device_addr); 209 210 ata_wait_idle(ap); 211 } 212 213 214 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 215 { 216 struct ata_ioports *ioaddr = &ap->ioaddr; 217 u16 nsect, lbal, lbam, lbah, feature; 218 219 tf->command = k2_stat_check_status(ap); 220 tf->device = readw(ioaddr->device_addr); 221 feature = readw(ioaddr->error_addr); 222 nsect = readw(ioaddr->nsect_addr); 223 lbal = readw(ioaddr->lbal_addr); 224 lbam = readw(ioaddr->lbam_addr); 225 lbah = readw(ioaddr->lbah_addr); 226 227 tf->feature = feature; 228 tf->nsect = nsect; 229 tf->lbal = lbal; 230 tf->lbam = lbam; 231 tf->lbah = lbah; 232 233 if (tf->flags & ATA_TFLAG_LBA48) { 234 tf->hob_feature = feature >> 8; 235 tf->hob_nsect = nsect >> 8; 236 tf->hob_lbal = lbal >> 8; 237 tf->hob_lbam = lbam >> 8; 238 tf->hob_lbah = lbah >> 8; 239 } 240 } 241 242 /** 243 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) 244 * @qc: Info associated with this ATA transaction. 245 * 246 * LOCKING: 247 * spin_lock_irqsave(host lock) 248 */ 249 250 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) 251 { 252 struct ata_port *ap = qc->ap; 253 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 254 u8 dmactl; 255 void __iomem *mmio = ap->ioaddr.bmdma_addr; 256 257 /* load PRD table addr. */ 258 mb(); /* make sure PRD table writes are visible to controller */ 259 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS); 260 261 /* specify data direction, triple-check start bit is clear */ 262 dmactl = readb(mmio + ATA_DMA_CMD); 263 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 264 if (!rw) 265 dmactl |= ATA_DMA_WR; 266 writeb(dmactl, mmio + ATA_DMA_CMD); 267 268 /* issue r/w command if this is not a ATA DMA command*/ 269 if (qc->tf.protocol != ATA_PROT_DMA) 270 ap->ops->sff_exec_command(ap, &qc->tf); 271 } 272 273 /** 274 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) 275 * @qc: Info associated with this ATA transaction. 276 * 277 * LOCKING: 278 * spin_lock_irqsave(host lock) 279 */ 280 281 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) 282 { 283 struct ata_port *ap = qc->ap; 284 void __iomem *mmio = ap->ioaddr.bmdma_addr; 285 u8 dmactl; 286 287 /* start host DMA transaction */ 288 dmactl = readb(mmio + ATA_DMA_CMD); 289 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); 290 /* This works around possible data corruption. 291 292 On certain SATA controllers that can be seen when the r/w 293 command is given to the controller before the host DMA is 294 started. 295 296 On a Read command, the controller would initiate the 297 command to the drive even before it sees the DMA 298 start. When there are very fast drives connected to the 299 controller, or when the data request hits in the drive 300 cache, there is the possibility that the drive returns a 301 part or all of the requested data to the controller before 302 the DMA start is issued. In this case, the controller 303 would become confused as to what to do with the data. In 304 the worst case when all the data is returned back to the 305 controller, the controller could hang. In other cases it 306 could return partial data returning in data 307 corruption. This problem has been seen in PPC systems and 308 can also appear on an system with very fast disks, where 309 the SATA controller is sitting behind a number of bridges, 310 and hence there is significant latency between the r/w 311 command and the start command. */ 312 /* issue r/w command if the access is to ATA */ 313 if (qc->tf.protocol == ATA_PROT_DMA) 314 ap->ops->sff_exec_command(ap, &qc->tf); 315 } 316 317 318 static u8 k2_stat_check_status(struct ata_port *ap) 319 { 320 return readl(ap->ioaddr.status_addr); 321 } 322 323 #ifdef CONFIG_PPC_OF 324 static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost) 325 { 326 struct ata_port *ap; 327 struct device_node *np; 328 int index; 329 330 /* Find the ata_port */ 331 ap = ata_shost_to_port(shost); 332 if (ap == NULL) 333 return 0; 334 335 /* Find the OF node for the PCI device proper */ 336 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); 337 if (np == NULL) 338 return 0; 339 340 /* Match it to a port node */ 341 index = (ap == ap->host->ports[0]) ? 0 : 1; 342 for (np = np->child; np != NULL; np = np->sibling) { 343 const u32 *reg = of_get_property(np, "reg", NULL); 344 if (!reg) 345 continue; 346 if (index == *reg) { 347 seq_printf(m, "devspec: %s\n", np->full_name); 348 break; 349 } 350 } 351 return 0; 352 } 353 #endif /* CONFIG_PPC_OF */ 354 355 356 static struct scsi_host_template k2_sata_sht = { 357 ATA_BMDMA_SHT(DRV_NAME), 358 #ifdef CONFIG_PPC_OF 359 .show_info = k2_sata_show_info, 360 #endif 361 }; 362 363 364 static struct ata_port_operations k2_sata_ops = { 365 .inherits = &ata_bmdma_port_ops, 366 .softreset = k2_sata_softreset, 367 .hardreset = k2_sata_hardreset, 368 .sff_tf_load = k2_sata_tf_load, 369 .sff_tf_read = k2_sata_tf_read, 370 .sff_check_status = k2_stat_check_status, 371 .check_atapi_dma = k2_sata_check_atapi_dma, 372 .bmdma_setup = k2_bmdma_setup_mmio, 373 .bmdma_start = k2_bmdma_start_mmio, 374 .scr_read = k2_sata_scr_read, 375 .scr_write = k2_sata_scr_write, 376 }; 377 378 static const struct ata_port_info k2_port_info[] = { 379 /* chip_svw4 */ 380 { 381 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA, 382 .pio_mask = ATA_PIO4, 383 .mwdma_mask = ATA_MWDMA2, 384 .udma_mask = ATA_UDMA6, 385 .port_ops = &k2_sata_ops, 386 }, 387 /* chip_svw8 */ 388 { 389 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA | 390 K2_FLAG_SATA_8_PORTS, 391 .pio_mask = ATA_PIO4, 392 .mwdma_mask = ATA_MWDMA2, 393 .udma_mask = ATA_UDMA6, 394 .port_ops = &k2_sata_ops, 395 }, 396 /* chip_svw42 */ 397 { 398 .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3, 399 .pio_mask = ATA_PIO4, 400 .mwdma_mask = ATA_MWDMA2, 401 .udma_mask = ATA_UDMA6, 402 .port_ops = &k2_sata_ops, 403 }, 404 /* chip_svw43 */ 405 { 406 .flags = ATA_FLAG_SATA, 407 .pio_mask = ATA_PIO4, 408 .mwdma_mask = ATA_MWDMA2, 409 .udma_mask = ATA_UDMA6, 410 .port_ops = &k2_sata_ops, 411 }, 412 }; 413 414 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) 415 { 416 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; 417 port->data_addr = base + K2_SATA_TF_DATA_OFFSET; 418 port->feature_addr = 419 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; 420 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; 421 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; 422 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; 423 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; 424 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; 425 port->command_addr = 426 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; 427 port->altstatus_addr = 428 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; 429 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; 430 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; 431 } 432 433 434 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 435 { 436 const struct ata_port_info *ppi[] = 437 { &k2_port_info[ent->driver_data], NULL }; 438 struct ata_host *host; 439 void __iomem *mmio_base; 440 int n_ports, i, rc, bar_pos; 441 442 ata_print_version_once(&pdev->dev, DRV_VERSION); 443 444 /* allocate host */ 445 n_ports = 4; 446 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) 447 n_ports = 8; 448 449 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 450 if (!host) 451 return -ENOMEM; 452 453 bar_pos = 5; 454 if (ppi[0]->flags & K2_FLAG_BAR_POS_3) 455 bar_pos = 3; 456 /* 457 * If this driver happens to only be useful on Apple's K2, then 458 * we should check that here as it has a normal Serverworks ID 459 */ 460 rc = pcim_enable_device(pdev); 461 if (rc) 462 return rc; 463 464 /* 465 * Check if we have resources mapped at all (second function may 466 * have been disabled by firmware) 467 */ 468 if (pci_resource_len(pdev, bar_pos) == 0) { 469 /* In IDE mode we need to pin the device to ensure that 470 pcim_release does not clear the busmaster bit in config 471 space, clearing causes busmaster DMA to fail on 472 ports 3 & 4 */ 473 pcim_pin_device(pdev); 474 return -ENODEV; 475 } 476 477 /* Request and iomap PCI regions */ 478 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); 479 if (rc == -EBUSY) 480 pcim_pin_device(pdev); 481 if (rc) 482 return rc; 483 host->iomap = pcim_iomap_table(pdev); 484 mmio_base = host->iomap[bar_pos]; 485 486 /* different controllers have different number of ports - currently 4 or 8 */ 487 /* All ports are on the same function. Multi-function device is no 488 * longer available. This should not be seen in any system. */ 489 for (i = 0; i < host->n_ports; i++) { 490 struct ata_port *ap = host->ports[i]; 491 unsigned int offset = i * K2_SATA_PORT_OFFSET; 492 493 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); 494 495 ata_port_pbar_desc(ap, 5, -1, "mmio"); 496 ata_port_pbar_desc(ap, 5, offset, "port"); 497 } 498 499 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 500 if (rc) 501 return rc; 502 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 503 if (rc) 504 return rc; 505 506 /* Clear a magic bit in SCR1 according to Darwin, those help 507 * some funky seagate drives (though so far, those were already 508 * set by the firmware on the machines I had access to) 509 */ 510 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, 511 mmio_base + K2_SATA_SICR1_OFFSET); 512 513 /* Clear SATA error & interrupts we don't use */ 514 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); 515 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); 516 517 pci_set_master(pdev); 518 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 519 IRQF_SHARED, &k2_sata_sht); 520 } 521 522 /* 0x240 is device ID for Apple K2 device 523 * 0x241 is device ID for Serverworks Frodo4 524 * 0x242 is device ID for Serverworks Frodo8 525 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA 526 * controller 527 * */ 528 static const struct pci_device_id k2_sata_pci_tbl[] = { 529 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, 530 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, 531 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, 532 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, 533 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, 534 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, 535 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, 536 537 { } 538 }; 539 540 static struct pci_driver k2_sata_pci_driver = { 541 .name = DRV_NAME, 542 .id_table = k2_sata_pci_tbl, 543 .probe = k2_sata_init_one, 544 .remove = ata_pci_remove_one, 545 }; 546 547 module_pci_driver(k2_sata_pci_driver); 548 549 MODULE_AUTHOR("Benjamin Herrenschmidt"); 550 MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); 551 MODULE_LICENSE("GPL"); 552 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); 553 MODULE_VERSION(DRV_VERSION); 554