xref: /openbmc/linux/drivers/ata/sata_svw.c (revision 64c70b1c) 
1 /*
2  *  sata_svw.c - ServerWorks / Apple K2 SATA
3  *
4  *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5  *		   Jeff Garzik <jgarzik@pobox.com>
6  *  		    Please ALWAYS copy linux-ide@vger.kernel.org
7  *		    on emails.
8  *
9  *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
10  *
11  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
12  *
13  *  This driver probably works with non-Apple versions of the
14  *  Broadcom chipset...
15  *
16  *
17  *  This program is free software; you can redistribute it and/or modify
18  *  it under the terms of the GNU General Public License as published by
19  *  the Free Software Foundation; either version 2, or (at your option)
20  *  any later version.
21  *
22  *  This program is distributed in the hope that it will be useful,
23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  *  GNU General Public License for more details.
26  *
27  *  You should have received a copy of the GNU General Public License
28  *  along with this program; see the file COPYING.  If not, write to
29  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
30  *
31  *
32  *  libata documentation is available via 'make {ps|pdf}docs',
33  *  as Documentation/DocBook/libata.*
34  *
35  *  Hardware documentation available under NDA.
36  *
37  */
38 
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <linux/libata.h>
49 
50 #ifdef CONFIG_PPC_OF
51 #include <asm/prom.h>
52 #include <asm/pci-bridge.h>
53 #endif /* CONFIG_PPC_OF */
54 
55 #define DRV_NAME	"sata_svw"
56 #define DRV_VERSION	"2.2"
57 
58 enum {
59 	/* ap->flags bits */
60 	K2_FLAG_SATA_8_PORTS		= (1 << 24),
61 	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
62 
63 	/* Taskfile registers offsets */
64 	K2_SATA_TF_CMD_OFFSET		= 0x00,
65 	K2_SATA_TF_DATA_OFFSET		= 0x00,
66 	K2_SATA_TF_ERROR_OFFSET		= 0x04,
67 	K2_SATA_TF_NSECT_OFFSET		= 0x08,
68 	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
69 	K2_SATA_TF_LBAM_OFFSET		= 0x10,
70 	K2_SATA_TF_LBAH_OFFSET		= 0x14,
71 	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
72 	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
73 	K2_SATA_TF_CTL_OFFSET		= 0x20,
74 
75 	/* DMA base */
76 	K2_SATA_DMA_CMD_OFFSET		= 0x30,
77 
78 	/* SCRs base */
79 	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
80 	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
81 	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,
82 
83 	/* Others */
84 	K2_SATA_SICR1_OFFSET		= 0x80,
85 	K2_SATA_SICR2_OFFSET		= 0x84,
86 	K2_SATA_SIM_OFFSET		= 0x88,
87 
88 	/* Port stride */
89 	K2_SATA_PORT_OFFSET		= 0x100,
90 
91 	board_svw4			= 0,
92 	board_svw8			= 1,
93 };
94 
95 static u8 k2_stat_check_status(struct ata_port *ap);
96 
97 
98 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
99 {
100 	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
101 		return -1;	/* ATAPI DMA not supported */
102 
103 	return 0;
104 }
105 
106 static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
107 {
108 	if (sc_reg > SCR_CONTROL)
109 		return 0xffffffffU;
110 	return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
111 }
112 
113 
114 static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
115 			       u32 val)
116 {
117 	if (sc_reg > SCR_CONTROL)
118 		return;
119 	writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
120 }
121 
122 
123 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
124 {
125 	struct ata_ioports *ioaddr = &ap->ioaddr;
126 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
127 
128 	if (tf->ctl != ap->last_ctl) {
129 		writeb(tf->ctl, ioaddr->ctl_addr);
130 		ap->last_ctl = tf->ctl;
131 		ata_wait_idle(ap);
132 	}
133 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
134 		writew(tf->feature | (((u16)tf->hob_feature) << 8),
135 		       ioaddr->feature_addr);
136 		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
137 		       ioaddr->nsect_addr);
138 		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
139 		       ioaddr->lbal_addr);
140 		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
141 		       ioaddr->lbam_addr);
142 		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
143 		       ioaddr->lbah_addr);
144 	} else if (is_addr) {
145 		writew(tf->feature, ioaddr->feature_addr);
146 		writew(tf->nsect, ioaddr->nsect_addr);
147 		writew(tf->lbal, ioaddr->lbal_addr);
148 		writew(tf->lbam, ioaddr->lbam_addr);
149 		writew(tf->lbah, ioaddr->lbah_addr);
150 	}
151 
152 	if (tf->flags & ATA_TFLAG_DEVICE)
153 		writeb(tf->device, ioaddr->device_addr);
154 
155 	ata_wait_idle(ap);
156 }
157 
158 
159 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
160 {
161 	struct ata_ioports *ioaddr = &ap->ioaddr;
162 	u16 nsect, lbal, lbam, lbah, feature;
163 
164 	tf->command = k2_stat_check_status(ap);
165 	tf->device = readw(ioaddr->device_addr);
166 	feature = readw(ioaddr->error_addr);
167 	nsect = readw(ioaddr->nsect_addr);
168 	lbal = readw(ioaddr->lbal_addr);
169 	lbam = readw(ioaddr->lbam_addr);
170 	lbah = readw(ioaddr->lbah_addr);
171 
172 	tf->feature = feature;
173 	tf->nsect = nsect;
174 	tf->lbal = lbal;
175 	tf->lbam = lbam;
176 	tf->lbah = lbah;
177 
178 	if (tf->flags & ATA_TFLAG_LBA48) {
179 		tf->hob_feature = feature >> 8;
180 		tf->hob_nsect = nsect >> 8;
181 		tf->hob_lbal = lbal >> 8;
182 		tf->hob_lbam = lbam >> 8;
183 		tf->hob_lbah = lbah >> 8;
184         }
185 }
186 
187 /**
188  *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
189  *	@qc: Info associated with this ATA transaction.
190  *
191  *	LOCKING:
192  *	spin_lock_irqsave(host lock)
193  */
194 
195 static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
196 {
197 	struct ata_port *ap = qc->ap;
198 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
199 	u8 dmactl;
200 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
201 
202 	/* load PRD table addr. */
203 	mb();	/* make sure PRD table writes are visible to controller */
204 	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
205 
206 	/* specify data direction, triple-check start bit is clear */
207 	dmactl = readb(mmio + ATA_DMA_CMD);
208 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
209 	if (!rw)
210 		dmactl |= ATA_DMA_WR;
211 	writeb(dmactl, mmio + ATA_DMA_CMD);
212 
213 	/* issue r/w command if this is not a ATA DMA command*/
214 	if (qc->tf.protocol != ATA_PROT_DMA)
215 		ap->ops->exec_command(ap, &qc->tf);
216 }
217 
218 /**
219  *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
220  *	@qc: Info associated with this ATA transaction.
221  *
222  *	LOCKING:
223  *	spin_lock_irqsave(host lock)
224  */
225 
226 static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
227 {
228 	struct ata_port *ap = qc->ap;
229 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
230 	u8 dmactl;
231 
232 	/* start host DMA transaction */
233 	dmactl = readb(mmio + ATA_DMA_CMD);
234 	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
235 	/* There is a race condition in certain SATA controllers that can
236 	   be seen when the r/w command is given to the controller before the
237 	   host DMA is started. On a Read command, the controller would initiate
238 	   the command to the drive even before it sees the DMA start. When there
239 	   are very fast drives connected to the controller, or when the data request
240 	   hits in the drive cache, there is the possibility that the drive returns a part
241 	   or all of the requested data to the controller before the DMA start is issued.
242 	   In this case, the controller would become confused as to what to do with the data.
243 	   In the worst case when all the data is returned back to the controller, the
244 	   controller could hang. In other cases it could return partial data returning
245 	   in data corruption. This problem has been seen in PPC systems and can also appear
246 	   on an system with very fast disks, where the SATA controller is sitting behind a
247 	   number of bridges, and hence there is significant latency between the r/w command
248 	   and the start command. */
249 	/* issue r/w command if the access is to ATA*/
250 	if (qc->tf.protocol == ATA_PROT_DMA)
251 		ap->ops->exec_command(ap, &qc->tf);
252 }
253 
254 
255 static u8 k2_stat_check_status(struct ata_port *ap)
256 {
257        	return readl(ap->ioaddr.status_addr);
258 }
259 
260 #ifdef CONFIG_PPC_OF
261 /*
262  * k2_sata_proc_info
263  * inout : decides on the direction of the dataflow and the meaning of the
264  *	   variables
265  * buffer: If inout==FALSE data is being written to it else read from it
266  * *start: If inout==FALSE start of the valid data in the buffer
267  * offset: If inout==FALSE offset from the beginning of the imaginary file
268  *	   from which we start writing into the buffer
269  * length: If inout==FALSE max number of bytes to be written into the buffer
270  *	   else number of bytes in the buffer
271  */
272 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
273 			     off_t offset, int count, int inout)
274 {
275 	struct ata_port *ap;
276 	struct device_node *np;
277 	int len, index;
278 
279 	/* Find  the ata_port */
280 	ap = ata_shost_to_port(shost);
281 	if (ap == NULL)
282 		return 0;
283 
284 	/* Find the OF node for the PCI device proper */
285 	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
286 	if (np == NULL)
287 		return 0;
288 
289 	/* Match it to a port node */
290 	index = (ap == ap->host->ports[0]) ? 0 : 1;
291 	for (np = np->child; np != NULL; np = np->sibling) {
292 		const u32 *reg = of_get_property(np, "reg", NULL);
293 		if (!reg)
294 			continue;
295 		if (index == *reg)
296 			break;
297 	}
298 	if (np == NULL)
299 		return 0;
300 
301 	len = sprintf(page, "devspec: %s\n", np->full_name);
302 
303 	return len;
304 }
305 #endif /* CONFIG_PPC_OF */
306 
307 
308 static struct scsi_host_template k2_sata_sht = {
309 	.module			= THIS_MODULE,
310 	.name			= DRV_NAME,
311 	.ioctl			= ata_scsi_ioctl,
312 	.queuecommand		= ata_scsi_queuecmd,
313 	.can_queue		= ATA_DEF_QUEUE,
314 	.this_id		= ATA_SHT_THIS_ID,
315 	.sg_tablesize		= LIBATA_MAX_PRD,
316 	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
317 	.emulated		= ATA_SHT_EMULATED,
318 	.use_clustering		= ATA_SHT_USE_CLUSTERING,
319 	.proc_name		= DRV_NAME,
320 	.dma_boundary		= ATA_DMA_BOUNDARY,
321 	.slave_configure	= ata_scsi_slave_config,
322 	.slave_destroy		= ata_scsi_slave_destroy,
323 #ifdef CONFIG_PPC_OF
324 	.proc_info		= k2_sata_proc_info,
325 #endif
326 	.bios_param		= ata_std_bios_param,
327 };
328 
329 
330 static const struct ata_port_operations k2_sata_ops = {
331 	.port_disable		= ata_port_disable,
332 	.tf_load		= k2_sata_tf_load,
333 	.tf_read		= k2_sata_tf_read,
334 	.check_status		= k2_stat_check_status,
335 	.exec_command		= ata_exec_command,
336 	.dev_select		= ata_std_dev_select,
337 	.check_atapi_dma	= k2_sata_check_atapi_dma,
338 	.bmdma_setup		= k2_bmdma_setup_mmio,
339 	.bmdma_start		= k2_bmdma_start_mmio,
340 	.bmdma_stop		= ata_bmdma_stop,
341 	.bmdma_status		= ata_bmdma_status,
342 	.qc_prep		= ata_qc_prep,
343 	.qc_issue		= ata_qc_issue_prot,
344 	.data_xfer		= ata_data_xfer,
345 	.freeze			= ata_bmdma_freeze,
346 	.thaw			= ata_bmdma_thaw,
347 	.error_handler		= ata_bmdma_error_handler,
348 	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
349 	.irq_clear		= ata_bmdma_irq_clear,
350 	.irq_on			= ata_irq_on,
351 	.irq_ack		= ata_irq_ack,
352 	.scr_read		= k2_sata_scr_read,
353 	.scr_write		= k2_sata_scr_write,
354 	.port_start		= ata_port_start,
355 };
356 
357 static const struct ata_port_info k2_port_info[] = {
358 	/* board_svw4 */
359 	{
360 		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
361 				  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
362 		.pio_mask	= 0x1f,
363 		.mwdma_mask	= 0x07,
364 		.udma_mask	= ATA_UDMA6,
365 		.port_ops	= &k2_sata_ops,
366 	},
367 	/* board_svw8 */
368 	{
369 		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
370 				  ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
371 				  K2_FLAG_SATA_8_PORTS,
372 		.pio_mask	= 0x1f,
373 		.mwdma_mask	= 0x07,
374 		.udma_mask	= ATA_UDMA6,
375 		.port_ops	= &k2_sata_ops,
376 	},
377 };
378 
379 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
380 {
381 	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
382 	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
383 	port->feature_addr	=
384 	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
385 	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
386 	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
387 	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
388 	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
389 	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
390 	port->command_addr	=
391 	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
392 	port->altstatus_addr	=
393 	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
394 	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
395 	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
396 }
397 
398 
399 static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
400 {
401 	static int printed_version;
402 	const struct ata_port_info *ppi[] =
403 		{ &k2_port_info[ent->driver_data], NULL };
404 	struct ata_host *host;
405 	void __iomem *mmio_base;
406 	int n_ports, i, rc;
407 
408 	if (!printed_version++)
409 		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
410 
411 	/* allocate host */
412 	n_ports = 4;
413 	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
414 		n_ports = 8;
415 
416 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
417 	if (!host)
418 		return -ENOMEM;
419 
420 	/*
421 	 * If this driver happens to only be useful on Apple's K2, then
422 	 * we should check that here as it has a normal Serverworks ID
423 	 */
424 	rc = pcim_enable_device(pdev);
425 	if (rc)
426 		return rc;
427 
428 	/*
429 	 * Check if we have resources mapped at all (second function may
430 	 * have been disabled by firmware)
431 	 */
432 	if (pci_resource_len(pdev, 5) == 0)
433 		return -ENODEV;
434 
435 	/* Request and iomap PCI regions */
436 	rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
437 	if (rc == -EBUSY)
438 		pcim_pin_device(pdev);
439 	if (rc)
440 		return rc;
441 	host->iomap = pcim_iomap_table(pdev);
442 	mmio_base = host->iomap[5];
443 
444 	/* different controllers have different number of ports - currently 4 or 8 */
445 	/* All ports are on the same function. Multi-function device is no
446 	 * longer available. This should not be seen in any system. */
447 	for (i = 0; i < host->n_ports; i++)
448 		k2_sata_setup_port(&host->ports[i]->ioaddr,
449 				   mmio_base + i * K2_SATA_PORT_OFFSET);
450 
451 	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
452 	if (rc)
453 		return rc;
454 	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
455 	if (rc)
456 		return rc;
457 
458 	/* Clear a magic bit in SCR1 according to Darwin, those help
459 	 * some funky seagate drives (though so far, those were already
460 	 * set by the firmware on the machines I had access to)
461 	 */
462 	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
463 	       mmio_base + K2_SATA_SICR1_OFFSET);
464 
465 	/* Clear SATA error & interrupts we don't use */
466 	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
467 	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
468 
469 	pci_set_master(pdev);
470 	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
471 				 &k2_sata_sht);
472 }
473 
474 /* 0x240 is device ID for Apple K2 device
475  * 0x241 is device ID for Serverworks Frodo4
476  * 0x242 is device ID for Serverworks Frodo8
477  * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
478  * controller
479  * */
480 static const struct pci_device_id k2_sata_pci_tbl[] = {
481 	{ PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 },
482 	{ PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 },
483 	{ PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 },
484 	{ PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 },
485 	{ PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 },
486 
487 	{ }
488 };
489 
490 static struct pci_driver k2_sata_pci_driver = {
491 	.name			= DRV_NAME,
492 	.id_table		= k2_sata_pci_tbl,
493 	.probe			= k2_sata_init_one,
494 	.remove			= ata_pci_remove_one,
495 };
496 
497 static int __init k2_sata_init(void)
498 {
499 	return pci_register_driver(&k2_sata_pci_driver);
500 }
501 
502 static void __exit k2_sata_exit(void)
503 {
504 	pci_unregister_driver(&k2_sata_pci_driver);
505 }
506 
507 MODULE_AUTHOR("Benjamin Herrenschmidt");
508 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
509 MODULE_LICENSE("GPL");
510 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
511 MODULE_VERSION(DRV_VERSION);
512 
513 module_init(k2_sata_init);
514 module_exit(k2_sata_exit);
515