1 /* 2 * sata_svw.c - ServerWorks / Apple K2 SATA 3 * 4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and 5 * Jeff Garzik <jgarzik@pobox.com> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 10 * 11 * Bits from Jeff Garzik, Copyright RedHat, Inc. 12 * 13 * This driver probably works with non-Apple versions of the 14 * Broadcom chipset... 15 * 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; see the file COPYING. If not, write to 29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 * 32 * libata documentation is available via 'make {ps|pdf}docs', 33 * as Documentation/DocBook/libata.* 34 * 35 * Hardware documentation available under NDA. 36 * 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/pci.h> 42 #include <linux/init.h> 43 #include <linux/blkdev.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/device.h> 47 #include <scsi/scsi_host.h> 48 #include <scsi/scsi_cmnd.h> 49 #include <scsi/scsi.h> 50 #include <linux/libata.h> 51 52 #ifdef CONFIG_PPC_OF 53 #include <asm/prom.h> 54 #include <asm/pci-bridge.h> 55 #endif /* CONFIG_PPC_OF */ 56 57 #define DRV_NAME "sata_svw" 58 #define DRV_VERSION "2.3" 59 60 enum { 61 /* ap->flags bits */ 62 K2_FLAG_SATA_8_PORTS = (1 << 24), 63 K2_FLAG_NO_ATAPI_DMA = (1 << 25), 64 K2_FLAG_BAR_POS_3 = (1 << 26), 65 66 /* Taskfile registers offsets */ 67 K2_SATA_TF_CMD_OFFSET = 0x00, 68 K2_SATA_TF_DATA_OFFSET = 0x00, 69 K2_SATA_TF_ERROR_OFFSET = 0x04, 70 K2_SATA_TF_NSECT_OFFSET = 0x08, 71 K2_SATA_TF_LBAL_OFFSET = 0x0c, 72 K2_SATA_TF_LBAM_OFFSET = 0x10, 73 K2_SATA_TF_LBAH_OFFSET = 0x14, 74 K2_SATA_TF_DEVICE_OFFSET = 0x18, 75 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, 76 K2_SATA_TF_CTL_OFFSET = 0x20, 77 78 /* DMA base */ 79 K2_SATA_DMA_CMD_OFFSET = 0x30, 80 81 /* SCRs base */ 82 K2_SATA_SCR_STATUS_OFFSET = 0x40, 83 K2_SATA_SCR_ERROR_OFFSET = 0x44, 84 K2_SATA_SCR_CONTROL_OFFSET = 0x48, 85 86 /* Others */ 87 K2_SATA_SICR1_OFFSET = 0x80, 88 K2_SATA_SICR2_OFFSET = 0x84, 89 K2_SATA_SIM_OFFSET = 0x88, 90 91 /* Port stride */ 92 K2_SATA_PORT_OFFSET = 0x100, 93 94 chip_svw4 = 0, 95 chip_svw8 = 1, 96 chip_svw42 = 2, /* bar 3 */ 97 chip_svw43 = 3, /* bar 5 */ 98 }; 99 100 static u8 k2_stat_check_status(struct ata_port *ap); 101 102 103 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) 104 { 105 u8 cmnd = qc->scsicmd->cmnd[0]; 106 107 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) 108 return -1; /* ATAPI DMA not supported */ 109 else { 110 switch (cmnd) { 111 case READ_10: 112 case READ_12: 113 case READ_16: 114 case WRITE_10: 115 case WRITE_12: 116 case WRITE_16: 117 return 0; 118 119 default: 120 return -1; 121 } 122 123 } 124 } 125 126 static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 127 { 128 if (sc_reg > SCR_CONTROL) 129 return -EINVAL; 130 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 131 return 0; 132 } 133 134 135 static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 136 { 137 if (sc_reg > SCR_CONTROL) 138 return -EINVAL; 139 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 140 return 0; 141 } 142 143 144 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 145 { 146 struct ata_ioports *ioaddr = &ap->ioaddr; 147 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 148 149 if (tf->ctl != ap->last_ctl) { 150 writeb(tf->ctl, ioaddr->ctl_addr); 151 ap->last_ctl = tf->ctl; 152 ata_wait_idle(ap); 153 } 154 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 155 writew(tf->feature | (((u16)tf->hob_feature) << 8), 156 ioaddr->feature_addr); 157 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), 158 ioaddr->nsect_addr); 159 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), 160 ioaddr->lbal_addr); 161 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), 162 ioaddr->lbam_addr); 163 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), 164 ioaddr->lbah_addr); 165 } else if (is_addr) { 166 writew(tf->feature, ioaddr->feature_addr); 167 writew(tf->nsect, ioaddr->nsect_addr); 168 writew(tf->lbal, ioaddr->lbal_addr); 169 writew(tf->lbam, ioaddr->lbam_addr); 170 writew(tf->lbah, ioaddr->lbah_addr); 171 } 172 173 if (tf->flags & ATA_TFLAG_DEVICE) 174 writeb(tf->device, ioaddr->device_addr); 175 176 ata_wait_idle(ap); 177 } 178 179 180 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 181 { 182 struct ata_ioports *ioaddr = &ap->ioaddr; 183 u16 nsect, lbal, lbam, lbah, feature; 184 185 tf->command = k2_stat_check_status(ap); 186 tf->device = readw(ioaddr->device_addr); 187 feature = readw(ioaddr->error_addr); 188 nsect = readw(ioaddr->nsect_addr); 189 lbal = readw(ioaddr->lbal_addr); 190 lbam = readw(ioaddr->lbam_addr); 191 lbah = readw(ioaddr->lbah_addr); 192 193 tf->feature = feature; 194 tf->nsect = nsect; 195 tf->lbal = lbal; 196 tf->lbam = lbam; 197 tf->lbah = lbah; 198 199 if (tf->flags & ATA_TFLAG_LBA48) { 200 tf->hob_feature = feature >> 8; 201 tf->hob_nsect = nsect >> 8; 202 tf->hob_lbal = lbal >> 8; 203 tf->hob_lbam = lbam >> 8; 204 tf->hob_lbah = lbah >> 8; 205 } 206 } 207 208 /** 209 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) 210 * @qc: Info associated with this ATA transaction. 211 * 212 * LOCKING: 213 * spin_lock_irqsave(host lock) 214 */ 215 216 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) 217 { 218 struct ata_port *ap = qc->ap; 219 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 220 u8 dmactl; 221 void __iomem *mmio = ap->ioaddr.bmdma_addr; 222 223 /* load PRD table addr. */ 224 mb(); /* make sure PRD table writes are visible to controller */ 225 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); 226 227 /* specify data direction, triple-check start bit is clear */ 228 dmactl = readb(mmio + ATA_DMA_CMD); 229 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 230 if (!rw) 231 dmactl |= ATA_DMA_WR; 232 writeb(dmactl, mmio + ATA_DMA_CMD); 233 234 /* issue r/w command if this is not a ATA DMA command*/ 235 if (qc->tf.protocol != ATA_PROT_DMA) 236 ap->ops->sff_exec_command(ap, &qc->tf); 237 } 238 239 /** 240 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) 241 * @qc: Info associated with this ATA transaction. 242 * 243 * LOCKING: 244 * spin_lock_irqsave(host lock) 245 */ 246 247 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) 248 { 249 struct ata_port *ap = qc->ap; 250 void __iomem *mmio = ap->ioaddr.bmdma_addr; 251 u8 dmactl; 252 253 /* start host DMA transaction */ 254 dmactl = readb(mmio + ATA_DMA_CMD); 255 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); 256 /* This works around possible data corruption. 257 258 On certain SATA controllers that can be seen when the r/w 259 command is given to the controller before the host DMA is 260 started. 261 262 On a Read command, the controller would initiate the 263 command to the drive even before it sees the DMA 264 start. When there are very fast drives connected to the 265 controller, or when the data request hits in the drive 266 cache, there is the possibility that the drive returns a 267 part or all of the requested data to the controller before 268 the DMA start is issued. In this case, the controller 269 would become confused as to what to do with the data. In 270 the worst case when all the data is returned back to the 271 controller, the controller could hang. In other cases it 272 could return partial data returning in data 273 corruption. This problem has been seen in PPC systems and 274 can also appear on an system with very fast disks, where 275 the SATA controller is sitting behind a number of bridges, 276 and hence there is significant latency between the r/w 277 command and the start command. */ 278 /* issue r/w command if the access is to ATA */ 279 if (qc->tf.protocol == ATA_PROT_DMA) 280 ap->ops->sff_exec_command(ap, &qc->tf); 281 } 282 283 284 static u8 k2_stat_check_status(struct ata_port *ap) 285 { 286 return readl(ap->ioaddr.status_addr); 287 } 288 289 #ifdef CONFIG_PPC_OF 290 /* 291 * k2_sata_proc_info 292 * inout : decides on the direction of the dataflow and the meaning of the 293 * variables 294 * buffer: If inout==FALSE data is being written to it else read from it 295 * *start: If inout==FALSE start of the valid data in the buffer 296 * offset: If inout==FALSE offset from the beginning of the imaginary file 297 * from which we start writing into the buffer 298 * length: If inout==FALSE max number of bytes to be written into the buffer 299 * else number of bytes in the buffer 300 */ 301 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, 302 off_t offset, int count, int inout) 303 { 304 struct ata_port *ap; 305 struct device_node *np; 306 int len, index; 307 308 /* Find the ata_port */ 309 ap = ata_shost_to_port(shost); 310 if (ap == NULL) 311 return 0; 312 313 /* Find the OF node for the PCI device proper */ 314 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); 315 if (np == NULL) 316 return 0; 317 318 /* Match it to a port node */ 319 index = (ap == ap->host->ports[0]) ? 0 : 1; 320 for (np = np->child; np != NULL; np = np->sibling) { 321 const u32 *reg = of_get_property(np, "reg", NULL); 322 if (!reg) 323 continue; 324 if (index == *reg) 325 break; 326 } 327 if (np == NULL) 328 return 0; 329 330 len = sprintf(page, "devspec: %s\n", np->full_name); 331 332 return len; 333 } 334 #endif /* CONFIG_PPC_OF */ 335 336 337 static struct scsi_host_template k2_sata_sht = { 338 ATA_BMDMA_SHT(DRV_NAME), 339 #ifdef CONFIG_PPC_OF 340 .proc_info = k2_sata_proc_info, 341 #endif 342 }; 343 344 345 static struct ata_port_operations k2_sata_ops = { 346 .inherits = &ata_bmdma_port_ops, 347 .sff_tf_load = k2_sata_tf_load, 348 .sff_tf_read = k2_sata_tf_read, 349 .sff_check_status = k2_stat_check_status, 350 .check_atapi_dma = k2_sata_check_atapi_dma, 351 .bmdma_setup = k2_bmdma_setup_mmio, 352 .bmdma_start = k2_bmdma_start_mmio, 353 .scr_read = k2_sata_scr_read, 354 .scr_write = k2_sata_scr_write, 355 }; 356 357 static const struct ata_port_info k2_port_info[] = { 358 /* chip_svw4 */ 359 { 360 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 361 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA, 362 .pio_mask = 0x1f, 363 .mwdma_mask = 0x07, 364 .udma_mask = ATA_UDMA6, 365 .port_ops = &k2_sata_ops, 366 }, 367 /* chip_svw8 */ 368 { 369 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 370 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA | 371 K2_FLAG_SATA_8_PORTS, 372 .pio_mask = 0x1f, 373 .mwdma_mask = 0x07, 374 .udma_mask = ATA_UDMA6, 375 .port_ops = &k2_sata_ops, 376 }, 377 /* chip_svw42 */ 378 { 379 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 380 ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3, 381 .pio_mask = 0x1f, 382 .mwdma_mask = 0x07, 383 .udma_mask = ATA_UDMA6, 384 .port_ops = &k2_sata_ops, 385 }, 386 /* chip_svw43 */ 387 { 388 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 389 ATA_FLAG_MMIO, 390 .pio_mask = 0x1f, 391 .mwdma_mask = 0x07, 392 .udma_mask = ATA_UDMA6, 393 .port_ops = &k2_sata_ops, 394 }, 395 }; 396 397 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) 398 { 399 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; 400 port->data_addr = base + K2_SATA_TF_DATA_OFFSET; 401 port->feature_addr = 402 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; 403 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; 404 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; 405 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; 406 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; 407 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; 408 port->command_addr = 409 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; 410 port->altstatus_addr = 411 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; 412 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; 413 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; 414 } 415 416 417 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 418 { 419 static int printed_version; 420 const struct ata_port_info *ppi[] = 421 { &k2_port_info[ent->driver_data], NULL }; 422 struct ata_host *host; 423 void __iomem *mmio_base; 424 int n_ports, i, rc, bar_pos; 425 426 if (!printed_version++) 427 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 428 429 /* allocate host */ 430 n_ports = 4; 431 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) 432 n_ports = 8; 433 434 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 435 if (!host) 436 return -ENOMEM; 437 438 bar_pos = 5; 439 if (ppi[0]->flags & K2_FLAG_BAR_POS_3) 440 bar_pos = 3; 441 /* 442 * If this driver happens to only be useful on Apple's K2, then 443 * we should check that here as it has a normal Serverworks ID 444 */ 445 rc = pcim_enable_device(pdev); 446 if (rc) 447 return rc; 448 449 /* 450 * Check if we have resources mapped at all (second function may 451 * have been disabled by firmware) 452 */ 453 if (pci_resource_len(pdev, bar_pos) == 0) { 454 /* In IDE mode we need to pin the device to ensure that 455 pcim_release does not clear the busmaster bit in config 456 space, clearing causes busmaster DMA to fail on 457 ports 3 & 4 */ 458 pcim_pin_device(pdev); 459 return -ENODEV; 460 } 461 462 /* Request and iomap PCI regions */ 463 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); 464 if (rc == -EBUSY) 465 pcim_pin_device(pdev); 466 if (rc) 467 return rc; 468 host->iomap = pcim_iomap_table(pdev); 469 mmio_base = host->iomap[bar_pos]; 470 471 /* different controllers have different number of ports - currently 4 or 8 */ 472 /* All ports are on the same function. Multi-function device is no 473 * longer available. This should not be seen in any system. */ 474 for (i = 0; i < host->n_ports; i++) { 475 struct ata_port *ap = host->ports[i]; 476 unsigned int offset = i * K2_SATA_PORT_OFFSET; 477 478 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); 479 480 ata_port_pbar_desc(ap, 5, -1, "mmio"); 481 ata_port_pbar_desc(ap, 5, offset, "port"); 482 } 483 484 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 485 if (rc) 486 return rc; 487 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 488 if (rc) 489 return rc; 490 491 /* Clear a magic bit in SCR1 according to Darwin, those help 492 * some funky seagate drives (though so far, those were already 493 * set by the firmware on the machines I had access to) 494 */ 495 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, 496 mmio_base + K2_SATA_SICR1_OFFSET); 497 498 /* Clear SATA error & interrupts we don't use */ 499 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); 500 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); 501 502 pci_set_master(pdev); 503 return ata_host_activate(host, pdev->irq, ata_sff_interrupt, 504 IRQF_SHARED, &k2_sata_sht); 505 } 506 507 /* 0x240 is device ID for Apple K2 device 508 * 0x241 is device ID for Serverworks Frodo4 509 * 0x242 is device ID for Serverworks Frodo8 510 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA 511 * controller 512 * */ 513 static const struct pci_device_id k2_sata_pci_tbl[] = { 514 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, 515 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, 516 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, 517 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, 518 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, 519 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, 520 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, 521 522 { } 523 }; 524 525 static struct pci_driver k2_sata_pci_driver = { 526 .name = DRV_NAME, 527 .id_table = k2_sata_pci_tbl, 528 .probe = k2_sata_init_one, 529 .remove = ata_pci_remove_one, 530 }; 531 532 static int __init k2_sata_init(void) 533 { 534 return pci_register_driver(&k2_sata_pci_driver); 535 } 536 537 static void __exit k2_sata_exit(void) 538 { 539 pci_unregister_driver(&k2_sata_pci_driver); 540 } 541 542 MODULE_AUTHOR("Benjamin Herrenschmidt"); 543 MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); 544 MODULE_LICENSE("GPL"); 545 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); 546 MODULE_VERSION(DRV_VERSION); 547 548 module_init(k2_sata_init); 549 module_exit(k2_sata_exit); 550