1 /* 2 * sata_sis.c - Silicon Integrated Systems SATA 3 * 4 * Maintained by: Uwe Koziolek 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004 Uwe Koziolek 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * Hardware documentation available under NDA. 30 * 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/init.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/device.h> 41 #include <scsi/scsi_host.h> 42 #include <linux/libata.h> 43 #include "sis.h" 44 45 #define DRV_NAME "sata_sis" 46 #define DRV_VERSION "1.0" 47 48 enum { 49 sis_180 = 0, 50 SIS_SCR_PCI_BAR = 5, 51 52 /* PCI configuration registers */ 53 SIS_GENCTL = 0x54, /* IDE General Control register */ 54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ 55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ 56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ 57 SIS_PMR = 0x90, /* port mapping register */ 58 SIS_PMR_COMBINED = 0x30, 59 60 /* random bits */ 61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ 62 63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ 64 }; 65 66 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 67 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 68 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 69 70 static const struct pci_device_id sis_pci_tbl[] = { 71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ 72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ 73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ 74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ 75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */ 76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */ 77 78 { } /* terminate list */ 79 }; 80 81 static struct pci_driver sis_pci_driver = { 82 .name = DRV_NAME, 83 .id_table = sis_pci_tbl, 84 .probe = sis_init_one, 85 .remove = ata_pci_remove_one, 86 #ifdef CONFIG_PM 87 .suspend = ata_pci_device_suspend, 88 .resume = ata_pci_device_resume, 89 #endif 90 }; 91 92 static struct scsi_host_template sis_sht = { 93 ATA_BMDMA_SHT(DRV_NAME), 94 }; 95 96 static struct ata_port_operations sis_ops = { 97 .inherits = &ata_bmdma_port_ops, 98 .scr_read = sis_scr_read, 99 .scr_write = sis_scr_write, 100 }; 101 102 static const struct ata_port_info sis_port_info = { 103 .flags = ATA_FLAG_SATA, 104 .pio_mask = ATA_PIO4, 105 .mwdma_mask = ATA_MWDMA2, 106 .udma_mask = ATA_UDMA6, 107 .port_ops = &sis_ops, 108 }; 109 110 MODULE_AUTHOR("Uwe Koziolek"); 111 MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller"); 112 MODULE_LICENSE("GPL"); 113 MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 114 MODULE_VERSION(DRV_VERSION); 115 116 static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg) 117 { 118 struct ata_port *ap = link->ap; 119 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 120 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); 121 u8 pmr; 122 123 if (ap->port_no) { 124 switch (pdev->device) { 125 case 0x0180: 126 case 0x0181: 127 pci_read_config_byte(pdev, SIS_PMR, &pmr); 128 if ((pmr & SIS_PMR_COMBINED) == 0) 129 addr += SIS180_SATA1_OFS; 130 break; 131 132 case 0x0182: 133 case 0x0183: 134 case 0x1182: 135 addr += SIS182_SATA1_OFS; 136 break; 137 } 138 } 139 if (link->pmp) 140 addr += 0x10; 141 142 return addr; 143 } 144 145 static u32 sis_scr_cfg_read(struct ata_link *link, 146 unsigned int sc_reg, u32 *val) 147 { 148 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 149 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); 150 151 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ 152 return -EINVAL; 153 154 pci_read_config_dword(pdev, cfg_addr, val); 155 return 0; 156 } 157 158 static int sis_scr_cfg_write(struct ata_link *link, 159 unsigned int sc_reg, u32 val) 160 { 161 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 162 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); 163 164 pci_write_config_dword(pdev, cfg_addr, val); 165 return 0; 166 } 167 168 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 169 { 170 struct ata_port *ap = link->ap; 171 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; 172 173 if (sc_reg > SCR_CONTROL) 174 return -EINVAL; 175 176 if (ap->flags & SIS_FLAG_CFGSCR) 177 return sis_scr_cfg_read(link, sc_reg, val); 178 179 *val = ioread32(base + sc_reg * 4); 180 return 0; 181 } 182 183 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 184 { 185 struct ata_port *ap = link->ap; 186 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; 187 188 if (sc_reg > SCR_CONTROL) 189 return -EINVAL; 190 191 if (ap->flags & SIS_FLAG_CFGSCR) 192 return sis_scr_cfg_write(link, sc_reg, val); 193 194 iowrite32(val, base + (sc_reg * 4)); 195 return 0; 196 } 197 198 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 199 { 200 struct ata_port_info pi = sis_port_info; 201 const struct ata_port_info *ppi[] = { &pi, &pi }; 202 struct ata_host *host; 203 u32 genctl, val; 204 u8 pmr; 205 u8 port2_start = 0x20; 206 int i, rc; 207 208 ata_print_version_once(&pdev->dev, DRV_VERSION); 209 210 rc = pcim_enable_device(pdev); 211 if (rc) 212 return rc; 213 214 /* check and see if the SCRs are in IO space or PCI cfg space */ 215 pci_read_config_dword(pdev, SIS_GENCTL, &genctl); 216 if ((genctl & GENCTL_IOMAPPED_SCR) == 0) 217 pi.flags |= SIS_FLAG_CFGSCR; 218 219 /* if hardware thinks SCRs are in IO space, but there are 220 * no IO resources assigned, change to PCI cfg space. 221 */ 222 if ((!(pi.flags & SIS_FLAG_CFGSCR)) && 223 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || 224 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { 225 genctl &= ~GENCTL_IOMAPPED_SCR; 226 pci_write_config_dword(pdev, SIS_GENCTL, genctl); 227 pi.flags |= SIS_FLAG_CFGSCR; 228 } 229 230 pci_read_config_byte(pdev, SIS_PMR, &pmr); 231 switch (ent->device) { 232 case 0x0180: 233 case 0x0181: 234 235 /* The PATA-handling is provided by pata_sis */ 236 switch (pmr & 0x30) { 237 case 0x10: 238 ppi[1] = &sis_info133_for_sata; 239 break; 240 241 case 0x30: 242 ppi[0] = &sis_info133_for_sata; 243 break; 244 } 245 if ((pmr & SIS_PMR_COMBINED) == 0) { 246 dev_info(&pdev->dev, 247 "Detected SiS 180/181/964 chipset in SATA mode\n"); 248 port2_start = 64; 249 } else { 250 dev_info(&pdev->dev, 251 "Detected SiS 180/181 chipset in combined mode\n"); 252 port2_start = 0; 253 pi.flags |= ATA_FLAG_SLAVE_POSS; 254 } 255 break; 256 257 case 0x0182: 258 case 0x0183: 259 pci_read_config_dword(pdev, 0x6C, &val); 260 if (val & (1L << 31)) { 261 dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n"); 262 pi.flags |= ATA_FLAG_SLAVE_POSS; 263 } else { 264 dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n"); 265 } 266 break; 267 268 case 0x1182: 269 dev_info(&pdev->dev, 270 "Detected SiS 1182/966/680 SATA controller\n"); 271 pi.flags |= ATA_FLAG_SLAVE_POSS; 272 break; 273 274 case 0x1183: 275 dev_info(&pdev->dev, 276 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); 277 ppi[0] = &sis_info133_for_sata; 278 ppi[1] = &sis_info133_for_sata; 279 break; 280 } 281 282 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 283 if (rc) 284 return rc; 285 286 for (i = 0; i < 2; i++) { 287 struct ata_port *ap = host->ports[i]; 288 289 if (ap->flags & ATA_FLAG_SATA && 290 ap->flags & ATA_FLAG_SLAVE_POSS) { 291 rc = ata_slave_link_init(ap); 292 if (rc) 293 return rc; 294 } 295 } 296 297 if (!(pi.flags & SIS_FLAG_CFGSCR)) { 298 void __iomem *mmio; 299 300 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); 301 if (rc) 302 return rc; 303 mmio = host->iomap[SIS_SCR_PCI_BAR]; 304 305 host->ports[0]->ioaddr.scr_addr = mmio; 306 host->ports[1]->ioaddr.scr_addr = mmio + port2_start; 307 } 308 309 pci_set_master(pdev); 310 pci_intx(pdev, 1); 311 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 312 IRQF_SHARED, &sis_sht); 313 } 314 315 module_pci_driver(sis_pci_driver); 316