1 /* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 32 #define DRV_NAME "sata_sil24" 33 #define DRV_VERSION "1.1" 34 35 /* 36 * Port request block (PRB) 32 bytes 37 */ 38 struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43 }; 44 45 /* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48 struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52 }; 53 54 55 enum { 56 SIL24_HOST_BAR = 0, 57 SIL24_PORT_BAR = 2, 58 59 /* sil24 fetches in chunks of 64bytes. The first block 60 * contains the PRB and two SGEs. From the second block, it's 61 * consisted of four SGEs and called SGT. Calculate the 62 * number of SGTs that fit into one page. 63 */ 64 SIL24_PRB_SZ = sizeof(struct sil24_prb) 65 + 2 * sizeof(struct sil24_sge), 66 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) 67 / (4 * sizeof(struct sil24_sge)), 68 69 /* This will give us one unused SGEs for ATA. This extra SGE 70 * will be used to store CDB for ATAPI devices. 71 */ 72 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, 73 74 /* 75 * Global controller registers (128 bytes @ BAR0) 76 */ 77 /* 32 bit regs */ 78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 79 HOST_CTRL = 0x40, 80 HOST_IRQ_STAT = 0x44, 81 HOST_PHY_CFG = 0x48, 82 HOST_BIST_CTRL = 0x50, 83 HOST_BIST_PTRN = 0x54, 84 HOST_BIST_STAT = 0x58, 85 HOST_MEM_BIST_STAT = 0x5c, 86 HOST_FLASH_CMD = 0x70, 87 /* 8 bit regs */ 88 HOST_FLASH_DATA = 0x74, 89 HOST_TRANSITION_DETECT = 0x75, 90 HOST_GPIO_CTRL = 0x76, 91 HOST_I2C_ADDR = 0x78, /* 32 bit */ 92 HOST_I2C_DATA = 0x7c, 93 HOST_I2C_XFER_CNT = 0x7e, 94 HOST_I2C_CTRL = 0x7f, 95 96 /* HOST_SLOT_STAT bits */ 97 HOST_SSTAT_ATTN = (1 << 31), 98 99 /* HOST_CTRL bits */ 100 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 101 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 102 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 103 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 104 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 105 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 106 107 /* 108 * Port registers 109 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 110 */ 111 PORT_REGS_SIZE = 0x2000, 112 113 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 114 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 115 116 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 117 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 118 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 119 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 120 121 /* 32 bit regs */ 122 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 123 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 124 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 125 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 126 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 127 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 128 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 129 PORT_CMD_ERR = 0x1024, /* command error number */ 130 PORT_FIS_CFG = 0x1028, 131 PORT_FIFO_THRES = 0x102c, 132 /* 16 bit regs */ 133 PORT_DECODE_ERR_CNT = 0x1040, 134 PORT_DECODE_ERR_THRESH = 0x1042, 135 PORT_CRC_ERR_CNT = 0x1044, 136 PORT_CRC_ERR_THRESH = 0x1046, 137 PORT_HSHK_ERR_CNT = 0x1048, 138 PORT_HSHK_ERR_THRESH = 0x104a, 139 /* 32 bit regs */ 140 PORT_PHY_CFG = 0x1050, 141 PORT_SLOT_STAT = 0x1800, 142 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 143 PORT_CONTEXT = 0x1e04, 144 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 145 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 146 PORT_SCONTROL = 0x1f00, 147 PORT_SSTATUS = 0x1f04, 148 PORT_SERROR = 0x1f08, 149 PORT_SACTIVE = 0x1f0c, 150 151 /* PORT_CTRL_STAT bits */ 152 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 153 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 154 PORT_CS_INIT = (1 << 2), /* port initialize */ 155 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 156 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 157 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 158 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 159 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 160 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 161 162 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 163 /* bits[11:0] are masked */ 164 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 165 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 166 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 167 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 168 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 169 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 170 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 171 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 172 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 173 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 174 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 175 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 176 177 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 178 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 179 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 180 181 /* bits[27:16] are unmasked (raw) */ 182 PORT_IRQ_RAW_SHIFT = 16, 183 PORT_IRQ_MASKED_MASK = 0x7ff, 184 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 185 186 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 187 PORT_IRQ_STEER_SHIFT = 30, 188 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 189 190 /* PORT_CMD_ERR constants */ 191 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 192 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 193 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 194 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 195 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 196 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 197 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 198 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 199 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 200 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 201 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 202 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 203 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 204 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 205 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 206 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 207 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 208 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 209 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 210 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 211 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 212 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 213 214 /* bits of PRB control field */ 215 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 216 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 217 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 218 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 219 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 220 221 /* PRB protocol field */ 222 PRB_PROT_PACKET = (1 << 0), 223 PRB_PROT_TCQ = (1 << 1), 224 PRB_PROT_NCQ = (1 << 2), 225 PRB_PROT_READ = (1 << 3), 226 PRB_PROT_WRITE = (1 << 4), 227 PRB_PROT_TRANSPARENT = (1 << 5), 228 229 /* 230 * Other constants 231 */ 232 SGE_TRM = (1 << 31), /* Last SGE in chain */ 233 SGE_LNK = (1 << 30), /* linked list 234 Points to SGT, not SGE */ 235 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 236 data address ignored */ 237 238 SIL24_MAX_CMDS = 31, 239 240 /* board id */ 241 BID_SIL3124 = 0, 242 BID_SIL3132 = 1, 243 BID_SIL3131 = 2, 244 245 /* host flags */ 246 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 247 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 248 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | 249 ATA_FLAG_AN | ATA_FLAG_PMP, 250 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 251 252 IRQ_STAT_4PORTS = 0xf, 253 }; 254 255 struct sil24_ata_block { 256 struct sil24_prb prb; 257 struct sil24_sge sge[SIL24_MAX_SGE]; 258 }; 259 260 struct sil24_atapi_block { 261 struct sil24_prb prb; 262 u8 cdb[16]; 263 struct sil24_sge sge[SIL24_MAX_SGE]; 264 }; 265 266 union sil24_cmd_block { 267 struct sil24_ata_block ata; 268 struct sil24_atapi_block atapi; 269 }; 270 271 static struct sil24_cerr_info { 272 unsigned int err_mask, action; 273 const char *desc; 274 } sil24_cerr_db[] = { 275 [0] = { AC_ERR_DEV, 0, 276 "device error" }, 277 [PORT_CERR_DEV] = { AC_ERR_DEV, 0, 278 "device error via D2H FIS" }, 279 [PORT_CERR_SDB] = { AC_ERR_DEV, 0, 280 "device error via SDB FIS" }, 281 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET, 282 "error in data FIS" }, 283 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET, 284 "failed to transmit command FIS" }, 285 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET, 286 "protocol mismatch" }, 287 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET, 288 "data directon mismatch" }, 289 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET, 290 "ran out of SGEs while writing" }, 291 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET, 292 "ran out of SGEs while reading" }, 293 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET, 294 "invalid data directon for ATAPI CDB" }, 295 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, 296 "SGT not on qword boundary" }, 297 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 298 "PCI target abort while fetching SGT" }, 299 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 300 "PCI master abort while fetching SGT" }, 301 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 302 "PCI parity error while fetching SGT" }, 303 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, 304 "PRB not on qword boundary" }, 305 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 306 "PCI target abort while fetching PRB" }, 307 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 308 "PCI master abort while fetching PRB" }, 309 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 310 "PCI parity error while fetching PRB" }, 311 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 312 "undefined error while transferring data" }, 313 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 314 "PCI target abort while transferring data" }, 315 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 316 "PCI master abort while transferring data" }, 317 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, 318 "PCI parity error while transferring data" }, 319 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET, 320 "FIS received while sending service FIS" }, 321 }; 322 323 /* 324 * ap->private_data 325 * 326 * The preview driver always returned 0 for status. We emulate it 327 * here from the previous interrupt. 328 */ 329 struct sil24_port_priv { 330 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 331 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 332 int do_port_rst; 333 }; 334 335 static void sil24_dev_config(struct ata_device *dev); 336 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); 337 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); 338 static int sil24_qc_defer(struct ata_queued_cmd *qc); 339 static void sil24_qc_prep(struct ata_queued_cmd *qc); 340 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 341 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc); 342 static void sil24_pmp_attach(struct ata_port *ap); 343 static void sil24_pmp_detach(struct ata_port *ap); 344 static void sil24_freeze(struct ata_port *ap); 345 static void sil24_thaw(struct ata_port *ap); 346 static int sil24_softreset(struct ata_link *link, unsigned int *class, 347 unsigned long deadline); 348 static int sil24_hardreset(struct ata_link *link, unsigned int *class, 349 unsigned long deadline); 350 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, 351 unsigned long deadline); 352 static void sil24_error_handler(struct ata_port *ap); 353 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 354 static int sil24_port_start(struct ata_port *ap); 355 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 356 #ifdef CONFIG_PM 357 static int sil24_pci_device_resume(struct pci_dev *pdev); 358 static int sil24_port_resume(struct ata_port *ap); 359 #endif 360 361 static const struct pci_device_id sil24_pci_tbl[] = { 362 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 363 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 364 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 365 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 366 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 }, 367 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 368 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 369 370 { } /* terminate list */ 371 }; 372 373 static struct pci_driver sil24_pci_driver = { 374 .name = DRV_NAME, 375 .id_table = sil24_pci_tbl, 376 .probe = sil24_init_one, 377 .remove = ata_pci_remove_one, 378 #ifdef CONFIG_PM 379 .suspend = ata_pci_device_suspend, 380 .resume = sil24_pci_device_resume, 381 #endif 382 }; 383 384 static struct scsi_host_template sil24_sht = { 385 ATA_NCQ_SHT(DRV_NAME), 386 .can_queue = SIL24_MAX_CMDS, 387 .sg_tablesize = SIL24_MAX_SGE, 388 .dma_boundary = ATA_DMA_BOUNDARY, 389 }; 390 391 static struct ata_port_operations sil24_ops = { 392 .inherits = &sata_pmp_port_ops, 393 394 .qc_defer = sil24_qc_defer, 395 .qc_prep = sil24_qc_prep, 396 .qc_issue = sil24_qc_issue, 397 .qc_fill_rtf = sil24_qc_fill_rtf, 398 399 .freeze = sil24_freeze, 400 .thaw = sil24_thaw, 401 .softreset = sil24_softreset, 402 .hardreset = sil24_hardreset, 403 .pmp_softreset = sil24_softreset, 404 .pmp_hardreset = sil24_pmp_hardreset, 405 .error_handler = sil24_error_handler, 406 .post_internal_cmd = sil24_post_internal_cmd, 407 .dev_config = sil24_dev_config, 408 409 .scr_read = sil24_scr_read, 410 .scr_write = sil24_scr_write, 411 .pmp_attach = sil24_pmp_attach, 412 .pmp_detach = sil24_pmp_detach, 413 414 .port_start = sil24_port_start, 415 #ifdef CONFIG_PM 416 .port_resume = sil24_port_resume, 417 #endif 418 }; 419 420 /* 421 * Use bits 30-31 of port_flags to encode available port numbers. 422 * Current maxium is 4. 423 */ 424 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 425 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 426 427 static const struct ata_port_info sil24_port_info[] = { 428 /* sil_3124 */ 429 { 430 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 431 SIL24_FLAG_PCIX_IRQ_WOC, 432 .pio_mask = ATA_PIO4, 433 .mwdma_mask = ATA_MWDMA2, 434 .udma_mask = ATA_UDMA5, 435 .port_ops = &sil24_ops, 436 }, 437 /* sil_3132 */ 438 { 439 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 440 .pio_mask = ATA_PIO4, 441 .mwdma_mask = ATA_MWDMA2, 442 .udma_mask = ATA_UDMA5, 443 .port_ops = &sil24_ops, 444 }, 445 /* sil_3131/sil_3531 */ 446 { 447 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 448 .pio_mask = ATA_PIO4, 449 .mwdma_mask = ATA_MWDMA2, 450 .udma_mask = ATA_UDMA5, 451 .port_ops = &sil24_ops, 452 }, 453 }; 454 455 static int sil24_tag(int tag) 456 { 457 if (unlikely(ata_tag_internal(tag))) 458 return 0; 459 return tag; 460 } 461 462 static unsigned long sil24_port_offset(struct ata_port *ap) 463 { 464 return ap->port_no * PORT_REGS_SIZE; 465 } 466 467 static void __iomem *sil24_port_base(struct ata_port *ap) 468 { 469 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); 470 } 471 472 static void sil24_dev_config(struct ata_device *dev) 473 { 474 void __iomem *port = sil24_port_base(dev->link->ap); 475 476 if (dev->cdb_len == 16) 477 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 478 else 479 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 480 } 481 482 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) 483 { 484 void __iomem *port = sil24_port_base(ap); 485 struct sil24_prb __iomem *prb; 486 u8 fis[6 * 4]; 487 488 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; 489 memcpy_fromio(fis, prb->fis, sizeof(fis)); 490 ata_tf_from_fis(fis, tf); 491 } 492 493 static int sil24_scr_map[] = { 494 [SCR_CONTROL] = 0, 495 [SCR_STATUS] = 1, 496 [SCR_ERROR] = 2, 497 [SCR_ACTIVE] = 3, 498 }; 499 500 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) 501 { 502 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; 503 504 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 505 void __iomem *addr; 506 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 507 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); 508 return 0; 509 } 510 return -EINVAL; 511 } 512 513 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) 514 { 515 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; 516 517 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 518 void __iomem *addr; 519 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 520 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 521 return 0; 522 } 523 return -EINVAL; 524 } 525 526 static void sil24_config_port(struct ata_port *ap) 527 { 528 void __iomem *port = sil24_port_base(ap); 529 530 /* configure IRQ WoC */ 531 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 532 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 533 else 534 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 535 536 /* zero error counters. */ 537 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 538 writel(0x8000, port + PORT_CRC_ERR_THRESH); 539 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 540 writel(0x0000, port + PORT_DECODE_ERR_CNT); 541 writel(0x0000, port + PORT_CRC_ERR_CNT); 542 writel(0x0000, port + PORT_HSHK_ERR_CNT); 543 544 /* always use 64bit activation */ 545 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 546 547 /* clear port multiplier enable and resume bits */ 548 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 549 } 550 551 static void sil24_config_pmp(struct ata_port *ap, int attached) 552 { 553 void __iomem *port = sil24_port_base(ap); 554 555 if (attached) 556 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); 557 else 558 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); 559 } 560 561 static void sil24_clear_pmp(struct ata_port *ap) 562 { 563 void __iomem *port = sil24_port_base(ap); 564 int i; 565 566 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 567 568 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { 569 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; 570 571 writel(0, pmp_base + PORT_PMP_STATUS); 572 writel(0, pmp_base + PORT_PMP_QACTIVE); 573 } 574 } 575 576 static int sil24_init_port(struct ata_port *ap) 577 { 578 void __iomem *port = sil24_port_base(ap); 579 struct sil24_port_priv *pp = ap->private_data; 580 u32 tmp; 581 582 /* clear PMP error status */ 583 if (sata_pmp_attached(ap)) 584 sil24_clear_pmp(ap); 585 586 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 587 ata_wait_register(port + PORT_CTRL_STAT, 588 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 589 tmp = ata_wait_register(port + PORT_CTRL_STAT, 590 PORT_CS_RDY, 0, 10, 100); 591 592 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { 593 pp->do_port_rst = 1; 594 ap->link.eh_context.i.action |= ATA_EH_RESET; 595 return -EIO; 596 } 597 598 return 0; 599 } 600 601 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, 602 const struct ata_taskfile *tf, 603 int is_cmd, u32 ctrl, 604 unsigned long timeout_msec) 605 { 606 void __iomem *port = sil24_port_base(ap); 607 struct sil24_port_priv *pp = ap->private_data; 608 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 609 dma_addr_t paddr = pp->cmd_block_dma; 610 u32 irq_enabled, irq_mask, irq_stat; 611 int rc; 612 613 prb->ctrl = cpu_to_le16(ctrl); 614 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); 615 616 /* temporarily plug completion and error interrupts */ 617 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); 618 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); 619 620 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 621 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 622 623 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 624 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, 625 10, timeout_msec); 626 627 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ 628 irq_stat >>= PORT_IRQ_RAW_SHIFT; 629 630 if (irq_stat & PORT_IRQ_COMPLETE) 631 rc = 0; 632 else { 633 /* force port into known state */ 634 sil24_init_port(ap); 635 636 if (irq_stat & PORT_IRQ_ERROR) 637 rc = -EIO; 638 else 639 rc = -EBUSY; 640 } 641 642 /* restore IRQ enabled */ 643 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); 644 645 return rc; 646 } 647 648 static int sil24_softreset(struct ata_link *link, unsigned int *class, 649 unsigned long deadline) 650 { 651 struct ata_port *ap = link->ap; 652 int pmp = sata_srst_pmp(link); 653 unsigned long timeout_msec = 0; 654 struct ata_taskfile tf; 655 const char *reason; 656 int rc; 657 658 DPRINTK("ENTER\n"); 659 660 /* put the port into known state */ 661 if (sil24_init_port(ap)) { 662 reason = "port not ready"; 663 goto err; 664 } 665 666 /* do SRST */ 667 if (time_after(deadline, jiffies)) 668 timeout_msec = jiffies_to_msecs(deadline - jiffies); 669 670 ata_tf_init(link->device, &tf); /* doesn't really matter */ 671 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, 672 timeout_msec); 673 if (rc == -EBUSY) { 674 reason = "timeout"; 675 goto err; 676 } else if (rc) { 677 reason = "SRST command error"; 678 goto err; 679 } 680 681 sil24_read_tf(ap, 0, &tf); 682 *class = ata_dev_classify(&tf); 683 684 DPRINTK("EXIT, class=%u\n", *class); 685 return 0; 686 687 err: 688 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 689 return -EIO; 690 } 691 692 static int sil24_hardreset(struct ata_link *link, unsigned int *class, 693 unsigned long deadline) 694 { 695 struct ata_port *ap = link->ap; 696 void __iomem *port = sil24_port_base(ap); 697 struct sil24_port_priv *pp = ap->private_data; 698 int did_port_rst = 0; 699 const char *reason; 700 int tout_msec, rc; 701 u32 tmp; 702 703 retry: 704 /* Sometimes, DEV_RST is not enough to recover the controller. 705 * This happens often after PM DMA CS errata. 706 */ 707 if (pp->do_port_rst) { 708 ata_port_printk(ap, KERN_WARNING, "controller in dubious " 709 "state, performing PORT_RST\n"); 710 711 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); 712 msleep(10); 713 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 714 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, 715 10, 5000); 716 717 /* restore port configuration */ 718 sil24_config_port(ap); 719 sil24_config_pmp(ap, ap->nr_pmp_links); 720 721 pp->do_port_rst = 0; 722 did_port_rst = 1; 723 } 724 725 /* sil24 does the right thing(tm) without any protection */ 726 sata_set_spd(link); 727 728 tout_msec = 100; 729 if (ata_link_online(link)) 730 tout_msec = 5000; 731 732 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 733 tmp = ata_wait_register(port + PORT_CTRL_STAT, 734 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, 735 tout_msec); 736 737 /* SStatus oscillates between zero and valid status after 738 * DEV_RST, debounce it. 739 */ 740 rc = sata_link_debounce(link, sata_deb_timing_long, deadline); 741 if (rc) { 742 reason = "PHY debouncing failed"; 743 goto err; 744 } 745 746 if (tmp & PORT_CS_DEV_RST) { 747 if (ata_link_offline(link)) 748 return 0; 749 reason = "link not ready"; 750 goto err; 751 } 752 753 /* Sil24 doesn't store signature FIS after hardreset, so we 754 * can't wait for BSY to clear. Some devices take a long time 755 * to get ready and those devices will choke if we don't wait 756 * for BSY clearance here. Tell libata to perform follow-up 757 * softreset. 758 */ 759 return -EAGAIN; 760 761 err: 762 if (!did_port_rst) { 763 pp->do_port_rst = 1; 764 goto retry; 765 } 766 767 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason); 768 return -EIO; 769 } 770 771 static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 772 struct sil24_sge *sge) 773 { 774 struct scatterlist *sg; 775 struct sil24_sge *last_sge = NULL; 776 unsigned int si; 777 778 for_each_sg(qc->sg, sg, qc->n_elem, si) { 779 sge->addr = cpu_to_le64(sg_dma_address(sg)); 780 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 781 sge->flags = 0; 782 783 last_sge = sge; 784 sge++; 785 } 786 787 last_sge->flags = cpu_to_le32(SGE_TRM); 788 } 789 790 static int sil24_qc_defer(struct ata_queued_cmd *qc) 791 { 792 struct ata_link *link = qc->dev->link; 793 struct ata_port *ap = link->ap; 794 u8 prot = qc->tf.protocol; 795 796 /* 797 * There is a bug in the chip: 798 * Port LRAM Causes the PRB/SGT Data to be Corrupted 799 * If the host issues a read request for LRAM and SActive registers 800 * while active commands are available in the port, PRB/SGT data in 801 * the LRAM can become corrupted. This issue applies only when 802 * reading from, but not writing to, the LRAM. 803 * 804 * Therefore, reading LRAM when there is no particular error [and 805 * other commands may be outstanding] is prohibited. 806 * 807 * To avoid this bug there are two situations where a command must run 808 * exclusive of any other commands on the port: 809 * 810 * - ATAPI commands which check the sense data 811 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF 812 * set. 813 * 814 */ 815 int is_excl = (ata_is_atapi(prot) || 816 (qc->flags & ATA_QCFLAG_RESULT_TF)); 817 818 if (unlikely(ap->excl_link)) { 819 if (link == ap->excl_link) { 820 if (ap->nr_active_links) 821 return ATA_DEFER_PORT; 822 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 823 } else 824 return ATA_DEFER_PORT; 825 } else if (unlikely(is_excl)) { 826 ap->excl_link = link; 827 if (ap->nr_active_links) 828 return ATA_DEFER_PORT; 829 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 830 } 831 832 return ata_std_qc_defer(qc); 833 } 834 835 static void sil24_qc_prep(struct ata_queued_cmd *qc) 836 { 837 struct ata_port *ap = qc->ap; 838 struct sil24_port_priv *pp = ap->private_data; 839 union sil24_cmd_block *cb; 840 struct sil24_prb *prb; 841 struct sil24_sge *sge; 842 u16 ctrl = 0; 843 844 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 845 846 if (!ata_is_atapi(qc->tf.protocol)) { 847 prb = &cb->ata.prb; 848 sge = cb->ata.sge; 849 } else { 850 prb = &cb->atapi.prb; 851 sge = cb->atapi.sge; 852 memset(cb->atapi.cdb, 0, 32); 853 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 854 855 if (ata_is_data(qc->tf.protocol)) { 856 if (qc->tf.flags & ATA_TFLAG_WRITE) 857 ctrl = PRB_CTRL_PACKET_WRITE; 858 else 859 ctrl = PRB_CTRL_PACKET_READ; 860 } 861 } 862 863 prb->ctrl = cpu_to_le16(ctrl); 864 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); 865 866 if (qc->flags & ATA_QCFLAG_DMAMAP) 867 sil24_fill_sg(qc, sge); 868 } 869 870 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 871 { 872 struct ata_port *ap = qc->ap; 873 struct sil24_port_priv *pp = ap->private_data; 874 void __iomem *port = sil24_port_base(ap); 875 unsigned int tag = sil24_tag(qc->tag); 876 dma_addr_t paddr; 877 void __iomem *activate; 878 879 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 880 activate = port + PORT_CMD_ACTIVATE + tag * 8; 881 882 writel((u32)paddr, activate); 883 writel((u64)paddr >> 32, activate + 4); 884 885 return 0; 886 } 887 888 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc) 889 { 890 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf); 891 return true; 892 } 893 894 static void sil24_pmp_attach(struct ata_port *ap) 895 { 896 u32 *gscr = ap->link.device->gscr; 897 898 sil24_config_pmp(ap, 1); 899 sil24_init_port(ap); 900 901 if (sata_pmp_gscr_vendor(gscr) == 0x11ab && 902 sata_pmp_gscr_devid(gscr) == 0x4140) { 903 ata_port_printk(ap, KERN_INFO, 904 "disabling NCQ support due to sil24-mv4140 quirk\n"); 905 ap->flags &= ~ATA_FLAG_NCQ; 906 } 907 } 908 909 static void sil24_pmp_detach(struct ata_port *ap) 910 { 911 sil24_init_port(ap); 912 sil24_config_pmp(ap, 0); 913 914 ap->flags |= ATA_FLAG_NCQ; 915 } 916 917 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, 918 unsigned long deadline) 919 { 920 int rc; 921 922 rc = sil24_init_port(link->ap); 923 if (rc) { 924 ata_link_printk(link, KERN_ERR, 925 "hardreset failed (port not ready)\n"); 926 return rc; 927 } 928 929 return sata_std_hardreset(link, class, deadline); 930 } 931 932 static void sil24_freeze(struct ata_port *ap) 933 { 934 void __iomem *port = sil24_port_base(ap); 935 936 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 937 * PORT_IRQ_ENABLE instead. 938 */ 939 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 940 } 941 942 static void sil24_thaw(struct ata_port *ap) 943 { 944 void __iomem *port = sil24_port_base(ap); 945 u32 tmp; 946 947 /* clear IRQ */ 948 tmp = readl(port + PORT_IRQ_STAT); 949 writel(tmp, port + PORT_IRQ_STAT); 950 951 /* turn IRQ back on */ 952 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 953 } 954 955 static void sil24_error_intr(struct ata_port *ap) 956 { 957 void __iomem *port = sil24_port_base(ap); 958 struct sil24_port_priv *pp = ap->private_data; 959 struct ata_queued_cmd *qc = NULL; 960 struct ata_link *link; 961 struct ata_eh_info *ehi; 962 int abort = 0, freeze = 0; 963 u32 irq_stat; 964 965 /* on error, we need to clear IRQ explicitly */ 966 irq_stat = readl(port + PORT_IRQ_STAT); 967 writel(irq_stat, port + PORT_IRQ_STAT); 968 969 /* first, analyze and record host port events */ 970 link = &ap->link; 971 ehi = &link->eh_info; 972 ata_ehi_clear_desc(ehi); 973 974 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 975 976 if (irq_stat & PORT_IRQ_SDB_NOTIFY) { 977 ata_ehi_push_desc(ehi, "SDB notify"); 978 sata_async_notification(ap); 979 } 980 981 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 982 ata_ehi_hotplugged(ehi); 983 ata_ehi_push_desc(ehi, "%s", 984 irq_stat & PORT_IRQ_PHYRDY_CHG ? 985 "PHY RDY changed" : "device exchanged"); 986 freeze = 1; 987 } 988 989 if (irq_stat & PORT_IRQ_UNK_FIS) { 990 ehi->err_mask |= AC_ERR_HSM; 991 ehi->action |= ATA_EH_RESET; 992 ata_ehi_push_desc(ehi, "unknown FIS"); 993 freeze = 1; 994 } 995 996 /* deal with command error */ 997 if (irq_stat & PORT_IRQ_ERROR) { 998 struct sil24_cerr_info *ci = NULL; 999 unsigned int err_mask = 0, action = 0; 1000 u32 context, cerr; 1001 int pmp; 1002 1003 abort = 1; 1004 1005 /* DMA Context Switch Failure in Port Multiplier Mode 1006 * errata. If we have active commands to 3 or more 1007 * devices, any error condition on active devices can 1008 * corrupt DMA context switching. 1009 */ 1010 if (ap->nr_active_links >= 3) { 1011 ehi->err_mask |= AC_ERR_OTHER; 1012 ehi->action |= ATA_EH_RESET; 1013 ata_ehi_push_desc(ehi, "PMP DMA CS errata"); 1014 pp->do_port_rst = 1; 1015 freeze = 1; 1016 } 1017 1018 /* find out the offending link and qc */ 1019 if (sata_pmp_attached(ap)) { 1020 context = readl(port + PORT_CONTEXT); 1021 pmp = (context >> 5) & 0xf; 1022 1023 if (pmp < ap->nr_pmp_links) { 1024 link = &ap->pmp_link[pmp]; 1025 ehi = &link->eh_info; 1026 qc = ata_qc_from_tag(ap, link->active_tag); 1027 1028 ata_ehi_clear_desc(ehi); 1029 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", 1030 irq_stat); 1031 } else { 1032 err_mask |= AC_ERR_HSM; 1033 action |= ATA_EH_RESET; 1034 freeze = 1; 1035 } 1036 } else 1037 qc = ata_qc_from_tag(ap, link->active_tag); 1038 1039 /* analyze CMD_ERR */ 1040 cerr = readl(port + PORT_CMD_ERR); 1041 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 1042 ci = &sil24_cerr_db[cerr]; 1043 1044 if (ci && ci->desc) { 1045 err_mask |= ci->err_mask; 1046 action |= ci->action; 1047 if (action & ATA_EH_RESET) 1048 freeze = 1; 1049 ata_ehi_push_desc(ehi, "%s", ci->desc); 1050 } else { 1051 err_mask |= AC_ERR_OTHER; 1052 action |= ATA_EH_RESET; 1053 freeze = 1; 1054 ata_ehi_push_desc(ehi, "unknown command error %d", 1055 cerr); 1056 } 1057 1058 /* record error info */ 1059 if (qc) 1060 qc->err_mask |= err_mask; 1061 else 1062 ehi->err_mask |= err_mask; 1063 1064 ehi->action |= action; 1065 1066 /* if PMP, resume */ 1067 if (sata_pmp_attached(ap)) 1068 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); 1069 } 1070 1071 /* freeze or abort */ 1072 if (freeze) 1073 ata_port_freeze(ap); 1074 else if (abort) { 1075 if (qc) 1076 ata_link_abort(qc->dev->link); 1077 else 1078 ata_port_abort(ap); 1079 } 1080 } 1081 1082 static inline void sil24_host_intr(struct ata_port *ap) 1083 { 1084 void __iomem *port = sil24_port_base(ap); 1085 u32 slot_stat, qc_active; 1086 int rc; 1087 1088 /* If PCIX_IRQ_WOC, there's an inherent race window between 1089 * clearing IRQ pending status and reading PORT_SLOT_STAT 1090 * which may cause spurious interrupts afterwards. This is 1091 * unavoidable and much better than losing interrupts which 1092 * happens if IRQ pending is cleared after reading 1093 * PORT_SLOT_STAT. 1094 */ 1095 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 1096 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 1097 1098 slot_stat = readl(port + PORT_SLOT_STAT); 1099 1100 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 1101 sil24_error_intr(ap); 1102 return; 1103 } 1104 1105 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 1106 rc = ata_qc_complete_multiple(ap, qc_active); 1107 if (rc > 0) 1108 return; 1109 if (rc < 0) { 1110 struct ata_eh_info *ehi = &ap->link.eh_info; 1111 ehi->err_mask |= AC_ERR_HSM; 1112 ehi->action |= ATA_EH_RESET; 1113 ata_port_freeze(ap); 1114 return; 1115 } 1116 1117 /* spurious interrupts are expected if PCIX_IRQ_WOC */ 1118 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) 1119 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 1120 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 1121 slot_stat, ap->link.active_tag, ap->link.sactive); 1122 } 1123 1124 static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 1125 { 1126 struct ata_host *host = dev_instance; 1127 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1128 unsigned handled = 0; 1129 u32 status; 1130 int i; 1131 1132 status = readl(host_base + HOST_IRQ_STAT); 1133 1134 if (status == 0xffffffff) { 1135 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 1136 "PCI fault or device removal?\n"); 1137 goto out; 1138 } 1139 1140 if (!(status & IRQ_STAT_4PORTS)) 1141 goto out; 1142 1143 spin_lock(&host->lock); 1144 1145 for (i = 0; i < host->n_ports; i++) 1146 if (status & (1 << i)) { 1147 struct ata_port *ap = host->ports[i]; 1148 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 1149 sil24_host_intr(ap); 1150 handled++; 1151 } else 1152 printk(KERN_ERR DRV_NAME 1153 ": interrupt from disabled port %d\n", i); 1154 } 1155 1156 spin_unlock(&host->lock); 1157 out: 1158 return IRQ_RETVAL(handled); 1159 } 1160 1161 static void sil24_error_handler(struct ata_port *ap) 1162 { 1163 struct sil24_port_priv *pp = ap->private_data; 1164 1165 if (sil24_init_port(ap)) 1166 ata_eh_freeze_port(ap); 1167 1168 sata_pmp_error_handler(ap); 1169 1170 pp->do_port_rst = 0; 1171 } 1172 1173 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 1174 { 1175 struct ata_port *ap = qc->ap; 1176 1177 /* make DMA engine forget about the failed command */ 1178 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) 1179 ata_eh_freeze_port(ap); 1180 } 1181 1182 static int sil24_port_start(struct ata_port *ap) 1183 { 1184 struct device *dev = ap->host->dev; 1185 struct sil24_port_priv *pp; 1186 union sil24_cmd_block *cb; 1187 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 1188 dma_addr_t cb_dma; 1189 1190 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1191 if (!pp) 1192 return -ENOMEM; 1193 1194 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 1195 if (!cb) 1196 return -ENOMEM; 1197 memset(cb, 0, cb_size); 1198 1199 pp->cmd_block = cb; 1200 pp->cmd_block_dma = cb_dma; 1201 1202 ap->private_data = pp; 1203 1204 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); 1205 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port"); 1206 1207 return 0; 1208 } 1209 1210 static void sil24_init_controller(struct ata_host *host) 1211 { 1212 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1213 u32 tmp; 1214 int i; 1215 1216 /* GPIO off */ 1217 writel(0, host_base + HOST_FLASH_CMD); 1218 1219 /* clear global reset & mask interrupts during initialization */ 1220 writel(0, host_base + HOST_CTRL); 1221 1222 /* init ports */ 1223 for (i = 0; i < host->n_ports; i++) { 1224 struct ata_port *ap = host->ports[i]; 1225 void __iomem *port = sil24_port_base(ap); 1226 1227 1228 /* Initial PHY setting */ 1229 writel(0x20c, port + PORT_PHY_CFG); 1230 1231 /* Clear port RST */ 1232 tmp = readl(port + PORT_CTRL_STAT); 1233 if (tmp & PORT_CS_PORT_RST) { 1234 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 1235 tmp = ata_wait_register(port + PORT_CTRL_STAT, 1236 PORT_CS_PORT_RST, 1237 PORT_CS_PORT_RST, 10, 100); 1238 if (tmp & PORT_CS_PORT_RST) 1239 dev_printk(KERN_ERR, host->dev, 1240 "failed to clear port RST\n"); 1241 } 1242 1243 /* configure port */ 1244 sil24_config_port(ap); 1245 } 1246 1247 /* Turn on interrupts */ 1248 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1249 } 1250 1251 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1252 { 1253 extern int __MARKER__sil24_cmd_block_is_sized_wrongly; 1254 static int printed_version; 1255 struct ata_port_info pi = sil24_port_info[ent->driver_data]; 1256 const struct ata_port_info *ppi[] = { &pi, NULL }; 1257 void __iomem * const *iomap; 1258 struct ata_host *host; 1259 int rc; 1260 u32 tmp; 1261 1262 /* cause link error if sil24_cmd_block is sized wrongly */ 1263 if (sizeof(union sil24_cmd_block) != PAGE_SIZE) 1264 __MARKER__sil24_cmd_block_is_sized_wrongly = 1; 1265 1266 if (!printed_version++) 1267 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1268 1269 /* acquire resources */ 1270 rc = pcim_enable_device(pdev); 1271 if (rc) 1272 return rc; 1273 1274 rc = pcim_iomap_regions(pdev, 1275 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1276 DRV_NAME); 1277 if (rc) 1278 return rc; 1279 iomap = pcim_iomap_table(pdev); 1280 1281 /* apply workaround for completion IRQ loss on PCI-X errata */ 1282 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1283 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); 1284 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1285 dev_printk(KERN_INFO, &pdev->dev, 1286 "Applying completion IRQ loss on PCI-X " 1287 "errata fix\n"); 1288 else 1289 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1290 } 1291 1292 /* allocate and fill host */ 1293 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1294 SIL24_FLAG2NPORTS(ppi[0]->flags)); 1295 if (!host) 1296 return -ENOMEM; 1297 host->iomap = iomap; 1298 1299 /* configure and activate the device */ 1300 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 1301 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1302 if (rc) { 1303 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1304 if (rc) { 1305 dev_printk(KERN_ERR, &pdev->dev, 1306 "64-bit DMA enable failed\n"); 1307 return rc; 1308 } 1309 } 1310 } else { 1311 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1312 if (rc) { 1313 dev_printk(KERN_ERR, &pdev->dev, 1314 "32-bit DMA enable failed\n"); 1315 return rc; 1316 } 1317 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1318 if (rc) { 1319 dev_printk(KERN_ERR, &pdev->dev, 1320 "32-bit consistent DMA enable failed\n"); 1321 return rc; 1322 } 1323 } 1324 1325 /* Set max read request size to 4096. This slightly increases 1326 * write throughput for pci-e variants. 1327 */ 1328 pcie_set_readrq(pdev, 4096); 1329 1330 sil24_init_controller(host); 1331 1332 pci_set_master(pdev); 1333 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, 1334 &sil24_sht); 1335 } 1336 1337 #ifdef CONFIG_PM 1338 static int sil24_pci_device_resume(struct pci_dev *pdev) 1339 { 1340 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1341 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1342 int rc; 1343 1344 rc = ata_pci_device_do_resume(pdev); 1345 if (rc) 1346 return rc; 1347 1348 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1349 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1350 1351 sil24_init_controller(host); 1352 1353 ata_host_resume(host); 1354 1355 return 0; 1356 } 1357 1358 static int sil24_port_resume(struct ata_port *ap) 1359 { 1360 sil24_config_pmp(ap, ap->nr_pmp_links); 1361 return 0; 1362 } 1363 #endif 1364 1365 static int __init sil24_init(void) 1366 { 1367 return pci_register_driver(&sil24_pci_driver); 1368 } 1369 1370 static void __exit sil24_exit(void) 1371 { 1372 pci_unregister_driver(&sil24_pci_driver); 1373 } 1374 1375 MODULE_AUTHOR("Tejun Heo"); 1376 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1377 MODULE_LICENSE("GPL"); 1378 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1379 1380 module_init(sil24_init); 1381 module_exit(sil24_exit); 1382