1 /* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 32 #define DRV_NAME "sata_sil24" 33 #define DRV_VERSION "1.1" 34 35 /* 36 * Port request block (PRB) 32 bytes 37 */ 38 struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43 }; 44 45 /* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48 struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52 }; 53 54 /* 55 * Port multiplier 56 */ 57 struct sil24_port_multiplier { 58 __le32 diag; 59 __le32 sactive; 60 }; 61 62 enum { 63 SIL24_HOST_BAR = 0, 64 SIL24_PORT_BAR = 2, 65 66 /* sil24 fetches in chunks of 64bytes. The first block 67 * contains the PRB and two SGEs. From the second block, it's 68 * consisted of four SGEs and called SGT. Calculate the 69 * number of SGTs that fit into one page. 70 */ 71 SIL24_PRB_SZ = sizeof(struct sil24_prb) 72 + 2 * sizeof(struct sil24_sge), 73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) 74 / (4 * sizeof(struct sil24_sge)), 75 76 /* This will give us one unused SGEs for ATA. This extra SGE 77 * will be used to store CDB for ATAPI devices. 78 */ 79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, 80 81 /* 82 * Global controller registers (128 bytes @ BAR0) 83 */ 84 /* 32 bit regs */ 85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 86 HOST_CTRL = 0x40, 87 HOST_IRQ_STAT = 0x44, 88 HOST_PHY_CFG = 0x48, 89 HOST_BIST_CTRL = 0x50, 90 HOST_BIST_PTRN = 0x54, 91 HOST_BIST_STAT = 0x58, 92 HOST_MEM_BIST_STAT = 0x5c, 93 HOST_FLASH_CMD = 0x70, 94 /* 8 bit regs */ 95 HOST_FLASH_DATA = 0x74, 96 HOST_TRANSITION_DETECT = 0x75, 97 HOST_GPIO_CTRL = 0x76, 98 HOST_I2C_ADDR = 0x78, /* 32 bit */ 99 HOST_I2C_DATA = 0x7c, 100 HOST_I2C_XFER_CNT = 0x7e, 101 HOST_I2C_CTRL = 0x7f, 102 103 /* HOST_SLOT_STAT bits */ 104 HOST_SSTAT_ATTN = (1 << 31), 105 106 /* HOST_CTRL bits */ 107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 113 114 /* 115 * Port registers 116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 117 */ 118 PORT_REGS_SIZE = 0x2000, 119 120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 122 123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 124 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 127 128 /* 32 bit regs */ 129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 134 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 136 PORT_CMD_ERR = 0x1024, /* command error number */ 137 PORT_FIS_CFG = 0x1028, 138 PORT_FIFO_THRES = 0x102c, 139 /* 16 bit regs */ 140 PORT_DECODE_ERR_CNT = 0x1040, 141 PORT_DECODE_ERR_THRESH = 0x1042, 142 PORT_CRC_ERR_CNT = 0x1044, 143 PORT_CRC_ERR_THRESH = 0x1046, 144 PORT_HSHK_ERR_CNT = 0x1048, 145 PORT_HSHK_ERR_THRESH = 0x104a, 146 /* 32 bit regs */ 147 PORT_PHY_CFG = 0x1050, 148 PORT_SLOT_STAT = 0x1800, 149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 150 PORT_CONTEXT = 0x1e04, 151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 153 PORT_SCONTROL = 0x1f00, 154 PORT_SSTATUS = 0x1f04, 155 PORT_SERROR = 0x1f08, 156 PORT_SACTIVE = 0x1f0c, 157 158 /* PORT_CTRL_STAT bits */ 159 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 160 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 161 PORT_CS_INIT = (1 << 2), /* port initialize */ 162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 168 169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 170 /* bits[11:0] are masked */ 171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 183 184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 187 188 /* bits[27:16] are unmasked (raw) */ 189 PORT_IRQ_RAW_SHIFT = 16, 190 PORT_IRQ_MASKED_MASK = 0x7ff, 191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 192 193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 194 PORT_IRQ_STEER_SHIFT = 30, 195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 196 197 /* PORT_CMD_ERR constants */ 198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 220 221 /* bits of PRB control field */ 222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 227 228 /* PRB protocol field */ 229 PRB_PROT_PACKET = (1 << 0), 230 PRB_PROT_TCQ = (1 << 1), 231 PRB_PROT_NCQ = (1 << 2), 232 PRB_PROT_READ = (1 << 3), 233 PRB_PROT_WRITE = (1 << 4), 234 PRB_PROT_TRANSPARENT = (1 << 5), 235 236 /* 237 * Other constants 238 */ 239 SGE_TRM = (1 << 31), /* Last SGE in chain */ 240 SGE_LNK = (1 << 30), /* linked list 241 Points to SGT, not SGE */ 242 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 243 data address ignored */ 244 245 SIL24_MAX_CMDS = 31, 246 247 /* board id */ 248 BID_SIL3124 = 0, 249 BID_SIL3132 = 1, 250 BID_SIL3131 = 2, 251 252 /* host flags */ 253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | 256 ATA_FLAG_AN | ATA_FLAG_PMP, 257 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY, 258 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 259 260 IRQ_STAT_4PORTS = 0xf, 261 }; 262 263 struct sil24_ata_block { 264 struct sil24_prb prb; 265 struct sil24_sge sge[SIL24_MAX_SGE]; 266 }; 267 268 struct sil24_atapi_block { 269 struct sil24_prb prb; 270 u8 cdb[16]; 271 struct sil24_sge sge[SIL24_MAX_SGE]; 272 }; 273 274 union sil24_cmd_block { 275 struct sil24_ata_block ata; 276 struct sil24_atapi_block atapi; 277 }; 278 279 static struct sil24_cerr_info { 280 unsigned int err_mask, action; 281 const char *desc; 282 } sil24_cerr_db[] = { 283 [0] = { AC_ERR_DEV, 0, 284 "device error" }, 285 [PORT_CERR_DEV] = { AC_ERR_DEV, 0, 286 "device error via D2H FIS" }, 287 [PORT_CERR_SDB] = { AC_ERR_DEV, 0, 288 "device error via SDB FIS" }, 289 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 290 "error in data FIS" }, 291 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 292 "failed to transmit command FIS" }, 293 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 294 "protocol mismatch" }, 295 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 296 "data directon mismatch" }, 297 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 298 "ran out of SGEs while writing" }, 299 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 300 "ran out of SGEs while reading" }, 301 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 302 "invalid data directon for ATAPI CDB" }, 303 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 304 "SGT not on qword boundary" }, 305 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 306 "PCI target abort while fetching SGT" }, 307 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 308 "PCI master abort while fetching SGT" }, 309 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 310 "PCI parity error while fetching SGT" }, 311 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 312 "PRB not on qword boundary" }, 313 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 314 "PCI target abort while fetching PRB" }, 315 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 316 "PCI master abort while fetching PRB" }, 317 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 318 "PCI parity error while fetching PRB" }, 319 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 320 "undefined error while transferring data" }, 321 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 322 "PCI target abort while transferring data" }, 323 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 324 "PCI master abort while transferring data" }, 325 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 326 "PCI parity error while transferring data" }, 327 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 328 "FIS received while sending service FIS" }, 329 }; 330 331 /* 332 * ap->private_data 333 * 334 * The preview driver always returned 0 for status. We emulate it 335 * here from the previous interrupt. 336 */ 337 struct sil24_port_priv { 338 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 339 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 340 struct ata_taskfile tf; /* Cached taskfile registers */ 341 int do_port_rst; 342 }; 343 344 static void sil24_dev_config(struct ata_device *dev); 345 static u8 sil24_check_status(struct ata_port *ap); 346 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val); 347 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 348 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 349 static int sil24_qc_defer(struct ata_queued_cmd *qc); 350 static void sil24_qc_prep(struct ata_queued_cmd *qc); 351 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 352 static void sil24_irq_clear(struct ata_port *ap); 353 static void sil24_pmp_attach(struct ata_port *ap); 354 static void sil24_pmp_detach(struct ata_port *ap); 355 static void sil24_freeze(struct ata_port *ap); 356 static void sil24_thaw(struct ata_port *ap); 357 static void sil24_error_handler(struct ata_port *ap); 358 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 359 static int sil24_port_start(struct ata_port *ap); 360 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 361 #ifdef CONFIG_PM 362 static int sil24_pci_device_resume(struct pci_dev *pdev); 363 static int sil24_port_resume(struct ata_port *ap); 364 #endif 365 366 static const struct pci_device_id sil24_pci_tbl[] = { 367 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 368 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 369 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 370 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 371 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 372 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 373 374 { } /* terminate list */ 375 }; 376 377 static struct pci_driver sil24_pci_driver = { 378 .name = DRV_NAME, 379 .id_table = sil24_pci_tbl, 380 .probe = sil24_init_one, 381 .remove = ata_pci_remove_one, 382 #ifdef CONFIG_PM 383 .suspend = ata_pci_device_suspend, 384 .resume = sil24_pci_device_resume, 385 #endif 386 }; 387 388 static struct scsi_host_template sil24_sht = { 389 .module = THIS_MODULE, 390 .name = DRV_NAME, 391 .ioctl = ata_scsi_ioctl, 392 .queuecommand = ata_scsi_queuecmd, 393 .change_queue_depth = ata_scsi_change_queue_depth, 394 .can_queue = SIL24_MAX_CMDS, 395 .this_id = ATA_SHT_THIS_ID, 396 .sg_tablesize = SIL24_MAX_SGE, 397 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 398 .emulated = ATA_SHT_EMULATED, 399 .use_clustering = ATA_SHT_USE_CLUSTERING, 400 .proc_name = DRV_NAME, 401 .dma_boundary = ATA_DMA_BOUNDARY, 402 .slave_configure = ata_scsi_slave_config, 403 .slave_destroy = ata_scsi_slave_destroy, 404 .bios_param = ata_std_bios_param, 405 }; 406 407 static const struct ata_port_operations sil24_ops = { 408 .dev_config = sil24_dev_config, 409 410 .check_status = sil24_check_status, 411 .check_altstatus = sil24_check_status, 412 .dev_select = ata_noop_dev_select, 413 414 .tf_read = sil24_tf_read, 415 416 .qc_defer = sil24_qc_defer, 417 .qc_prep = sil24_qc_prep, 418 .qc_issue = sil24_qc_issue, 419 420 .irq_clear = sil24_irq_clear, 421 422 .scr_read = sil24_scr_read, 423 .scr_write = sil24_scr_write, 424 425 .pmp_attach = sil24_pmp_attach, 426 .pmp_detach = sil24_pmp_detach, 427 428 .freeze = sil24_freeze, 429 .thaw = sil24_thaw, 430 .error_handler = sil24_error_handler, 431 .post_internal_cmd = sil24_post_internal_cmd, 432 433 .port_start = sil24_port_start, 434 435 #ifdef CONFIG_PM 436 .port_resume = sil24_port_resume, 437 #endif 438 }; 439 440 /* 441 * Use bits 30-31 of port_flags to encode available port numbers. 442 * Current maxium is 4. 443 */ 444 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 445 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 446 447 static const struct ata_port_info sil24_port_info[] = { 448 /* sil_3124 */ 449 { 450 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 451 SIL24_FLAG_PCIX_IRQ_WOC, 452 .link_flags = SIL24_COMMON_LFLAGS, 453 .pio_mask = 0x1f, /* pio0-4 */ 454 .mwdma_mask = 0x07, /* mwdma0-2 */ 455 .udma_mask = ATA_UDMA5, /* udma0-5 */ 456 .port_ops = &sil24_ops, 457 }, 458 /* sil_3132 */ 459 { 460 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 461 .link_flags = SIL24_COMMON_LFLAGS, 462 .pio_mask = 0x1f, /* pio0-4 */ 463 .mwdma_mask = 0x07, /* mwdma0-2 */ 464 .udma_mask = ATA_UDMA5, /* udma0-5 */ 465 .port_ops = &sil24_ops, 466 }, 467 /* sil_3131/sil_3531 */ 468 { 469 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 470 .link_flags = SIL24_COMMON_LFLAGS, 471 .pio_mask = 0x1f, /* pio0-4 */ 472 .mwdma_mask = 0x07, /* mwdma0-2 */ 473 .udma_mask = ATA_UDMA5, /* udma0-5 */ 474 .port_ops = &sil24_ops, 475 }, 476 }; 477 478 static int sil24_tag(int tag) 479 { 480 if (unlikely(ata_tag_internal(tag))) 481 return 0; 482 return tag; 483 } 484 485 static void sil24_dev_config(struct ata_device *dev) 486 { 487 void __iomem *port = dev->link->ap->ioaddr.cmd_addr; 488 489 if (dev->cdb_len == 16) 490 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 491 else 492 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 493 } 494 495 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) 496 { 497 void __iomem *port = ap->ioaddr.cmd_addr; 498 struct sil24_prb __iomem *prb; 499 u8 fis[6 * 4]; 500 501 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; 502 memcpy_fromio(fis, prb->fis, sizeof(fis)); 503 ata_tf_from_fis(fis, tf); 504 } 505 506 static u8 sil24_check_status(struct ata_port *ap) 507 { 508 struct sil24_port_priv *pp = ap->private_data; 509 return pp->tf.command; 510 } 511 512 static int sil24_scr_map[] = { 513 [SCR_CONTROL] = 0, 514 [SCR_STATUS] = 1, 515 [SCR_ERROR] = 2, 516 [SCR_ACTIVE] = 3, 517 }; 518 519 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) 520 { 521 void __iomem *scr_addr = ap->ioaddr.scr_addr; 522 523 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 524 void __iomem *addr; 525 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 526 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); 527 return 0; 528 } 529 return -EINVAL; 530 } 531 532 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 533 { 534 void __iomem *scr_addr = ap->ioaddr.scr_addr; 535 536 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 537 void __iomem *addr; 538 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 539 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 540 return 0; 541 } 542 return -EINVAL; 543 } 544 545 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 546 { 547 struct sil24_port_priv *pp = ap->private_data; 548 *tf = pp->tf; 549 } 550 551 static void sil24_config_port(struct ata_port *ap) 552 { 553 void __iomem *port = ap->ioaddr.cmd_addr; 554 555 /* configure IRQ WoC */ 556 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 557 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 558 else 559 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 560 561 /* zero error counters. */ 562 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 563 writel(0x8000, port + PORT_CRC_ERR_THRESH); 564 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 565 writel(0x0000, port + PORT_DECODE_ERR_CNT); 566 writel(0x0000, port + PORT_CRC_ERR_CNT); 567 writel(0x0000, port + PORT_HSHK_ERR_CNT); 568 569 /* always use 64bit activation */ 570 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 571 572 /* clear port multiplier enable and resume bits */ 573 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 574 } 575 576 static void sil24_config_pmp(struct ata_port *ap, int attached) 577 { 578 void __iomem *port = ap->ioaddr.cmd_addr; 579 580 if (attached) 581 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); 582 else 583 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); 584 } 585 586 static void sil24_clear_pmp(struct ata_port *ap) 587 { 588 void __iomem *port = ap->ioaddr.cmd_addr; 589 int i; 590 591 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 592 593 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { 594 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; 595 596 writel(0, pmp_base + PORT_PMP_STATUS); 597 writel(0, pmp_base + PORT_PMP_QACTIVE); 598 } 599 } 600 601 static int sil24_init_port(struct ata_port *ap) 602 { 603 void __iomem *port = ap->ioaddr.cmd_addr; 604 struct sil24_port_priv *pp = ap->private_data; 605 u32 tmp; 606 607 /* clear PMP error status */ 608 if (ap->nr_pmp_links) 609 sil24_clear_pmp(ap); 610 611 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 612 ata_wait_register(port + PORT_CTRL_STAT, 613 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 614 tmp = ata_wait_register(port + PORT_CTRL_STAT, 615 PORT_CS_RDY, 0, 10, 100); 616 617 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { 618 pp->do_port_rst = 1; 619 ap->link.eh_context.i.action |= ATA_EH_HARDRESET; 620 return -EIO; 621 } 622 623 return 0; 624 } 625 626 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, 627 const struct ata_taskfile *tf, 628 int is_cmd, u32 ctrl, 629 unsigned long timeout_msec) 630 { 631 void __iomem *port = ap->ioaddr.cmd_addr; 632 struct sil24_port_priv *pp = ap->private_data; 633 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 634 dma_addr_t paddr = pp->cmd_block_dma; 635 u32 irq_enabled, irq_mask, irq_stat; 636 int rc; 637 638 prb->ctrl = cpu_to_le16(ctrl); 639 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); 640 641 /* temporarily plug completion and error interrupts */ 642 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); 643 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); 644 645 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 646 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 647 648 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 649 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, 650 10, timeout_msec); 651 652 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ 653 irq_stat >>= PORT_IRQ_RAW_SHIFT; 654 655 if (irq_stat & PORT_IRQ_COMPLETE) 656 rc = 0; 657 else { 658 /* force port into known state */ 659 sil24_init_port(ap); 660 661 if (irq_stat & PORT_IRQ_ERROR) 662 rc = -EIO; 663 else 664 rc = -EBUSY; 665 } 666 667 /* restore IRQ enabled */ 668 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); 669 670 return rc; 671 } 672 673 static int sil24_do_softreset(struct ata_link *link, unsigned int *class, 674 int pmp, unsigned long deadline) 675 { 676 struct ata_port *ap = link->ap; 677 unsigned long timeout_msec = 0; 678 struct ata_taskfile tf; 679 const char *reason; 680 int rc; 681 682 DPRINTK("ENTER\n"); 683 684 if (ata_link_offline(link)) { 685 DPRINTK("PHY reports no device\n"); 686 *class = ATA_DEV_NONE; 687 goto out; 688 } 689 690 /* put the port into known state */ 691 if (sil24_init_port(ap)) { 692 reason = "port not ready"; 693 goto err; 694 } 695 696 /* do SRST */ 697 if (time_after(deadline, jiffies)) 698 timeout_msec = jiffies_to_msecs(deadline - jiffies); 699 700 ata_tf_init(link->device, &tf); /* doesn't really matter */ 701 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, 702 timeout_msec); 703 if (rc == -EBUSY) { 704 reason = "timeout"; 705 goto err; 706 } else if (rc) { 707 reason = "SRST command error"; 708 goto err; 709 } 710 711 sil24_read_tf(ap, 0, &tf); 712 *class = ata_dev_classify(&tf); 713 714 if (*class == ATA_DEV_UNKNOWN) 715 *class = ATA_DEV_NONE; 716 717 out: 718 DPRINTK("EXIT, class=%u\n", *class); 719 return 0; 720 721 err: 722 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 723 return -EIO; 724 } 725 726 static int sil24_softreset(struct ata_link *link, unsigned int *class, 727 unsigned long deadline) 728 { 729 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline); 730 } 731 732 static int sil24_hardreset(struct ata_link *link, unsigned int *class, 733 unsigned long deadline) 734 { 735 struct ata_port *ap = link->ap; 736 void __iomem *port = ap->ioaddr.cmd_addr; 737 struct sil24_port_priv *pp = ap->private_data; 738 int did_port_rst = 0; 739 const char *reason; 740 int tout_msec, rc; 741 u32 tmp; 742 743 retry: 744 /* Sometimes, DEV_RST is not enough to recover the controller. 745 * This happens often after PM DMA CS errata. 746 */ 747 if (pp->do_port_rst) { 748 ata_port_printk(ap, KERN_WARNING, "controller in dubious " 749 "state, performing PORT_RST\n"); 750 751 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); 752 msleep(10); 753 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 754 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, 755 10, 5000); 756 757 /* restore port configuration */ 758 sil24_config_port(ap); 759 sil24_config_pmp(ap, ap->nr_pmp_links); 760 761 pp->do_port_rst = 0; 762 did_port_rst = 1; 763 } 764 765 /* sil24 does the right thing(tm) without any protection */ 766 sata_set_spd(link); 767 768 tout_msec = 100; 769 if (ata_link_online(link)) 770 tout_msec = 5000; 771 772 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 773 tmp = ata_wait_register(port + PORT_CTRL_STAT, 774 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, 775 tout_msec); 776 777 /* SStatus oscillates between zero and valid status after 778 * DEV_RST, debounce it. 779 */ 780 rc = sata_link_debounce(link, sata_deb_timing_long, deadline); 781 if (rc) { 782 reason = "PHY debouncing failed"; 783 goto err; 784 } 785 786 if (tmp & PORT_CS_DEV_RST) { 787 if (ata_link_offline(link)) 788 return 0; 789 reason = "link not ready"; 790 goto err; 791 } 792 793 /* Sil24 doesn't store signature FIS after hardreset, so we 794 * can't wait for BSY to clear. Some devices take a long time 795 * to get ready and those devices will choke if we don't wait 796 * for BSY clearance here. Tell libata to perform follow-up 797 * softreset. 798 */ 799 return -EAGAIN; 800 801 err: 802 if (!did_port_rst) { 803 pp->do_port_rst = 1; 804 goto retry; 805 } 806 807 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason); 808 return -EIO; 809 } 810 811 static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 812 struct sil24_sge *sge) 813 { 814 struct scatterlist *sg; 815 struct sil24_sge *last_sge = NULL; 816 unsigned int si; 817 818 for_each_sg(qc->sg, sg, qc->n_elem, si) { 819 sge->addr = cpu_to_le64(sg_dma_address(sg)); 820 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 821 sge->flags = 0; 822 823 last_sge = sge; 824 sge++; 825 } 826 827 last_sge->flags = cpu_to_le32(SGE_TRM); 828 } 829 830 static int sil24_qc_defer(struct ata_queued_cmd *qc) 831 { 832 struct ata_link *link = qc->dev->link; 833 struct ata_port *ap = link->ap; 834 u8 prot = qc->tf.protocol; 835 836 /* 837 * There is a bug in the chip: 838 * Port LRAM Causes the PRB/SGT Data to be Corrupted 839 * If the host issues a read request for LRAM and SActive registers 840 * while active commands are available in the port, PRB/SGT data in 841 * the LRAM can become corrupted. This issue applies only when 842 * reading from, but not writing to, the LRAM. 843 * 844 * Therefore, reading LRAM when there is no particular error [and 845 * other commands may be outstanding] is prohibited. 846 * 847 * To avoid this bug there are two situations where a command must run 848 * exclusive of any other commands on the port: 849 * 850 * - ATAPI commands which check the sense data 851 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF 852 * set. 853 * 854 */ 855 int is_excl = (ata_is_atapi(prot) || 856 (qc->flags & ATA_QCFLAG_RESULT_TF)); 857 858 if (unlikely(ap->excl_link)) { 859 if (link == ap->excl_link) { 860 if (ap->nr_active_links) 861 return ATA_DEFER_PORT; 862 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 863 } else 864 return ATA_DEFER_PORT; 865 } else if (unlikely(is_excl)) { 866 ap->excl_link = link; 867 if (ap->nr_active_links) 868 return ATA_DEFER_PORT; 869 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 870 } 871 872 return ata_std_qc_defer(qc); 873 } 874 875 static void sil24_qc_prep(struct ata_queued_cmd *qc) 876 { 877 struct ata_port *ap = qc->ap; 878 struct sil24_port_priv *pp = ap->private_data; 879 union sil24_cmd_block *cb; 880 struct sil24_prb *prb; 881 struct sil24_sge *sge; 882 u16 ctrl = 0; 883 884 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 885 886 if (!ata_is_atapi(qc->tf.protocol)) { 887 prb = &cb->ata.prb; 888 sge = cb->ata.sge; 889 } else { 890 prb = &cb->atapi.prb; 891 sge = cb->atapi.sge; 892 memset(cb->atapi.cdb, 0, 32); 893 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 894 895 if (ata_is_data(qc->tf.protocol)) { 896 if (qc->tf.flags & ATA_TFLAG_WRITE) 897 ctrl = PRB_CTRL_PACKET_WRITE; 898 else 899 ctrl = PRB_CTRL_PACKET_READ; 900 } 901 } 902 903 prb->ctrl = cpu_to_le16(ctrl); 904 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); 905 906 if (qc->flags & ATA_QCFLAG_DMAMAP) 907 sil24_fill_sg(qc, sge); 908 } 909 910 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 911 { 912 struct ata_port *ap = qc->ap; 913 struct sil24_port_priv *pp = ap->private_data; 914 void __iomem *port = ap->ioaddr.cmd_addr; 915 unsigned int tag = sil24_tag(qc->tag); 916 dma_addr_t paddr; 917 void __iomem *activate; 918 919 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 920 activate = port + PORT_CMD_ACTIVATE + tag * 8; 921 922 writel((u32)paddr, activate); 923 writel((u64)paddr >> 32, activate + 4); 924 925 return 0; 926 } 927 928 static void sil24_irq_clear(struct ata_port *ap) 929 { 930 /* unused */ 931 } 932 933 static void sil24_pmp_attach(struct ata_port *ap) 934 { 935 sil24_config_pmp(ap, 1); 936 sil24_init_port(ap); 937 } 938 939 static void sil24_pmp_detach(struct ata_port *ap) 940 { 941 sil24_init_port(ap); 942 sil24_config_pmp(ap, 0); 943 } 944 945 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class, 946 unsigned long deadline) 947 { 948 return sil24_do_softreset(link, class, link->pmp, deadline); 949 } 950 951 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, 952 unsigned long deadline) 953 { 954 int rc; 955 956 rc = sil24_init_port(link->ap); 957 if (rc) { 958 ata_link_printk(link, KERN_ERR, 959 "hardreset failed (port not ready)\n"); 960 return rc; 961 } 962 963 return sata_pmp_std_hardreset(link, class, deadline); 964 } 965 966 static void sil24_freeze(struct ata_port *ap) 967 { 968 void __iomem *port = ap->ioaddr.cmd_addr; 969 970 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 971 * PORT_IRQ_ENABLE instead. 972 */ 973 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 974 } 975 976 static void sil24_thaw(struct ata_port *ap) 977 { 978 void __iomem *port = ap->ioaddr.cmd_addr; 979 u32 tmp; 980 981 /* clear IRQ */ 982 tmp = readl(port + PORT_IRQ_STAT); 983 writel(tmp, port + PORT_IRQ_STAT); 984 985 /* turn IRQ back on */ 986 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 987 } 988 989 static void sil24_error_intr(struct ata_port *ap) 990 { 991 void __iomem *port = ap->ioaddr.cmd_addr; 992 struct sil24_port_priv *pp = ap->private_data; 993 struct ata_queued_cmd *qc = NULL; 994 struct ata_link *link; 995 struct ata_eh_info *ehi; 996 int abort = 0, freeze = 0; 997 u32 irq_stat; 998 999 /* on error, we need to clear IRQ explicitly */ 1000 irq_stat = readl(port + PORT_IRQ_STAT); 1001 writel(irq_stat, port + PORT_IRQ_STAT); 1002 1003 /* first, analyze and record host port events */ 1004 link = &ap->link; 1005 ehi = &link->eh_info; 1006 ata_ehi_clear_desc(ehi); 1007 1008 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 1009 1010 if (irq_stat & PORT_IRQ_SDB_NOTIFY) { 1011 ata_ehi_push_desc(ehi, "SDB notify"); 1012 sata_async_notification(ap); 1013 } 1014 1015 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 1016 ata_ehi_hotplugged(ehi); 1017 ata_ehi_push_desc(ehi, "%s", 1018 irq_stat & PORT_IRQ_PHYRDY_CHG ? 1019 "PHY RDY changed" : "device exchanged"); 1020 freeze = 1; 1021 } 1022 1023 if (irq_stat & PORT_IRQ_UNK_FIS) { 1024 ehi->err_mask |= AC_ERR_HSM; 1025 ehi->action |= ATA_EH_SOFTRESET; 1026 ata_ehi_push_desc(ehi, "unknown FIS"); 1027 freeze = 1; 1028 } 1029 1030 /* deal with command error */ 1031 if (irq_stat & PORT_IRQ_ERROR) { 1032 struct sil24_cerr_info *ci = NULL; 1033 unsigned int err_mask = 0, action = 0; 1034 u32 context, cerr; 1035 int pmp; 1036 1037 abort = 1; 1038 1039 /* DMA Context Switch Failure in Port Multiplier Mode 1040 * errata. If we have active commands to 3 or more 1041 * devices, any error condition on active devices can 1042 * corrupt DMA context switching. 1043 */ 1044 if (ap->nr_active_links >= 3) { 1045 ehi->err_mask |= AC_ERR_OTHER; 1046 ehi->action |= ATA_EH_HARDRESET; 1047 ata_ehi_push_desc(ehi, "PMP DMA CS errata"); 1048 pp->do_port_rst = 1; 1049 freeze = 1; 1050 } 1051 1052 /* find out the offending link and qc */ 1053 if (ap->nr_pmp_links) { 1054 context = readl(port + PORT_CONTEXT); 1055 pmp = (context >> 5) & 0xf; 1056 1057 if (pmp < ap->nr_pmp_links) { 1058 link = &ap->pmp_link[pmp]; 1059 ehi = &link->eh_info; 1060 qc = ata_qc_from_tag(ap, link->active_tag); 1061 1062 ata_ehi_clear_desc(ehi); 1063 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", 1064 irq_stat); 1065 } else { 1066 err_mask |= AC_ERR_HSM; 1067 action |= ATA_EH_HARDRESET; 1068 freeze = 1; 1069 } 1070 } else 1071 qc = ata_qc_from_tag(ap, link->active_tag); 1072 1073 /* analyze CMD_ERR */ 1074 cerr = readl(port + PORT_CMD_ERR); 1075 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 1076 ci = &sil24_cerr_db[cerr]; 1077 1078 if (ci && ci->desc) { 1079 err_mask |= ci->err_mask; 1080 action |= ci->action; 1081 if (action & ATA_EH_RESET_MASK) 1082 freeze = 1; 1083 ata_ehi_push_desc(ehi, "%s", ci->desc); 1084 } else { 1085 err_mask |= AC_ERR_OTHER; 1086 action |= ATA_EH_SOFTRESET; 1087 freeze = 1; 1088 ata_ehi_push_desc(ehi, "unknown command error %d", 1089 cerr); 1090 } 1091 1092 /* record error info */ 1093 if (qc) { 1094 sil24_read_tf(ap, qc->tag, &pp->tf); 1095 qc->err_mask |= err_mask; 1096 } else 1097 ehi->err_mask |= err_mask; 1098 1099 ehi->action |= action; 1100 1101 /* if PMP, resume */ 1102 if (ap->nr_pmp_links) 1103 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); 1104 } 1105 1106 /* freeze or abort */ 1107 if (freeze) 1108 ata_port_freeze(ap); 1109 else if (abort) { 1110 if (qc) 1111 ata_link_abort(qc->dev->link); 1112 else 1113 ata_port_abort(ap); 1114 } 1115 } 1116 1117 static void sil24_finish_qc(struct ata_queued_cmd *qc) 1118 { 1119 struct ata_port *ap = qc->ap; 1120 struct sil24_port_priv *pp = ap->private_data; 1121 1122 if (qc->flags & ATA_QCFLAG_RESULT_TF) 1123 sil24_read_tf(ap, qc->tag, &pp->tf); 1124 } 1125 1126 static inline void sil24_host_intr(struct ata_port *ap) 1127 { 1128 void __iomem *port = ap->ioaddr.cmd_addr; 1129 u32 slot_stat, qc_active; 1130 int rc; 1131 1132 /* If PCIX_IRQ_WOC, there's an inherent race window between 1133 * clearing IRQ pending status and reading PORT_SLOT_STAT 1134 * which may cause spurious interrupts afterwards. This is 1135 * unavoidable and much better than losing interrupts which 1136 * happens if IRQ pending is cleared after reading 1137 * PORT_SLOT_STAT. 1138 */ 1139 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 1140 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 1141 1142 slot_stat = readl(port + PORT_SLOT_STAT); 1143 1144 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 1145 sil24_error_intr(ap); 1146 return; 1147 } 1148 1149 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 1150 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); 1151 if (rc > 0) 1152 return; 1153 if (rc < 0) { 1154 struct ata_eh_info *ehi = &ap->link.eh_info; 1155 ehi->err_mask |= AC_ERR_HSM; 1156 ehi->action |= ATA_EH_SOFTRESET; 1157 ata_port_freeze(ap); 1158 return; 1159 } 1160 1161 /* spurious interrupts are expected if PCIX_IRQ_WOC */ 1162 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) 1163 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 1164 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 1165 slot_stat, ap->link.active_tag, ap->link.sactive); 1166 } 1167 1168 static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 1169 { 1170 struct ata_host *host = dev_instance; 1171 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1172 unsigned handled = 0; 1173 u32 status; 1174 int i; 1175 1176 status = readl(host_base + HOST_IRQ_STAT); 1177 1178 if (status == 0xffffffff) { 1179 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 1180 "PCI fault or device removal?\n"); 1181 goto out; 1182 } 1183 1184 if (!(status & IRQ_STAT_4PORTS)) 1185 goto out; 1186 1187 spin_lock(&host->lock); 1188 1189 for (i = 0; i < host->n_ports; i++) 1190 if (status & (1 << i)) { 1191 struct ata_port *ap = host->ports[i]; 1192 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 1193 sil24_host_intr(ap); 1194 handled++; 1195 } else 1196 printk(KERN_ERR DRV_NAME 1197 ": interrupt from disabled port %d\n", i); 1198 } 1199 1200 spin_unlock(&host->lock); 1201 out: 1202 return IRQ_RETVAL(handled); 1203 } 1204 1205 static void sil24_error_handler(struct ata_port *ap) 1206 { 1207 struct sil24_port_priv *pp = ap->private_data; 1208 1209 if (sil24_init_port(ap)) 1210 ata_eh_freeze_port(ap); 1211 1212 /* perform recovery */ 1213 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, 1214 ata_std_postreset, sata_pmp_std_prereset, 1215 sil24_pmp_softreset, sil24_pmp_hardreset, 1216 sata_pmp_std_postreset); 1217 1218 pp->do_port_rst = 0; 1219 } 1220 1221 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 1222 { 1223 struct ata_port *ap = qc->ap; 1224 1225 /* make DMA engine forget about the failed command */ 1226 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) 1227 ata_eh_freeze_port(ap); 1228 } 1229 1230 static int sil24_port_start(struct ata_port *ap) 1231 { 1232 struct device *dev = ap->host->dev; 1233 struct sil24_port_priv *pp; 1234 union sil24_cmd_block *cb; 1235 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 1236 dma_addr_t cb_dma; 1237 1238 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1239 if (!pp) 1240 return -ENOMEM; 1241 1242 pp->tf.command = ATA_DRDY; 1243 1244 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 1245 if (!cb) 1246 return -ENOMEM; 1247 memset(cb, 0, cb_size); 1248 1249 pp->cmd_block = cb; 1250 pp->cmd_block_dma = cb_dma; 1251 1252 ap->private_data = pp; 1253 1254 return 0; 1255 } 1256 1257 static void sil24_init_controller(struct ata_host *host) 1258 { 1259 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1260 u32 tmp; 1261 int i; 1262 1263 /* GPIO off */ 1264 writel(0, host_base + HOST_FLASH_CMD); 1265 1266 /* clear global reset & mask interrupts during initialization */ 1267 writel(0, host_base + HOST_CTRL); 1268 1269 /* init ports */ 1270 for (i = 0; i < host->n_ports; i++) { 1271 struct ata_port *ap = host->ports[i]; 1272 void __iomem *port = ap->ioaddr.cmd_addr; 1273 1274 /* Initial PHY setting */ 1275 writel(0x20c, port + PORT_PHY_CFG); 1276 1277 /* Clear port RST */ 1278 tmp = readl(port + PORT_CTRL_STAT); 1279 if (tmp & PORT_CS_PORT_RST) { 1280 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 1281 tmp = ata_wait_register(port + PORT_CTRL_STAT, 1282 PORT_CS_PORT_RST, 1283 PORT_CS_PORT_RST, 10, 100); 1284 if (tmp & PORT_CS_PORT_RST) 1285 dev_printk(KERN_ERR, host->dev, 1286 "failed to clear port RST\n"); 1287 } 1288 1289 /* configure port */ 1290 sil24_config_port(ap); 1291 } 1292 1293 /* Turn on interrupts */ 1294 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1295 } 1296 1297 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1298 { 1299 extern int __MARKER__sil24_cmd_block_is_sized_wrongly; 1300 static int printed_version; 1301 struct ata_port_info pi = sil24_port_info[ent->driver_data]; 1302 const struct ata_port_info *ppi[] = { &pi, NULL }; 1303 void __iomem * const *iomap; 1304 struct ata_host *host; 1305 int i, rc; 1306 u32 tmp; 1307 1308 /* cause link error if sil24_cmd_block is sized wrongly */ 1309 if (sizeof(union sil24_cmd_block) != PAGE_SIZE) 1310 __MARKER__sil24_cmd_block_is_sized_wrongly = 1; 1311 1312 if (!printed_version++) 1313 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1314 1315 /* acquire resources */ 1316 rc = pcim_enable_device(pdev); 1317 if (rc) 1318 return rc; 1319 1320 rc = pcim_iomap_regions(pdev, 1321 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1322 DRV_NAME); 1323 if (rc) 1324 return rc; 1325 iomap = pcim_iomap_table(pdev); 1326 1327 /* apply workaround for completion IRQ loss on PCI-X errata */ 1328 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1329 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); 1330 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1331 dev_printk(KERN_INFO, &pdev->dev, 1332 "Applying completion IRQ loss on PCI-X " 1333 "errata fix\n"); 1334 else 1335 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1336 } 1337 1338 /* allocate and fill host */ 1339 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1340 SIL24_FLAG2NPORTS(ppi[0]->flags)); 1341 if (!host) 1342 return -ENOMEM; 1343 host->iomap = iomap; 1344 1345 for (i = 0; i < host->n_ports; i++) { 1346 struct ata_port *ap = host->ports[i]; 1347 size_t offset = ap->port_no * PORT_REGS_SIZE; 1348 void __iomem *port = iomap[SIL24_PORT_BAR] + offset; 1349 1350 host->ports[i]->ioaddr.cmd_addr = port; 1351 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL; 1352 1353 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); 1354 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port"); 1355 } 1356 1357 /* configure and activate the device */ 1358 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1359 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1360 if (rc) { 1361 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1362 if (rc) { 1363 dev_printk(KERN_ERR, &pdev->dev, 1364 "64-bit DMA enable failed\n"); 1365 return rc; 1366 } 1367 } 1368 } else { 1369 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1370 if (rc) { 1371 dev_printk(KERN_ERR, &pdev->dev, 1372 "32-bit DMA enable failed\n"); 1373 return rc; 1374 } 1375 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1376 if (rc) { 1377 dev_printk(KERN_ERR, &pdev->dev, 1378 "32-bit consistent DMA enable failed\n"); 1379 return rc; 1380 } 1381 } 1382 1383 sil24_init_controller(host); 1384 1385 pci_set_master(pdev); 1386 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, 1387 &sil24_sht); 1388 } 1389 1390 #ifdef CONFIG_PM 1391 static int sil24_pci_device_resume(struct pci_dev *pdev) 1392 { 1393 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1394 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1395 int rc; 1396 1397 rc = ata_pci_device_do_resume(pdev); 1398 if (rc) 1399 return rc; 1400 1401 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1402 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1403 1404 sil24_init_controller(host); 1405 1406 ata_host_resume(host); 1407 1408 return 0; 1409 } 1410 1411 static int sil24_port_resume(struct ata_port *ap) 1412 { 1413 sil24_config_pmp(ap, ap->nr_pmp_links); 1414 return 0; 1415 } 1416 #endif 1417 1418 static int __init sil24_init(void) 1419 { 1420 return pci_register_driver(&sil24_pci_driver); 1421 } 1422 1423 static void __exit sil24_exit(void) 1424 { 1425 pci_unregister_driver(&sil24_pci_driver); 1426 } 1427 1428 MODULE_AUTHOR("Tejun Heo"); 1429 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1430 MODULE_LICENSE("GPL"); 1431 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1432 1433 module_init(sil24_init); 1434 module_exit(sil24_exit); 1435