1c6fd2807SJeff Garzik /* 2c6fd2807SJeff Garzik * sata_sil.c - Silicon Image SATA 3c6fd2807SJeff Garzik * 4c6fd2807SJeff Garzik * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5c6fd2807SJeff Garzik * Please ALWAYS copy linux-ide@vger.kernel.org 6c6fd2807SJeff Garzik * on emails. 7c6fd2807SJeff Garzik * 8c6fd2807SJeff Garzik * Copyright 2003-2005 Red Hat, Inc. 9c6fd2807SJeff Garzik * Copyright 2003 Benjamin Herrenschmidt 10c6fd2807SJeff Garzik * 11c6fd2807SJeff Garzik * 12c6fd2807SJeff Garzik * This program is free software; you can redistribute it and/or modify 13c6fd2807SJeff Garzik * it under the terms of the GNU General Public License as published by 14c6fd2807SJeff Garzik * the Free Software Foundation; either version 2, or (at your option) 15c6fd2807SJeff Garzik * any later version. 16c6fd2807SJeff Garzik * 17c6fd2807SJeff Garzik * This program is distributed in the hope that it will be useful, 18c6fd2807SJeff Garzik * but WITHOUT ANY WARRANTY; without even the implied warranty of 19c6fd2807SJeff Garzik * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20c6fd2807SJeff Garzik * GNU General Public License for more details. 21c6fd2807SJeff Garzik * 22c6fd2807SJeff Garzik * You should have received a copy of the GNU General Public License 23c6fd2807SJeff Garzik * along with this program; see the file COPYING. If not, write to 24c6fd2807SJeff Garzik * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25c6fd2807SJeff Garzik * 26c6fd2807SJeff Garzik * 27c6fd2807SJeff Garzik * libata documentation is available via 'make {ps|pdf}docs', 28c6fd2807SJeff Garzik * as Documentation/DocBook/libata.* 29c6fd2807SJeff Garzik * 30c6fd2807SJeff Garzik * Documentation for SiI 3112: 31c6fd2807SJeff Garzik * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 32c6fd2807SJeff Garzik * 33c6fd2807SJeff Garzik * Other errata and documentation available under NDA. 34c6fd2807SJeff Garzik * 35c6fd2807SJeff Garzik */ 36c6fd2807SJeff Garzik 37c6fd2807SJeff Garzik #include <linux/kernel.h> 38c6fd2807SJeff Garzik #include <linux/module.h> 39c6fd2807SJeff Garzik #include <linux/pci.h> 40c6fd2807SJeff Garzik #include <linux/init.h> 41c6fd2807SJeff Garzik #include <linux/blkdev.h> 42c6fd2807SJeff Garzik #include <linux/delay.h> 43c6fd2807SJeff Garzik #include <linux/interrupt.h> 44c6fd2807SJeff Garzik #include <linux/device.h> 45c6fd2807SJeff Garzik #include <scsi/scsi_host.h> 46c6fd2807SJeff Garzik #include <linux/libata.h> 47c6fd2807SJeff Garzik 48c6fd2807SJeff Garzik #define DRV_NAME "sata_sil" 499d2c7c75SAlan Cox #define DRV_VERSION "2.2" 50c6fd2807SJeff Garzik 51c6fd2807SJeff Garzik enum { 520d5ff566STejun Heo SIL_MMIO_BAR = 5, 530d5ff566STejun Heo 54c6fd2807SJeff Garzik /* 55c6fd2807SJeff Garzik * host flags 56c6fd2807SJeff Garzik */ 57c6fd2807SJeff Garzik SIL_FLAG_NO_SATA_IRQ = (1 << 28), 58c6fd2807SJeff Garzik SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), 59c6fd2807SJeff Garzik SIL_FLAG_MOD15WRITE = (1 << 30), 60c6fd2807SJeff Garzik 61cca3974eSJeff Garzik SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 62c6fd2807SJeff Garzik ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, 63c6fd2807SJeff Garzik 64c6fd2807SJeff Garzik /* 65c6fd2807SJeff Garzik * Controller IDs 66c6fd2807SJeff Garzik */ 67c6fd2807SJeff Garzik sil_3112 = 0, 68c6fd2807SJeff Garzik sil_3112_no_sata_irq = 1, 69c6fd2807SJeff Garzik sil_3512 = 2, 70c6fd2807SJeff Garzik sil_3114 = 3, 71c6fd2807SJeff Garzik 72c6fd2807SJeff Garzik /* 73c6fd2807SJeff Garzik * Register offsets 74c6fd2807SJeff Garzik */ 75c6fd2807SJeff Garzik SIL_SYSCFG = 0x48, 76c6fd2807SJeff Garzik 77c6fd2807SJeff Garzik /* 78c6fd2807SJeff Garzik * Register bits 79c6fd2807SJeff Garzik */ 80c6fd2807SJeff Garzik /* SYSCFG */ 81c6fd2807SJeff Garzik SIL_MASK_IDE0_INT = (1 << 22), 82c6fd2807SJeff Garzik SIL_MASK_IDE1_INT = (1 << 23), 83c6fd2807SJeff Garzik SIL_MASK_IDE2_INT = (1 << 24), 84c6fd2807SJeff Garzik SIL_MASK_IDE3_INT = (1 << 25), 85c6fd2807SJeff Garzik SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, 86c6fd2807SJeff Garzik SIL_MASK_4PORT = SIL_MASK_2PORT | 87c6fd2807SJeff Garzik SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, 88c6fd2807SJeff Garzik 89c6fd2807SJeff Garzik /* BMDMA/BMDMA2 */ 90c6fd2807SJeff Garzik SIL_INTR_STEERING = (1 << 1), 91c6fd2807SJeff Garzik 92c6fd2807SJeff Garzik SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ 93c6fd2807SJeff Garzik SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ 94c6fd2807SJeff Garzik SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ 95c6fd2807SJeff Garzik SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ 96c6fd2807SJeff Garzik SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ 97c6fd2807SJeff Garzik SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ 98c6fd2807SJeff Garzik SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ 99c6fd2807SJeff Garzik SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ 100c6fd2807SJeff Garzik SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ 101c6fd2807SJeff Garzik SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ 102c6fd2807SJeff Garzik 103c6fd2807SJeff Garzik /* SIEN */ 104c6fd2807SJeff Garzik SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ 105c6fd2807SJeff Garzik 106c6fd2807SJeff Garzik /* 107c6fd2807SJeff Garzik * Others 108c6fd2807SJeff Garzik */ 109c6fd2807SJeff Garzik SIL_QUIRK_MOD15WRITE = (1 << 0), 110c6fd2807SJeff Garzik SIL_QUIRK_UDMA5MAX = (1 << 1), 111c6fd2807SJeff Garzik }; 112c6fd2807SJeff Garzik 113c6fd2807SJeff Garzik static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 114281d426cSAlexey Dobriyan #ifdef CONFIG_PM 115c6fd2807SJeff Garzik static int sil_pci_device_resume(struct pci_dev *pdev); 116281d426cSAlexey Dobriyan #endif 117cd0d3bbcSAlan static void sil_dev_config(struct ata_device *dev); 118c6fd2807SJeff Garzik static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); 119c6fd2807SJeff Garzik static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 1209d2c7c75SAlan Cox static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed); 121c6fd2807SJeff Garzik static void sil_freeze(struct ata_port *ap); 122c6fd2807SJeff Garzik static void sil_thaw(struct ata_port *ap); 123c6fd2807SJeff Garzik 124c6fd2807SJeff Garzik 125c6fd2807SJeff Garzik static const struct pci_device_id sil_pci_tbl[] = { 12654bb3a94SJeff Garzik { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, 12754bb3a94SJeff Garzik { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, 12854bb3a94SJeff Garzik { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, 12954bb3a94SJeff Garzik { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, 13054bb3a94SJeff Garzik { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, 13154bb3a94SJeff Garzik { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, 13254bb3a94SJeff Garzik { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, 13354bb3a94SJeff Garzik 134c6fd2807SJeff Garzik { } /* terminate list */ 135c6fd2807SJeff Garzik }; 136c6fd2807SJeff Garzik 137c6fd2807SJeff Garzik 138c6fd2807SJeff Garzik /* TODO firmware versions should be added - eric */ 139c6fd2807SJeff Garzik static const struct sil_drivelist { 140c6fd2807SJeff Garzik const char * product; 141c6fd2807SJeff Garzik unsigned int quirk; 142c6fd2807SJeff Garzik } sil_blacklist [] = { 143c6fd2807SJeff Garzik { "ST320012AS", SIL_QUIRK_MOD15WRITE }, 144c6fd2807SJeff Garzik { "ST330013AS", SIL_QUIRK_MOD15WRITE }, 145c6fd2807SJeff Garzik { "ST340017AS", SIL_QUIRK_MOD15WRITE }, 146c6fd2807SJeff Garzik { "ST360015AS", SIL_QUIRK_MOD15WRITE }, 147c6fd2807SJeff Garzik { "ST380023AS", SIL_QUIRK_MOD15WRITE }, 148c6fd2807SJeff Garzik { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, 149c6fd2807SJeff Garzik { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, 150c6fd2807SJeff Garzik { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, 151c6fd2807SJeff Garzik { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, 152c6fd2807SJeff Garzik { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, 153c6fd2807SJeff Garzik { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, 154c6fd2807SJeff Garzik { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, 155c6fd2807SJeff Garzik { } 156c6fd2807SJeff Garzik }; 157c6fd2807SJeff Garzik 158c6fd2807SJeff Garzik static struct pci_driver sil_pci_driver = { 159c6fd2807SJeff Garzik .name = DRV_NAME, 160c6fd2807SJeff Garzik .id_table = sil_pci_tbl, 161c6fd2807SJeff Garzik .probe = sil_init_one, 162c6fd2807SJeff Garzik .remove = ata_pci_remove_one, 163281d426cSAlexey Dobriyan #ifdef CONFIG_PM 164c6fd2807SJeff Garzik .suspend = ata_pci_device_suspend, 165c6fd2807SJeff Garzik .resume = sil_pci_device_resume, 166281d426cSAlexey Dobriyan #endif 167c6fd2807SJeff Garzik }; 168c6fd2807SJeff Garzik 169c6fd2807SJeff Garzik static struct scsi_host_template sil_sht = { 170c6fd2807SJeff Garzik .module = THIS_MODULE, 171c6fd2807SJeff Garzik .name = DRV_NAME, 172c6fd2807SJeff Garzik .ioctl = ata_scsi_ioctl, 173c6fd2807SJeff Garzik .queuecommand = ata_scsi_queuecmd, 174c6fd2807SJeff Garzik .can_queue = ATA_DEF_QUEUE, 175c6fd2807SJeff Garzik .this_id = ATA_SHT_THIS_ID, 176c6fd2807SJeff Garzik .sg_tablesize = LIBATA_MAX_PRD, 177c6fd2807SJeff Garzik .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 178c6fd2807SJeff Garzik .emulated = ATA_SHT_EMULATED, 179c6fd2807SJeff Garzik .use_clustering = ATA_SHT_USE_CLUSTERING, 180c6fd2807SJeff Garzik .proc_name = DRV_NAME, 181c6fd2807SJeff Garzik .dma_boundary = ATA_DMA_BOUNDARY, 182c6fd2807SJeff Garzik .slave_configure = ata_scsi_slave_config, 183c6fd2807SJeff Garzik .slave_destroy = ata_scsi_slave_destroy, 184c6fd2807SJeff Garzik .bios_param = ata_std_bios_param, 185438ac6d5STejun Heo #ifdef CONFIG_PM 186c6fd2807SJeff Garzik .suspend = ata_scsi_device_suspend, 187c6fd2807SJeff Garzik .resume = ata_scsi_device_resume, 188438ac6d5STejun Heo #endif 189c6fd2807SJeff Garzik }; 190c6fd2807SJeff Garzik 191c6fd2807SJeff Garzik static const struct ata_port_operations sil_ops = { 192c6fd2807SJeff Garzik .port_disable = ata_port_disable, 193c6fd2807SJeff Garzik .dev_config = sil_dev_config, 194c6fd2807SJeff Garzik .tf_load = ata_tf_load, 195c6fd2807SJeff Garzik .tf_read = ata_tf_read, 196c6fd2807SJeff Garzik .check_status = ata_check_status, 197c6fd2807SJeff Garzik .exec_command = ata_exec_command, 198c6fd2807SJeff Garzik .dev_select = ata_std_dev_select, 1999d2c7c75SAlan Cox .set_mode = sil_set_mode, 200c6fd2807SJeff Garzik .bmdma_setup = ata_bmdma_setup, 201c6fd2807SJeff Garzik .bmdma_start = ata_bmdma_start, 202c6fd2807SJeff Garzik .bmdma_stop = ata_bmdma_stop, 203c6fd2807SJeff Garzik .bmdma_status = ata_bmdma_status, 204c6fd2807SJeff Garzik .qc_prep = ata_qc_prep, 205c6fd2807SJeff Garzik .qc_issue = ata_qc_issue_prot, 2060d5ff566STejun Heo .data_xfer = ata_data_xfer, 207c6fd2807SJeff Garzik .freeze = sil_freeze, 208c6fd2807SJeff Garzik .thaw = sil_thaw, 209c6fd2807SJeff Garzik .error_handler = ata_bmdma_error_handler, 210c6fd2807SJeff Garzik .post_internal_cmd = ata_bmdma_post_internal_cmd, 211c6fd2807SJeff Garzik .irq_clear = ata_bmdma_irq_clear, 212246ce3b6SAkira Iguchi .irq_on = ata_irq_on, 213246ce3b6SAkira Iguchi .irq_ack = ata_irq_ack, 214c6fd2807SJeff Garzik .scr_read = sil_scr_read, 215c6fd2807SJeff Garzik .scr_write = sil_scr_write, 216c6fd2807SJeff Garzik .port_start = ata_port_start, 217c6fd2807SJeff Garzik }; 218c6fd2807SJeff Garzik 219c6fd2807SJeff Garzik static const struct ata_port_info sil_port_info[] = { 220c6fd2807SJeff Garzik /* sil_3112 */ 221c6fd2807SJeff Garzik { 222cca3974eSJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 223c6fd2807SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 224c6fd2807SJeff Garzik .mwdma_mask = 0x07, /* mwdma0-2 */ 225c6fd2807SJeff Garzik .udma_mask = 0x3f, /* udma0-5 */ 226c6fd2807SJeff Garzik .port_ops = &sil_ops, 227c6fd2807SJeff Garzik }, 228c6fd2807SJeff Garzik /* sil_3112_no_sata_irq */ 229c6fd2807SJeff Garzik { 230cca3974eSJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 231c6fd2807SJeff Garzik SIL_FLAG_NO_SATA_IRQ, 232c6fd2807SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 233c6fd2807SJeff Garzik .mwdma_mask = 0x07, /* mwdma0-2 */ 234c6fd2807SJeff Garzik .udma_mask = 0x3f, /* udma0-5 */ 235c6fd2807SJeff Garzik .port_ops = &sil_ops, 236c6fd2807SJeff Garzik }, 237c6fd2807SJeff Garzik /* sil_3512 */ 238c6fd2807SJeff Garzik { 239cca3974eSJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 240c6fd2807SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 241c6fd2807SJeff Garzik .mwdma_mask = 0x07, /* mwdma0-2 */ 242c6fd2807SJeff Garzik .udma_mask = 0x3f, /* udma0-5 */ 243c6fd2807SJeff Garzik .port_ops = &sil_ops, 244c6fd2807SJeff Garzik }, 245c6fd2807SJeff Garzik /* sil_3114 */ 246c6fd2807SJeff Garzik { 247cca3974eSJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 248c6fd2807SJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 249c6fd2807SJeff Garzik .mwdma_mask = 0x07, /* mwdma0-2 */ 250c6fd2807SJeff Garzik .udma_mask = 0x3f, /* udma0-5 */ 251c6fd2807SJeff Garzik .port_ops = &sil_ops, 252c6fd2807SJeff Garzik }, 253c6fd2807SJeff Garzik }; 254c6fd2807SJeff Garzik 255c6fd2807SJeff Garzik /* per-port register offsets */ 256c6fd2807SJeff Garzik /* TODO: we can probably calculate rather than use a table */ 257c6fd2807SJeff Garzik static const struct { 258c6fd2807SJeff Garzik unsigned long tf; /* ATA taskfile register block */ 259c6fd2807SJeff Garzik unsigned long ctl; /* ATA control/altstatus register block */ 260c6fd2807SJeff Garzik unsigned long bmdma; /* DMA register block */ 261c6fd2807SJeff Garzik unsigned long bmdma2; /* DMA register block #2 */ 262c6fd2807SJeff Garzik unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ 263c6fd2807SJeff Garzik unsigned long scr; /* SATA control register block */ 264c6fd2807SJeff Garzik unsigned long sien; /* SATA Interrupt Enable register */ 265c6fd2807SJeff Garzik unsigned long xfer_mode;/* data transfer mode register */ 266c6fd2807SJeff Garzik unsigned long sfis_cfg; /* SATA FIS reception config register */ 267c6fd2807SJeff Garzik } sil_port[] = { 268c6fd2807SJeff Garzik /* port 0 ... */ 269c6fd2807SJeff Garzik { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, 270c6fd2807SJeff Garzik { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, 271c6fd2807SJeff Garzik { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, 272c6fd2807SJeff Garzik { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, 273c6fd2807SJeff Garzik /* ... port 3 */ 274c6fd2807SJeff Garzik }; 275c6fd2807SJeff Garzik 276c6fd2807SJeff Garzik MODULE_AUTHOR("Jeff Garzik"); 277c6fd2807SJeff Garzik MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); 278c6fd2807SJeff Garzik MODULE_LICENSE("GPL"); 279c6fd2807SJeff Garzik MODULE_DEVICE_TABLE(pci, sil_pci_tbl); 280c6fd2807SJeff Garzik MODULE_VERSION(DRV_VERSION); 281c6fd2807SJeff Garzik 282c6fd2807SJeff Garzik static int slow_down = 0; 283c6fd2807SJeff Garzik module_param(slow_down, int, 0444); 284c6fd2807SJeff Garzik MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); 285c6fd2807SJeff Garzik 286c6fd2807SJeff Garzik 287c6fd2807SJeff Garzik static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) 288c6fd2807SJeff Garzik { 289c6fd2807SJeff Garzik u8 cache_line = 0; 290c6fd2807SJeff Garzik pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); 291c6fd2807SJeff Garzik return cache_line; 292c6fd2807SJeff Garzik } 293c6fd2807SJeff Garzik 2949d2c7c75SAlan Cox /** 2959d2c7c75SAlan Cox * sil_set_mode - wrap set_mode functions 2969d2c7c75SAlan Cox * @ap: port to set up 2979d2c7c75SAlan Cox * @r_failed: returned device when we fail 2989d2c7c75SAlan Cox * 2999d2c7c75SAlan Cox * Wrap the libata method for device setup as after the setup we need 3009d2c7c75SAlan Cox * to inspect the results and do some configuration work 3019d2c7c75SAlan Cox */ 3029d2c7c75SAlan Cox 3039d2c7c75SAlan Cox static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed) 304c6fd2807SJeff Garzik { 305cca3974eSJeff Garzik struct ata_host *host = ap->host; 306c6fd2807SJeff Garzik struct ata_device *dev; 3070d5ff566STejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 3080d5ff566STejun Heo void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; 309c6fd2807SJeff Garzik u32 tmp, dev_mode[2]; 310c6fd2807SJeff Garzik unsigned int i; 3119d2c7c75SAlan Cox int rc; 3129d2c7c75SAlan Cox 3139d2c7c75SAlan Cox rc = ata_do_set_mode(ap, r_failed); 3149d2c7c75SAlan Cox if (rc) 3159d2c7c75SAlan Cox return rc; 316c6fd2807SJeff Garzik 317c6fd2807SJeff Garzik for (i = 0; i < 2; i++) { 318c6fd2807SJeff Garzik dev = &ap->device[i]; 319c6fd2807SJeff Garzik if (!ata_dev_enabled(dev)) 320c6fd2807SJeff Garzik dev_mode[i] = 0; /* PIO0/1/2 */ 321c6fd2807SJeff Garzik else if (dev->flags & ATA_DFLAG_PIO) 322c6fd2807SJeff Garzik dev_mode[i] = 1; /* PIO3/4 */ 323c6fd2807SJeff Garzik else 324c6fd2807SJeff Garzik dev_mode[i] = 3; /* UDMA */ 325c6fd2807SJeff Garzik /* value 2 indicates MDMA */ 326c6fd2807SJeff Garzik } 327c6fd2807SJeff Garzik 328c6fd2807SJeff Garzik tmp = readl(addr); 329c6fd2807SJeff Garzik tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); 330c6fd2807SJeff Garzik tmp |= dev_mode[0]; 331c6fd2807SJeff Garzik tmp |= (dev_mode[1] << 4); 332c6fd2807SJeff Garzik writel(tmp, addr); 333c6fd2807SJeff Garzik readl(addr); /* flush */ 3349d2c7c75SAlan Cox return 0; 335c6fd2807SJeff Garzik } 336c6fd2807SJeff Garzik 3370d5ff566STejun Heo static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) 338c6fd2807SJeff Garzik { 3390d5ff566STejun Heo void __iomem *offset = ap->ioaddr.scr_addr; 340c6fd2807SJeff Garzik 341c6fd2807SJeff Garzik switch (sc_reg) { 342c6fd2807SJeff Garzik case SCR_STATUS: 343c6fd2807SJeff Garzik return offset + 4; 344c6fd2807SJeff Garzik case SCR_ERROR: 345c6fd2807SJeff Garzik return offset + 8; 346c6fd2807SJeff Garzik case SCR_CONTROL: 347c6fd2807SJeff Garzik return offset; 348c6fd2807SJeff Garzik default: 349c6fd2807SJeff Garzik /* do nothing */ 350c6fd2807SJeff Garzik break; 351c6fd2807SJeff Garzik } 352c6fd2807SJeff Garzik 3538d9db2d2SRandy Dunlap return NULL; 354c6fd2807SJeff Garzik } 355c6fd2807SJeff Garzik 356c6fd2807SJeff Garzik static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) 357c6fd2807SJeff Garzik { 3580d5ff566STejun Heo void __iomem *mmio = sil_scr_addr(ap, sc_reg); 359c6fd2807SJeff Garzik if (mmio) 360c6fd2807SJeff Garzik return readl(mmio); 361c6fd2807SJeff Garzik return 0xffffffffU; 362c6fd2807SJeff Garzik } 363c6fd2807SJeff Garzik 364c6fd2807SJeff Garzik static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) 365c6fd2807SJeff Garzik { 3660d5ff566STejun Heo void __iomem *mmio = sil_scr_addr(ap, sc_reg); 367c6fd2807SJeff Garzik if (mmio) 368c6fd2807SJeff Garzik writel(val, mmio); 369c6fd2807SJeff Garzik } 370c6fd2807SJeff Garzik 371c6fd2807SJeff Garzik static void sil_host_intr(struct ata_port *ap, u32 bmdma2) 372c6fd2807SJeff Garzik { 373ea54763fSTejun Heo struct ata_eh_info *ehi = &ap->eh_info; 374c6fd2807SJeff Garzik struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); 375c6fd2807SJeff Garzik u8 status; 376c6fd2807SJeff Garzik 377c6fd2807SJeff Garzik if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { 378c6fd2807SJeff Garzik u32 serror; 379c6fd2807SJeff Garzik 380c6fd2807SJeff Garzik /* SIEN doesn't mask SATA IRQs on some 3112s. Those 381c6fd2807SJeff Garzik * controllers continue to assert IRQ as long as 382c6fd2807SJeff Garzik * SError bits are pending. Clear SError immediately. 383c6fd2807SJeff Garzik */ 384c6fd2807SJeff Garzik serror = sil_scr_read(ap, SCR_ERROR); 385c6fd2807SJeff Garzik sil_scr_write(ap, SCR_ERROR, serror); 386c6fd2807SJeff Garzik 387c6fd2807SJeff Garzik /* Trigger hotplug and accumulate SError only if the 388c6fd2807SJeff Garzik * port isn't already frozen. Otherwise, PHY events 389c6fd2807SJeff Garzik * during hardreset makes controllers with broken SIEN 390c6fd2807SJeff Garzik * repeat probing needlessly. 391c6fd2807SJeff Garzik */ 392c6fd2807SJeff Garzik if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 393c6fd2807SJeff Garzik ata_ehi_hotplugged(&ap->eh_info); 394c6fd2807SJeff Garzik ap->eh_info.serror |= serror; 395c6fd2807SJeff Garzik } 396c6fd2807SJeff Garzik 397c6fd2807SJeff Garzik goto freeze; 398c6fd2807SJeff Garzik } 399c6fd2807SJeff Garzik 400e2f8fb72STejun Heo if (unlikely(!qc)) 401c6fd2807SJeff Garzik goto freeze; 402c6fd2807SJeff Garzik 403e2f8fb72STejun Heo if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) { 404e2f8fb72STejun Heo /* this sometimes happens, just clear IRQ */ 405e2f8fb72STejun Heo ata_chk_status(ap); 406e2f8fb72STejun Heo return; 407e2f8fb72STejun Heo } 408e2f8fb72STejun Heo 409c6fd2807SJeff Garzik /* Check whether we are expecting interrupt in this state */ 410c6fd2807SJeff Garzik switch (ap->hsm_task_state) { 411c6fd2807SJeff Garzik case HSM_ST_FIRST: 412c6fd2807SJeff Garzik /* Some pre-ATAPI-4 devices assert INTRQ 413c6fd2807SJeff Garzik * at this state when ready to receive CDB. 414c6fd2807SJeff Garzik */ 415c6fd2807SJeff Garzik 416c6fd2807SJeff Garzik /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 417c6fd2807SJeff Garzik * The flag was turned on only for atapi devices. 418c6fd2807SJeff Garzik * No need to check is_atapi_taskfile(&qc->tf) again. 419c6fd2807SJeff Garzik */ 420c6fd2807SJeff Garzik if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 421c6fd2807SJeff Garzik goto err_hsm; 422c6fd2807SJeff Garzik break; 423c6fd2807SJeff Garzik case HSM_ST_LAST: 424c6fd2807SJeff Garzik if (qc->tf.protocol == ATA_PROT_DMA || 425c6fd2807SJeff Garzik qc->tf.protocol == ATA_PROT_ATAPI_DMA) { 426c6fd2807SJeff Garzik /* clear DMA-Start bit */ 427c6fd2807SJeff Garzik ap->ops->bmdma_stop(qc); 428c6fd2807SJeff Garzik 429c6fd2807SJeff Garzik if (bmdma2 & SIL_DMA_ERROR) { 430c6fd2807SJeff Garzik qc->err_mask |= AC_ERR_HOST_BUS; 431c6fd2807SJeff Garzik ap->hsm_task_state = HSM_ST_ERR; 432c6fd2807SJeff Garzik } 433c6fd2807SJeff Garzik } 434c6fd2807SJeff Garzik break; 435c6fd2807SJeff Garzik case HSM_ST: 436c6fd2807SJeff Garzik break; 437c6fd2807SJeff Garzik default: 438c6fd2807SJeff Garzik goto err_hsm; 439c6fd2807SJeff Garzik } 440c6fd2807SJeff Garzik 441c6fd2807SJeff Garzik /* check main status, clearing INTRQ */ 442c6fd2807SJeff Garzik status = ata_chk_status(ap); 443c6fd2807SJeff Garzik if (unlikely(status & ATA_BUSY)) 444c6fd2807SJeff Garzik goto err_hsm; 445c6fd2807SJeff Garzik 446c6fd2807SJeff Garzik /* ack bmdma irq events */ 447c6fd2807SJeff Garzik ata_bmdma_irq_clear(ap); 448c6fd2807SJeff Garzik 449c6fd2807SJeff Garzik /* kick HSM in the ass */ 450c6fd2807SJeff Garzik ata_hsm_move(ap, qc, status, 0); 451c6fd2807SJeff Garzik 452ea54763fSTejun Heo if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 453ea54763fSTejun Heo qc->tf.protocol == ATA_PROT_ATAPI_DMA)) 454ea54763fSTejun Heo ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); 455ea54763fSTejun Heo 456c6fd2807SJeff Garzik return; 457c6fd2807SJeff Garzik 458c6fd2807SJeff Garzik err_hsm: 459c6fd2807SJeff Garzik qc->err_mask |= AC_ERR_HSM; 460c6fd2807SJeff Garzik freeze: 461c6fd2807SJeff Garzik ata_port_freeze(ap); 462c6fd2807SJeff Garzik } 463c6fd2807SJeff Garzik 4647d12e780SDavid Howells static irqreturn_t sil_interrupt(int irq, void *dev_instance) 465c6fd2807SJeff Garzik { 466cca3974eSJeff Garzik struct ata_host *host = dev_instance; 4670d5ff566STejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 468c6fd2807SJeff Garzik int handled = 0; 469c6fd2807SJeff Garzik int i; 470c6fd2807SJeff Garzik 471cca3974eSJeff Garzik spin_lock(&host->lock); 472c6fd2807SJeff Garzik 473cca3974eSJeff Garzik for (i = 0; i < host->n_ports; i++) { 474cca3974eSJeff Garzik struct ata_port *ap = host->ports[i]; 475c6fd2807SJeff Garzik u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 476c6fd2807SJeff Garzik 477c6fd2807SJeff Garzik if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) 478c6fd2807SJeff Garzik continue; 479c6fd2807SJeff Garzik 480c6fd2807SJeff Garzik /* turn off SATA_IRQ if not supported */ 481c6fd2807SJeff Garzik if (ap->flags & SIL_FLAG_NO_SATA_IRQ) 482c6fd2807SJeff Garzik bmdma2 &= ~SIL_DMA_SATA_IRQ; 483c6fd2807SJeff Garzik 484c6fd2807SJeff Garzik if (bmdma2 == 0xffffffff || 485c6fd2807SJeff Garzik !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) 486c6fd2807SJeff Garzik continue; 487c6fd2807SJeff Garzik 488c6fd2807SJeff Garzik sil_host_intr(ap, bmdma2); 489c6fd2807SJeff Garzik handled = 1; 490c6fd2807SJeff Garzik } 491c6fd2807SJeff Garzik 492cca3974eSJeff Garzik spin_unlock(&host->lock); 493c6fd2807SJeff Garzik 494c6fd2807SJeff Garzik return IRQ_RETVAL(handled); 495c6fd2807SJeff Garzik } 496c6fd2807SJeff Garzik 497c6fd2807SJeff Garzik static void sil_freeze(struct ata_port *ap) 498c6fd2807SJeff Garzik { 4990d5ff566STejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 500c6fd2807SJeff Garzik u32 tmp; 501c6fd2807SJeff Garzik 502c6fd2807SJeff Garzik /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ 503c6fd2807SJeff Garzik writel(0, mmio_base + sil_port[ap->port_no].sien); 504c6fd2807SJeff Garzik 505c6fd2807SJeff Garzik /* plug IRQ */ 506c6fd2807SJeff Garzik tmp = readl(mmio_base + SIL_SYSCFG); 507c6fd2807SJeff Garzik tmp |= SIL_MASK_IDE0_INT << ap->port_no; 508c6fd2807SJeff Garzik writel(tmp, mmio_base + SIL_SYSCFG); 509c6fd2807SJeff Garzik readl(mmio_base + SIL_SYSCFG); /* flush */ 510c6fd2807SJeff Garzik } 511c6fd2807SJeff Garzik 512c6fd2807SJeff Garzik static void sil_thaw(struct ata_port *ap) 513c6fd2807SJeff Garzik { 5140d5ff566STejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 515c6fd2807SJeff Garzik u32 tmp; 516c6fd2807SJeff Garzik 517c6fd2807SJeff Garzik /* clear IRQ */ 518c6fd2807SJeff Garzik ata_chk_status(ap); 519c6fd2807SJeff Garzik ata_bmdma_irq_clear(ap); 520c6fd2807SJeff Garzik 521c6fd2807SJeff Garzik /* turn on SATA IRQ if supported */ 522c6fd2807SJeff Garzik if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) 523c6fd2807SJeff Garzik writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); 524c6fd2807SJeff Garzik 525c6fd2807SJeff Garzik /* turn on IRQ */ 526c6fd2807SJeff Garzik tmp = readl(mmio_base + SIL_SYSCFG); 527c6fd2807SJeff Garzik tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); 528c6fd2807SJeff Garzik writel(tmp, mmio_base + SIL_SYSCFG); 529c6fd2807SJeff Garzik } 530c6fd2807SJeff Garzik 531c6fd2807SJeff Garzik /** 532c6fd2807SJeff Garzik * sil_dev_config - Apply device/host-specific errata fixups 533c6fd2807SJeff Garzik * @dev: Device to be examined 534c6fd2807SJeff Garzik * 535c6fd2807SJeff Garzik * After the IDENTIFY [PACKET] DEVICE step is complete, and a 536c6fd2807SJeff Garzik * device is known to be present, this function is called. 537c6fd2807SJeff Garzik * We apply two errata fixups which are specific to Silicon Image, 538c6fd2807SJeff Garzik * a Seagate and a Maxtor fixup. 539c6fd2807SJeff Garzik * 540c6fd2807SJeff Garzik * For certain Seagate devices, we must limit the maximum sectors 541c6fd2807SJeff Garzik * to under 8K. 542c6fd2807SJeff Garzik * 543c6fd2807SJeff Garzik * For certain Maxtor devices, we must not program the drive 544c6fd2807SJeff Garzik * beyond udma5. 545c6fd2807SJeff Garzik * 546c6fd2807SJeff Garzik * Both fixups are unfairly pessimistic. As soon as I get more 547c6fd2807SJeff Garzik * information on these errata, I will create a more exhaustive 548c6fd2807SJeff Garzik * list, and apply the fixups to only the specific 549c6fd2807SJeff Garzik * devices/hosts/firmwares that need it. 550c6fd2807SJeff Garzik * 551c6fd2807SJeff Garzik * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted 552c6fd2807SJeff Garzik * The Maxtor quirk is in the blacklist, but I'm keeping the original 553c6fd2807SJeff Garzik * pessimistic fix for the following reasons... 554c6fd2807SJeff Garzik * - There seems to be less info on it, only one device gleaned off the 555c6fd2807SJeff Garzik * Windows driver, maybe only one is affected. More info would be greatly 556c6fd2807SJeff Garzik * appreciated. 557c6fd2807SJeff Garzik * - But then again UDMA5 is hardly anything to complain about 558c6fd2807SJeff Garzik */ 559cd0d3bbcSAlan static void sil_dev_config(struct ata_device *dev) 560c6fd2807SJeff Garzik { 561cd0d3bbcSAlan struct ata_port *ap = dev->ap; 562efdaedc4STejun Heo int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO; 563c6fd2807SJeff Garzik unsigned int n, quirks = 0; 564a0cf733bSTejun Heo unsigned char model_num[ATA_ID_PROD_LEN + 1]; 565c6fd2807SJeff Garzik 566a0cf733bSTejun Heo ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 567c6fd2807SJeff Garzik 568c6fd2807SJeff Garzik for (n = 0; sil_blacklist[n].product; n++) 569c6fd2807SJeff Garzik if (!strcmp(sil_blacklist[n].product, model_num)) { 570c6fd2807SJeff Garzik quirks = sil_blacklist[n].quirk; 571c6fd2807SJeff Garzik break; 572c6fd2807SJeff Garzik } 573c6fd2807SJeff Garzik 574c6fd2807SJeff Garzik /* limit requests to 15 sectors */ 575c6fd2807SJeff Garzik if (slow_down || 576c6fd2807SJeff Garzik ((ap->flags & SIL_FLAG_MOD15WRITE) && 577c6fd2807SJeff Garzik (quirks & SIL_QUIRK_MOD15WRITE))) { 578efdaedc4STejun Heo if (print_info) 579efdaedc4STejun Heo ata_dev_printk(dev, KERN_INFO, "applying Seagate " 580efdaedc4STejun Heo "errata fix (mod15write workaround)\n"); 581c6fd2807SJeff Garzik dev->max_sectors = 15; 582c6fd2807SJeff Garzik return; 583c6fd2807SJeff Garzik } 584c6fd2807SJeff Garzik 585c6fd2807SJeff Garzik /* limit to udma5 */ 586c6fd2807SJeff Garzik if (quirks & SIL_QUIRK_UDMA5MAX) { 587efdaedc4STejun Heo if (print_info) 588efdaedc4STejun Heo ata_dev_printk(dev, KERN_INFO, "applying Maxtor " 589efdaedc4STejun Heo "errata fix %s\n", model_num); 590c6fd2807SJeff Garzik dev->udma_mask &= ATA_UDMA5; 591c6fd2807SJeff Garzik return; 592c6fd2807SJeff Garzik } 593c6fd2807SJeff Garzik } 594c6fd2807SJeff Garzik 5954447d351STejun Heo static void sil_init_controller(struct ata_host *host) 596c6fd2807SJeff Garzik { 5974447d351STejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 5984447d351STejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 599c6fd2807SJeff Garzik u8 cls; 600c6fd2807SJeff Garzik u32 tmp; 601c6fd2807SJeff Garzik int i; 602c6fd2807SJeff Garzik 603c6fd2807SJeff Garzik /* Initialize FIFO PCI bus arbitration */ 604c6fd2807SJeff Garzik cls = sil_get_device_cache_line(pdev); 605c6fd2807SJeff Garzik if (cls) { 606c6fd2807SJeff Garzik cls >>= 3; 607c6fd2807SJeff Garzik cls++; /* cls = (line_size/8)+1 */ 6084447d351STejun Heo for (i = 0; i < host->n_ports; i++) 609c6fd2807SJeff Garzik writew(cls << 8 | cls, 610c6fd2807SJeff Garzik mmio_base + sil_port[i].fifo_cfg); 611c6fd2807SJeff Garzik } else 612c6fd2807SJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 613c6fd2807SJeff Garzik "cache line size not set. Driver may not function\n"); 614c6fd2807SJeff Garzik 615c6fd2807SJeff Garzik /* Apply R_ERR on DMA activate FIS errata workaround */ 6164447d351STejun Heo if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { 617c6fd2807SJeff Garzik int cnt; 618c6fd2807SJeff Garzik 6194447d351STejun Heo for (i = 0, cnt = 0; i < host->n_ports; i++) { 620c6fd2807SJeff Garzik tmp = readl(mmio_base + sil_port[i].sfis_cfg); 621c6fd2807SJeff Garzik if ((tmp & 0x3) != 0x01) 622c6fd2807SJeff Garzik continue; 623c6fd2807SJeff Garzik if (!cnt) 624c6fd2807SJeff Garzik dev_printk(KERN_INFO, &pdev->dev, 625c6fd2807SJeff Garzik "Applying R_ERR on DMA activate " 626c6fd2807SJeff Garzik "FIS errata fix\n"); 627c6fd2807SJeff Garzik writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); 628c6fd2807SJeff Garzik cnt++; 629c6fd2807SJeff Garzik } 630c6fd2807SJeff Garzik } 631c6fd2807SJeff Garzik 6324447d351STejun Heo if (host->n_ports == 4) { 633c6fd2807SJeff Garzik /* flip the magic "make 4 ports work" bit */ 634c6fd2807SJeff Garzik tmp = readl(mmio_base + sil_port[2].bmdma); 635c6fd2807SJeff Garzik if ((tmp & SIL_INTR_STEERING) == 0) 636c6fd2807SJeff Garzik writel(tmp | SIL_INTR_STEERING, 637c6fd2807SJeff Garzik mmio_base + sil_port[2].bmdma); 638c6fd2807SJeff Garzik } 639c6fd2807SJeff Garzik } 640c6fd2807SJeff Garzik 641c6fd2807SJeff Garzik static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 642c6fd2807SJeff Garzik { 643c6fd2807SJeff Garzik static int printed_version; 6444447d351STejun Heo int board_id = ent->driver_data; 6454447d351STejun Heo const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL }; 6464447d351STejun Heo struct ata_host *host; 647c6fd2807SJeff Garzik void __iomem *mmio_base; 6484447d351STejun Heo int n_ports, rc; 649c6fd2807SJeff Garzik unsigned int i; 650c6fd2807SJeff Garzik 651c6fd2807SJeff Garzik if (!printed_version++) 652c6fd2807SJeff Garzik dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 653c6fd2807SJeff Garzik 6544447d351STejun Heo /* allocate host */ 6554447d351STejun Heo n_ports = 2; 6564447d351STejun Heo if (board_id == sil_3114) 6574447d351STejun Heo n_ports = 4; 6584447d351STejun Heo 6594447d351STejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 6604447d351STejun Heo if (!host) 6614447d351STejun Heo return -ENOMEM; 6624447d351STejun Heo 6634447d351STejun Heo /* acquire resources and fill host */ 66424dc5f33STejun Heo rc = pcim_enable_device(pdev); 665c6fd2807SJeff Garzik if (rc) 666c6fd2807SJeff Garzik return rc; 667c6fd2807SJeff Garzik 6680d5ff566STejun Heo rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); 6690d5ff566STejun Heo if (rc == -EBUSY) 67024dc5f33STejun Heo pcim_pin_device(pdev); 6710d5ff566STejun Heo if (rc) 67224dc5f33STejun Heo return rc; 6734447d351STejun Heo host->iomap = pcim_iomap_table(pdev); 674c6fd2807SJeff Garzik 675c6fd2807SJeff Garzik rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 676c6fd2807SJeff Garzik if (rc) 67724dc5f33STejun Heo return rc; 678c6fd2807SJeff Garzik rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 679c6fd2807SJeff Garzik if (rc) 68024dc5f33STejun Heo return rc; 681c6fd2807SJeff Garzik 6824447d351STejun Heo mmio_base = host->iomap[SIL_MMIO_BAR]; 683c6fd2807SJeff Garzik 6844447d351STejun Heo for (i = 0; i < host->n_ports; i++) { 6854447d351STejun Heo struct ata_ioports *ioaddr = &host->ports[i]->ioaddr; 686c6fd2807SJeff Garzik 6874447d351STejun Heo ioaddr->cmd_addr = mmio_base + sil_port[i].tf; 6884447d351STejun Heo ioaddr->altstatus_addr = 6894447d351STejun Heo ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; 6904447d351STejun Heo ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; 6914447d351STejun Heo ioaddr->scr_addr = mmio_base + sil_port[i].scr; 6924447d351STejun Heo ata_std_ports(ioaddr); 693c6fd2807SJeff Garzik } 694c6fd2807SJeff Garzik 6954447d351STejun Heo /* initialize and activate */ 6964447d351STejun Heo sil_init_controller(host); 697c6fd2807SJeff Garzik 698c6fd2807SJeff Garzik pci_set_master(pdev); 6994447d351STejun Heo return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, 7004447d351STejun Heo &sil_sht); 701c6fd2807SJeff Garzik } 702c6fd2807SJeff Garzik 703281d426cSAlexey Dobriyan #ifdef CONFIG_PM 704c6fd2807SJeff Garzik static int sil_pci_device_resume(struct pci_dev *pdev) 705c6fd2807SJeff Garzik { 706cca3974eSJeff Garzik struct ata_host *host = dev_get_drvdata(&pdev->dev); 707553c4aa6STejun Heo int rc; 708c6fd2807SJeff Garzik 709553c4aa6STejun Heo rc = ata_pci_device_do_resume(pdev); 710553c4aa6STejun Heo if (rc) 711553c4aa6STejun Heo return rc; 712553c4aa6STejun Heo 7134447d351STejun Heo sil_init_controller(host); 714cca3974eSJeff Garzik ata_host_resume(host); 715c6fd2807SJeff Garzik 716c6fd2807SJeff Garzik return 0; 717c6fd2807SJeff Garzik } 718281d426cSAlexey Dobriyan #endif 719c6fd2807SJeff Garzik 720c6fd2807SJeff Garzik static int __init sil_init(void) 721c6fd2807SJeff Garzik { 722c6fd2807SJeff Garzik return pci_register_driver(&sil_pci_driver); 723c6fd2807SJeff Garzik } 724c6fd2807SJeff Garzik 725c6fd2807SJeff Garzik static void __exit sil_exit(void) 726c6fd2807SJeff Garzik { 727c6fd2807SJeff Garzik pci_unregister_driver(&sil_pci_driver); 728c6fd2807SJeff Garzik } 729c6fd2807SJeff Garzik 730c6fd2807SJeff Garzik 731c6fd2807SJeff Garzik module_init(sil_init); 732c6fd2807SJeff Garzik module_exit(sil_exit); 733