1 /* 2 * Renesas R-Car SATA driver 3 * 4 * Author: Vladimir Barinov <source@cogentembedded.com> 5 * Copyright (C) 2013-2015 Cogent Embedded, Inc. 6 * Copyright (C) 2013-2015 Renesas Solutions Corp. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/ata.h> 17 #include <linux/libata.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/err.h> 22 23 #define DRV_NAME "sata_rcar" 24 25 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 26 #define DATA_REG 0x100 27 #define SDEVCON_REG 0x138 28 29 /* SH-Navi2G/ATAPI module compatible control registers */ 30 #define ATAPI_CONTROL1_REG 0x180 31 #define ATAPI_STATUS_REG 0x184 32 #define ATAPI_INT_ENABLE_REG 0x188 33 #define ATAPI_DTB_ADR_REG 0x198 34 #define ATAPI_DMA_START_ADR_REG 0x19C 35 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 36 #define ATAPI_CONTROL2_REG 0x1A4 37 #define ATAPI_SIG_ST_REG 0x1B0 38 #define ATAPI_BYTE_SWAP_REG 0x1BC 39 40 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 41 #define ATAPI_CONTROL1_ISM BIT(16) 42 #define ATAPI_CONTROL1_DTA32M BIT(11) 43 #define ATAPI_CONTROL1_RESET BIT(7) 44 #define ATAPI_CONTROL1_DESE BIT(3) 45 #define ATAPI_CONTROL1_RW BIT(2) 46 #define ATAPI_CONTROL1_STOP BIT(1) 47 #define ATAPI_CONTROL1_START BIT(0) 48 49 /* ATAPI status register (ATAPI_STATUS) bits */ 50 #define ATAPI_STATUS_SATAINT BIT(11) 51 #define ATAPI_STATUS_DNEND BIT(6) 52 #define ATAPI_STATUS_DEVTRM BIT(5) 53 #define ATAPI_STATUS_DEVINT BIT(4) 54 #define ATAPI_STATUS_ERR BIT(2) 55 #define ATAPI_STATUS_NEND BIT(1) 56 #define ATAPI_STATUS_ACT BIT(0) 57 58 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 59 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 60 #define ATAPI_INT_ENABLE_DNEND BIT(6) 61 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 62 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 63 #define ATAPI_INT_ENABLE_ERR BIT(2) 64 #define ATAPI_INT_ENABLE_NEND BIT(1) 65 #define ATAPI_INT_ENABLE_ACT BIT(0) 66 67 /* Access control registers for physical layer control register */ 68 #define SATAPHYADDR_REG 0x200 69 #define SATAPHYWDATA_REG 0x204 70 #define SATAPHYACCEN_REG 0x208 71 #define SATAPHYRESET_REG 0x20C 72 #define SATAPHYRDATA_REG 0x210 73 #define SATAPHYACK_REG 0x214 74 75 /* Physical layer control address command register (SATAPHYADDR) bits */ 76 #define SATAPHYADDR_PHYRATEMODE BIT(10) 77 #define SATAPHYADDR_PHYCMD_READ BIT(9) 78 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 79 80 /* Physical layer control enable register (SATAPHYACCEN) bits */ 81 #define SATAPHYACCEN_PHYLANE BIT(0) 82 83 /* Physical layer control reset register (SATAPHYRESET) bits */ 84 #define SATAPHYRESET_PHYRST BIT(1) 85 #define SATAPHYRESET_PHYSRES BIT(0) 86 87 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 88 #define SATAPHYACK_PHYACK BIT(0) 89 90 /* Serial-ATA HOST control registers */ 91 #define BISTCONF_REG 0x102C 92 #define SDATA_REG 0x1100 93 #define SSDEVCON_REG 0x1204 94 95 #define SCRSSTS_REG 0x1400 96 #define SCRSERR_REG 0x1404 97 #define SCRSCON_REG 0x1408 98 #define SCRSACT_REG 0x140C 99 100 #define SATAINTSTAT_REG 0x1508 101 #define SATAINTMASK_REG 0x150C 102 103 /* SATA INT status register (SATAINTSTAT) bits */ 104 #define SATAINTSTAT_SERR BIT(3) 105 #define SATAINTSTAT_ATA BIT(0) 106 107 /* SATA INT mask register (SATAINTSTAT) bits */ 108 #define SATAINTMASK_SERRMSK BIT(3) 109 #define SATAINTMASK_ERRMSK BIT(2) 110 #define SATAINTMASK_ERRCRTMSK BIT(1) 111 #define SATAINTMASK_ATAMSK BIT(0) 112 #define SATAINTMASK_ALL_GEN1 0x7ff 113 #define SATAINTMASK_ALL_GEN2 0xfff 114 115 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 116 SATAINTMASK_ATAMSK) 117 118 /* Physical Layer Control Registers */ 119 #define SATAPCTLR1_REG 0x43 120 #define SATAPCTLR2_REG 0x52 121 #define SATAPCTLR3_REG 0x5A 122 #define SATAPCTLR4_REG 0x60 123 124 /* Descriptor table word 0 bit (when DTA32M = 1) */ 125 #define SATA_RCAR_DTEND BIT(0) 126 127 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL 128 129 /* Gen2 Physical Layer Control Registers */ 130 #define RCAR_GEN2_PHY_CTL1_REG 0x1704 131 #define RCAR_GEN2_PHY_CTL1 0x34180002 132 #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ 133 134 #define RCAR_GEN2_PHY_CTL2_REG 0x170C 135 #define RCAR_GEN2_PHY_CTL2 0x00002303 136 137 #define RCAR_GEN2_PHY_CTL3_REG 0x171C 138 #define RCAR_GEN2_PHY_CTL3 0x000B0194 139 140 #define RCAR_GEN2_PHY_CTL4_REG 0x1724 141 #define RCAR_GEN2_PHY_CTL4 0x00030994 142 143 #define RCAR_GEN2_PHY_CTL5_REG 0x1740 144 #define RCAR_GEN2_PHY_CTL5 0x03004001 145 #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ 146 #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ 147 148 enum sata_rcar_type { 149 RCAR_GEN1_SATA, 150 RCAR_GEN2_SATA, 151 RCAR_GEN3_SATA, 152 RCAR_R8A7790_ES1_SATA, 153 }; 154 155 struct sata_rcar_priv { 156 void __iomem *base; 157 u32 sataint_mask; 158 enum sata_rcar_type type; 159 }; 160 161 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) 162 { 163 void __iomem *base = priv->base; 164 165 /* idle state */ 166 iowrite32(0, base + SATAPHYADDR_REG); 167 /* reset */ 168 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); 169 udelay(10); 170 /* deassert reset */ 171 iowrite32(0, base + SATAPHYRESET_REG); 172 } 173 174 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, 175 u32 val, int group) 176 { 177 void __iomem *base = priv->base; 178 int timeout; 179 180 /* deassert reset */ 181 iowrite32(0, base + SATAPHYRESET_REG); 182 /* lane 1 */ 183 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); 184 /* write phy register value */ 185 iowrite32(val, base + SATAPHYWDATA_REG); 186 /* set register group */ 187 if (group) 188 reg |= SATAPHYADDR_PHYRATEMODE; 189 /* write command */ 190 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); 191 /* wait for ack */ 192 for (timeout = 0; timeout < 100; timeout++) { 193 val = ioread32(base + SATAPHYACK_REG); 194 if (val & SATAPHYACK_PHYACK) 195 break; 196 } 197 if (timeout >= 100) 198 pr_err("%s timeout\n", __func__); 199 /* idle state */ 200 iowrite32(0, base + SATAPHYADDR_REG); 201 } 202 203 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) 204 { 205 sata_rcar_gen1_phy_preinit(priv); 206 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 207 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 208 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 209 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 210 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 211 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 212 } 213 214 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) 215 { 216 void __iomem *base = priv->base; 217 218 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); 219 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); 220 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); 221 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); 222 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | 223 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); 224 } 225 226 static void sata_rcar_freeze(struct ata_port *ap) 227 { 228 struct sata_rcar_priv *priv = ap->host->private_data; 229 230 /* mask */ 231 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); 232 233 ata_sff_freeze(ap); 234 } 235 236 static void sata_rcar_thaw(struct ata_port *ap) 237 { 238 struct sata_rcar_priv *priv = ap->host->private_data; 239 void __iomem *base = priv->base; 240 241 /* ack */ 242 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); 243 244 ata_sff_thaw(ap); 245 246 /* unmask */ 247 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); 248 } 249 250 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 251 { 252 u16 *ptr = buffer; 253 254 while (count--) { 255 u16 data = ioread32(reg); 256 257 *ptr++ = data; 258 } 259 } 260 261 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 262 { 263 const u16 *ptr = buffer; 264 265 while (count--) 266 iowrite32(*ptr++, reg); 267 } 268 269 static u8 sata_rcar_check_status(struct ata_port *ap) 270 { 271 return ioread32(ap->ioaddr.status_addr); 272 } 273 274 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 275 { 276 return ioread32(ap->ioaddr.altstatus_addr); 277 } 278 279 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 280 { 281 iowrite32(ctl, ap->ioaddr.ctl_addr); 282 } 283 284 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 285 { 286 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 287 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 288 } 289 290 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, 291 unsigned int device) 292 { 293 struct ata_ioports *ioaddr = &ap->ioaddr; 294 u8 nsect, lbal; 295 296 sata_rcar_dev_select(ap, device); 297 298 iowrite32(0x55, ioaddr->nsect_addr); 299 iowrite32(0xaa, ioaddr->lbal_addr); 300 301 iowrite32(0xaa, ioaddr->nsect_addr); 302 iowrite32(0x55, ioaddr->lbal_addr); 303 304 iowrite32(0x55, ioaddr->nsect_addr); 305 iowrite32(0xaa, ioaddr->lbal_addr); 306 307 nsect = ioread32(ioaddr->nsect_addr); 308 lbal = ioread32(ioaddr->lbal_addr); 309 310 if (nsect == 0x55 && lbal == 0xaa) 311 return 1; /* found a device */ 312 313 return 0; /* nothing found */ 314 } 315 316 static int sata_rcar_wait_after_reset(struct ata_link *link, 317 unsigned long deadline) 318 { 319 struct ata_port *ap = link->ap; 320 321 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 322 323 return ata_sff_wait_ready(link, deadline); 324 } 325 326 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 327 { 328 struct ata_ioports *ioaddr = &ap->ioaddr; 329 330 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 331 332 /* software reset. causes dev0 to be selected */ 333 iowrite32(ap->ctl, ioaddr->ctl_addr); 334 udelay(20); 335 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 336 udelay(20); 337 iowrite32(ap->ctl, ioaddr->ctl_addr); 338 ap->last_ctl = ap->ctl; 339 340 /* wait the port to become ready */ 341 return sata_rcar_wait_after_reset(&ap->link, deadline); 342 } 343 344 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 345 unsigned long deadline) 346 { 347 struct ata_port *ap = link->ap; 348 unsigned int devmask = 0; 349 int rc; 350 u8 err; 351 352 /* determine if device 0 is present */ 353 if (sata_rcar_ata_devchk(ap, 0)) 354 devmask |= 1 << 0; 355 356 /* issue bus reset */ 357 DPRINTK("about to softreset, devmask=%x\n", devmask); 358 rc = sata_rcar_bus_softreset(ap, deadline); 359 /* if link is occupied, -ENODEV too is an error */ 360 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 361 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 362 return rc; 363 } 364 365 /* determine by signature whether we have ATA or ATAPI devices */ 366 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 367 368 DPRINTK("classes[0]=%u\n", classes[0]); 369 return 0; 370 } 371 372 static void sata_rcar_tf_load(struct ata_port *ap, 373 const struct ata_taskfile *tf) 374 { 375 struct ata_ioports *ioaddr = &ap->ioaddr; 376 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 377 378 if (tf->ctl != ap->last_ctl) { 379 iowrite32(tf->ctl, ioaddr->ctl_addr); 380 ap->last_ctl = tf->ctl; 381 ata_wait_idle(ap); 382 } 383 384 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 385 iowrite32(tf->hob_feature, ioaddr->feature_addr); 386 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 387 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 388 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 389 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 390 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 391 tf->hob_feature, 392 tf->hob_nsect, 393 tf->hob_lbal, 394 tf->hob_lbam, 395 tf->hob_lbah); 396 } 397 398 if (is_addr) { 399 iowrite32(tf->feature, ioaddr->feature_addr); 400 iowrite32(tf->nsect, ioaddr->nsect_addr); 401 iowrite32(tf->lbal, ioaddr->lbal_addr); 402 iowrite32(tf->lbam, ioaddr->lbam_addr); 403 iowrite32(tf->lbah, ioaddr->lbah_addr); 404 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 405 tf->feature, 406 tf->nsect, 407 tf->lbal, 408 tf->lbam, 409 tf->lbah); 410 } 411 412 if (tf->flags & ATA_TFLAG_DEVICE) { 413 iowrite32(tf->device, ioaddr->device_addr); 414 VPRINTK("device 0x%X\n", tf->device); 415 } 416 417 ata_wait_idle(ap); 418 } 419 420 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 421 { 422 struct ata_ioports *ioaddr = &ap->ioaddr; 423 424 tf->command = sata_rcar_check_status(ap); 425 tf->feature = ioread32(ioaddr->error_addr); 426 tf->nsect = ioread32(ioaddr->nsect_addr); 427 tf->lbal = ioread32(ioaddr->lbal_addr); 428 tf->lbam = ioread32(ioaddr->lbam_addr); 429 tf->lbah = ioread32(ioaddr->lbah_addr); 430 tf->device = ioread32(ioaddr->device_addr); 431 432 if (tf->flags & ATA_TFLAG_LBA48) { 433 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 434 tf->hob_feature = ioread32(ioaddr->error_addr); 435 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 436 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 437 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 438 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 439 iowrite32(tf->ctl, ioaddr->ctl_addr); 440 ap->last_ctl = tf->ctl; 441 } 442 } 443 444 static void sata_rcar_exec_command(struct ata_port *ap, 445 const struct ata_taskfile *tf) 446 { 447 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 448 449 iowrite32(tf->command, ap->ioaddr.command_addr); 450 ata_sff_pause(ap); 451 } 452 453 static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, 454 unsigned char *buf, 455 unsigned int buflen, int rw) 456 { 457 struct ata_port *ap = qc->dev->link->ap; 458 void __iomem *data_addr = ap->ioaddr.data_addr; 459 unsigned int words = buflen >> 1; 460 461 /* Transfer multiple of 2 bytes */ 462 if (rw == READ) 463 sata_rcar_ioread16_rep(data_addr, buf, words); 464 else 465 sata_rcar_iowrite16_rep(data_addr, buf, words); 466 467 /* Transfer trailing byte, if any. */ 468 if (unlikely(buflen & 0x01)) { 469 unsigned char pad[2] = { }; 470 471 /* Point buf to the tail of buffer */ 472 buf += buflen - 1; 473 474 /* 475 * Use io*16_rep() accessors here as well to avoid pointlessly 476 * swapping bytes to and from on the big endian machines... 477 */ 478 if (rw == READ) { 479 sata_rcar_ioread16_rep(data_addr, pad, 1); 480 *buf = pad[0]; 481 } else { 482 pad[0] = *buf; 483 sata_rcar_iowrite16_rep(data_addr, pad, 1); 484 } 485 words++; 486 } 487 488 return words << 1; 489 } 490 491 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 492 { 493 int count; 494 struct ata_port *ap; 495 496 /* We only need to flush incoming data when a command was running */ 497 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 498 return; 499 500 ap = qc->ap; 501 /* Drain up to 64K of data before we give up this recovery method */ 502 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 503 count < 65536; count += 2) 504 ioread32(ap->ioaddr.data_addr); 505 506 /* Can become DEBUG later */ 507 if (count) 508 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 509 } 510 511 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 512 u32 *val) 513 { 514 if (sc_reg > SCR_ACTIVE) 515 return -EINVAL; 516 517 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 518 return 0; 519 } 520 521 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 522 u32 val) 523 { 524 if (sc_reg > SCR_ACTIVE) 525 return -EINVAL; 526 527 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 528 return 0; 529 } 530 531 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 532 { 533 struct ata_port *ap = qc->ap; 534 struct ata_bmdma_prd *prd = ap->bmdma_prd; 535 struct scatterlist *sg; 536 unsigned int si; 537 538 for_each_sg(qc->sg, sg, qc->n_elem, si) { 539 u32 addr, sg_len; 540 541 /* 542 * Note: h/w doesn't support 64-bit, so we unconditionally 543 * truncate dma_addr_t to u32. 544 */ 545 addr = (u32)sg_dma_address(sg); 546 sg_len = sg_dma_len(sg); 547 548 prd[si].addr = cpu_to_le32(addr); 549 prd[si].flags_len = cpu_to_le32(sg_len); 550 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); 551 } 552 553 /* end-of-table flag */ 554 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 555 } 556 557 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) 558 { 559 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 560 return; 561 562 sata_rcar_bmdma_fill_sg(qc); 563 } 564 565 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 566 { 567 struct ata_port *ap = qc->ap; 568 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 569 struct sata_rcar_priv *priv = ap->host->private_data; 570 void __iomem *base = priv->base; 571 u32 dmactl; 572 573 /* load PRD table addr. */ 574 mb(); /* make sure PRD table writes are visible to controller */ 575 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); 576 577 /* specify data direction, triple-check start bit is clear */ 578 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 579 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 580 if (dmactl & ATAPI_CONTROL1_START) { 581 dmactl &= ~ATAPI_CONTROL1_START; 582 dmactl |= ATAPI_CONTROL1_STOP; 583 } 584 if (!rw) 585 dmactl |= ATAPI_CONTROL1_RW; 586 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 587 588 /* issue r/w command */ 589 ap->ops->sff_exec_command(ap, &qc->tf); 590 } 591 592 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 593 { 594 struct ata_port *ap = qc->ap; 595 struct sata_rcar_priv *priv = ap->host->private_data; 596 void __iomem *base = priv->base; 597 u32 dmactl; 598 599 /* start host DMA transaction */ 600 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 601 dmactl &= ~ATAPI_CONTROL1_STOP; 602 dmactl |= ATAPI_CONTROL1_START; 603 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 604 } 605 606 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 607 { 608 struct ata_port *ap = qc->ap; 609 struct sata_rcar_priv *priv = ap->host->private_data; 610 void __iomem *base = priv->base; 611 u32 dmactl; 612 613 /* force termination of DMA transfer if active */ 614 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 615 if (dmactl & ATAPI_CONTROL1_START) { 616 dmactl &= ~ATAPI_CONTROL1_START; 617 dmactl |= ATAPI_CONTROL1_STOP; 618 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 619 } 620 621 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 622 ata_sff_dma_pause(ap); 623 } 624 625 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 626 { 627 struct sata_rcar_priv *priv = ap->host->private_data; 628 u8 host_stat = 0; 629 u32 status; 630 631 status = ioread32(priv->base + ATAPI_STATUS_REG); 632 if (status & ATAPI_STATUS_DEVINT) 633 host_stat |= ATA_DMA_INTR; 634 if (status & ATAPI_STATUS_ACT) 635 host_stat |= ATA_DMA_ACTIVE; 636 637 return host_stat; 638 } 639 640 static struct scsi_host_template sata_rcar_sht = { 641 ATA_BASE_SHT(DRV_NAME), 642 /* 643 * This controller allows transfer chunks up to 512MB which cross 64KB 644 * boundaries, therefore the DMA limits are more relaxed than standard 645 * ATA SFF. 646 */ 647 .sg_tablesize = ATA_MAX_PRD, 648 .dma_boundary = SATA_RCAR_DMA_BOUNDARY, 649 }; 650 651 static struct ata_port_operations sata_rcar_port_ops = { 652 .inherits = &ata_bmdma_port_ops, 653 654 .freeze = sata_rcar_freeze, 655 .thaw = sata_rcar_thaw, 656 .softreset = sata_rcar_softreset, 657 658 .scr_read = sata_rcar_scr_read, 659 .scr_write = sata_rcar_scr_write, 660 661 .sff_dev_select = sata_rcar_dev_select, 662 .sff_set_devctl = sata_rcar_set_devctl, 663 .sff_check_status = sata_rcar_check_status, 664 .sff_check_altstatus = sata_rcar_check_altstatus, 665 .sff_tf_load = sata_rcar_tf_load, 666 .sff_tf_read = sata_rcar_tf_read, 667 .sff_exec_command = sata_rcar_exec_command, 668 .sff_data_xfer = sata_rcar_data_xfer, 669 .sff_drain_fifo = sata_rcar_drain_fifo, 670 671 .qc_prep = sata_rcar_qc_prep, 672 673 .bmdma_setup = sata_rcar_bmdma_setup, 674 .bmdma_start = sata_rcar_bmdma_start, 675 .bmdma_stop = sata_rcar_bmdma_stop, 676 .bmdma_status = sata_rcar_bmdma_status, 677 }; 678 679 static void sata_rcar_serr_interrupt(struct ata_port *ap) 680 { 681 struct sata_rcar_priv *priv = ap->host->private_data; 682 struct ata_eh_info *ehi = &ap->link.eh_info; 683 int freeze = 0; 684 u32 serror; 685 686 serror = ioread32(priv->base + SCRSERR_REG); 687 if (!serror) 688 return; 689 690 DPRINTK("SError @host_intr: 0x%x\n", serror); 691 692 /* first, analyze and record host port events */ 693 ata_ehi_clear_desc(ehi); 694 695 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 696 /* Setup a soft-reset EH action */ 697 ata_ehi_hotplugged(ehi); 698 ata_ehi_push_desc(ehi, "%s", "hotplug"); 699 700 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 701 } 702 703 /* freeze or abort */ 704 if (freeze) 705 ata_port_freeze(ap); 706 else 707 ata_port_abort(ap); 708 } 709 710 static void sata_rcar_ata_interrupt(struct ata_port *ap) 711 { 712 struct ata_queued_cmd *qc; 713 int handled = 0; 714 715 qc = ata_qc_from_tag(ap, ap->link.active_tag); 716 if (qc) 717 handled |= ata_bmdma_port_intr(ap, qc); 718 719 /* be sure to clear ATA interrupt */ 720 if (!handled) 721 sata_rcar_check_status(ap); 722 } 723 724 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 725 { 726 struct ata_host *host = dev_instance; 727 struct sata_rcar_priv *priv = host->private_data; 728 void __iomem *base = priv->base; 729 unsigned int handled = 0; 730 struct ata_port *ap; 731 u32 sataintstat; 732 unsigned long flags; 733 734 spin_lock_irqsave(&host->lock, flags); 735 736 sataintstat = ioread32(base + SATAINTSTAT_REG); 737 sataintstat &= SATA_RCAR_INT_MASK; 738 if (!sataintstat) 739 goto done; 740 /* ack */ 741 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); 742 743 ap = host->ports[0]; 744 745 if (sataintstat & SATAINTSTAT_ATA) 746 sata_rcar_ata_interrupt(ap); 747 748 if (sataintstat & SATAINTSTAT_SERR) 749 sata_rcar_serr_interrupt(ap); 750 751 handled = 1; 752 done: 753 spin_unlock_irqrestore(&host->lock, flags); 754 755 return IRQ_RETVAL(handled); 756 } 757 758 static void sata_rcar_setup_port(struct ata_host *host) 759 { 760 struct ata_port *ap = host->ports[0]; 761 struct ata_ioports *ioaddr = &ap->ioaddr; 762 struct sata_rcar_priv *priv = host->private_data; 763 void __iomem *base = priv->base; 764 765 ap->ops = &sata_rcar_port_ops; 766 ap->pio_mask = ATA_PIO4; 767 ap->udma_mask = ATA_UDMA6; 768 ap->flags |= ATA_FLAG_SATA; 769 770 if (priv->type == RCAR_R8A7790_ES1_SATA) 771 ap->flags |= ATA_FLAG_NO_DIPM; 772 773 ioaddr->cmd_addr = base + SDATA_REG; 774 ioaddr->ctl_addr = base + SSDEVCON_REG; 775 ioaddr->scr_addr = base + SCRSSTS_REG; 776 ioaddr->altstatus_addr = ioaddr->ctl_addr; 777 778 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 779 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 780 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 781 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 782 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 783 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 784 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 785 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 786 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 787 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 788 } 789 790 static void sata_rcar_init_module(struct sata_rcar_priv *priv) 791 { 792 void __iomem *base = priv->base; 793 u32 val; 794 795 /* SATA-IP reset state */ 796 val = ioread32(base + ATAPI_CONTROL1_REG); 797 val |= ATAPI_CONTROL1_RESET; 798 iowrite32(val, base + ATAPI_CONTROL1_REG); 799 800 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 801 val = ioread32(base + ATAPI_CONTROL1_REG); 802 val |= ATAPI_CONTROL1_ISM; 803 val |= ATAPI_CONTROL1_DESE; 804 val |= ATAPI_CONTROL1_DTA32M; 805 iowrite32(val, base + ATAPI_CONTROL1_REG); 806 807 /* Release the SATA-IP from the reset state */ 808 val = ioread32(base + ATAPI_CONTROL1_REG); 809 val &= ~ATAPI_CONTROL1_RESET; 810 iowrite32(val, base + ATAPI_CONTROL1_REG); 811 812 /* ack and mask */ 813 iowrite32(0, base + SATAINTSTAT_REG); 814 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 815 816 /* enable interrupts */ 817 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 818 } 819 820 static void sata_rcar_init_controller(struct ata_host *host) 821 { 822 struct sata_rcar_priv *priv = host->private_data; 823 824 priv->sataint_mask = SATAINTMASK_ALL_GEN2; 825 826 /* reset and setup phy */ 827 switch (priv->type) { 828 case RCAR_GEN1_SATA: 829 priv->sataint_mask = SATAINTMASK_ALL_GEN1; 830 sata_rcar_gen1_phy_init(priv); 831 break; 832 case RCAR_GEN2_SATA: 833 case RCAR_R8A7790_ES1_SATA: 834 sata_rcar_gen2_phy_init(priv); 835 break; 836 case RCAR_GEN3_SATA: 837 break; 838 default: 839 dev_warn(host->dev, "SATA phy is not initialized\n"); 840 break; 841 } 842 843 sata_rcar_init_module(priv); 844 } 845 846 static const struct of_device_id sata_rcar_match[] = { 847 { 848 /* Deprecated by "renesas,sata-r8a7779" */ 849 .compatible = "renesas,rcar-sata", 850 .data = (void *)RCAR_GEN1_SATA, 851 }, 852 { 853 .compatible = "renesas,sata-r8a7779", 854 .data = (void *)RCAR_GEN1_SATA, 855 }, 856 { 857 .compatible = "renesas,sata-r8a7790", 858 .data = (void *)RCAR_GEN2_SATA 859 }, 860 { 861 .compatible = "renesas,sata-r8a7790-es1", 862 .data = (void *)RCAR_R8A7790_ES1_SATA 863 }, 864 { 865 .compatible = "renesas,sata-r8a7791", 866 .data = (void *)RCAR_GEN2_SATA 867 }, 868 { 869 .compatible = "renesas,sata-r8a7793", 870 .data = (void *)RCAR_GEN2_SATA 871 }, 872 { 873 .compatible = "renesas,sata-r8a7795", 874 .data = (void *)RCAR_GEN3_SATA 875 }, 876 { 877 .compatible = "renesas,rcar-gen2-sata", 878 .data = (void *)RCAR_GEN2_SATA 879 }, 880 { 881 .compatible = "renesas,rcar-gen3-sata", 882 .data = (void *)RCAR_GEN3_SATA 883 }, 884 { }, 885 }; 886 MODULE_DEVICE_TABLE(of, sata_rcar_match); 887 888 static int sata_rcar_probe(struct platform_device *pdev) 889 { 890 struct device *dev = &pdev->dev; 891 struct ata_host *host; 892 struct sata_rcar_priv *priv; 893 struct resource *mem; 894 int irq; 895 int ret = 0; 896 897 irq = platform_get_irq(pdev, 0); 898 if (irq <= 0) 899 return -EINVAL; 900 901 priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL); 902 if (!priv) 903 return -ENOMEM; 904 905 priv->type = (enum sata_rcar_type)of_device_get_match_data(dev); 906 907 pm_runtime_enable(dev); 908 ret = pm_runtime_get_sync(dev); 909 if (ret < 0) 910 goto err_pm_disable; 911 912 host = ata_host_alloc(dev, 1); 913 if (!host) { 914 dev_err(dev, "ata_host_alloc failed\n"); 915 ret = -ENOMEM; 916 goto err_pm_put; 917 } 918 919 host->private_data = priv; 920 921 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 922 priv->base = devm_ioremap_resource(dev, mem); 923 if (IS_ERR(priv->base)) { 924 ret = PTR_ERR(priv->base); 925 goto err_pm_put; 926 } 927 928 /* setup port */ 929 sata_rcar_setup_port(host); 930 931 /* initialize host controller */ 932 sata_rcar_init_controller(host); 933 934 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 935 &sata_rcar_sht); 936 if (!ret) 937 return 0; 938 939 err_pm_put: 940 pm_runtime_put(dev); 941 err_pm_disable: 942 pm_runtime_disable(dev); 943 return ret; 944 } 945 946 static int sata_rcar_remove(struct platform_device *pdev) 947 { 948 struct ata_host *host = platform_get_drvdata(pdev); 949 struct sata_rcar_priv *priv = host->private_data; 950 void __iomem *base = priv->base; 951 952 ata_host_detach(host); 953 954 /* disable interrupts */ 955 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 956 /* ack and mask */ 957 iowrite32(0, base + SATAINTSTAT_REG); 958 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 959 960 pm_runtime_put(&pdev->dev); 961 pm_runtime_disable(&pdev->dev); 962 963 return 0; 964 } 965 966 #ifdef CONFIG_PM_SLEEP 967 static int sata_rcar_suspend(struct device *dev) 968 { 969 struct ata_host *host = dev_get_drvdata(dev); 970 struct sata_rcar_priv *priv = host->private_data; 971 void __iomem *base = priv->base; 972 int ret; 973 974 ret = ata_host_suspend(host, PMSG_SUSPEND); 975 if (!ret) { 976 /* disable interrupts */ 977 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 978 /* mask */ 979 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 980 981 pm_runtime_put(dev); 982 } 983 984 return ret; 985 } 986 987 static int sata_rcar_resume(struct device *dev) 988 { 989 struct ata_host *host = dev_get_drvdata(dev); 990 struct sata_rcar_priv *priv = host->private_data; 991 void __iomem *base = priv->base; 992 int ret; 993 994 ret = pm_runtime_get_sync(dev); 995 if (ret < 0) 996 return ret; 997 998 if (priv->type == RCAR_GEN3_SATA) { 999 sata_rcar_init_module(priv); 1000 } else { 1001 /* ack and mask */ 1002 iowrite32(0, base + SATAINTSTAT_REG); 1003 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); 1004 1005 /* enable interrupts */ 1006 iowrite32(ATAPI_INT_ENABLE_SATAINT, 1007 base + ATAPI_INT_ENABLE_REG); 1008 } 1009 1010 ata_host_resume(host); 1011 1012 return 0; 1013 } 1014 1015 static int sata_rcar_restore(struct device *dev) 1016 { 1017 struct ata_host *host = dev_get_drvdata(dev); 1018 int ret; 1019 1020 ret = pm_runtime_get_sync(dev); 1021 if (ret < 0) 1022 return ret; 1023 1024 sata_rcar_setup_port(host); 1025 1026 /* initialize host controller */ 1027 sata_rcar_init_controller(host); 1028 1029 ata_host_resume(host); 1030 1031 return 0; 1032 } 1033 1034 static const struct dev_pm_ops sata_rcar_pm_ops = { 1035 .suspend = sata_rcar_suspend, 1036 .resume = sata_rcar_resume, 1037 .freeze = sata_rcar_suspend, 1038 .thaw = sata_rcar_resume, 1039 .poweroff = sata_rcar_suspend, 1040 .restore = sata_rcar_restore, 1041 }; 1042 #endif 1043 1044 static struct platform_driver sata_rcar_driver = { 1045 .probe = sata_rcar_probe, 1046 .remove = sata_rcar_remove, 1047 .driver = { 1048 .name = DRV_NAME, 1049 .of_match_table = sata_rcar_match, 1050 #ifdef CONFIG_PM_SLEEP 1051 .pm = &sata_rcar_pm_ops, 1052 #endif 1053 }, 1054 }; 1055 1056 module_platform_driver(sata_rcar_driver); 1057 1058 MODULE_LICENSE("GPL"); 1059 MODULE_AUTHOR("Vladimir Barinov"); 1060 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); 1061