1 /* 2 * Renesas R-Car SATA driver 3 * 4 * Author: Vladimir Barinov <source@cogentembedded.com> 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/ata.h> 17 #include <linux/libata.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 21 #define DRV_NAME "sata_rcar" 22 23 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 24 #define DATA_REG 0x100 25 #define SDEVCON_REG 0x138 26 27 /* SH-Navi2G/ATAPI module compatible control registers */ 28 #define ATAPI_CONTROL1_REG 0x180 29 #define ATAPI_STATUS_REG 0x184 30 #define ATAPI_INT_ENABLE_REG 0x188 31 #define ATAPI_DTB_ADR_REG 0x198 32 #define ATAPI_DMA_START_ADR_REG 0x19C 33 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 34 #define ATAPI_CONTROL2_REG 0x1A4 35 #define ATAPI_SIG_ST_REG 0x1B0 36 #define ATAPI_BYTE_SWAP_REG 0x1BC 37 38 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 39 #define ATAPI_CONTROL1_ISM BIT(16) 40 #define ATAPI_CONTROL1_DTA32M BIT(11) 41 #define ATAPI_CONTROL1_RESET BIT(7) 42 #define ATAPI_CONTROL1_DESE BIT(3) 43 #define ATAPI_CONTROL1_RW BIT(2) 44 #define ATAPI_CONTROL1_STOP BIT(1) 45 #define ATAPI_CONTROL1_START BIT(0) 46 47 /* ATAPI status register (ATAPI_STATUS) bits */ 48 #define ATAPI_STATUS_SATAINT BIT(11) 49 #define ATAPI_STATUS_DNEND BIT(6) 50 #define ATAPI_STATUS_DEVTRM BIT(5) 51 #define ATAPI_STATUS_DEVINT BIT(4) 52 #define ATAPI_STATUS_ERR BIT(2) 53 #define ATAPI_STATUS_NEND BIT(1) 54 #define ATAPI_STATUS_ACT BIT(0) 55 56 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 57 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 58 #define ATAPI_INT_ENABLE_DNEND BIT(6) 59 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 60 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 61 #define ATAPI_INT_ENABLE_ERR BIT(2) 62 #define ATAPI_INT_ENABLE_NEND BIT(1) 63 #define ATAPI_INT_ENABLE_ACT BIT(0) 64 65 /* Access control registers for physical layer control register */ 66 #define SATAPHYADDR_REG 0x200 67 #define SATAPHYWDATA_REG 0x204 68 #define SATAPHYACCEN_REG 0x208 69 #define SATAPHYRESET_REG 0x20C 70 #define SATAPHYRDATA_REG 0x210 71 #define SATAPHYACK_REG 0x214 72 73 /* Physical layer control address command register (SATAPHYADDR) bits */ 74 #define SATAPHYADDR_PHYRATEMODE BIT(10) 75 #define SATAPHYADDR_PHYCMD_READ BIT(9) 76 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 77 78 /* Physical layer control enable register (SATAPHYACCEN) bits */ 79 #define SATAPHYACCEN_PHYLANE BIT(0) 80 81 /* Physical layer control reset register (SATAPHYRESET) bits */ 82 #define SATAPHYRESET_PHYRST BIT(1) 83 #define SATAPHYRESET_PHYSRES BIT(0) 84 85 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 86 #define SATAPHYACK_PHYACK BIT(0) 87 88 /* Serial-ATA HOST control registers */ 89 #define BISTCONF_REG 0x102C 90 #define SDATA_REG 0x1100 91 #define SSDEVCON_REG 0x1204 92 93 #define SCRSSTS_REG 0x1400 94 #define SCRSERR_REG 0x1404 95 #define SCRSCON_REG 0x1408 96 #define SCRSACT_REG 0x140C 97 98 #define SATAINTSTAT_REG 0x1508 99 #define SATAINTMASK_REG 0x150C 100 101 /* SATA INT status register (SATAINTSTAT) bits */ 102 #define SATAINTSTAT_SERR BIT(3) 103 #define SATAINTSTAT_ATA BIT(0) 104 105 /* SATA INT mask register (SATAINTSTAT) bits */ 106 #define SATAINTMASK_SERRMSK BIT(3) 107 #define SATAINTMASK_ERRMSK BIT(2) 108 #define SATAINTMASK_ERRCRTMSK BIT(1) 109 #define SATAINTMASK_ATAMSK BIT(0) 110 111 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 112 SATAINTMASK_ATAMSK) 113 114 /* Physical Layer Control Registers */ 115 #define SATAPCTLR1_REG 0x43 116 #define SATAPCTLR2_REG 0x52 117 #define SATAPCTLR3_REG 0x5A 118 #define SATAPCTLR4_REG 0x60 119 120 /* Descriptor table word 0 bit (when DTA32M = 1) */ 121 #define SATA_RCAR_DTEND BIT(0) 122 123 struct sata_rcar_priv { 124 void __iomem *base; 125 struct clk *clk; 126 }; 127 128 static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) 129 { 130 /* idle state */ 131 iowrite32(0, priv->base + SATAPHYADDR_REG); 132 /* reset */ 133 iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG); 134 udelay(10); 135 /* deassert reset */ 136 iowrite32(0, priv->base + SATAPHYRESET_REG); 137 } 138 139 static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, 140 int group) 141 { 142 int timeout; 143 144 /* deassert reset */ 145 iowrite32(0, priv->base + SATAPHYRESET_REG); 146 /* lane 1 */ 147 iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG); 148 /* write phy register value */ 149 iowrite32(val, priv->base + SATAPHYWDATA_REG); 150 /* set register group */ 151 if (group) 152 reg |= SATAPHYADDR_PHYRATEMODE; 153 /* write command */ 154 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG); 155 /* wait for ack */ 156 for (timeout = 0; timeout < 100; timeout++) { 157 val = ioread32(priv->base + SATAPHYACK_REG); 158 if (val & SATAPHYACK_PHYACK) 159 break; 160 } 161 if (timeout >= 100) 162 pr_err("%s timeout\n", __func__); 163 /* idle state */ 164 iowrite32(0, priv->base + SATAPHYADDR_REG); 165 } 166 167 static void sata_rcar_freeze(struct ata_port *ap) 168 { 169 struct sata_rcar_priv *priv = ap->host->private_data; 170 171 /* mask */ 172 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 173 174 ata_sff_freeze(ap); 175 } 176 177 static void sata_rcar_thaw(struct ata_port *ap) 178 { 179 struct sata_rcar_priv *priv = ap->host->private_data; 180 181 /* ack */ 182 iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG); 183 184 ata_sff_thaw(ap); 185 186 /* unmask */ 187 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG); 188 } 189 190 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 191 { 192 u16 *ptr = buffer; 193 194 while (count--) { 195 u16 data = ioread32(reg); 196 197 *ptr++ = data; 198 } 199 } 200 201 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 202 { 203 const u16 *ptr = buffer; 204 205 while (count--) 206 iowrite32(*ptr++, reg); 207 } 208 209 static u8 sata_rcar_check_status(struct ata_port *ap) 210 { 211 return ioread32(ap->ioaddr.status_addr); 212 } 213 214 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 215 { 216 return ioread32(ap->ioaddr.altstatus_addr); 217 } 218 219 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 220 { 221 iowrite32(ctl, ap->ioaddr.ctl_addr); 222 } 223 224 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 225 { 226 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 227 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 228 } 229 230 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, 231 unsigned int device) 232 { 233 struct ata_ioports *ioaddr = &ap->ioaddr; 234 u8 nsect, lbal; 235 236 sata_rcar_dev_select(ap, device); 237 238 iowrite32(0x55, ioaddr->nsect_addr); 239 iowrite32(0xaa, ioaddr->lbal_addr); 240 241 iowrite32(0xaa, ioaddr->nsect_addr); 242 iowrite32(0x55, ioaddr->lbal_addr); 243 244 iowrite32(0x55, ioaddr->nsect_addr); 245 iowrite32(0xaa, ioaddr->lbal_addr); 246 247 nsect = ioread32(ioaddr->nsect_addr); 248 lbal = ioread32(ioaddr->lbal_addr); 249 250 if (nsect == 0x55 && lbal == 0xaa) 251 return 1; /* found a device */ 252 253 return 0; /* nothing found */ 254 } 255 256 static int sata_rcar_wait_after_reset(struct ata_link *link, 257 unsigned long deadline) 258 { 259 struct ata_port *ap = link->ap; 260 261 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 262 263 return ata_sff_wait_ready(link, deadline); 264 } 265 266 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 267 { 268 struct ata_ioports *ioaddr = &ap->ioaddr; 269 270 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 271 272 /* software reset. causes dev0 to be selected */ 273 iowrite32(ap->ctl, ioaddr->ctl_addr); 274 udelay(20); 275 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 276 udelay(20); 277 iowrite32(ap->ctl, ioaddr->ctl_addr); 278 ap->last_ctl = ap->ctl; 279 280 /* wait the port to become ready */ 281 return sata_rcar_wait_after_reset(&ap->link, deadline); 282 } 283 284 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 285 unsigned long deadline) 286 { 287 struct ata_port *ap = link->ap; 288 unsigned int devmask = 0; 289 int rc; 290 u8 err; 291 292 /* determine if device 0 is present */ 293 if (sata_rcar_ata_devchk(ap, 0)) 294 devmask |= 1 << 0; 295 296 /* issue bus reset */ 297 DPRINTK("about to softreset, devmask=%x\n", devmask); 298 rc = sata_rcar_bus_softreset(ap, deadline); 299 /* if link is occupied, -ENODEV too is an error */ 300 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 301 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 302 return rc; 303 } 304 305 /* determine by signature whether we have ATA or ATAPI devices */ 306 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 307 308 DPRINTK("classes[0]=%u\n", classes[0]); 309 return 0; 310 } 311 312 static void sata_rcar_tf_load(struct ata_port *ap, 313 const struct ata_taskfile *tf) 314 { 315 struct ata_ioports *ioaddr = &ap->ioaddr; 316 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 317 318 if (tf->ctl != ap->last_ctl) { 319 iowrite32(tf->ctl, ioaddr->ctl_addr); 320 ap->last_ctl = tf->ctl; 321 ata_wait_idle(ap); 322 } 323 324 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 325 iowrite32(tf->hob_feature, ioaddr->feature_addr); 326 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 327 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 328 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 329 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 330 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 331 tf->hob_feature, 332 tf->hob_nsect, 333 tf->hob_lbal, 334 tf->hob_lbam, 335 tf->hob_lbah); 336 } 337 338 if (is_addr) { 339 iowrite32(tf->feature, ioaddr->feature_addr); 340 iowrite32(tf->nsect, ioaddr->nsect_addr); 341 iowrite32(tf->lbal, ioaddr->lbal_addr); 342 iowrite32(tf->lbam, ioaddr->lbam_addr); 343 iowrite32(tf->lbah, ioaddr->lbah_addr); 344 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 345 tf->feature, 346 tf->nsect, 347 tf->lbal, 348 tf->lbam, 349 tf->lbah); 350 } 351 352 if (tf->flags & ATA_TFLAG_DEVICE) { 353 iowrite32(tf->device, ioaddr->device_addr); 354 VPRINTK("device 0x%X\n", tf->device); 355 } 356 357 ata_wait_idle(ap); 358 } 359 360 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 361 { 362 struct ata_ioports *ioaddr = &ap->ioaddr; 363 364 tf->command = sata_rcar_check_status(ap); 365 tf->feature = ioread32(ioaddr->error_addr); 366 tf->nsect = ioread32(ioaddr->nsect_addr); 367 tf->lbal = ioread32(ioaddr->lbal_addr); 368 tf->lbam = ioread32(ioaddr->lbam_addr); 369 tf->lbah = ioread32(ioaddr->lbah_addr); 370 tf->device = ioread32(ioaddr->device_addr); 371 372 if (tf->flags & ATA_TFLAG_LBA48) { 373 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 374 tf->hob_feature = ioread32(ioaddr->error_addr); 375 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 376 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 377 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 378 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 379 iowrite32(tf->ctl, ioaddr->ctl_addr); 380 ap->last_ctl = tf->ctl; 381 } 382 } 383 384 static void sata_rcar_exec_command(struct ata_port *ap, 385 const struct ata_taskfile *tf) 386 { 387 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 388 389 iowrite32(tf->command, ap->ioaddr.command_addr); 390 ata_sff_pause(ap); 391 } 392 393 static unsigned int sata_rcar_data_xfer(struct ata_device *dev, 394 unsigned char *buf, 395 unsigned int buflen, int rw) 396 { 397 struct ata_port *ap = dev->link->ap; 398 void __iomem *data_addr = ap->ioaddr.data_addr; 399 unsigned int words = buflen >> 1; 400 401 /* Transfer multiple of 2 bytes */ 402 if (rw == READ) 403 sata_rcar_ioread16_rep(data_addr, buf, words); 404 else 405 sata_rcar_iowrite16_rep(data_addr, buf, words); 406 407 /* Transfer trailing byte, if any. */ 408 if (unlikely(buflen & 0x01)) { 409 unsigned char pad[2] = { }; 410 411 /* Point buf to the tail of buffer */ 412 buf += buflen - 1; 413 414 /* 415 * Use io*16_rep() accessors here as well to avoid pointlessly 416 * swapping bytes to and from on the big endian machines... 417 */ 418 if (rw == READ) { 419 sata_rcar_ioread16_rep(data_addr, pad, 1); 420 *buf = pad[0]; 421 } else { 422 pad[0] = *buf; 423 sata_rcar_iowrite16_rep(data_addr, pad, 1); 424 } 425 words++; 426 } 427 428 return words << 1; 429 } 430 431 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 432 { 433 int count; 434 struct ata_port *ap; 435 436 /* We only need to flush incoming data when a command was running */ 437 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 438 return; 439 440 ap = qc->ap; 441 /* Drain up to 64K of data before we give up this recovery method */ 442 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 443 count < 65536; count += 2) 444 ioread32(ap->ioaddr.data_addr); 445 446 /* Can become DEBUG later */ 447 if (count) 448 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 449 } 450 451 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 452 u32 *val) 453 { 454 if (sc_reg > SCR_ACTIVE) 455 return -EINVAL; 456 457 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 458 return 0; 459 } 460 461 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 462 u32 val) 463 { 464 if (sc_reg > SCR_ACTIVE) 465 return -EINVAL; 466 467 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 468 return 0; 469 } 470 471 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 472 { 473 struct ata_port *ap = qc->ap; 474 struct ata_bmdma_prd *prd = ap->bmdma_prd; 475 struct scatterlist *sg; 476 unsigned int si, pi; 477 478 pi = 0; 479 for_each_sg(qc->sg, sg, qc->n_elem, si) { 480 u32 addr, sg_len, len; 481 482 /* 483 * Note: h/w doesn't support 64-bit, so we unconditionally 484 * truncate dma_addr_t to u32. 485 */ 486 addr = (u32)sg_dma_address(sg); 487 sg_len = sg_dma_len(sg); 488 489 /* H/w transfer count is only 29 bits long, let's be careful */ 490 while (sg_len) { 491 len = sg_len; 492 if (len > 0x1ffffffe) 493 len = 0x1ffffffe; 494 495 prd[pi].addr = cpu_to_le32(addr); 496 prd[pi].flags_len = cpu_to_le32(len); 497 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); 498 499 pi++; 500 sg_len -= len; 501 addr += len; 502 } 503 } 504 505 /* end-of-table flag */ 506 prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 507 } 508 509 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) 510 { 511 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 512 return; 513 514 sata_rcar_bmdma_fill_sg(qc); 515 } 516 517 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 518 { 519 struct ata_port *ap = qc->ap; 520 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 521 u32 dmactl; 522 struct sata_rcar_priv *priv = ap->host->private_data; 523 524 /* load PRD table addr. */ 525 mb(); /* make sure PRD table writes are visible to controller */ 526 iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG); 527 528 /* specify data direction, triple-check start bit is clear */ 529 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 530 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 531 if (dmactl & ATAPI_CONTROL1_START) { 532 dmactl &= ~ATAPI_CONTROL1_START; 533 dmactl |= ATAPI_CONTROL1_STOP; 534 } 535 if (!rw) 536 dmactl |= ATAPI_CONTROL1_RW; 537 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 538 539 /* issue r/w command */ 540 ap->ops->sff_exec_command(ap, &qc->tf); 541 } 542 543 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 544 { 545 struct ata_port *ap = qc->ap; 546 u32 dmactl; 547 struct sata_rcar_priv *priv = ap->host->private_data; 548 549 /* start host DMA transaction */ 550 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 551 dmactl |= ATAPI_CONTROL1_START; 552 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 553 } 554 555 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 556 { 557 struct ata_port *ap = qc->ap; 558 struct sata_rcar_priv *priv = ap->host->private_data; 559 u32 dmactl; 560 561 /* force termination of DMA transfer if active */ 562 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG); 563 if (dmactl & ATAPI_CONTROL1_START) { 564 dmactl &= ~ATAPI_CONTROL1_START; 565 dmactl |= ATAPI_CONTROL1_STOP; 566 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG); 567 } 568 569 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 570 ata_sff_dma_pause(ap); 571 } 572 573 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 574 { 575 struct sata_rcar_priv *priv = ap->host->private_data; 576 u32 status; 577 u8 host_stat = 0; 578 579 status = ioread32(priv->base + ATAPI_STATUS_REG); 580 if (status & ATAPI_STATUS_DEVINT) 581 host_stat |= ATA_DMA_INTR; 582 if (status & ATAPI_STATUS_ACT) 583 host_stat |= ATA_DMA_ACTIVE; 584 585 return host_stat; 586 } 587 588 static struct scsi_host_template sata_rcar_sht = { 589 ATA_BMDMA_SHT(DRV_NAME), 590 }; 591 592 static struct ata_port_operations sata_rcar_port_ops = { 593 .inherits = &ata_bmdma_port_ops, 594 595 .freeze = sata_rcar_freeze, 596 .thaw = sata_rcar_thaw, 597 .softreset = sata_rcar_softreset, 598 599 .scr_read = sata_rcar_scr_read, 600 .scr_write = sata_rcar_scr_write, 601 602 .sff_dev_select = sata_rcar_dev_select, 603 .sff_set_devctl = sata_rcar_set_devctl, 604 .sff_check_status = sata_rcar_check_status, 605 .sff_check_altstatus = sata_rcar_check_altstatus, 606 .sff_tf_load = sata_rcar_tf_load, 607 .sff_tf_read = sata_rcar_tf_read, 608 .sff_exec_command = sata_rcar_exec_command, 609 .sff_data_xfer = sata_rcar_data_xfer, 610 .sff_drain_fifo = sata_rcar_drain_fifo, 611 612 .qc_prep = sata_rcar_qc_prep, 613 614 .bmdma_setup = sata_rcar_bmdma_setup, 615 .bmdma_start = sata_rcar_bmdma_start, 616 .bmdma_stop = sata_rcar_bmdma_stop, 617 .bmdma_status = sata_rcar_bmdma_status, 618 }; 619 620 static int sata_rcar_serr_interrupt(struct ata_port *ap) 621 { 622 struct sata_rcar_priv *priv = ap->host->private_data; 623 struct ata_eh_info *ehi = &ap->link.eh_info; 624 int freeze = 0; 625 int handled = 0; 626 u32 serror; 627 628 serror = ioread32(priv->base + SCRSERR_REG); 629 if (!serror) 630 return 0; 631 632 DPRINTK("SError @host_intr: 0x%x\n", serror); 633 634 /* first, analyze and record host port events */ 635 ata_ehi_clear_desc(ehi); 636 637 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 638 /* Setup a soft-reset EH action */ 639 ata_ehi_hotplugged(ehi); 640 ata_ehi_push_desc(ehi, "%s", "hotplug"); 641 642 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 643 handled = 1; 644 } 645 646 /* freeze or abort */ 647 if (freeze) 648 ata_port_freeze(ap); 649 else 650 ata_port_abort(ap); 651 652 return handled; 653 } 654 655 static int sata_rcar_ata_interrupt(struct ata_port *ap) 656 { 657 struct ata_queued_cmd *qc; 658 int handled = 0; 659 660 qc = ata_qc_from_tag(ap, ap->link.active_tag); 661 if (qc) 662 handled |= ata_bmdma_port_intr(ap, qc); 663 664 return handled; 665 } 666 667 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 668 { 669 struct ata_host *host = dev_instance; 670 struct sata_rcar_priv *priv = host->private_data; 671 struct ata_port *ap; 672 unsigned int handled = 0; 673 u32 sataintstat; 674 unsigned long flags; 675 676 spin_lock_irqsave(&host->lock, flags); 677 678 sataintstat = ioread32(priv->base + SATAINTSTAT_REG); 679 if (!sataintstat) 680 goto done; 681 /* ack */ 682 iowrite32(sataintstat & ~SATA_RCAR_INT_MASK, 683 priv->base + SATAINTSTAT_REG); 684 685 ap = host->ports[0]; 686 687 if (sataintstat & SATAINTSTAT_ATA) 688 handled |= sata_rcar_ata_interrupt(ap); 689 690 if (sataintstat & SATAINTSTAT_SERR) 691 handled |= sata_rcar_serr_interrupt(ap); 692 693 done: 694 spin_unlock_irqrestore(&host->lock, flags); 695 696 return IRQ_RETVAL(handled); 697 } 698 699 static void sata_rcar_setup_port(struct ata_host *host) 700 { 701 struct ata_port *ap = host->ports[0]; 702 struct ata_ioports *ioaddr = &ap->ioaddr; 703 struct sata_rcar_priv *priv = host->private_data; 704 705 ap->ops = &sata_rcar_port_ops; 706 ap->pio_mask = ATA_PIO4; 707 ap->udma_mask = ATA_UDMA6; 708 ap->flags |= ATA_FLAG_SATA; 709 710 ioaddr->cmd_addr = priv->base + SDATA_REG; 711 ioaddr->ctl_addr = priv->base + SSDEVCON_REG; 712 ioaddr->scr_addr = priv->base + SCRSSTS_REG; 713 ioaddr->altstatus_addr = ioaddr->ctl_addr; 714 715 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 716 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 717 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 718 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 719 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 720 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 721 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 722 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 723 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 724 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 725 } 726 727 static void sata_rcar_init_controller(struct ata_host *host) 728 { 729 struct sata_rcar_priv *priv = host->private_data; 730 u32 val; 731 732 /* reset and setup phy */ 733 sata_rcar_phy_initialize(priv); 734 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 735 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 736 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 737 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 738 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 739 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 740 741 /* SATA-IP reset state */ 742 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 743 val |= ATAPI_CONTROL1_RESET; 744 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 745 746 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 747 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 748 val |= ATAPI_CONTROL1_ISM; 749 val |= ATAPI_CONTROL1_DESE; 750 val |= ATAPI_CONTROL1_DTA32M; 751 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 752 753 /* Release the SATA-IP from the reset state */ 754 val = ioread32(priv->base + ATAPI_CONTROL1_REG); 755 val &= ~ATAPI_CONTROL1_RESET; 756 iowrite32(val, priv->base + ATAPI_CONTROL1_REG); 757 758 /* ack and mask */ 759 iowrite32(0, priv->base + SATAINTSTAT_REG); 760 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 761 /* enable interrupts */ 762 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); 763 } 764 765 static int sata_rcar_probe(struct platform_device *pdev) 766 { 767 struct ata_host *host; 768 struct sata_rcar_priv *priv; 769 struct resource *mem; 770 int irq; 771 int ret = 0; 772 773 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 774 if (mem == NULL) 775 return -EINVAL; 776 777 irq = platform_get_irq(pdev, 0); 778 if (irq <= 0) 779 return -EINVAL; 780 781 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv), 782 GFP_KERNEL); 783 if (!priv) 784 return -ENOMEM; 785 786 priv->clk = devm_clk_get(&pdev->dev, NULL); 787 if (IS_ERR(priv->clk)) { 788 dev_err(&pdev->dev, "failed to get access to sata clock\n"); 789 return PTR_ERR(priv->clk); 790 } 791 clk_enable(priv->clk); 792 793 host = ata_host_alloc(&pdev->dev, 1); 794 if (!host) { 795 dev_err(&pdev->dev, "ata_host_alloc failed\n"); 796 ret = -ENOMEM; 797 goto cleanup; 798 } 799 800 host->private_data = priv; 801 802 priv->base = devm_request_and_ioremap(&pdev->dev, mem); 803 if (!priv->base) { 804 ret = -EADDRNOTAVAIL; 805 goto cleanup; 806 } 807 808 /* setup port */ 809 sata_rcar_setup_port(host); 810 811 /* initialize host controller */ 812 sata_rcar_init_controller(host); 813 814 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 815 &sata_rcar_sht); 816 if (!ret) 817 return 0; 818 819 cleanup: 820 clk_disable(priv->clk); 821 822 return ret; 823 } 824 825 static int sata_rcar_remove(struct platform_device *pdev) 826 { 827 struct ata_host *host = dev_get_drvdata(&pdev->dev); 828 struct sata_rcar_priv *priv = host->private_data; 829 830 ata_host_detach(host); 831 832 /* disable interrupts */ 833 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); 834 /* ack and mask */ 835 iowrite32(0, priv->base + SATAINTSTAT_REG); 836 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 837 838 clk_disable(priv->clk); 839 840 return 0; 841 } 842 843 #ifdef CONFIG_PM 844 static int sata_rcar_suspend(struct device *dev) 845 { 846 struct ata_host *host = dev_get_drvdata(dev); 847 struct sata_rcar_priv *priv = host->private_data; 848 int ret; 849 850 ret = ata_host_suspend(host, PMSG_SUSPEND); 851 if (!ret) { 852 /* disable interrupts */ 853 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG); 854 /* mask */ 855 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 856 857 clk_disable(priv->clk); 858 } 859 860 return ret; 861 } 862 863 static int sata_rcar_resume(struct device *dev) 864 { 865 struct ata_host *host = dev_get_drvdata(dev); 866 struct sata_rcar_priv *priv = host->private_data; 867 868 clk_enable(priv->clk); 869 870 /* ack and mask */ 871 iowrite32(0, priv->base + SATAINTSTAT_REG); 872 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 873 /* enable interrupts */ 874 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG); 875 876 ata_host_resume(host); 877 878 return 0; 879 } 880 881 static const struct dev_pm_ops sata_rcar_pm_ops = { 882 .suspend = sata_rcar_suspend, 883 .resume = sata_rcar_resume, 884 }; 885 #endif 886 887 static struct of_device_id sata_rcar_match[] = { 888 { .compatible = "renesas,rcar-sata", }, 889 {}, 890 }; 891 MODULE_DEVICE_TABLE(of, sata_rcar_match); 892 893 static struct platform_driver sata_rcar_driver = { 894 .probe = sata_rcar_probe, 895 .remove = sata_rcar_remove, 896 .driver = { 897 .name = DRV_NAME, 898 .owner = THIS_MODULE, 899 .of_match_table = sata_rcar_match, 900 #ifdef CONFIG_PM 901 .pm = &sata_rcar_pm_ops, 902 #endif 903 }, 904 }; 905 906 module_platform_driver(sata_rcar_driver); 907 908 MODULE_LICENSE("GPL"); 909 MODULE_AUTHOR("Vladimir Barinov"); 910 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); 911